[PATCH 00/10] board: sl28: various updates
This is an update for the sl28 board which adds support for - 8 GiB memory variant - different boot sources, like eMMC, SD-card - dynamic prompts - various cleanups
Michael Walle (10): armv8: layerscape: add missing RCW source defines armv8: layerscape: spl: mark OCRAM as non-secure board: sl28: set CPO value board: sl28: remove unneeded ddr config parameter board: sl28: support 8 GiB memory board: sl28: rename include guard macro board: sl28: implement additional bootsources board: sl28: add user friendly names for the boot sources board: sl28: support dynamic prompts board: sl28: remove COUNTER_FREQUENCY_REAL
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 11 ++++ .../asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++ board/kontron/sl28/common.c | 22 ++++++++ board/kontron/sl28/ddr.c | 12 ++++- board/kontron/sl28/sl28.c | 43 +++++++++++++++ board/kontron/sl28/sl28.h | 16 ++++++ board/kontron/sl28/spl.c | 54 ++++++++++++++++++- configs/kontron_sl28_defconfig | 6 ++- include/configs/kontron_sl28.h | 8 ++- 9 files changed, 167 insertions(+), 9 deletions(-) create mode 100644 board/kontron/sl28/sl28.h
A board might need to get the source of the RCW word, which is also the boot source in most cases.
These defines are taken from the LS1028A and I expect they are the same across the SoCs with the same chassis, after all, there was already a reset source for NOR flash.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 863618a5f3..304cd7980a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -230,6 +230,10 @@ #define DCFG_BASE 0x01e00000 #define DCFG_PORSR1 0x000 #define DCFG_PORSR1_RCW_SRC 0xff800000 +#define DCFG_PORSR1_RCW_SRC_SDHC1 0x04000000 +#define DCFG_PORSR1_RCW_SRC_SDHC2 0x04800000 +#define DCFG_PORSR1_RCW_SRC_I2C 0x05000000 +#define DCFG_PORSR1_RCW_SRC_FSPI_NOR 0x07800000 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 #define DCFG_RCWSR12 0x12c #define DCFG_RCWSR12_SDHC_SHIFT 24
By default the OCRAM is marked as secure. While the SPL runs in EL3 and thus can access it, DMA devices cannot. Mark the whole OCRAM as non-secure. This will fix MMC and SD card boot on LS1028A when using SPL instead of TF-A.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 5f09ef0a4a..f57ab85dab 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -67,11 +67,22 @@ void spl_board_init(void) #endif }
+void tzpc_init(void) +{ + /* + * Mark the whole OCRAM as non-secure, otherwise DMA devices cannot + * access it. This is for example necessary for MMC boot. + */ + out_le32(TZPCR0SIZE_BASE, 0); +} + void board_init_f(ulong dummy) { int ret;
icache_enable(); + tzpc_init(); + /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); if (IS_ENABLED(CONFIG_DEBUG_UART))
With a 8GiB memory board, it seems that the "very unlikely event" of a DDR initialization with non-optimal values are not really that unlikely. It happens in about every other reboot. As described in erratum A-009942, preset the DEBUG_28 register with an optimal value. The value iself depends on the memory configuration of the board, but the used value seems to work well for all variants.
Signed-off-by: Michael Walle michael@walle.cc --- board/kontron/sl28/ddr.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index 41426996ab..d75b23e54c 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -54,6 +54,9 @@ static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = {
.ddr_cdr1 = 0x80040000, .ddr_cdr2 = 0x0000bc01, + + /* Erratum A-009942, set optimal CPO value */ + .debug[28] = 0x00700040, };
int fsl_initdram(void)
config_2 doesn't need to be set to zero because that is already the default value.
Signed-off-by: Michael Walle michael@walle.cc --- board/kontron/sl28/ddr.c | 1 - 1 file changed, 1 deletion(-)
diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index d75b23e54c..ed799c6e34 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -69,7 +69,6 @@ int fsl_initdram(void) dram_size = 0x80000000; ddr_cfg_regs.cs[1].bnds = 0; ddr_cfg_regs.cs[1].config = 0; - ddr_cfg_regs.cs[1].config_2 = 0; break; case GPPORCR1_MEM_4GB_CS0_1: dram_size = 0x100000000ULL;
The board supports up to 8 GiB memory. The memory is soldered on the board but the configuration is equivalent to a dual chip select, dual rank DIMM module.
Signed-off-by: Michael Walle michael@walle.cc --- board/kontron/sl28/ddr.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index ed799c6e34..315d9f99c7 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -73,6 +73,13 @@ int fsl_initdram(void) case GPPORCR1_MEM_4GB_CS0_1: dram_size = 0x100000000ULL; break; + case GPPORCR1_MEM_8GB_CS0_1: + dram_size = 0x200000000ULL; + ddr_cfg_regs.cs[0].bnds = 0x000000ff; + ddr_cfg_regs.cs[0].config = 0x80044403; + ddr_cfg_regs.cs[1].bnds = 0x010001ff; + ddr_cfg_regs.cs[1].config = 0x80044403; + break; case GPPORCR1_MEM_512MB_CS0: dram_size = 0x20000000; fallthrough; /* for now */ @@ -82,7 +89,6 @@ int fsl_initdram(void) case GPPORCR1_MEM_4GB_CS0_2: dram_size = 0x100000000ULL; fallthrough; /* for now */ - case GPPORCR1_MEM_8GB_CS0_1: case GPPORCR1_MEM_8GB_CS0_1_2_3: dram_size = 0x200000000ULL; fallthrough; /* for now */
Avoid name clashes with an include file on board level.
Signed-off-by: Michael Walle michael@walle.cc --- include/configs/kontron_sl28.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index c47b5940fb..0cc543716a 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */
-#ifndef __SL28_H -#define __SL28_H +#ifndef __SL28_CONFIG_H +#define __SL28_CONFIG_H
#include <asm/arch/stream_id_lsch3.h> #include <asm/arch/config.h> @@ -87,4 +87,4 @@ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV
-#endif /* __SL28_H */ +#endif /* __SL28_CONFIG_H */
The board is able to boot from the following source: - user-updateble SPI flash - write-protected part of the same SPI flash - eMMC - SD card
Implement the needed function hooks to support all of these boot sources.
Signed-off-by: Michael Walle michael@walle.cc --- board/kontron/sl28/common.c | 22 ++++++++++++++++++++ board/kontron/sl28/sl28.c | 23 ++++++++++++++++++++ board/kontron/sl28/sl28.h | 16 ++++++++++++++ board/kontron/sl28/spl.c | 38 +++++++++++++++++++++++++++++++++- configs/kontron_sl28_defconfig | 5 ++++- 5 files changed, 102 insertions(+), 2 deletions(-) create mode 100644 board/kontron/sl28/sl28.h
diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c index 33c6843c3f..331de29bae 100644 --- a/board/kontron/sl28/common.c +++ b/board/kontron/sl28/common.c @@ -2,6 +2,9 @@
#include <common.h> #include <asm/global_data.h> +#include <asm/io.h> + +#include "sl28.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -9,3 +12,22 @@ u32 get_lpuart_clk(void) { return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV; } + +enum boot_source sl28_boot_source(void) +{ + u32 rcw_src = in_le32(DCFG_BASE + DCFG_PORSR1) & DCFG_PORSR1_RCW_SRC; + + switch (rcw_src) { + case DCFG_PORSR1_RCW_SRC_SDHC1: + return BOOT_SOURCE_SDHC; + case DCFG_PORSR1_RCW_SRC_SDHC2: + return BOOT_SOURCE_MMC; + case DCFG_PORSR1_RCW_SRC_I2C: + return BOOT_SOURCE_I2C; + case DCFG_PORSR1_RCW_SRC_FSPI_NOR: + return BOOT_SOURCE_SPI; + default: + debug("unknown bootsource (%08x)\n", rcw_src); + return BOOT_SOURCE_UNKNOWN; + } +} diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 32e9694b77..54719cc01c 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -24,6 +24,8 @@ #include <fdtdec.h> #include <miiphy.h>
+#include "sl28.h" + DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) @@ -60,6 +62,27 @@ int board_eth_init(struct bd_info *bis) return pci_eth_init(bis); }
+enum env_location env_get_location(enum env_operation op, int prio) +{ + enum boot_source src = sl28_boot_source(); + + if (prio) + return ENVL_UNKNOWN; + + if (!CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) + return ENVL_NOWHERE; + + /* write and erase always operate on the environment */ + if (op == ENVOP_SAVE || op == ENVOP_ERASE) + return ENVL_SPI_FLASH; + + /* failsafe boot will always use the compiled-in default environment */ + if (src == BOOT_SOURCE_SPI) + return ENVL_NOWHERE; + + return ENVL_SPI_FLASH; +} + static int __sl28cpld_read(uint reg) { struct udevice *dev; diff --git a/board/kontron/sl28/sl28.h b/board/kontron/sl28/sl28.h new file mode 100644 index 0000000000..7f0105049c --- /dev/null +++ b/board/kontron/sl28/sl28.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SL28_H +#define __SL28_H + +enum boot_source { + BOOT_SOURCE_UNKNOWN, + BOOT_SOURCE_SDHC, + BOOT_SOURCE_MMC, + BOOT_SOURCE_I2C, + BOOT_SOURCE_SPI, +}; + +enum boot_source sl28_boot_source(void); + +#endif diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index 0e6ad5f37e..b1fefc22b2 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -5,6 +5,9 @@ #include <asm/spl.h> #include <asm/arch-fsl-layerscape/fsl_serdes.h> #include <asm/arch-fsl-layerscape/soc.h> +#include <spi_flash.h> + +#include "sl28.h"
#define DCFG_RCWSR25 0x160 #define GPINFO_HW_VARIANT_MASK 0xff @@ -58,7 +61,40 @@ int board_fit_config_name_match(const char *name)
void board_boot_order(u32 *spl_boot_list) { - spl_boot_list[0] = BOOT_DEVICE_SPI; + enum boot_source src = sl28_boot_source(); + + switch (src) { + case BOOT_SOURCE_SDHC: + spl_boot_list[0] = BOOT_DEVICE_MMC2; + break; + case BOOT_SOURCE_SPI: + case BOOT_SOURCE_I2C: + spl_boot_list[0] = BOOT_DEVICE_SPI; + break; + case BOOT_SOURCE_MMC: + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + default: + panic("unexpected bootsource (%d)\n", src); + break; + } +} + +unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash) +{ + enum boot_source src = sl28_boot_source(); + + switch (src) { + case BOOT_SOURCE_SPI: + return 0x000000; + case BOOT_SOURCE_I2C: + return 0x230000; + default: + panic("unexpected bootsource (%d)\n", src); + break; + } +} + }
int board_early_init_f(void) diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index dc8c28f8cc..7e5c1fc064 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -12,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28" CONFIG_SPL_TEXT_BASE=0x18010000 CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_SIZE_LIMIT=0x20000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0 @@ -36,9 +37,11 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOARD_LATE_INIT=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x900 CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y
During startup the SPL will print where the u-boot proper is read from. Instead of using the default names, provide more user friendly names.
Signed-off-by: Michael Walle michael@walle.cc --- board/kontron/sl28/spl.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index b1fefc22b2..ffaf517a8b 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -95,6 +95,22 @@ unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash) } }
+const char *spl_board_loader_name(u32 boot_device) +{ + enum boot_source src = sl28_boot_source(); + + switch (src) { + case BOOT_SOURCE_SDHC: + return "SD card (Test mode)"; + case BOOT_SOURCE_SPI: + return "Failsafe SPI flash"; + case BOOT_SOURCE_I2C: + return "SPI flash"; + case BOOT_SOURCE_MMC: + return "eMMC"; + default: + return "(unknown)"; + } }
int board_early_init_f(void)
Depending on the boot source, set different CLI prompts. This will help the user to figure out in which mode the bootloader was started. There are two special modes: failsafe and SDHC boot.
Signed-off-by: Michael Walle michael@walle.cc --- board/kontron/sl28/sl28.c | 20 ++++++++++++++++++++ configs/kontron_sl28_defconfig | 1 + 2 files changed, 21 insertions(+)
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 54719cc01c..0576b3eae4 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -126,8 +126,28 @@ static void stop_recovery_watchdog(void) wdt_stop(dev); }
+static void sl28_set_prompt(void) +{ + enum boot_source src = sl28_boot_source(); + + switch (src) { + case BOOT_SOURCE_SPI: + env_set("PS1", "[FAILSAFE] => "); + break; + case BOOT_SOURCE_SDHC: + env_set("PS1", "[SDHC] => "); + break; + default: + env_set("PS1", NULL); + break; + } +} + int fsl_board_late_init(void) { + if (IS_ENABLED(CONFIG_CMDLINE_PS_SUPPORT)) + sl28_set_prompt(); + /* * Usually, the after a board reset, the watchdog is enabled by * default. This is to supervise the bootloader boot-up. Therefore, diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 7e5c1fc064..3d142d5470 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x900 CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_SPI_LOAD=y +CONFIG_CMDLINE_PS_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y
The frequency of the system counter is static which is given by the COUNTER_FREQUENCY option. Remove COUNTER_FREQUENCY_REAL.
Signed-off-by: Michael Walle michael@walle.cc --- include/configs/kontron_sl28.h | 2 -- 1 file changed, 2 deletions(-)
diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 0cc543716a..b7d2edb75b 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -39,8 +39,6 @@ /* serial port */ #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) - /* SPL */ #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
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Michael Walle