From: Holger Brunck holger.brunck@keymile.com

The MACH_TYPE SUEN3 is now to specific for keymile boards, because other boards similar to suen3 will follow. So the MACH_SUEN3 was renamed to MACH_KM_KIRKWOOD.

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Wolfgang Denk wd@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - new patch in v2, first patch of v1 serie was split up

board/keymile/common/common.c | 4 ++-- board/keymile/km_arm/km_arm.c | 2 +- include/configs/km_arm.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 7b4eefd..86be9c2 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -500,7 +500,7 @@ void i2c_init_board(void) out_8 (&dev->cr, (I2C_CR_MEN));

#else -#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_MACH_SUEN3) +#if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;

@@ -578,7 +578,7 @@ int fdt_get_node_and_value (void *blob, } #endif

-#if !defined(CONFIG_MACH_SUEN3) +#if !defined(MACH_TYPE_KM_KIRKWOOD) int ethernet_present (void) { return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80); diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 2e20644..5c1e822 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -180,7 +180,7 @@ int board_init(void) /* * arch number of board */ - gd->bd->bi_arch_number = MACH_TYPE_SUEN3; + gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;

/* address of boot parameters */ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index bf77cc0..533da73 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -38,7 +38,7 @@ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KIRKWOOD /* SOC Family Name */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_MACH_SUEN3 /* Machine type */ +#define CONFIG_MACH_KM_KIRKWOOD /* Machine type */

/* include common defines/options for all Keymile boards */ #include "keymile-common.h"

From: Holger Brunck holger.brunck@keymile.com

This patch reworks all headerfiles for keymile boards. Furthermore the environment variables are refactored.

Changes: - introduce km-powerpc.h file and extract ppc specific parts to it - move ARM specific options and vaiables to km_arm.h - sort the environment variables to logical groups - enhance the description of the environment variables - remove KM specific HW key and board id from kernel command line

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Wolfgang Denk wd@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - new patch in v2, first patch in v1 was split up - fix checkpatch.pl errors and warnings

include/configs/keymile-common.h | 234 ++++++++++++++++++++++--------------- include/configs/km-powerpc.h | 92 +++++++++++++++ include/configs/km_arm.h | 25 ++++- include/configs/kmeter1.h | 36 +++---- include/configs/mgcoge.h | 31 +++--- 5 files changed, 286 insertions(+), 132 deletions(-) create mode 100644 include/configs/km-powerpc.h

diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 242a3c6..f548994 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -86,10 +86,6 @@ #define CONFIG_HUSH_INIT_VAR

#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */

#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */

@@ -142,7 +138,6 @@ #define CONFIG_CMD_UBI #define CONFIG_RBTREE #define CONFIG_MTD_PARTITIONS -#define CONFIG_FLASH_CFI_MTD #define CONFIG_MTD_DEVICE #define CONFIG_MTD_CONCAT

@@ -170,103 +165,152 @@ "kmprivate=empty\0" #endif

+#ifndef CONFIG_KM_DEF_NETDEV +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" +#endif + +#ifndef CONFIG_KM_UBI_PARTITION_NAME +#define CONFIG_KM_UBI_PARTITION_NAME "ubi0" +#endif +#ifndef CONFIG_KM_UBI_LINUX_MTD_NAME +#define CONFIG_KM_UBI_LINUX_MTD_NAME "ubi0" +#endif + #define xstr(s) str(s) #define str(s) #s

+/* + * bootargs + * - modify 'bootargs' + * + * - 'addip': add ip configuration + * - 'addpanic': add kernel panic options + * - 'addramfs': add phram device for the rootfilesysten in ram + * - 'addtty': add console=... + * - 'nfsargs': default arguments for nfs boot + * - 'flashargs': defaults arguments for flash base boot + * + * processor specific settings + * - 'addmtdparts': add mtd partition information + */ +#define CONFIG_KM_DEF_ENV_BOOTARGS \ + "addinit=" \ + "setenv bootargs ${bootargs} init=${init}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off\0" \ + "addpanic=" \ + "setenv bootargs ${bootargs} " \ + "panic=1 panic_on_oops=1\0" \ + "addramfs=" \ + "setenv bootargs "" \ + "${bootargs} phram.phram=" \ + "rootfs${actual_bank},${rootfsaddr},${rootfssize}"\0" \ + "addtty=" \ + "setenv bootargs ${bootargs}" \ + " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}\0" \ + "nfsargs=" \ + "setenv bootargs " \ + "ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \ + "root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "flashargs=" \ + "setenv bootargs " \ + "ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \ + "root=mtdblock:rootfs${actual_bank} " \ + "rootfstype=squashfs ro\0" \ + "" + +#define CONFIG_KM_DEF_ENV_COMPUTE_ADDR \ + "setboardid=" \ + "if test "x${boardId}" = "x"; then; " \ + "setenv boardId ${IVM_BoardId} && " \ + "setenv hwKey ${IVM_HWKey}; " \ + "else; " \ + "echo \\c; " \ + "fi\0" + +/* + * flash_boot + * - commands for booting from flash + * + * - 'cramfsaddr': address to the cramfs (in ram) + * - 'cramfsloadkernel': copy kernel from a cramfs to ram + * - 'ubiattach': attach ubi partition + * - 'ubicopy': copy ubi volume to ram + * - volume names: bootfs0, bootfs1, bootfs2, ... + * - 'ubiparition': mtd parition name for ubi + * + * processor specific settings + * - 'cramfsloadfdt': copy fdt from a cramfs to ram + */ +#define CONFIG_KM_DEF_ENV_FLASH_BOOT \ + "cramfsaddr="xstr(CONFIG_KM_CRAMFS_ADDR) "\0" \ + "cramfsloadkernel=" \ + "cramfsload ${kernel_addr_r} uImage && " \ + "setenv actual_kernel_addr ${kernel_addr_r}\0" \ + "ubiattach=ubi part ${ubipartition}\0" \ + "ubicopy=ubi read ${cramfsaddr} bootfs${actual_bank}\0" \ + "ubipartition=" CONFIG_KM_UBI_PARTITION_NAME "\0" \ + "" + +/* + * net_boot + * - commands for booting over the network + * + * - 'tftpkernel': load a kernel with tftp into ram + * + * processor specific settings + * - 'tftpfdt': load fdt with tftp into ram + */ +#define CONFIG_KM_DEF_ENV_NET_BOOT \ + "tftpkernel=" \ + "tftpboot ${kernel_addr_r} ${kernel_file} && " \ + "setenv actual_kernel_addr ${kernel_addr_r} \0" + +/* + * constants + * - KM specific constants and commands + * + * - 'default': setup default environment + */ +#define CONFIG_KM_DEF_ENV_CONSTANTS \ + "actual=setenv actual_bank ${initial_boot_bank}\0" \ + "actual0=setenv actual_bank 0\0" \ + "actual_bank=${initial_boot_bank}\0" \ + "default=" \ + "setenv default 'run newenv; reset' && " \ + "run release && saveenv; reset\0" \ + "checkboardid=" \ + "test "x${boardId}" = "x${IVM_BoardId}"\0" \ + "printbootargs=print bootargs\0" \ + "rootfsfile="xstr(CONFIG_HOSTNAME) "/rootfsImage\0" \ + "" + #ifndef CONFIG_KM_DEF_ENV #define CONFIG_KM_DEF_ENV \ - "netdev=eth0\0" \ - "u-boot_addr_r=100000\0" \ - "kernel_addr_r=200000\0" \ - "fdt_addr_r=600000\0" \ - "ram_ws=800000 \0" \ - "script_ws=780000 \0" \ - "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \ - xstr(CONFIG_HOSTNAME) ".dtb\0" \ - "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \ - "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off " xstr(BOOTFLASH_START) " +${filesize};" \ - "erase " xstr(BOOTFLASH_START) " +${filesize};" \ - "cp.b ${u-boot_addr_r} " xstr(BOOTFLASH_START) \ - " ${filesize};" \ - "protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \ - "load_fdt=tftp ${fdt_addr_r} ${fdt_file}; " \ - "setenv actual_fdt_addr ${fdt_addr_r} \0" \ - "load_kernel=tftp ${kernel_addr_r} ${kernel_file}; " \ - "setenv actual_kernel_addr ${kernel_addr_r} \0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "mtdargs=setenv bootargs root=${actual_rootfs} rw " \ - "rootfstype=jffs2 \0" \ - "altmtdargs=setenv bootargs root=${backup_rootfs} rw " \ - "rootfstype=jffs2 \0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addboardid=setenv bootargs ${bootargs} " \ - "hwKey=${IVM_HWKey} boardId=0x${IVM_BoardId} \0" \ - "addpram=setenv bootargs ${bootargs} " \ - "mem=${mem} pram=${pram}\0" \ - "pram=" xstr(CONFIG_PRAM) "k\0" \ - "net_nfs=tftp ${kernel_addr_r} ${kernel_file}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addcon addboardid addpram;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_self=tftp ${kernel_addr_r} ${kernel_file}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "tftp ${ramdisk_addr} ${ramdisk_file}; " \ - "run ramargs addip addboardid addpram; " \ - "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0"\ - "flash_nfs=run nfsargs addip addcon;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addcon addboardid addpram;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "bootcmd=run mtdargs addip addcon addboardid addpram; " \ - "bootm ${actual_kernel_addr} - ${actual_fdt_addr} \0" \ - "altbootcmd=run altmtdargs addip addcon addboardid addpram; " \ - "bootm ${backup_kernel_addr} - ${backup_fdt_addr} \0" \ - "actual0=setenv actual_bank 0; setenv actual_kernel_addr " \ - "${bank0_kernel_addr}; " \ - "setenv actual_fdt_addr ${bank0_fdt_addr}; " \ - "setenv actual_rootfs ${bank0_rootfs} \0" \ - "actual1=setenv actual_bank 1; setenv actual_kernel_addr " \ - "${bank1_kernel_addr}; " \ - "setenv actual_fdt_addr ${bank1_fdt_addr}; " \ - "setenv actual_rootfs ${bank1_rootfs} \0" \ - "backup0=setenv backup_bank 0; setenv backup_kernel_addr " \ - "${bank0_kernel_addr}; " \ - "setenv backup_fdt_addr ${bank0_fdt_addr}; " \ - "setenv backup_rootfs ${bank0_rootfs} \0" \ - "backup1=setenv backup_bank 1; setenv backup_kernel_addr " \ - "${bank1_kernel_addr}; " \ - "setenv backup_fdt_addr ${bank1_fdt_addr}; " \ - "setenv backup_rootfs ${bank1_rootfs} \0" \ - "setbank0=run actual0 backup1 \0" \ - "setbank1=run actual1 backup0 \0" \ - "release=setenv bootcmd " \ - "'run mtdargs addip addcon addboardid addpram;" \ - "bootm ${actual_kernel_addr} - ${actual_fdt_addr} '; " \ - "saveenv \0" \ - "develop=setenv bootcmd " \ - "'run nfsargs addip addcon addboardid addpram;" \ - "bootm ${actual_kernel_addr} - ${actual_fdt_addr} '; " \ - "saveenv \0" \ - "developall=setenv bootcmd " \ - "'run load_fdt load_kernel nfsargs " \ - "addip addcon addboardid addpram; " \ - "bootm ${actual_kernel_addr} - ${actual_fdt_addr} '; " \ - "saveenv \0" \ - "set_new_esw_script=setenv new_esw_script " \ - "new_esw_0x${IVM_BoardId}_0x${IVM_HWKey}.scr \0" \ - "new_esw=run set_new_esw_script; " \ - "tftp ${script_ws} ${new_esw_script}; " \ - "iminfo ${script_ws}; source ${script_ws} \0" \ - "bootlimit=0 \0" \ CONFIG_KM_DEF_ENV_IOMUX \ CONFIG_KM_DEF_ENV_PRIVATE \ + CONFIG_KM_DEF_NETDEV \ + CONFIG_KM_DEF_ENV_CPU \ + CONFIG_KM_DEF_ENV_BOOTARGS \ + CONFIG_KM_DEF_ENV_COMPUTE_ADDR \ + CONFIG_KM_DEF_ENV_FLASH_BOOT \ + CONFIG_KM_DEF_ENV_NET_BOOT \ + "altbootcmd=run bootcmd\0" \ + "bootcmd=run default\0" \ + "bootlimit=2\0" \ + "init=/sbin/init-overlay.sh\0" \ + "kernel_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \ + "kernel_file="xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "kernel_name=uImage\0" \ + "load=tftpboot ${u-boot_addr_r} ${u-boot}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "u-boot_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \ "" #endif /* CONFIG_KM_DEF_ENV */

diff --git a/include/configs/km-powerpc.h b/include/configs/km-powerpc.h new file mode 100644 index 0000000..3351609 --- /dev/null +++ b/include/configs/km-powerpc.h @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_KEYMILE_POWERPC_H +#define __CONFIG_KEYMILE_POWERPC_H + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_CMD_DTT +#define CONFIG_JFFS2_CMDLINE + +#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */ +#define CONFIG_FLASH_CFI_MTD + +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ + +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ + +/****************************************************************************** + * (PRAM usage) + * ... ------------------------------------------------------- + * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM + * ... |<------------------- pram -------------------------->| + * ... ------------------------------------------------------- + * @END_OF_RAM: + * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose + * @CONFIG_KM_PHRAM: address for /var + * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) + * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM + */ + +/* size of rootfs in RAM */ +#define CONFIG_KM_ROOTFSSIZE 0x0 +/* pseudo-non volatile RAM [hex] */ +#define CONFIG_KM_PNVRAM 0x80000 +/* physical RAM MTD size [hex] */ +#define CONFIG_KM_PHRAM 0x100000 +/* resereved pram area at the end of memroy [hex] */ +#define CONFIG_KM_RESERVED_PRAM 0x0 +/* enable protected RAM */ +#define CONFIG_PRAM 0 + +#define CONFIG_KM_CRAMFS_ADDR 0x800000 +#define CONFIG_KM_KERNEL_ADDR 0x400000 /* 3968Kbytes */ +#define CONFIG_KM_FDT_ADDR 0x7E0000 /* 128Kbytes */ + +#define CONFIG_KM_DEF_ENV_CPU \ + "addbootcount=echo \\c\0" \ + "addmtdparts=echo \\c\0" \ + "boot=bootm ${actual_kernel_addr} - ${actual_fdt_addr}\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb && " \ + "setenv actual_fdt_addr ${fdt_addr_r}\0" \ + "fdt_addr_r=" xstr(CONFIG_KM_FDT_ADDR) "\0" \ + "fdt_file=" \ + xstr(CONFIG_HOSTNAME) "/" \ + xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "tftpfdt=" \ + "tftpboot ${fdt_addr_r} ${fdt_file} && " \ + "setenv actual_fdt_addr ${fdt_addr_r} \0" \ + "update=" \ + "protect off " xstr(BOOTFLASH_START) " +${filesize} && "\ + "erase " xstr(BOOTFLASH_START) " +${filesize} && " \ + "cp.b ${u-boot_addr_r} " xstr(BOOTFLASH_START) \ + " ${filesize} && " \ + "protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \ + "" + +#endif /* __CONFIG_KEYMILE_POWERPC_H */ diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index af564c7..8221579 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -46,8 +46,29 @@

/* include common defines/options for all Keymile boards */ #include "keymile-common.h" -#undef CONFIG_CMD_DTT -#undef CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_ENV_SIZE (128 << 10) /* NAND chip block size */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ + +/* pseudo-non volatile RAM [hex] */ +#define CONFIG_KM_PNVRAM 0x80000 +/* physical RAM MTD size [hex] */ +#define CONFIG_KM_PHRAM 0x17F000 + +#define CONFIG_KM_CRAMFS_ADDR 0x2400000 +#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */ + +#define CONFIG_KM_DEF_ENV_CPU \ + "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "boot=bootm ${actual_kernel_addr} - -\0" \ + "cramfsloadfdt=echo \\c\0" \ + "tftpfdt=echo \\c\0" \ + CONFIG_KM_DEF_ENV_UPDATE \ + "" + +

#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 533d0d2..71268bc 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -29,16 +29,20 @@ #define CONFIG_HOSTNAME kmeter1

#define CONFIG_SYS_TEXT_BASE 0xF0000000 +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth2\0" \

/* include common defines/options for all Keymile boards */ #include "keymile-common.h" - -#define CONFIG_KM_UBI_PARTITION_NAME "ubi0" +#include "km-powerpc.h"

#define MTDIDS_DEFAULT "nor0=boot" -#define MTDPARTS_DEFAULT \ - "mtdparts=boot:768k(u-boot),128k(env),128k(envred)," \ - "-(" CONFIG_KM_UBI_PARTITION_NAME ")" +#define MTDPARTS_DEFAULT "mtdparts=" \ + "boot:" \ + "768k(u-boot)," \ + "128k(env)," \ + "128k(envred)," \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")"

#define CONFIG_MISC_INIT_R /* @@ -443,7 +447,7 @@

#define BOOTFLASH_START F0000000

-#define CONFIG_PRAM 512 /* protected RAM [KBytes] */ +#define CONFIG_KM_CONSOLE_TTY "ttyS0"

/* * Environment Configuration @@ -455,22 +459,14 @@

#define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ + "dtt_bus=pca9547:70:a\0" \ + "EEprom_ivm=pca9547:70:9\0" \ + "newenv=" \ + "prot off 0xF00C0000 +0x40000 && " \ + "era 0xF00C0000 +0x40000\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ - "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \ - "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \ - "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ - "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0" \ "unlock=yes\0" \ - "fdt_addr=F0080000\0" \ - "kernel_addr=F00a0000\0" \ - "ramdisk_addr=F03a0000\0" \ - "ramdisk_addr_r=F10000\0" \ - "EEprom_ivm=pca9547:70:9\0" \ - "dtt_bus=pca9547:70:a\0" \ - "mtdids=nor0=app \0" \ - "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \ - "" + ""

#if defined(CONFIG_UEC_ETH) #define CONFIG_HAS_ETH0 diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 9c239a4..455246a 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -39,6 +39,7 @@

/* include common defines/options for all Keymile boards */ #include "keymile-common.h" +#include "km-powerpc.h"

/* * Select serial console configuration @@ -82,28 +83,28 @@

#define BOOTFLASH_START 0xFE000000

-#define MTDIDS_DEFAULT "nor0=boot,nor1=app" -#define MTDPARTS_DEFAULT \ - "mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \ - "app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)" +#define CONFIG_KM_CONSOLE_TTY "ttyCPM0" + +#define MTDIDS_DEFAULT "nor3=app" +#define MTDPARTS_DEFAULT "mtdparts=" \ + "app:" \ + "768k(u-boot)," \ + "128k(env)," \ + "128k(envred)," \ + "3072k(free)," \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")"

-#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif /* * Default environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "addcon=setenv bootargs ${bootargs} " \ - "console=ttyCPM0,${baudrate}\0" \ - "mtdids=nor0=boot,nor1=app \0" \ - "partition=nor1,5 \0" \ - "new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0" \ "EEprom_ivm=pca9544a:70:4 \0" \ - "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \ "unlock=yes\0" \ + "newenv=" \ + "prot off 0xFE0C0000 +0x40000 && " \ + "era 0xFE0C0000 +0x40000\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ ""

#define CONFIG_SYS_SDRAM_BASE 0x00000000

This board is similar to suvd3 board. So most initialisation topics are taken from suvd3 (UART1, Ethernet, piggy PHY, flash, ram) only the application specific chip selects differ.

Signed-off-by: Lukas Roggli lukas.roggli@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - fix checkpatch.pl errors and warnings

MAINTAINERS | 1 + boards.cfg | 1 + include/configs/tuxa1.h | 234 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 236 insertions(+), 0 deletions(-) create mode 100644 include/configs/tuxa1.h

diff --git a/MAINTAINERS b/MAINTAINERS index 75b7343..801e4dd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -434,6 +434,7 @@ Heiko Schocher hs@denx.de sc3 PPC405GP suen3 ARM926EJS (Kirkwood SoC) suvd3 MPC8321 + tuxa1 MPC8321 uc101 MPC5200 ve8313 MPC8313

diff --git a/boards.cfg b/boards.cfg index dc583ba..ed5e0e7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -476,6 +476,7 @@ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP suvd3 powerpc mpc83xx km83xx keymile TQM834x powerpc mpc83xx tqm834x tqc +tuxa1 powerpc mpc83xx km83xx keymile sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540 diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h new file mode 100644 index 0000000..c4b48d1 --- /dev/null +++ b/include/configs/tuxa1.h @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010 + * Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_MPC832x /* MPC832x CPU specific */ +#define CONFIG_TUXA1 /* TUXA1 board specific */ +#define CONFIG_HOSTNAME tuxa1 +#define CONFIG_KM_BOARD_NAME "tuxa1" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" + +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +#define CONFIG_MISC_INIT_R + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x00000006 +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_2T_EN | \ + SDRAM_CFG_SREN) +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860252 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (2 << TIMING_CFG1_WRREC_SHIFT) | \ + (6 << TIMING_CFG1_REFREC_SHIFT) | \ + (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_PIGGY_BASE 0xE8000000 +#define CONFIG_SYS_PIGGY_SIZE 128 +#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */ +#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_PINC2_BASE 0xB0000000 /* PINC2 */ +#define CONFIG_SYS_PINC2_SIZE 256 /* Megabytes */ + + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local GPCM 8 bit 256MB LPXF + * 3 Local GPCM 8 bit 256MB PINC2 + * + */ + +/* + * LPXF on the local bus CS2 + * Window base at flash base + * Window size: 256 MB + */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + (OR_GPCM_TRLX & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_EAD) +/* + * PINC2 on the local bus CS3 + * Access window base at PINC2 base + * Window size: 256 MB + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PINC2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PINC2_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \ + OR_GPCM_CSNT | \ + (OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \ + (~OR_GPCM_XACS)) | /* XACS = 0 */ \ + (OR_GPCM_SCY_2 & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_TRLX) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +/* + * MMU Setup + */ +/* LPXF: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else /* CONFIG_PCI */ + +/* PINC2: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif /* CONFIG_PCI */ + +#endif /* __CONFIG_H */

This board is similar to keymile suen3.

Signed-off-by: Clive Stubbings clive.stubbings@xentech.co.uk Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Prafulla Wadaskar prafulla@marvell.com --- Changes for v2: - fix checkpatch.pl errors and warnings

MAINTAINERS | 1 + boards.cfg | 1 + include/configs/km_arm.h | 41 ++++++++++++++++++++++++++++ include/configs/mgcoge2un.h | 63 +++++++++++++++++++++++++++++++++++++++++++ include/configs/suen3.h | 41 ---------------------------- 5 files changed, 106 insertions(+), 41 deletions(-) create mode 100644 include/configs/mgcoge2un.h

diff --git a/MAINTAINERS b/MAINTAINERS index cbc34af..4e7a8f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -428,6 +428,7 @@ Heiko Schocher hs@denx.de jupiter MPC5200 kmeter1 MPC8360 mgcoge MPC8247 + mgcoge2un ARM926EJS (Kirkwood SoC) mucmc52 MPC5200 muas3001 MPC8270 municse MPC5200 diff --git a/boards.cfg b/boards.cfg index b3a4e9e..1b45b5e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -94,6 +94,7 @@ davinci_schmoogie arm arm926ejs schmoogie davinci davinci_sffsdr arm arm926ejs sffsdr davinci davinci davinci_sonata arm arm926ejs sonata davinci davinci suen3 arm arm926ejs km_arm keymile kirkwood +mgcoge2un arm arm926ejs km_arm keymile kirkwood guruplug arm arm926ejs - Marvell kirkwood mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood openrd_base arm arm926ejs - Marvell kirkwood diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 8221579..6e8e8b7 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -198,6 +198,47 @@ int get_scl (void); #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

+/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ +#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_EEPROM_WREN +#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) +#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0" + +/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#define CONFIG_CMD_SF + +#define CONFIG_SPI_FLASH +#define CONFIG_HARD_SPI +#define CONFIG_KIRKWOOD_SPI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */ + +#define FLASH_GPIO_PIN 0x00010000 + +#define MTDIDS_DEFAULT "nand0=orion_nand" +/* test-only: partitioning needs some tuning, this is just for tests */ +#define MTDPARTS_DEFAULT "mtdparts=" \ + "orion_nand:" \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")" + +#define CONFIG_KM_DEF_ENV_UPDATE \ + "update=" \ + "spi on;sf probe 0;sf erase 0 50000;" \ + "sf write ${u-boot_addr_r} 0 ${filesize};" \ + "spi off\0" + #if defined(CONFIG_SYS_NO_FLASH) #define CONFIG_KM_UBI_PARTITION_NAME "ubi0" #undef CONFIG_FLASH_CFI_MTD diff --git a/include/configs/mgcoge2un.h b/include/configs/mgcoge2un.h new file mode 100644 index 0000000..9f5464b --- /dev/null +++ b/include/configs/mgcoge2un.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar prafulla@marvell.com + * + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2010-2011 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ + +#ifndef _CONFIG_MGCOGE2UN_H +#define _CONFIG_MGCOGE2UN_H + +/* include common defines/options for all arm based Keymile boards */ +#include "km_arm.h" + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nKeymile MGCOGE2UN" + +#define CONFIG_HOSTNAME mgcoge2un + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + "memsize=0x8000000\0" \ + "newenv=setenv addr 0x100000 && " \ + "i2c dev 1; mw.b ${addr} 0 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ + "rootpath=/opt/eldk/arm\0" \ + "EEprom_ivm=pca9547:70:9\0" \ + "" + +#endif /* _CONFIG_MGCOGE2UN_H */ diff --git a/include/configs/suen3.h b/include/configs/suen3.h index b2730a3..87f524a 100644 --- a/include/configs/suen3.h +++ b/include/configs/suen3.h @@ -44,47 +44,6 @@ #define CONFIG_HOSTNAME suen3

/* - * Environment variables configurations - */ -#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ -#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 -#define CONFIG_ENV_EEPROM_IS_ON_I2C 1 -#define CONFIG_SYS_EEPROM_WREN 1 -#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) -#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0" - -/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_CMD_SF - -#define CONFIG_SPI_FLASH -#define CONFIG_HARD_SPI -#define CONFIG_KIRKWOOD_SPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */ - -#define FLASH_GPIO_PIN 0x00010000 - -#define MTDIDS_DEFAULT "nand0=orion_nand" -/* test-only: partitioning needs some tuning, this is just for tests */ -#define MTDPARTS_DEFAULT "mtdparts=" \ - "orion_nand:" \ - "-(" CONFIG_KM_UBI_PARTITION_NAME ")" - -#define CONFIG_KM_DEF_ENV_UPDATE \ - "update=" \ - "spi on;sf probe 0;sf erase 0 50000;" \ - "sf write ${u-boot_addr_r} 0 ${filesize};" \ - "spi off\0" - -/* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \

The mgcoge2 board from keymile deploys two different porcessors. An ARM based Kirkwood for the "unit" part of the SW and a PPC for the "ne" part of the SW. Therefore in Linux and U-Boot the names for the board are mgcoge2un and mgcoge2ne. This patch adds the mgcoge2ne part of the board. The ppc part of mgboge2 is quite similar to mgcoge, therefore a generic header km82xx-common.h was introduced to collect all similiarities. Currently the only difference is that mgcoge2ne has a 64 MB numonyx NOR flash with a single die. The mgcoge has a dual die flash 2*32MB from spansion.

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Wolfgang Denk wd@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - fix checkpatch.pl errors and warnings

MAINTAINERS | 1 + board/keymile/common/common.c | 4 +- board/keymile/mgcoge/mgcoge.c | 10 +- boards.cfg | 1 + include/configs/km82xx-common.h | 318 +++++++++++++++++++++++++++++++++++++++ include/configs/mgcoge.h | 294 +----------------------------------- include/configs/mgcoge2ne.h | 66 ++++++++ 7 files changed, 398 insertions(+), 296 deletions(-) create mode 100644 include/configs/km82xx-common.h create mode 100644 include/configs/mgcoge2ne.h

diff --git a/MAINTAINERS b/MAINTAINERS index 9644d38..e4525e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -428,6 +428,7 @@ Heiko Schocher hs@denx.de jupiter MPC5200 kmeter1 MPC8360 mgcoge MPC8247 + mgcoge2ne MPC8247 mgcoge2un ARM926EJS (Kirkwood SoC) mucmc52 MPC5200 muas3001 MPC8270 diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index f0b99ed..f723cfa 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -22,7 +22,7 @@ */

#include <common.h> -#if defined(CONFIG_MGCOGE) +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGCOGE2NE) #include <mpc8260.h> #endif #include <ioports.h> @@ -337,7 +337,7 @@ int ivm_read_eeprom (void) #define DELAY_ABORT_SEQ 62 #define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))

-#if defined(CONFIG_MGCOGE) +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGCOGE2NE) #define SDA_MASK 0x00010000 #define SCL_MASK 0x00020000 static void set_pin (int state, unsigned long mask) diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index 5c9496c..1a6bdd8 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -286,10 +286,14 @@ phys_size_t initdram (int board_type)

int checkboard(void) { - puts ("Board: Keymile mgcoge"); +#if defined(CONFIG_MGCOGE) + puts("Board: Keymile mgcoge"); +#else + puts("Board: Keymile mgcoge2ne"); +#endif if (ethernet_present ()) - puts (" with PIGGY."); - puts ("\n"); + puts(" with PIGGY."); + puts("\n"); return 0; }

diff --git a/boards.cfg b/boards.cfg index 22cb509..3c45456 100644 --- a/boards.cfg +++ b/boards.cfg @@ -424,6 +424,7 @@ PQ2FADS-ZU_66MHz_lowboot powerpc mpc8260 mpc8260ads freesca PQ2FADS-ZU_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw funkwerk - VoVPN-GW:CLKIN_66MHz mgcoge powerpc mpc8260 - keymile +mgcoge2ne powerpc mpc8260 mgcoge keymile SCM powerpc mpc8260 - siemens TQM8255_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8255,300MHz TQM8260_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz diff --git a/include/configs/km82xx-common.h b/include/configs/km82xx-common.h new file mode 100644 index 0000000..262536c --- /dev/null +++ b/include/configs/km82xx-common.h @@ -0,0 +1,318 @@ +/* + * (C) Copyright 2007-2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __KM82XX_COMMON +#define __KM82XX_COMMON + +/* + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#define CONFIG_CONS_ON_SMC /* Console is on SMC */ +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ +#undef CONFIG_CONS_NONE /* It's not on external UART */ +#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ +#define CONFIG_SYS_SMC_RXBUFLEN 128 +#define CONFIG_SYS_MAXIDLE 10 + +/* + * Select ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for + * SCC, 1-3 for FCC) + * + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines + * must be defined elsewhere (as for the console), or CONFIG_CMD_NET + * must be unset. + */ +#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ +#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ +#undef CONFIG_ETHER_NONE /* No external Ethernet */ +#define CONFIG_NET_MULTI + +#define CONFIG_ETHER_INDEX 4 +#define CONFIG_HAS_ETH0 +#define CONFIG_SYS_SCC_TOUT_LOOP 10000000 + +# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) + +#ifndef CONFIG_8260_CLKIN +#define CONFIG_8260_CLKIN 66000000 /* in Hz */ +#endif + +#define BOOTFLASH_START 0xFE000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyCPM0" + +#define MTDPARTS_DEFAULT "mtdparts=" \ + "app:" \ + "768k(u-boot)," \ + "128k(env)," \ + "128k(envred)," \ + "3072k(free)," \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")" + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + "EEprom_ivm=pca9544a:70:4 \0" \ + "unlock=yes\0" \ + "newenv=" \ + "prot off 0xFE0C0000 +0x40000 && " \ + "era 0xFE0C0000 +0x40000\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "" + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_LEN (768 << 10) + +#define CONFIG_ENV_IS_IN_FLASH + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed */ +#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ + +/* + * Software (bit-bang) I2C driver configuration + */ + +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if (bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if (bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 +#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +#define CONFIG_SYS_IMMR 0xF0000000 + +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* Hard reset configuration word */ +#define CONFIG_SYS_HRCW_MASTER 0x0604b211 + +/* No slaves */ +#define CONFIG_SYS_HRCW_SLAVE1 0 +#define CONFIG_SYS_HRCW_SLAVE2 0 +#define CONFIG_SYS_HRCW_SLAVE3 0 +#define CONFIG_SYS_HRCW_SLAVE4 0 +#define CONFIG_SYS_HRCW_SLAVE5 0 +#define CONFIG_SYS_HRCW_SLAVE6 0 +#define CONFIG_SYS_HRCW_SLAVE7 0 + +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CONFIG_SYS_HID0_INIT 0 +#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) + +#define CONFIG_SYS_HID2 0 + +#define CONFIG_SYS_SIUMCR 0x4020c200 +#define CONFIG_SYS_SYPCR 0xFFFFFFC3 +#define CONFIG_SYS_BCR 0x10000000 +#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CONFIG_SYS_RMR 0 + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CONFIG_SYS_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 8 bit FLASH + * 1 60x SDRAM 32 bit SDRAM + * 3 60x GPCM 8 bit GPIO/PIGGY + * 5 60x GPCM 16 bit CFG-Flash + * + */ +/* Bank 0 - FLASH + */ +#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV2 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX) + + +/* Bank 1 - 60x bus SDRAM + */ +#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ + +#define CONFIG_SYS_MPTPR 0x1800 + +/*----------------------------------------------------------------------------- + * Address for Mode Register Set (MRS) command + *----------------------------------------------------------------------------- + */ +#define CONFIG_SYS_MRS_OFFS 0x00000110 +#define CONFIG_SYS_PSRT 0x0e + +#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 + +/* SDRAM initialization values +*/ + +#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_8 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + +#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_5_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + +/* GPIO/PIGGY on CS3 initialization values +*/ +#define CONFIG_SYS_PIGGY_BASE 0x30000000 +#define CONFIG_SYS_PIGGY_SIZE 128 + +#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\ + BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\ + ORxG_CSNT | ORxG_ACS_DIV2 |\ + ORxG_SCY_3_CLK | ORxG_TRLX) + +/* Board FPGA on CS4 initialization values +*/ +#define CONFIG_SYS_FPGA_BASE 0x40000000 +#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ + +#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\ + BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) + +#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\ + ORxG_CSNT | ORxG_ACS_DIV2 |\ + ORxG_SCY_3_CLK | ORxG_TRLX) + +/* CFG-Flash on CS5 initialization values +*/ +#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ + BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) + +#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \ + CONFIG_SYS_FLASH_SIZE_2) |\ + ORxG_CSNT | ORxG_ACS_DIV2 |\ + ORxG_SCY_5_CLK | ORxG_TRLX) + +#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ + +/* pass open firmware flat tree */ +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" + +#endif /* __KM82XX_COMMON */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 455246a..54f80c3 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -35,78 +35,10 @@

#define CONFIG_SYS_TEXT_BASE 0xFE000000

-#define CONFIG_CPM2 1 /* Has a CPM2 */ - /* include common defines/options for all Keymile boards */ #include "keymile-common.h" #include "km-powerpc.h"

-/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ -#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ -#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ -#define CONFIG_NET_MULTI 1 - -#define CONFIG_ETHER_INDEX 4 -#define CONFIG_HAS_ETH0 -#define CONFIG_SYS_SCC_TOUT_LOOP 10000000 - -# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif - -#define BOOTFLASH_START 0xFE000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyCPM0" - -#define MTDIDS_DEFAULT "nor3=app" -#define MTDPARTS_DEFAULT "mtdparts=" \ - "app:" \ - "768k(u-boot)," \ - "128k(env)," \ - "128k(envred)," \ - "3072k(free)," \ - "-(" CONFIG_KM_UBI_PARTITION_NAME ")" - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - "EEprom_ivm=pca9544a:70:4 \0" \ - "unlock=yes\0" \ - "newenv=" \ - "prot off 0xFE0C0000 +0x40000 && " \ - "era 0xFE0C0000 +0x40000\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "" - #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE 0xFE000000 #define CONFIG_SYS_FLASH_SIZE 32 @@ -123,229 +55,9 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ CONFIG_SYS_FLASH_BASE_1, \ CONFIG_SYS_FLASH_BASE_2 } +#define MTDIDS_DEFAULT "nor3=app"

-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (768 << 10) - -#define CONFIG_ENV_IS_IN_FLASH - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ -#define CONFIG_ENV_BUFFER_PRINT - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave addr */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 -#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -#define CONFIG_SYS_IMMR 0xF0000000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CONFIG_SYS_HRCW_MASTER 0x0604b211 - -/* No slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -#define CONFIG_SYS_BOOTMAPSZ (8 << 20)/* Initial mem map for Linux */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SIUMCR 0x4020c200 -#define CONFIG_SYS_SYPCR 0xFFFFFFC3 -#define CONFIG_SYS_BCR 0x10000000 -#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 8 bit FLASH - * 1 60x SDRAM 32 bit SDRAM - * 3 60x GPCM 8 bit GPIO/PIGGY - * 5 60x GPCM 16 bit CFG-Flash - * - */ -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX ) - - -/* Bank 1 - 60x bus SDRAM - */ -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ - -#define CONFIG_SYS_MPTPR 0x1800 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 -#define CONFIG_SYS_PSRT 0x0e - -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 - -/* SDRAM initialization values -*/ - -#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_8 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* GPIO/PIGGY on CS3 initialization values -*/ -#define CONFIG_SYS_PIGGY_BASE 0x30000000 -#define CONFIG_SYS_PIGGY_SIZE 128 - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\ - BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_3_CLK | ORxG_TRLX ) - -/* Board FPGA on CS4 initialization values -*/ -#define CONFIG_SYS_FPGA_BASE 0x40000000 -#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ - -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\ - BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_3_CLK | ORxG_TRLX ) - -/* CFG-Flash on CS5 initialization values -*/ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ - BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \ - CONFIG_SYS_FLASH_SIZE_2) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK | ORxG_TRLX ) - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* pass open firmware flat tree */ -#define CONFIG_FIT -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP - -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" +/* include further common stuff for all keymile 82xx boards */ +#include "km82xx-common.h"

#endif /* __CONFIG_H */ diff --git a/include/configs/mgcoge2ne.h b/include/configs/mgcoge2ne.h new file mode 100644 index 0000000..8ace959 --- /dev/null +++ b/include/configs/mgcoge2ne.h @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2007-2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MGCOGE2NE +#define __MGCOGE2NE + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8247 1 +#define CONFIG_MPC8272_FAMILY 1 +#define CONFIG_MGCOGE 1 +#define CONFIG_HOSTNAME mgcoge2ne + +#define CONFIG_SYS_TEXT_BASE 0xFE000000 + +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" +#include "km-powerpc.h" + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0xFE000000 +#define CONFIG_SYS_FLASH_SIZE 32 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* + * max num of sects on one + * chip + */ + +#define CONFIG_SYS_FLASH_BASE_1 0x50000000 +#define CONFIG_SYS_FLASH_SIZE_1 64 +#define CONFIG_SYS_FLASH_SIZE_2 0 + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_FLASH_BASE_1 } + +#define MTDIDS_DEFAULT "nor2=app" + +/* include further common stuff for all keymile 82xx boards */ +#include "km82xx-common.h" + +#endif /* __MGCOGE2NE */

The Keymile SUPx5 board series is based on a PBEC8321 but contains an additional PBUS FPGA (LPXF) on local bus CS2.

Signed-off-by: Thomas Reufer thomas.reufer@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Wolfgang Denk wd@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Valentin Longchamp valentin.longchamp@keymile.com cc: Holger Brunck holger.brunck@keymile.com --- Changes for v2: - fix checkpatch.pl errors and warnings

MAINTAINERS | 1 + boards.cfg | 1 + include/configs/kmsupx5.h | 91 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 93 insertions(+), 0 deletions(-) create mode 100644 include/configs/kmsupx5.h

diff --git a/MAINTAINERS b/MAINTAINERS index e4525e4..730e306 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -427,6 +427,7 @@ Heiko Schocher hs@denx.de ids8247 MPC8247 jupiter MPC5200 kmeter1 MPC8360 + kmsupx5 MPC8321 mgcoge MPC8247 mgcoge2ne MPC8247 mgcoge2un ARM926EJS (Kirkwood SoC) diff --git a/boards.cfg b/boards.cfg index 3c45456..d1ec52e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -477,6 +477,7 @@ kmeter1 powerpc mpc83xx km83xx keymile MVBLM7 powerpc mpc83xx mvblm7 matrix_vision SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP +kmsupx5 powerpc mpc83xx km83xx keymile suvd3 powerpc mpc83xx km83xx keymile TQM834x powerpc mpc83xx tqm834x tqc tuda1 powerpc mpc83xx km83xx keymile diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h new file mode 100644 index 0000000..28cc41a --- /dev/null +++ b/include/configs/kmsupx5.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * + * (C) Copyright 2010-2011 + * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_KMSUPX5 1 /* Keymile PBEC8321 board specific */ +#define CONFIG_HOSTNAME supx5 +#define CONFIG_KM_BOARD_NAME "supx5" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 + +/* include common defines/options for all 8321 Keymile boards */ +#include "km8321-common.h" + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local GPCM 8 bit 256MB LPXF + * 3 Local not used + * + */ + +/* + * LPXF on the local bus CS2 + * Window base at flash base + * Window size: 256 MB + */ + +#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */ +#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */ + +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + (OR_GPCM_TRLX & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_EAD) + +/* LPXF: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +/* Bank 3 not used */ +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#endif /* __CONFIG_H */

These new values were given by Clive Stubbings from Xentech. According to him they should be used on all bobcat designs.

The changes are the following: - enables UART0 and UART1 pins in MPP - define some L2 cache settings - changes a SDRAM timing to better fit the hardware - removed three writes that were the same as the reset values

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Holger Brunck holger.brunck@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- Changes for v2: - nothing

board/keymile/km_arm/kwbimage.cfg | 32 ++++++++++++++++++-------------- 1 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg index 26d6aa0..b2f5193 100644 --- a/board/keymile/km_arm/kwbimage.cfg +++ b/board/keymile/km_arm/kwbimage.cfg @@ -27,16 +27,18 @@ # Boot Media configurations BOOT_FROM spi # Boot from SPI flash

-DATA 0xFFD10000 0x01111111 # MPP Control 0 Register -# bit 3-0: MPPSel0 1, NF_IO[2] -# bit 7-4: MPPSel1 1, NF_IO[3] -# bit 12-8: MPPSel2 1, NF_IO[4] -# bit 15-12: MPPSel3 1, NF_IO[5] +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: MPPSel0 2, NF_IO[2] +# bit 7-4: MPPSel1 2, NF_IO[3] +# bit 12-8: MPPSel2 2, NF_IO[4] +# bit 15-12: MPPSel3 2, NF_IO[5] # bit 19-16: MPPSel4 1, NF_IO[6] # bit 23-20: MPPSel5 1, NF_IO[7] # bit 27-24: MPPSel6 1, SYSRST_O # bit 31-28: MPPSel7 0, GPO[7]

+DATA 0xFFD10004 0x03303300 + DATA 0xFFD10008 0x00001100 # MPP Control 2 Register # bit 3-0: MPPSel16 0, GPIO[16] # bit 7-4: MPPSel17 0, GPIO[17] @@ -48,8 +50,8 @@ DATA 0xFFD10008 0x00001100 # MPP Control 2 Register # bit 31-28: MPPSel23 0, GPIO[23]

DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -DATA 0xFFD20134 0xBBBBBBBB # L2 RAM Timing 0 Register -DATA 0xFFD20138 0x00BBBBBB # L2 RAM Timing 1 Register +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register @@ -63,7 +65,7 @@ DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register # bit29-26: zero # bit31-30: 01

-DATA 0xFFD01404 0x36343000 # DDR Controller Control Low +DATA 0xFFD01404 0x39543000 # DDR Controller Control Low # bit 3-0: 0 reserved # bit 4: 0=addr/cmd in smame cycle # bit 5: 0=clk is driven during self refresh, we don't care for APX @@ -75,7 +77,7 @@ DATA 0xFFD01404 0x36343000 # DDR Controller Control Low # bit30-28: 3 required # bit31: 0=no additional STARTBURST delay

-DATA 0xFFD01408 0x2302544B # DDR Timing (Low) (active cycles value +1) +DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1) # bit3-0: TRAS lsbs # bit7-4: TRCD # bit11- 8: TRP @@ -86,7 +88,7 @@ DATA 0xFFD01408 0x2302544B # DDR Timing (Low) (active cycles value +1) # bit27-24: TRRD # bit31-28: TRTP

-DATA 0xFFD0140C 0x00000032 # DDR Timing (High) +DATA 0xFFD0140C 0x00000033 # DDR Timing (High) # bit6-0: TRFC # bit8-7: TR2R # bit10-9: TR2W @@ -116,8 +118,8 @@ DATA 0xFFD01418 0x00000000 # DDR Operation # bit3-0: 0x0, DDR cmd # bit31-4: 0 required

-DATA 0xFFD0141C 0x00000642 # DDR Mode -DATA 0xFFD01420 0x00000040 # DDR Extended Mode +DATA 0xFFD0141C 0x00000652 # DDR Mode +DATA 0xFFD01420 0x00000044 # DDR Extended Mode # bit0: 0, DDR DLL enabled # bit1: 0, DDR drive strenght normal # bit2: 1, DDR ODT control lsd disabled @@ -140,6 +142,8 @@ DATA 0xFFD01424 0x0000F07F # DDR Controller Control High # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh # bit15-12: 1111 required # bit31-16: 0 required +DATA 0xFFD01428 0x00074510 +DATA 0xFFD0147c 0x00007451

DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size @@ -153,7 +157,7 @@ DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled

-DATA 0xFFD01494 0x00000000 # DDR ODT Control (Low) +DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low) # bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0 # bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0

@@ -162,7 +166,7 @@ DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) # bit3-2: 00, ODT1 controlled by register # bit31-4: zero, required

-DATA 0xFFD0149C 0x0000E90F # CPU ODT Control +DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0 # bit9-8: 1, ODTEn, never active

This patch fix the i2c deblocking facility with the i2c HW-Controller. The required delays for byte reading, the enhanced criteria for stop the dummy read and required 5 start/stop sequences are added.

Add i2c deblocking before ivm eeprom read.

Improve i2c deblocking sequence by respecting stop hold time.

Cleaned function for deblocking. Have now one function i2c_make_abort() available for bitbang, mpc82xx and mpc83xx harware controller.

Signed-off-by: Stefan Bigler stefan.bigler@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - fix checkpatch.pl errors and warnings

board/keymile/common/common.c | 148 ++++++++++++++++++++++++++++------------- board/keymile/common/common.h | 6 +- 2 files changed, 105 insertions(+), 49 deletions(-)

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index e84c214..5bb18a8 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -325,6 +325,9 @@ int ivm_read_eeprom (void) if (buf != NULL) dev_addr = simple_strtoul ((char *)buf, NULL, 16);

+ /* add deblocking here */ + i2c_make_abort(); + if (i2c_read(dev_addr, 0, 1, i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN) != 0) { printf ("Error reading EEprom\n"); return -2; @@ -334,7 +337,7 @@ int ivm_read_eeprom (void) }

#if defined(CONFIG_SYS_I2C_INIT_BOARD) -#define DELAY_ABORT_SEQ 62 +#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */ #define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))

#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGCOGE2NE) @@ -426,16 +429,16 @@ static int get_scl (void) #endif

#if !defined(CONFIG_MPC83xx) -static void writeStartSeq (void) +void writeStartSeq(void) { - set_sda (1); - udelay (DELAY_HALF_PERIOD); - set_scl (1); - udelay (DELAY_HALF_PERIOD); - set_sda (0); - udelay (DELAY_HALF_PERIOD); - set_scl (0); - udelay (DELAY_HALF_PERIOD); + set_sda(1); + udelay(DELAY_HALF_PERIOD); + set_scl(1); + udelay(DELAY_HALF_PERIOD); + set_sda(0); + udelay(DELAY_HALF_PERIOD); + set_scl(0); + udelay(DELAY_HALF_PERIOD); }

/* I2C is a synchronous protocol and resets of the processor in the middle @@ -445,14 +448,27 @@ static void writeStartSeq (void) This I2C Deblocking mechanism was developed by Keymile in association with Anatech and Atmel in 1998. */ -static int i2c_make_abort (void) +int i2c_make_abort(void) { + +#if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD) + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; + volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; + + /* disable I2C controller first, otherwhise it thinks we want to */ + /* talk to the slave port... */ + i2c->i2c_i2mod &= ~0x01; + + /* Set the PortPins to GPIO */ + setports(1); +#endif + int scl_state = 0; int sda_state = 0; int i = 0; int ret = 0;

- if (!get_sda ()) { + if (!get_sda()) { ret = -1; while (i < 16) { i++; @@ -469,58 +485,96 @@ static int i2c_make_abort (void) } } if (ret == 0) { - for (i =0; i < 5; i++) { + for (i = 0; i < 5; i++) writeStartSeq (); - } } - get_sda (); + + /* respect stop setup time */ + udelay(DELAY_ABORT_SEQ); + set_scl(1); + udelay(DELAY_ABORT_SEQ); + set_sda(1); + get_sda(); + +#if defined(CONFIG_HARD_I2C) + /* Set the PortPins back to use for I2C */ + setports(0); +#endif return ret; } #endif

-/** - * i2c_init_board - reset i2c bus. When the board is powercycled during a - * bus transfer it might hang; for details see doc/I2C_Edge_Conditions. - */ -void i2c_init_board(void) -{ #if defined(CONFIG_MPC83xx) +void writeStartSeq(void) +{ struct fsl_i2c *dev; dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); - uchar dummy; + udelay(DELAY_ABORT_SEQ); + out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); + udelay(DELAY_ABORT_SEQ); + out_8(&dev->cr, (I2C_CR_MEN)); +}

- out_8 (&dev->cr, (I2C_CR_MSTA)); - out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); - dummy = in_8(&dev->dr); +int i2c_make_abort(void) +{ + struct fsl_i2c *dev; + dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); + uchar dummy; + uchar last; + int nbr_read = 0; + int i = 0; + int ret = 0; + + /* wait after each operation to finsh with a delay */ + out_8(&dev->cr, (I2C_CR_MSTA)); + udelay(DELAY_ABORT_SEQ); + out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); + udelay(DELAY_ABORT_SEQ); dummy = in_8(&dev->dr); - if (dummy != 0xff) { - dummy = in_8(&dev->dr); + udelay(DELAY_ABORT_SEQ); + last = in_8(&dev->dr); + nbr_read++; + + /* + * do read until the last bit is 1, but stop if the full eeprom is + * read. + */ + while (((last & 0x01) != 0x01) && + (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) { + udelay(DELAY_ABORT_SEQ); + last = in_8(&dev->dr); + nbr_read++; } - out_8 (&dev->cr, (I2C_CR_MEN)); - out_8 (&dev->cr, 0x00); - out_8 (&dev->cr, (I2C_CR_MEN)); - -#else -#if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD) - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; - volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; + if ((last & 0x01) != 0x01) + ret = -2; + if ((last != 0xff) || (nbr_read > 1)) + printf("[INFO] i2c abort after %d bytes (0x%02x)\n", + nbr_read, last); + udelay(DELAY_ABORT_SEQ); + out_8(&dev->cr, (I2C_CR_MEN)); + udelay(DELAY_ABORT_SEQ); + /* clear status reg */ + out_8(&dev->sr, 0); + + for (i = 0; i < 5; i++) + writeStartSeq(); + if (ret != 0) + printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n", + nbr_read, last);

- /* disable I2C controller first, otherwhise it thinks we want to */ - /* talk to the slave port... */ - i2c->i2c_i2mod &= ~0x01; + return ret; +}

- /* Set the PortPins to GPIO */ - setports (1); #endif

+/** + * i2c_init_board - reset i2c bus. When the board is powercycled during a + * bus transfer it might hang; for details see doc/I2C_Edge_Conditions. + */ +void i2c_init_board(void) +{ /* Now run the AbortSequence() */ - i2c_make_abort (); - -#if defined(CONFIG_HARD_I2C) - /* Set the PortPins back to use for I2C */ - setports (0); -#endif -#endif + i2c_make_abort(); } #endif #endif diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index a38c727..8fabe77 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -11,8 +11,10 @@ #ifndef __KEYMILE_COMMON_H #define __KEYMILE_COMMON_H

-int ethernet_present (void); -int ivm_read_eeprom (void); +int ethernet_present(void); +int ivm_read_eeprom(void); +void writeStartSeq(void); +int i2c_make_abort(void);

#ifdef CONFIG_KEYMILE_HDLC_ENET int keymile_hdlc_enet_initialize (bd_t *bis);

Normaly the PIGGY_MAC_ADRESS can be read directly from the IVM on keymile boards. On mgcoge3 it differs. Because there are two piggy boards deployed the second MAC adress must be calculated with the IVM mac adress and an offset. This patch allows to set such a offset in the board config.

Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Valentin Longchamp valentin.longchamp@keymile.com cc: Heiko Schocher hs@denx.de --- Changes for v2: - fix checkpatch.pl errors and warnings

board/keymile/common/common.c | 20 ++++++++++++++++++++ board/keymile/common/common.h | 3 +++ 2 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 5bb18a8..ecb9664 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -227,8 +227,28 @@ static int ivm_analyze_block2 (unsigned char *buf, int len) buf[5], buf[6]); ivm_set_value ("IVM_MacAddress", (char *)valbuf); + /* if an offset is defined, add it */ +#if defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET) + if (CONFIG_PIGGY_MAC_ADRESS_OFFSET > 0) { + unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6]; + + val += CONFIG_PIGGY_MAC_ADRESS_OFFSET; + buf[4] = (val >> 16) & 0xff; + buf[5] = (val >> 8) & 0xff; + buf[6] = val & 0xff; + + sprintf((char *)valbuf, "%02X:%02X:%02X:%02X:%02X:%02X", + buf[1], + buf[2], + buf[3], + buf[4], + buf[5], + buf[6]); + } +#endif if (getenv ("ethaddr") == NULL) setenv ((char *)"ethaddr", (char *)valbuf); + /* IVM_MacCount */ count = (buf[10] << 24) + (buf[11] << 16) + diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index 8fabe77..a2adf1d 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -11,6 +11,9 @@ #ifndef __KEYMILE_COMMON_H #define __KEYMILE_COMMON_H

+#if !defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET) +#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 0 +#endif int ethernet_present(void); int ivm_read_eeprom(void); void writeStartSeq(void);

From: Holger Brunck holger.brunck@keymile.com

Add: - introduce "bootrunner" environment variable This allows to execute consecutive different commands specified in the list "subbootcmd". If one command fails the command serie will stop. - introduce environment variable "develop", "ramfs" and "release" Each variable is one way to boot our linux. "develop" is for development purpose and boots the SW via NFS. "release" is for booting the linux image from flash, "ramfs" allows to load an SW image via tftp into ram and executes from there - introduce "addmem" variable, this command adds the used memory for linux to the bootargs - introduce "addvar" variable, this command adress for the /var directory to the kernel command line - introduce "setramfspram" and "setrootfsaddr" these calculation were done if "ramfs" was used (only for debugging) - introduce "tftpramfs" used for "ramfs" to load the image into RAM (only for debugging) Remove unneeded stuff: - CONFIG_IO_MUXING is obsolete for keymile boards - CONFIG_KM_DEF_ENV_PRIVATE is also obsolete - define CONFIG_SYS_TEXT_BASE in board configs only

Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Wolfgang Denk wd@denx.de cc: Prafulla Wadaskar prafulla@marvell.com cc: Valentin Longchamp valentin.longchamp@keymile.com cc: Heiko Schocher hs@denx.de --- Changes for v2: - fix checkpatch.pl errors and warnings

include/configs/keymile-common.h | 163 +++++++++++++++++++++++++++++++------ include/configs/km_arm.h | 2 + 2 files changed, 138 insertions(+), 27 deletions(-)

diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index e4699e2..6c6169b 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -40,13 +40,6 @@ #endif /* CONFIG_SYS_KWD_CONFIG */

/* - * CONFIG_SYS_TEXT_BASE can be defined in board specific header file, if needed - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x00400000 -#endif /* CONFIG_SYS_TEXT_BASE */ - -/* * Command line configuration. */ #include <config_cmd_default.h> @@ -144,28 +137,16 @@ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_CONCAT

-/* define this to use the keymile's io muxing feature */ -/*#define CONFIG_IO_MUXING */ - -#ifdef CONFIG_IO_MUXING -#define CONFIG_KM_DEF_ENV_IOMUX \ - "nc=setenv ethact HDLC \0" \ - "nce=setenv ethact SCC \0" \ - "stderr=serial,nc \0" \ - "stdin=serial,nc \0" \ - "stdout=serial,nc \0" \ - "tftpsrcp=69 \0" \ - "tftpdstp=69 \0" -#else #define CONFIG_KM_DEF_ENV_IOMUX \ "stderr=serial \0" \ "stdin=serial \0" \ "stdout=serial \0" -#endif

-#ifndef CONFIG_KM_DEF_ENV_PRIVATE -#define CONFIG_KM_DEF_ENV_PRIVATE \ - "kmprivate=empty\0" +/* common powerpc specific env settings */ +#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS +#define CONFIG_KM_DEF_ENV_BOOTPARAMS \ + "bootparams=empty\0" \ + "initial_boot_bank=0\0" #endif

#ifndef CONFIG_KM_DEF_NETDEV @@ -184,17 +165,116 @@ #define str(s) #s

/* + * bootrunner + * - run all commands in 'subbootcmds' + * - on error, stop running the remaing commands + */ +#define CONFIG_KM_DEF_ENV_BOOTRUNNER \ + "bootrunner=" \ + "break=0; " \ + "for subbootcmd in ${subbootcmds}; do " \ + "if test ${break} -eq 0; then; " \ + "echo "[INFO] running \c"; " \ + "print ${subbootcmd}; " \ + "run ${subbootcmd} || break=1; " \ + "if test ${break} -eq 1; then; " \ + "echo "[ERR] failed \c"; " \ + "print ${subbootcmd}; " \ + "fi; " \ + "fi; " \ + "done\0" \ + "" + +/* + * boottargets + * - set 'subbootcmds' for the bootrunner + * - set 'bootcmd' and 'altbootcmd' + * available targets: + * - 'release': for a standalone system kernel/rootfs from flash + * - 'develop': for development kernel(tftp)/rootfs(NFS) + * - 'ramfs': rootfilesystem in RAM kernel(tftp)/rootfs(RAM) + * + * - 'commonargs': bootargs common to all targets + */ +#define CONFIG_KM_DEF_ENV_BOOTTARGETS \ + "commonargs=" \ + "addip " \ + "addtty " \ + "addmem " \ + "addinit " \ + "addvar " \ + "addmtdparts " \ + "addbootcount " \ + "\0" \ + "develop=" \ + "setenv subbootcmds "" \ + "tftpfdt tftpkernel " \ + "nfsargs ${commonargs} " \ + "printbootargs boot " \ + "" && " \ + "setenv bootcmd '" \ + "run bootrunner" \ + "' && " \ + "setenv altbootcmd '" \ + "run bootcmd" \ + "' && " \ + "run setboardid && " \ + "saveenv && " \ + "reset\0" \ + "ramfs=" \ + "setenv actual_bank -1 && " \ + "setenv subbootcmds "" \ + "tftpfdt tftpkernel " \ + "setrootfsaddr tftpramfs " \ + "flashargs ${commonargs} " \ + "addpanic addramfs " \ + "printbootargs boot " \ + "" && " \ + "setenv bootcmd '" \ + "run bootrunner" \ + "' && " \ + "setenv altbootcmd '" \ + "run bootcmd" \ + "' && " \ + "run setboardid && " \ + "run setramfspram && " \ + "saveenv && " \ + "reset\0" \ + "release=" \ + "setenv actual_bank ${initial_boot_bank} && " \ + "setenv subbootcmds "" \ + "checkboardid " \ + "ubiattach ubicopy " \ + "cramfsloadfdt cramfsloadkernel " \ + "flashargs ${commonargs} " \ + "addpanic " \ + "printbootargs boot " \ + "" && " \ + "setenv bootcmd '" \ + "run bootrunner; reset" \ + "' && " \ + "setenv altbootcmd '" \ + "run actual0 bootcmd; reset" \ + "' && " \ + "saveenv && " \ + "reset\0" \ + "" + +/* * bootargs * - modify 'bootargs' * * - 'addip': add ip configuration + * - 'addmem': limit kernel memory mem= * - 'addpanic': add kernel panic options * - 'addramfs': add phram device for the rootfilesysten in ram * - 'addtty': add console=... + * - 'addvar': add phram device for /var * - 'nfsargs': default arguments for nfs boot * - 'flashargs': defaults arguments for flash base boot * * processor specific settings + * - 'addbootcount': add boot counter * - 'addmtdparts': add mtd partition information */ #define CONFIG_KM_DEF_ENV_BOOTARGS \ @@ -204,6 +284,8 @@ "setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off\0" \ + "addmem=" \ + "setenv bootargs ${bootargs} mem=0x${pnvramaddr}\0" \ "addpanic=" \ "setenv bootargs ${bootargs} " \ "panic=1 panic_on_oops=1\0" \ @@ -214,6 +296,9 @@ "addtty=" \ "setenv bootargs ${bootargs}" \ " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}\0" \ + "addvar=" \ + "setenv bootargs ${bootargs} phram.phram=phvar," \ + "${varaddr},0x" xstr(CONFIG_KM_PHRAM) "\0" \ "nfsargs=" \ "setenv bootargs " \ "ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \ @@ -226,6 +311,14 @@ "rootfstype=squashfs ro\0" \ ""

+/* + * compute_addr + * - compute addresses and sizes + * - addresses are calculated form the end of memory 'memsize' + * + * - 'setramfspram': compute PRAM size for ramfs target + * - 'setrootfsaddr': compute rootfilesystem address for phram + */ #define CONFIG_KM_DEF_ENV_COMPUTE_ADDR \ "setboardid=" \ "if test "x${boardId}" = "x"; then; " \ @@ -233,7 +326,15 @@ "setenv hwKey ${IVM_HWKey}; " \ "else; " \ "echo \\c; " \ - "fi\0" + "fi\0" \ + "setramfspram=" \ + "setexpr value ${rootfssize} / 0x400 && " \ + "setexpr value 0x${value} + ${pram} && " \ + "setenv pram 0x${value}\0" \ + "setrootfsaddr=" \ + "setexpr value ${pnvramaddr} - ${rootfssize} && " \ + "setenv rootfsaddr 0x${value}\0" \ + ""

/* * flash_boot @@ -264,6 +365,7 @@ * - commands for booting over the network * * - 'tftpkernel': load a kernel with tftp into ram + * - 'tftpramfs': load rootfs with tftp into ram * * processor specific settings * - 'tftpfdt': load fdt with tftp into ram @@ -271,7 +373,11 @@ #define CONFIG_KM_DEF_ENV_NET_BOOT \ "tftpkernel=" \ "tftpboot ${kernel_addr_r} ${kernel_file} && " \ - "setenv actual_kernel_addr ${kernel_addr_r} \0" + "setenv actual_kernel_addr ${kernel_addr_r}\0" \ + "tftpramfs=" \ + "tftpboot ${rootfsaddr} "\"${rootfsfile}\"" && " \ + "setenv loadaddr\0" \ + ""

/* * constants @@ -294,14 +400,17 @@

#ifndef CONFIG_KM_DEF_ENV #define CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ENV_BOOTPARAMS \ CONFIG_KM_DEF_ENV_IOMUX \ - CONFIG_KM_DEF_ENV_PRIVATE \ CONFIG_KM_DEF_NETDEV \ CONFIG_KM_DEF_ENV_CPU \ + CONFIG_KM_DEF_ENV_BOOTRUNNER \ + CONFIG_KM_DEF_ENV_BOOTTARGETS \ CONFIG_KM_DEF_ENV_BOOTARGS \ CONFIG_KM_DEF_ENV_COMPUTE_ADDR \ CONFIG_KM_DEF_ENV_FLASH_BOOT \ CONFIG_KM_DEF_ENV_NET_BOOT \ + CONFIG_KM_DEF_ENV_CONSTANTS \ "altbootcmd=run bootcmd\0" \ "bootcmd=run default\0" \ "bootlimit=2\0" \ diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index f009059..0672801 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -256,5 +256,7 @@ int get_scl (void); /* resereved pram area at the end of memroy [hex] */ /* 8Mbytes for switch + 4Kbytes for bootcount */ #define CONFIG_KM_RESERVED_PRAM 0x801000 +/* address for the bootcount (taken from end of RAM) */ +#define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM)

#endif /* _CONFIG_KM_ARM_H */

From: Holger Brunck holger.brunck@keymile.com

Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Wolfgang Denk wd@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com cc: Heiko Schocher hs@denx.de --- Changes for v2: - fix checkpatch.pl errors and warnings

include/configs/keymile-common.h | 9 +++------ 1 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 4597ee9..5b54c80 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -137,11 +137,6 @@ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_CONCAT

-#define CONFIG_KM_DEF_ENV_IOMUX \ - "stderr=serial \0" \ - "stdin=serial \0" \ - "stdout=serial \0" - /* common powerpc specific env settings */ #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS #define CONFIG_KM_DEF_ENV_BOOTPARAMS \ @@ -428,7 +423,6 @@ #ifndef CONFIG_KM_DEF_ENV #define CONFIG_KM_DEF_ENV \ CONFIG_KM_DEF_ENV_BOOTPARAMS \ - CONFIG_KM_DEF_ENV_IOMUX \ CONFIG_KM_DEF_NETDEV \ CONFIG_KM_DEF_ENV_CPU \ CONFIG_KM_DEF_ENV_BOOTRUNNER \ @@ -448,6 +442,9 @@ "load=tftpboot ${u-boot_addr_r} ${u-boot}\0" \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "u-boot_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \ ""

Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Holger Brunck holger.brunck@keymile.com cc: Wolfgang Denk wd@denx.de cc: Detlev Zundel dzu@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v3: - new patch in v3, to avoid externs in keymile code

include/mpc83xx.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/include/mpc83xx.h b/include/mpc83xx.h index ea137c7..e1b0929 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1274,6 +1274,12 @@ struct pci_region; void mpc83xx_pci_init(int num_buses, struct pci_region **reg); void mpc83xx_pcislave_unlock(int bus); void mpc83xx_pcie_init(int num_buses, struct pci_region **reg); + +void disable_addr_trans(void); +void enable_addr_trans(void); +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +void ddr_enable_ecc(unsigned int dram_size); +#endif #endif

#endif /* __MPC83XX_H__ */

Hello Kim,

Kim Phillips wrote:

On Mon, 21 Mar 2011 08:01:57 +0100 Heiko Schocher hs@denx.de wrote:

...

Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Holger Brunck holger.brunck@keymile.com cc: Wolfgang Denk wd@denx.de cc: Detlev Zundel dzu@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com

---

Hi Heiko, sorry for the late review, but I must admit it doesn't help the reviewer at all when later patches in a patchseries modify things added by earlier patches in the same patchseries!

Sorry for that, I know, it is a big patchset ...

...

include/mpc83xx.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/include/mpc83xx.h b/include/mpc83xx.h index ea137c7..e1b0929 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1274,6 +1274,12 @@ struct pci_region; void mpc83xx_pci_init(int num_buses, struct pci_region **reg); void mpc83xx_pcislave_unlock(int bus); void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);

+void disable_addr_trans(void); +void enable_addr_trans(void); +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +void ddr_enable_ecc(unsigned int dram_size); +#endif

I don't believe these prototypes belong in mpc83xx.h - they're really not 83xx-specific - e.g., 74xx and 85xx have identical names for functions that have the same...function.

Looking around I think the best place for them would be the 'start.S' section of include/common.h. Feel free to protect with 83xx ifdefs; others can add their platforms as necessary.

Hmm.. I thought of this too, but that will result in adding ifdefs. (and special this file has a lot of ifdefs, so I wanted to prevent another ifdef mess...). But I can of course move it to include/common.h if thats the preferred place ... ?

bye, Heiko

From: Holger Brunck holger.brunck@keymile.com

The MACH_TYPE SUEN3 is now to specific for keymile boards, because other boards similar to suen3 will follow. So the MACH_SUEN3 was renamed to MACH_KM_KIRKWOOD.

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Wolfgang Denk wd@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

board/keymile/common/common.c | 4 ++-- board/keymile/km_arm/km_arm.c | 2 +- include/configs/km_arm.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 7b4eefd..86be9c2 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -500,7 +500,7 @@ void i2c_init_board(void) out_8 (&dev->cr, (I2C_CR_MEN));

#else -#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_MACH_SUEN3) +#if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;

@@ -578,7 +578,7 @@ int fdt_get_node_and_value (void *blob, } #endif

-#if !defined(CONFIG_MACH_SUEN3) +#if !defined(MACH_TYPE_KM_KIRKWOOD) int ethernet_present (void) { return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80); diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 2e20644..5c1e822 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -180,7 +180,7 @@ int board_init(void) /* * arch number of board */ - gd->bd->bi_arch_number = MACH_TYPE_SUEN3; + gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;

/* address of boot parameters */ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index bf77cc0..533da73 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -38,7 +38,7 @@ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KIRKWOOD /* SOC Family Name */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_MACH_SUEN3 /* Machine type */ +#define CONFIG_MACH_KM_KIRKWOOD /* Machine type */

/* include common defines/options for all Keymile boards */ #include "keymile-common.h"

From: Holger Brunck holger.brunck@keymile.com

- adapt copyright string - change bootdelay to 2 seconds - set max number of command args to 32 - set I/O buffer size to 512

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Wolfgang Denk wd@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - new patch in v2, first patch in v1 was split up - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

include/configs/keymile-common.h | 13 ++++--------- include/configs/kmeter1.h | 4 ++-- include/configs/mgcoge.h | 7 +++---- 3 files changed, 9 insertions(+), 15 deletions(-)

diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index b934620..6f37f53 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -27,8 +27,6 @@ /* Do boardspecific init for all boards */ #define CONFIG_BOARD_EARLY_INIT_R

-#define CONFIG_BOOTCOUNT_LIMIT - /* * By default kwbimage.cfg from board specific folder is used * If for some board, different configuration file need to be used, @@ -56,16 +54,15 @@ #define CONFIG_CMD_IMMAP #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#define CONFIG_CMD_DTT #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C #define CONFIG_CMD_JFFS2 -#define CONFIG_JFFS2_CMDLINE #define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_SETEXPR

#undef CONFIG_WATCHDOG /* disable platform specific watchdog */

-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */

/* @@ -78,10 +75,10 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #endif #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE @@ -139,8 +136,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME

-#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */ - #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)

/* UBI Support for all Keymile boards */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index f288cb0..15042b9 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -8,7 +8,7 @@ * Copyright (C) 2007 MontaVista Software, Inc. * Anton Vorontsov avorontsov@ru.mvista.com * - * (C) Copyright 2008 + * (C) Copyright 2008-2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * This program is free software; you can redistribute it and/or @@ -171,7 +171,7 @@ #undef CONFIG_SYS_RAMBOOT #endif

-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve for Mon */

/* * Initial RAM Base Address Setup diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 3a987ad..662d885 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * See file CREDITS for list of people who contributed to this @@ -78,8 +78,7 @@ #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #endif

-#define BOOTFLASH_START FE000000 -#define CONFIG_PRAM 512 /* protected RAM [KBytes] */ +#define BOOTFLASH_START 0xFE000000

#define MTDIDS_DEFAULT "nor0=boot,nor1=app" #define MTDPARTS_DEFAULT \ @@ -128,7 +127,7 @@ #define CONFIG_SYS_RAMBOOT #endif

-#define CONFIG_SYS_MONITOR_LEN (384 << 10) +#define CONFIG_SYS_MONITOR_LEN (768 << 10)

#define CONFIG_ENV_IS_IN_FLASH

- serial console on UART1 - Ethernet RMII over UCC4 - PHY SMSC LAN8700 - 64MB Flash - 128 MB DDR2 RAM - I2C - bootcount

This board is similiar to the kmeter1 (8360) board, so common config options are extracted into the include/configs/km83xx-common.h file.

Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Holger Brunck holger.brunck@keymile.com cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

MAINTAINERS | 1 + arch/powerpc/cpu/mpc83xx/fdt.c | 3 +- arch/powerpc/lib/bootcount.c | 2 +- board/keymile/common/common.c | 10 +- board/keymile/{kmeter1 => km83xx}/Makefile | 0 .../keymile/{kmeter1/kmeter1.c => km83xx/km83xx.c} | 94 +++++- boards.cfg | 3 +- include/configs/km83xx-common.h | 324 +++++++++++++++++++ include/configs/kmeter1.h | 333 +------------------- include/configs/suvd3.h | 215 +++++++++++++ 10 files changed, 642 insertions(+), 343 deletions(-) rename board/keymile/{kmeter1 => km83xx}/Makefile (100%) rename board/keymile/{kmeter1/kmeter1.c => km83xx/km83xx.c} (67%) create mode 100644 include/configs/km83xx-common.h create mode 100644 include/configs/suvd3.h

diff --git a/MAINTAINERS b/MAINTAINERS index 4756f14..75b7343 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -433,6 +433,7 @@ Heiko Schocher hs@denx.de municse MPC5200 sc3 PPC405GP suen3 ARM926EJS (Kirkwood SoC) + suvd3 MPC8321 uc101 MPC5200 ve8313 MPC8313

diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index daf73a6..fe40214 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -32,7 +32,8 @@ extern void ft_qe_setup(void *blob);

DECLARE_GLOBAL_DATA_PTR;

-#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360) +#if defined(CONFIG_BOOTCOUNT_LIMIT) && \ + (defined(CONFIG_MPC832x) || defined(CONFIG_MPC8360)) #include <asm/immap_qe.h>

void fdt_fixup_muram (void *blob) diff --git a/arch/powerpc/lib/bootcount.c b/arch/powerpc/lib/bootcount.c index 07ef28d..ff8d89c 100644 --- a/arch/powerpc/lib/bootcount.c +++ b/arch/powerpc/lib/bootcount.c @@ -51,7 +51,7 @@ #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR) #endif /* defined(CONFIG_MPC8260) */

-#if defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC832x) || defined(CONFIG_MPC8360) #include <asm/immap_qe.h>

#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \ diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index ea32028..85538d0 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -29,6 +29,7 @@ #include <malloc.h> #include <hush.h> #include <net.h> +#include <netdev.h> #include <asm/io.h>

#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) @@ -402,7 +403,7 @@ static void setports(int gpio) #endif #endif

-#if !defined(CONFIG_KMETER1) +#if !defined(CONFIG_MPC83xx) static void writeStartSeq(void) { set_sda(1); @@ -461,7 +462,7 @@ static int i2c_make_abort(void) */ void i2c_init_board(void) { -#if defined(CONFIG_KMETER1) +#if defined(CONFIG_MPC83xx) struct fsl_i2c *dev; dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); uchar dummy; @@ -573,6 +574,7 @@ int board_eth_init(bd_t *bis) (void)keymile_hdlc_enet_initialize(bis); #endif if (ethernet_present()) - return -1; - return 0; + return cpu_eth_init(bis); + + return -1; } diff --git a/board/keymile/kmeter1/Makefile b/board/keymile/km83xx/Makefile similarity index 100% rename from board/keymile/kmeter1/Makefile rename to board/keymile/km83xx/Makefile diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/km83xx/km83xx.c similarity index 67% rename from board/keymile/kmeter1/kmeter1.c rename to board/keymile/km83xx/km83xx.c index bfc9174..0911950 100644 --- a/board/keymile/kmeter1/kmeter1.c +++ b/board/keymile/km83xx/km83xx.c @@ -8,7 +8,7 @@ * Copyright (C) 2007 MontaVista Software, Inc. * Anton Vorontsov avorontsov@ru.mvista.com * - * (C) Copyright 2008 + * (C) Copyright 2008 - 2010 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * This program is free software; you can redistribute it and/or @@ -32,7 +32,7 @@

const qe_iop_conf_t qe_iop_conf_tab[] = { /* port pin dir open_drain assign */ - +#if defined(CONFIG_KMETER1) /* MDIO */ {0, 1, 3, 0, 2}, /* MDIO */ {0, 2, 1, 0, 1}, /* MDC */ @@ -55,6 +55,40 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {5, 2, 1, 0, 1}, /* UART2_RTS */ {5, 3, 2, 0, 2}, /* UART2_SIN */ {5, 1, 2, 0, 3}, /* UART2_CTS */ +#else + /* Local Bus */ + {0, 16, 1, 0, 3}, /* LA00 */ + {0, 17, 1, 0, 3}, /* LA01 */ + {0, 18, 1, 0, 3}, /* LA02 */ + {0, 19, 1, 0, 3}, /* LA03 */ + {0, 20, 1, 0, 3}, /* LA04 */ + {0, 21, 1, 0, 3}, /* LA05 */ + {0, 22, 1, 0, 3}, /* LA06 */ + {0, 23, 1, 0, 3}, /* LA07 */ + {0, 24, 1, 0, 3}, /* LA08 */ + {0, 25, 1, 0, 3}, /* LA09 */ + {0, 26, 1, 0, 3}, /* LA10 */ + {0, 27, 1, 0, 3}, /* LA11 */ + {0, 28, 1, 0, 3}, /* LA12 */ + {0, 29, 1, 0, 3}, /* LA13 */ + {0, 30, 1, 0, 3}, /* LA14 */ + {0, 31, 1, 0, 3}, /* LA15 */ + + /* MDIO */ + {3, 4, 3, 0, 2}, /* MDIO */ + {3, 5, 1, 0, 2}, /* MDC */ + + /* UCC4 - UEC */ + {1, 18, 1, 0, 1}, /* TxD0 */ + {1, 19, 1, 0, 1}, /* TxD1 */ + {1, 22, 2, 0, 1}, /* RxD0 */ + {1, 23, 2, 0, 1}, /* RxD1 */ + {1, 26, 2, 0, 1}, /* RxER */ + {1, 28, 2, 0, 1}, /* Rx_DV */ + {1, 30, 1, 0, 1}, /* TxEN */ + {1, 31, 2, 0, 1}, /* CRS */ + {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */ +#endif

/* END of table */ {0, 0, 0, 0, QE_IOP_TAB_END}, @@ -77,11 +111,38 @@ static int board_init_i2c_busses(void) return 0; }

+#if defined(CONFIG_SUVD3) +const uint upma_table[] = { + 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */ + 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */ + 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */ + 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */ +}; +#endif + int board_early_init_r(void) { struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE; - unsigned short svid; +#if defined(CONFIG_SUVD3) + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + fsl_lbc_t *lbc = &immap->im_lbc; + u32 *mxmr = &lbc->mamr; +#endif

+#if defined(CONFIG_MPC8360) + unsigned short svid; /* * Because of errata in the UCCs, we have to write to the reserved * registers to slow the clocks down. @@ -105,13 +166,19 @@ int board_early_init_r(void) 0x00000050, 0x000000a0); break; } +#endif + /* enable the PHY on the PIGGY */ setbits_8(&base->pgy_out, 0x01); /* enable the Unit LED (green) */ setbits_8(&base->oprth, WRL_BOOT); - /* take FE/GbE PHYs out of reset */ - setbits_8(&base->prst, 0x1c);

+#if defined(CONFIG_SUVD3) + /* configure UPMA for APP1 */ + upmconfig(UPMA, (uint *) upma_table, + sizeof(upma_table) / sizeof(uint)); + out_be32(mxmr, CONFIG_SYS_MAMR); +#endif return 0; }

@@ -185,12 +252,13 @@ phys_size_t initdram(int board_type) #endif

/* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); + return msize * 1024 * 1024; }

int checkboard(void) { - puts("Board: Keymile kmeter1"); + puts("Board: Keymile " CONFIG_KM_BOARD_NAME); + if (ethernet_present()) puts(" with PIGGY."); puts("\n"); @@ -198,19 +266,9 @@ int checkboard(void) }

#if defined(CONFIG_OF_BOARD_SETUP) -/* - * update property in the blob - */ -void ft_blob_update(void *blob, bd_t *bd) -{ - /* no board specific update */ -} - - void ft_board_setup(void *blob, bd_t *bd) { - ft_cpu_setup (blob, bd); - ft_blob_update (blob, bd); + ft_cpu_setup(blob, bd); } #endif

diff --git a/boards.cfg b/boards.cfg index 45c3102..dc583ba 100644 --- a/boards.cfg +++ b/boards.cfg @@ -470,10 +470,11 @@ MPC8360ERDK_66 powerpc mpc83xx mpc8360erdk freesca MPC837XEMDS powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI MPC837XERDB powerpc mpc83xx mpc837xerdb freescale -kmeter1 powerpc mpc83xx kmeter1 keymile +kmeter1 powerpc mpc83xx km83xx keymile MVBLM7 powerpc mpc83xx mvblm7 matrix_vision SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP +suvd3 powerpc mpc83xx km83xx keymile TQM834x powerpc mpc83xx tqm834x tqc sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 diff --git a/include/configs/km83xx-common.h b/include/configs/km83xx-common.h new file mode 100644 index 0000000..8cfb854 --- /dev/null +++ b/include/configs/km83xx-common.h @@ -0,0 +1,324 @@ +/* + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_KM83XX_H +#define __CONFIG_KM83XX_H + +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" +#include "km-powerpc.h" + +#define MTDIDS_DEFAULT "nor0=boot" +#define MTDPARTS_DEFAULT "mtdparts=" \ + "boot:" \ + "768k(u-boot)," \ + "128k(env)," \ + "128k(envred)," \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")" + +#define CONFIG_MISC_INIT_R +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ + (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_FSL_I2C +#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 +#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE +#endif + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ROOTPATH +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ROOTPATH \ + "dtt_bus=pca9547:70:a\0" \ + "EEprom_ivm=pca9547:70:9\0" \ + "newenv=" \ + "prot off 0xF00C0000 +0x40000 && " \ + "era 0xF00C0000 +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + +#endif /* __CONFIG_KM83XX_H */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2fbc774..1dcd274 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -27,30 +27,21 @@ #define CONFIG_MPC8360 /* MPC8360 CPU specific */ #define CONFIG_KMETER1 /* KMETER1 board specific */ #define CONFIG_HOSTNAME kmeter1 +#define CONFIG_KM_BOARD_NAME "kmeter1"

#define CONFIG_SYS_TEXT_BASE 0xF0000000 #define CONFIG_KM_DEF_NETDEV \ "netdev=eth2\0" \

-/* include common defines/options for all Keymile boards */ -#include "keymile-common.h" -#include "km-powerpc.h" - -#define MTDIDS_DEFAULT "nor0=boot" -#define MTDPARTS_DEFAULT "mtdparts=" \ - "boot:" \ - "768k(u-boot)," \ - "128k(env)," \ - "128k(envred)," \ - "-(" CONFIG_KM_UBI_PARTITION_NAME ")" +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h"

#define CONFIG_MISC_INIT_R /* - * System Clock Setup + * System IO Setup */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 +#define CONFIG_SYS_SICRH 0x00000006 +#define CONFIG_SYS_SICRL 0x00000000

/* * Hardware Reset Configuration Word @@ -71,55 +62,7 @@ HRCWH_LALE_EARLY | \ HRCWH_LDP_CLEAR )

-/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000006 -#define CONFIG_SYS_SICRL 0x00000000 - -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -#undef CONFIG_DDR_ECC - -/* - * DDRCDR - DDR Control Driver Register - */ - -#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10 | \ - CSCONFIG_ODT_WR_ACS) - #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_SREN) #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 @@ -127,6 +70,11 @@ #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))

+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10 | \ + CSCONFIG_ODT_WR_ACS) + #define CONFIG_SYS_DDRCDR 0x40000001 #define CONFIG_SYS_DDR_MODE 0x47860452 #define CONFIG_SYS_DDR_MODE2 0x8080c000 @@ -159,32 +107,13 @@

#define CONFIG_SYS_DDR_TIMING_3 0x00000000

-/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 #define CONFIG_SYS_PIGGY_BASE 0xE8000000 #define CONFIG_SYS_PIGGY_SIZE 128 #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 512

-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve for Mon */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

/* * Local Bus Configuration & Clock Setup @@ -198,52 +127,9 @@ * * Bank Bus Machine PortSz Size Device * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY * 3 Local GPCM 8 bit 512MB PAXE * */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX | OR_GPCM_EAD) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -/* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * PRIO1/PIGGY on the local bus CS1 - */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ - (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX | OR_GPCM_EAD)

/* * PAXE on the local bus CS3 @@ -260,176 +146,14 @@ OR_GPCM_TRLX | OR_GPCM_EAD)

/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#undef CONFIG_PCI /* No PCI */ - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI -#endif -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_RAMBOOT */ -#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ -#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_RAMBOOT */ - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_FSL_I2C -#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_I2C_MUX 1 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 -#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE -#endif - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -#if defined(CFG_RAMBOOT) -#undef CONFIG_CMD_SAVEENV -#undef CONFIG_CMD_LOADS -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* * MMU Setup */

-#define CONFIG_HIGH_BATS /* High BATs supported */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* PAXE: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ - BATL_MEMCOHERENCE) + BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U @@ -457,31 +181,4 @@ #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #endif /* CONFIG_PCI */

-#define BOOTFLASH_START F0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - "dtt_bus=pca9547:70:a\0" \ - "EEprom_ivm=pca9547:70:9\0" \ - "newenv=" \ - "prot off 0xF00C0000 +0x40000 && " \ - "era 0xF00C0000 +0x40000\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h new file mode 100644 index 0000000..ca444c2 --- /dev/null +++ b/include/configs/suvd3.h @@ -0,0 +1,215 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_MPC832x /* MPC832x CPU specific */ +#define CONFIG_SUVD3 /* SUVD3 board specific */ +#define CONFIG_HOSTNAME suvd3 +#define CONFIG_KM_BOARD_NAME "suvd3" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" + +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +#define CONFIG_MISC_INIT_R 1 + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x00000006 +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN) +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860252 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (2 << TIMING_CFG1_WRREC_SHIFT) | \ + (6 << TIMING_CFG1_REFREC_SHIFT) | \ + (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_PIGGY_BASE 0xE8000000 +#define CONFIG_SYS_PIGGY_SIZE 128 +#define CONFIG_SYS_APP1_BASE 0xA0000000 +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local UPMA 16 bit 256MB APP1 + * 3 Local GPCM 16 bit 256MB APP2 + * + */ + +/* + * APP1 on the local bus CS2 + */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_16 | \ + BR_MS_UPMA | \ + BR_V) +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_16 | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_3 | \ + OR_GPCM_TRLX) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +/* + * MMU Setup + */ + + +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else /* CONFIG_PCI */ + +/* APP2: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif /* CONFIG_PCI */ + +#endif /* __CONFIG_H */

Hello Kim,

Kim Phillips wrote:

On Mon, 21 Mar 2011 08:02:02 +0100 Heiko Schocher hs@denx.de wrote:

...

+++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -32,7 +32,8 @@ extern void ft_qe_setup(void *blob);

DECLARE_GLOBAL_DATA_PTR;

-#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360) +#if defined(CONFIG_BOOTCOUNT_LIMIT) && \

• (defined(CONFIG_MPC832x) || defined(CONFIG_MPC8360))

please replace 832x and 8360 with just CONFIG_QE

Ok.

...

+++ b/arch/powerpc/lib/bootcount.c @@ -51,7 +51,7 @@ #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR) #endif /* defined(CONFIG_MPC8260) */

-#if defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC832x) || defined(CONFIG_MPC8360)

same here

Ok.

...

diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 +#define CONFIG_SYS_SICRH 0x00000006

I realize this was a pre-existing condition, but please make this (SICRH_UC1EOBI | SICRH_UC2E1OBI) instead of 6.

Ok.

...

+#define CONFIG_SYS_SICRL 0x00000000

nit-pick, but fyi, one can save a raw write here by not defining it at all.

removed.

...

/* PAXE: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \

• 		BATL_MEMCOHERENCE)
  

• 			BATL_MEMCOHERENCE)
  

B in BATL_ should be aligned to fall directly under the C in CONFIG_SYS_PAXE_BASE, like this:

#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ BATL_MEMCOHERENCE)

Ok.

...

#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \

• 		BATU_VS | BATU_VP)
  

• 			BATU_VS | BATU_VP)
  

same here, just as the next one is already:

Ok.

...

#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)

<snip> > diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h <snip> > +#define CONFIG_SYS_SICRH 0x00000006

afaict, SICRH doesn't documentally exist on 832x, so omit this line. This comment also applies to the following patches in this series:

Ok.

[PATCH v3 07/23] mpc832x: add support for mpc8321 based tuxa1 board [PATCH v3 08/23] mpc832x: add support for mpc8321 based tuda1 board [PATCH v3 12/23] keymile, 8321 boards: move common definitions to km8321-common.h

even though the 12/23 patch seems to be a refactoring of the definition added by the others...<sigh>.

The rest of the 83xx-touching patches in the series look good to me.

Thanks for reviewing.

bye Heiko

This board is similar to suvd3 board. So most initialisation topics are taken from suvd3 (UART1, Ethernet, piggy PHY, flash, ram) only the application specific chip selects differ.

Signed-off-by: Lukas Roggli lukas.roggli@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Valentin Longchamp valentin.longchamp@keymile.com --- changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

MAINTAINERS | 1 + boards.cfg | 1 + include/configs/tuda1.h | 249 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 251 insertions(+), 0 deletions(-) create mode 100644 include/configs/tuda1.h

diff --git a/MAINTAINERS b/MAINTAINERS index 801e4dd..cbc34af 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -434,6 +434,7 @@ Heiko Schocher hs@denx.de sc3 PPC405GP suen3 ARM926EJS (Kirkwood SoC) suvd3 MPC8321 + tuda1 MPC8321 tuxa1 MPC8321 uc101 MPC5200 ve8313 MPC8313 diff --git a/boards.cfg b/boards.cfg index ed5e0e7..b3a4e9e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -476,6 +476,7 @@ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP suvd3 powerpc mpc83xx km83xx keymile TQM834x powerpc mpc83xx tqm834x tqc +tuda1 powerpc mpc83xx km83xx keymile tuxa1 powerpc mpc83xx km83xx keymile sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h new file mode 100644 index 0000000..a50a87d --- /dev/null +++ b/include/configs/tuda1.h @@ -0,0 +1,249 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2011 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_MPC832x /* MPC832x CPU specific */ +#define CONFIG_TUDA1 /* TUDA1 board specific */ +#define CONFIG_HOSTNAME tuda1 +#define CONFIG_KM_BOARD_NAME "tuda1" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" + +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +#define CONFIG_MISC_INIT_R + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x00000006 +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_2T_EN | \ + SDRAM_CFG_SREN) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860252 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (2 << TIMING_CFG1_WRREC_SHIFT) | \ + (6 << TIMING_CFG1_REFREC_SHIFT) | \ + (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + + +#define CONFIG_SYS_PIGGY_BASE 0xE8000000 +#define CONFIG_SYS_PIGGY_SIZE 128 +#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local GPCM 8 bit 256MB PAXG + * 3 Local GPCM 8 bit 256MB PINC3 + * + */ + +/* + * PAXG on the local bus CS2 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + (OR_GPCM_TRLX & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_EAD) +/* + * PINC3 on the local bus CS3 + */ +/* Access window base at PINC3 base */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_CSNT | \ + (OR_GPCM_ACS_DIV2 & /* ACS = 11 */\ + (~OR_GPCM_XACS)) | /* XACS = 0 */\ + (OR_GPCM_SCY_2 & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_TRLX) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +/* + * MMU Setup + */ +/* PAXG: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_10 | \ + BATL_MEMCOHERENCE) +/* 512M should also include APP2... */ +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | \ + BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else /* CONFIG_PCI */ + +/* PINC3: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif /* CONFIG_PCI */ + +#endif /* __CONFIG_H */

The Kirwood based SUEN8 board from Keymile is at this stage the same than the suen3 board. This patch adds the board support for the suen8.

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Prafulla Wadaskar prafulla@marvell.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

MAINTAINERS | 1 + boards.cfg | 1 + include/configs/suen8.h | 63 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 65 insertions(+), 0 deletions(-) create mode 100644 include/configs/suen8.h

diff --git a/MAINTAINERS b/MAINTAINERS index 4e7a8f7..9644d38 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -434,6 +434,7 @@ Heiko Schocher hs@denx.de municse MPC5200 sc3 PPC405GP suen3 ARM926EJS (Kirkwood SoC) + suen8 ARM926EJS (Kirkwood SoC) suvd3 MPC8321 tuda1 MPC8321 tuxa1 MPC8321 diff --git a/boards.cfg b/boards.cfg index 1b45b5e..22cb509 100644 --- a/boards.cfg +++ b/boards.cfg @@ -94,6 +94,7 @@ davinci_schmoogie arm arm926ejs schmoogie davinci davinci_sffsdr arm arm926ejs sffsdr davinci davinci davinci_sonata arm arm926ejs sonata davinci davinci suen3 arm arm926ejs km_arm keymile kirkwood +suen8 arm arm926ejs km_arm keymile kirkwood mgcoge2un arm arm926ejs km_arm keymile kirkwood guruplug arm arm926ejs - Marvell kirkwood mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood diff --git a/include/configs/suen8.h b/include/configs/suen8.h new file mode 100644 index 0000000..cdda4af --- /dev/null +++ b/include/configs/suen8.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar prafulla@marvell.com + * + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2010-2011 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ + +#ifndef _CONFIG_SUEN8_H +#define _CONFIG_SUEN8_H + +/* include common defines/options for all arm based Keymile boards */ +#include "km_arm.h" + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nKeymile SUEN8" + +#define CONFIG_HOSTNAME suen8 + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + "memsize=0x8000000\0" \ + "newenv=setenv addr 0x100000 && " \ + "i2c dev 1; mw.b ${addr} 0 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ + "rootpath=/opt/eldk/arm\0" \ + "EEprom_ivm=pca9544a:70:9\0" \ + "" + +#endif /* _CONFIG_SUEN8_H */

From: Thomas Reufer thomas.reufer@keymile.com

First step for a cleanup of all header files for km8321 boards.

Signed-off-by: Thomas Reufer thomas.reufer@keymile.com cc: Wolfgang Denk wd@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Valentin Longchamp valentin.longchamp@keymile.com cc: Holger Brunck holger.brunck@keymile.com cc: Heiko Schocher hs@denx.de --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

include/configs/km8321-common.h | 141 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 141 insertions(+), 0 deletions(-) create mode 100644 include/configs/km8321-common.h

diff --git a/include/configs/km8321-common.h b/include/configs/km8321-common.h new file mode 100644 index 0000000..9e48388 --- /dev/null +++ b/include/configs/km8321-common.h @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * + * (C) Copyright 2010-2011 + * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_KM8321_COMMON_H +#define __CONFIG_KM8321_COMMON_H + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_MPC832x /* MPC832x CPU specific */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" + +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +#define CONFIG_MISC_INIT_R + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x00000006 +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860252 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (2 << TIMING_CFG1_WRREC_SHIFT) | \ + (6 << TIMING_CFG1_REFREC_SHIFT) | \ + (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_PIGGY_BASE 0xE8000000 +#define CONFIG_SYS_PIGGY_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_KM8321_COMMON_H */

This patch renames the suen3 defines and functions to KM_KIRKWOOD which is more generic and more precise, because these values and functions where used by all suenX boards and not only suen3.

Signed-off-by: Lukas Roggli lukas.roggli@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Prafulla Wadaskar prafulla@marvell.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

board/keymile/km_arm/km_arm.c | 20 ++++++++++---------- include/configs/km_arm.h | 18 +++++++++--------- 2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 9d0892d..9dafcef 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -95,7 +95,7 @@ u32 kwmpp_config[] = { MPP41_GPIO, /* Piggy3 LED[4] */ MPP42_GPIO, /* Piggy3 LED[5] */ MPP43_GPIO, /* Piggy3 LED[6] */ - MPP44_GPIO, /* Piggy3 LED[7] */ + MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ MPP45_GPIO, /* Piggy3 LED[8] */ MPP46_GPIO, /* Reserved */ MPP47_GPIO, /* Reserved */ @@ -161,14 +161,14 @@ int board_early_init_f(void)

#if defined(CONFIG_SOFT_I2C) /* init the GPIO for I2C Bitbang driver */ - kw_gpio_set_valid(SUEN3_SDA_PIN, 1); - kw_gpio_set_valid(SUEN3_SCL_PIN, 1); - kw_gpio_direction_output(SUEN3_SDA_PIN, 0); - kw_gpio_direction_output(SUEN3_SCL_PIN, 0); + kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); + kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); + kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0); + kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0); #endif #if defined(CONFIG_SYS_EEPROM_WREN) - kw_gpio_set_valid(SUEN3_ENV_WP, 38); - kw_gpio_direction_output(SUEN3_ENV_WP, 1); + kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); + kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); #endif

return 0; @@ -321,15 +321,15 @@ int get_sda(void)

int get_scl(void) { - return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0); + return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; } #endif

#if defined(CONFIG_SYS_EEPROM_WREN) int eeprom_write_enable(unsigned dev_addr, int state) { - kw_gpio_set_value(SUEN3_ENV_WP, !state); + kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);

- return !kw_gpio_get_value(SUEN3_ENV_WP); + return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); } #endif diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 2e38c12..5fa0153 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -179,15 +179,15 @@ void set_sda (int state); void set_scl (int state); int get_sda (void); int get_scl (void); -#define SUEN3_SDA_PIN 8 -#define SUEN3_SCL_PIN 9 -#define SUEN3_ENV_WP 38 - -#define I2C_ACTIVE __set_direction(SUEN3_SDA_PIN, 0) -#define I2C_TRISTATE __set_direction(SUEN3_SDA_PIN, 1) -#define I2C_READ (kw_gpio_get_value(SUEN3_SDA_PIN) ? 1 : 0) -#define I2C_SDA(bit) kw_gpio_set_value(SUEN3_SDA_PIN, bit); -#define I2C_SCL(bit) kw_gpio_set_value(SUEN3_SCL_PIN, bit); +#define KM_KIRKWOOD_SDA_PIN 8 +#define KM_KIRKWOOD_SCL_PIN 9 +#define KM_KIRKWOOD_ENV_WP 38 + +#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0) +#define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1) +#define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0) +#define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit) +#define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit) #endif

#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */

For the kmsupx5 a new header file was introduced km8321-common.h. Now the common stuff from tuxa1, tuda1 and suvd3 was removed and the new header file included.

The defines CONFIG_SYS_PIGGY_BASE and CONFIG_SYS_PIGGY_SIZE are confusing. Because they actually describe the KMBEC FPGA values. The KMBEC FPGA can be PRIO on kmeter1 or upio on mgcoge. Therefore all the defines were renamed.

remove unneeded variable CONFIG_KM_DEF_NETDEV, as it is already declared in keymile-common.h

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Wolfgang Denk wd@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

board/keymile/common/common.c | 3 +- board/keymile/km83xx/km83xx.c | 3 +- board/keymile/mgcoge/mgcoge.c | 3 +- include/configs/keymile-common.h | 2 +- include/configs/km82xx-common.h | 12 ++-- include/configs/km8321-common.h | 7 +-- include/configs/km83xx-common.h | 19 +++--- include/configs/kmeter1.h | 8 ++- include/configs/suvd3.h | 115 +------------------------------------- include/configs/tuda1.h | 112 +------------------------------------ include/configs/tuxa1.h | 114 +------------------------------------- 11 files changed, 36 insertions(+), 362 deletions(-)

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 8564b9c..2d0aee9 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -562,7 +562,8 @@ int fdt_get_node_and_value(void *blob, #if !defined(MACH_TYPE_KM_KIRKWOOD) int ethernet_present(void) { - struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE; + struct km_bec_fpga *base = + (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;

return in_8(&base->bprth) & PIGGY_PRESENT; } diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 0911950..d940a1e 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -134,7 +134,8 @@ const uint upma_table[] = {

int board_early_init_r(void) { - struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE; + struct km_bec_fpga *base = + (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; #if defined(CONFIG_SUVD3) immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; fsl_lbc_t *lbc = &immap->im_lbc; diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index e32ff98..a58256e 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -300,7 +300,8 @@ int checkboard(void) */ int board_early_init_r(void) { - struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE; + struct km_bec_fpga *base = + (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;

/* setup the UPIOx */ /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */ diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index e952a19..77e2090 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -102,7 +102,7 @@ * driver to set the MAC. */ #define CONFIG_CHECK_ETHERNET_PRESENT -#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_KMBEC_FPGA_BASE #define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ #define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */

diff --git a/include/configs/km82xx-common.h b/include/configs/km82xx-common.h index f0a5893..345212c 100644 --- a/include/configs/km82xx-common.h +++ b/include/configs/km82xx-common.h @@ -287,20 +287,20 @@ PSDMR_CL_2)

/* - * GPIO/PIGGY on CS3 initialization values + * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values */ -#define CONFIG_SYS_PIGGY_BASE 0x30000000 -#define CONFIG_SYS_PIGGY_SIZE 128 +#define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128

-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\ +#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\ BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)

-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\ +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\ ORxG_CSNT | ORxG_ACS_DIV2 |\ ORxG_SCY_3_CLK | ORxG_TRLX)

/* - * Board FPGA on CS4 initialization values + * BFTICU board FPGA on CS4 initialization values */ #define CONFIG_SYS_FPGA_BASE 0x40000000 #define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ diff --git a/include/configs/km8321-common.h b/include/configs/km8321-common.h index 9e48388..9458289 100644 --- a/include/configs/km8321-common.h +++ b/include/configs/km8321-common.h @@ -33,9 +33,6 @@ #define CONFIG_MPC832x /* MPC832x CPU specific */ #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */

-#define CONFIG_KM_DEF_NETDEV \ - "netdev=eth0\0" - #define CONFIG_KM_DEF_ROOTPATH \ "rootpath=/opt/eldk/ppc_8xx\0"

@@ -118,8 +115,8 @@

#define CONFIG_SYS_DDR_TIMING_3 0x00000000

-#define CONFIG_SYS_PIGGY_BASE 0xE8000000 -#define CONFIG_SYS_PIGGY_SIZE 128 +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128

/* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 diff --git a/include/configs/km83xx-common.h b/include/configs/km83xx-common.h index 8cfb854..6752c04 100644 --- a/include/configs/km83xx-common.h +++ b/include/configs/km83xx-common.h @@ -121,13 +121,14 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */

-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \ +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX | OR_GPCM_EAD) @@ -212,7 +213,7 @@ #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_KMETER1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE #endif

#if defined(CONFIG_PCI) @@ -257,11 +258,11 @@ #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U

/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U

diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 1dcd274..9504d62 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -107,9 +107,11 @@

#define CONFIG_SYS_DDR_TIMING_3 0x00000000

-#define CONFIG_SYS_PIGGY_BASE 0xE8000000 -#define CONFIG_SYS_PIGGY_SIZE 128 -#define CONFIG_SYS_PAXE_BASE 0xA0000000 +/* PRIO FPGA */ +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 +/* PAXE FPGA */ +#define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 512

/* EEprom support */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index ca444c2..055fd6a 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -23,99 +23,15 @@ /* * High Level Configuration Options */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_MPC832x /* MPC832x CPU specific */ #define CONFIG_SUVD3 /* SUVD3 board specific */ #define CONFIG_HOSTNAME suvd3 #define CONFIG_KM_BOARD_NAME "suvd3"

#define CONFIG_SYS_TEXT_BASE 0xF0000000 -#define CONFIG_KM_DEF_NETDEV \ - "netdev=eth0\0"

-#define CONFIG_KM_DEF_ROOTPATH \ - "rootpath=/opt/eldk/ppc_8xx\0" +/* include common defines/options for all 8321 Keymile boards */ +#include "km8321-common.h"

-/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" - -#define CONFIG_MISC_INIT_R 1 - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000006 -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN) -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860252 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (2 << TIMING_CFG1_WRREC_SHIFT) | \ - (6 << TIMING_CFG1_REFREC_SHIFT) | \ - (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (2 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_PIGGY_BASE 0xE8000000 -#define CONFIG_SYS_PIGGY_SIZE 128 #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 @@ -125,12 +41,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1

/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* * Init Local Bus Memory Controller: * * Bank Bus Machine PortSz Size Device @@ -183,21 +93,6 @@ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U

-#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT6L CFG_IBAT6L -#define CFG_DBAT6U CFG_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT7L CFG_IBAT7L -#define CFG_DBAT7U CFG_IBAT7U -#else /* CONFIG_PCI */ - -/* APP2: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ @@ -206,10 +101,4 @@ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U

-#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif /* CONFIG_PCI */ - #endif /* __CONFIG_H */ diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h index a50a87d..6b4c4cc 100644 --- a/include/configs/tuda1.h +++ b/include/configs/tuda1.h @@ -26,111 +26,20 @@ /* * High Level Configuration Options */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_MPC832x /* MPC832x CPU specific */ #define CONFIG_TUDA1 /* TUDA1 board specific */ #define CONFIG_HOSTNAME tuda1 #define CONFIG_KM_BOARD_NAME "tuda1"

#define CONFIG_SYS_TEXT_BASE 0xF0000000 -#define CONFIG_KM_DEF_NETDEV \ - "netdev=eth0\0"

-#define CONFIG_KM_DEF_ROOTPATH \ - "rootpath=/opt/eldk/ppc_8xx\0" +/* include common defines/options for all 8321 Keymile boards */ +#include "km8321-common.h"

-/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" - -#define CONFIG_MISC_INIT_R - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000006 -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_2T_EN | \ - SDRAM_CFG_SREN) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860252 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (2 << TIMING_CFG1_WRREC_SHIFT) | \ - (6 << TIMING_CFG1_REFREC_SHIFT) | \ - (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (2 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - - -#define CONFIG_SYS_PIGGY_BASE 0xE8000000 -#define CONFIG_SYS_PIGGY_SIZE 128 #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */

- -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - /* * Local Bus Configuration & Clock Setup */ @@ -210,22 +119,6 @@ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U

-#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT6L CFG_IBAT6L -#define CFG_DBAT6U CFG_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | \ - BATL_PP_10 | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT7L CFG_IBAT7L -#define CFG_DBAT7U CFG_IBAT7U -#else /* CONFIG_PCI */ - /* PINC3: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ BATL_PP_10 | \ @@ -244,6 +137,5 @@ #define CONFIG_SYS_IBAT7U (0) #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif /* CONFIG_PCI */

#endif /* __CONFIG_H */ diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h index c4b48d1..724d92e 100644 --- a/include/configs/tuxa1.h +++ b/include/configs/tuxa1.h @@ -26,115 +26,20 @@ /* * High Level Configuration Options */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_MPC832x /* MPC832x CPU specific */ #define CONFIG_TUXA1 /* TUXA1 board specific */ #define CONFIG_HOSTNAME tuxa1 #define CONFIG_KM_BOARD_NAME "tuxa1"

#define CONFIG_SYS_TEXT_BASE 0xF0000000 -#define CONFIG_KM_DEF_NETDEV \ - "netdev=eth0\0"

-#define CONFIG_KM_DEF_ROOTPATH \ - "rootpath=/opt/eldk/ppc_8xx\0" +/* include common defines/options for all 8321 Keymile boards */ +#include "km8321-common.h"

-/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" - -#define CONFIG_MISC_INIT_R - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000006 -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_2T_EN | \ - SDRAM_CFG_SREN) -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860252 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (2 << TIMING_CFG1_WRREC_SHIFT) | \ - (6 << TIMING_CFG1_REFREC_SHIFT) | \ - (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (2 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_PIGGY_BASE 0xE8000000 -#define CONFIG_SYS_PIGGY_SIZE 128 #define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */ #define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */ #define CONFIG_SYS_PINC2_BASE 0xB0000000 /* PINC2 */ #define CONFIG_SYS_PINC2_SIZE 256 /* Megabytes */

- -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) -#define CONFIG_SYS_LBC_LBCR 0x00000000 - /* * Init Local Bus Memory Controller: * @@ -202,20 +107,6 @@ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U

-#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT6L CFG_IBAT6L -#define CFG_DBAT6U CFG_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT7L CFG_IBAT7L -#define CFG_DBAT7U CFG_IBAT7U -#else /* CONFIG_PCI */ - /* PINC2: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ BATL_MEMCOHERENCE) @@ -229,6 +120,5 @@ #define CONFIG_SYS_IBAT7U (0) #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif /* CONFIG_PCI */

#endif /* __CONFIG_H */

define KM_IVM_BUS and KM_ENV_BUS macros KM_IVM_BUS is used to define the EEprom_ivm environment variable. These macros allow the reuse of these I2C addresses in other code locations.

remove unneeded code On first HW versions the BOCO FPGA was behind a MUX device. These HW versions are not supported anymore. And therefore this code can be removed.

added LED initialization for SUEN3 The bootstat LED required to be initialized so to have a green colour after start-up.

define CONFIG_SYS_TEXT_BASE This is needed by the relocation code and is not the same for our ARM BEC and thus needs to be defined.

remove memsize variable An environment variable for memsize is not needed. this can be get via the board info struct.

remove unneeded double access to bi_dram[i].size field

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Luca Haab luca.haab@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Prafulla Wadaskar prafulla@marvell.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

board/keymile/km_arm/km_arm.c | 38 +++++++++++++++++++++++++++++++------- include/configs/km_arm.h | 1 + include/configs/mgcoge2un.h | 6 ++++-- include/configs/suen3.h | 6 ++++-- include/configs/suen8.h | 6 ++++-- 5 files changed, 44 insertions(+), 13 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 9dafcef..cb999b2 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -41,8 +41,6 @@

DECLARE_GLOBAL_DATA_PTR;

-static int io_dev; - /* Multi-Purpose Pins Functionality configuration */ u32 kwmpp_config[] = { MPP0_NF_IO2, @@ -119,15 +117,39 @@ int ethernet_present(void) return ret; }

+int initialize_unit_leds(void) +{ + /* + * init the unit LEDs + * per default they all are + * ok apart from bootstat + * LED connected through BOCO + * BOCO lies at the address 0x10 + * LEDs are in the block CTRL_H (addr 0x02) + * BOOTSTAT LED is the first 0x01 + */ + #define BOCO 0x10 + #define CTRL_H 0x02 + #define APPLEDMASK 0x01 + uchar buf; + + if (i2c_read(BOCO, CTRL_H, 1, &buf, 1) != 0) { + printf("%s: Error reading Boco\n", __func__); + return -1; + } + buf |= APPLEDMASK; + if (i2c_write(BOCO, CTRL_H, 1, &buf, 1) != 0) { + printf("%s: Error writing Boco\n", __func__); + return -1; + } + return 0; +} + int misc_init_r(void) { - I2C_MUX_DEVICE *i2cdev; char *str; int mach_type;

- /* add I2C Bus for I/O Expander */ - i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a"); - io_dev = i2cdev->busid; puts("Piggy:"); if (ethernet_present() == 0) puts (" not"); @@ -139,6 +161,9 @@ int misc_init_r(void) printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); gd->bd->bi_arch_number = mach_type; } + + initialize_unit_leds(); + return 0; }

@@ -245,7 +270,6 @@ void dram_init_banksize(void)

for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), kw_sdram_bs(i)); } diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 5fa0153..8cb0fe8 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -49,6 +49,7 @@ /* include common defines/options for all Keymile boards */ #include "keymile-common.h"

+#define CONFIG_SYS_TEXT_BASE 0x04000000 /* code address after reloc */ #define CONFIG_ENV_SIZE (128 << 10) /* NAND chip block size */ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ diff --git a/include/configs/mgcoge2un.h b/include/configs/mgcoge2un.h index 9f5464b..d3c7bdc 100644 --- a/include/configs/mgcoge2un.h +++ b/include/configs/mgcoge2un.h @@ -44,12 +44,14 @@

#define CONFIG_HOSTNAME mgcoge2un

+#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/ + /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ - "memsize=0x8000000\0" \ "newenv=setenv addr 0x100000 && " \ "i2c dev 1; mw.b ${addr} 0 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ @@ -57,7 +59,7 @@ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ "rootpath=/opt/eldk/arm\0" \ - "EEprom_ivm=pca9547:70:9\0" \ + "EEprom_ivm=" KM_IVM_BUS "\0" \ ""

#endif /* _CONFIG_MGCOGE2UN_H */ diff --git a/include/configs/suen3.h b/include/configs/suen3.h index 87f524a..2b6f19e 100644 --- a/include/configs/suen3.h +++ b/include/configs/suen3.h @@ -43,12 +43,14 @@

#define CONFIG_HOSTNAME suen3

+#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ + /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ - "memsize=0x8000000\0" \ "newenv=setenv addr 0x100000 && " \ "i2c dev 1; mw.b ${addr} 0 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ @@ -56,7 +58,7 @@ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ "rootpath=/opt/eldk/arm\0" \ - "EEprom_ivm=pca9544a:70:9\0" \ + "EEprom_ivm=" KM_IVM_BUS "\0" \ ""

#endif /* _CONFIG_SUEN3_H */ diff --git a/include/configs/suen8.h b/include/configs/suen8.h index cdda4af..3f60bc3 100644 --- a/include/configs/suen8.h +++ b/include/configs/suen8.h @@ -44,12 +44,14 @@

#define CONFIG_HOSTNAME suen8

+#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ + /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ - "memsize=0x8000000\0" \ "newenv=setenv addr 0x100000 && " \ "i2c dev 1; mw.b ${addr} 0 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ @@ -57,7 +59,7 @@ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ "rootpath=/opt/eldk/arm\0" \ - "EEprom_ivm=pca9544a:70:9\0" \ + "EEprom_ivm=" KM_IVM_BUS "\0" \ ""

#endif /* _CONFIG_SUEN8_H */

This patch adds last_stage_init to all keymile boards. And in the last stage init some environment variables for u-boot were set. Currently these are pnvramaddr, pram and var address.

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com cc: Wolfgang Denk wd@denx.de cc: Kim Phillips kim.phillips@freescale.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

board/keymile/common/common.c | 38 +++++++++++++++++++++++++++++++++++++- board/keymile/common/common.h | 1 + board/keymile/km83xx/km83xx.c | 6 ++++++ board/keymile/km_arm/km_arm.c | 6 ++++++ board/keymile/mgcoge/mgcoge.c | 6 ++++++ include/configs/keymile-common.h | 3 +++ include/configs/km_arm.h | 7 +++++++ 7 files changed, 66 insertions(+), 1 deletions(-)

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 8392a64..3908e63 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -42,6 +42,7 @@

static void i2c_write_start_seq(void); static int i2c_make_abort(void); +DECLARE_GLOBAL_DATA_PTR;

int ivm_calc_crc(unsigned char *buf, int len) { @@ -73,7 +74,42 @@ int ivm_calc_crc(unsigned char *buf, int len) return crc; }

-static int ivm_set_value(char *name, char *value) +/* + * Set Keymile specific environment variables + * Currently only some memory layout variables are calculated here + * ... ------------------------------------------------ + * ... |@rootfsaddr |@pnvramaddr |@varaddr |@reserved |@END_OF_RAM + * ... |<------------------- pram ------------------->| + * ... ------------------------------------------------ + * @END_OF_RAM: denotes the RAM size + * @pnvramaddr: Startadress of pseudo non volatile RAM in hex + * @pram : preserved ram size in k + * @varaddr : startadress for /var mounted into RAM + */ +int set_km_env(void) +{ + uchar buf[32]; + unsigned int pnvramaddr; + unsigned int pram; + unsigned int varaddr; + + pnvramaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM + - CONFIG_KM_PNVRAM; + sprintf((char *)buf, "0x%x", pnvramaddr); + setenv("pnvramaddr", (char *)buf); + + pram = (CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM + CONFIG_KM_PNVRAM) / + 0x400; + sprintf((char *)buf, "0x%x", pram); + setenv("pram", (char *)buf); + + varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; + sprintf((char *)buf, "0x%x", varaddr); + setenv("varaddr", (char *)buf); + return 0; +} + +static int ivm_set_value(char *name, char *value) { char tempbuf[256];

diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index 03838fe..7a8238c 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -49,6 +49,7 @@ int ivm_read_eeprom(void); int keymile_hdlc_enet_initialize(bd_t *bis); #endif

+int set_km_env(void); int fdt_set_node_and_value(void *blob, char *nodename, char *regname, diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index d940a1e..818e3e3 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -190,6 +190,12 @@ int misc_init_r(void) return 0; }

+int last_stage_init(void) +{ + set_km_env(); + return 0; +} + int fixed_sdram(void) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index cb999b2..c772ee2 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -212,6 +212,12 @@ int board_init(void) return 0; }

+int last_stage_init(void) +{ + set_km_env(); + return 0; +} + #if defined(CONFIG_CMD_SF) int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index a58256e..340016b 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -313,6 +313,12 @@ int board_early_init_r(void) return 0; }

+int last_stage_init(void) +{ + set_km_env(); + return 0; +} + int hush_init_var(void) { ivm_read_eeprom(); diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 77e2090..da5a447 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -26,6 +26,9 @@

/* Do boardspecific init for all boards */ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_LAST_STAGE_INIT + +#define CONFIG_BOOTCOUNT_LIMIT

/* * By default kwbimage.cfg from board specific folder is used diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 8cb0fe8..9c8d0e7 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -254,4 +254,11 @@ int get_scl (void); #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 /* Do early setups now in board_init_f() */ #define CONFIG_BOARD_EARLY_INIT_F + +/* + * resereved pram area at the end of memroy [hex] + * 8Mbytes for switch + 4Kbytes for bootcount + */ +#define CONFIG_KM_RESERVED_PRAM 0x801000 + #endif /* _CONFIG_KM_ARM_H */

From: Thomas Herzmann thomas.herzmann@keymile.com

In order to support boardId / hwkey lists, the u-boot default environment has been updated: Added a script checkboardidlist which checks the list of boardId / hwkey if the boadrId / hwkey of the IVM is included in that list. This feature is used if you got different HW variants but you only want to create one boot package. E.g. supx5 board series.

Signed-off-by: Thomas Herzmann thomas.herzmann@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Valentin Longchamp valentin.longchamp@keymile.com cc: Heiko Schocher hs@denx.de --- Changes for v2: - nothing Changes for v3: - rebased only

include/configs/keymile-common.h | 29 ++++++++++++++++++++++++++++- 1 files changed, 28 insertions(+), 1 deletions(-)

diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 1344ca9..e9a97b7 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -243,6 +243,7 @@ "release=" \ "setenv actual_bank ${initial_boot_bank} && " \ "setenv subbootcmds "" \ + "checkboardidlist " \ "checkboardid " \ "ubiattach ubicopy " \ "cramfsloadfdt cramfsloadkernel " \ @@ -392,8 +393,34 @@ "default=" \ "setenv default 'run newenv; reset' && " \ "run release && saveenv; reset\0" \ + "checkboardidlist=" \ + "if test "x${boardIdListHex}" != "x"; then " \ + "IVMbidhwk=${IVM_BoardId}_${IVM_HWKey}; " \ + "found=0; " \ + "for bidhwk in "${boardIdListHex}"; do " \ + "echo trying $bidhwk ...; " \ + "if test "x$bidhwk" = "x$IVMbidhwk"; then " \ + "found=1; " \ + "echo match found for $bidhwk; " \ + "if test "x$bidhwk" != "x${boardId}_${hwKey}";then "\ + "setenv boardid ${IVM_BoardId}; " \ + "setenv boardId ${IVM_BoardId}; " \ + "setenv hwkey ${IVM_HWKey}; " \ + "setenv hwKey ${IVM_HWKey}; " \ + "echo "boardId set to ${boardId}"; " \ + "echo "hwKey set to ${hwKey}"; " \ + "saveenv; " \ + "fi; " \ + "fi; " \ + "done; " \ + "else " \ + "echo "boardIdListHex not set, not checked"; "\ + "found=1; " \ + "fi; " \ + "test "$found" = 1 \0" \ "checkboardid=" \ - "test "x${boardId}" = "x${IVM_BoardId}"\0" \ + "test "x${boardId}" = "x${IVM_BoardId}" && " \ + "test "x${hwKey}" = "x${IVM_HWKey}"\0" \ "printbootargs=print bootargs\0" \ "rootfsfile="xstr(CONFIG_HOSTNAME) "/rootfsImage\0" \ ""

- use I/O accessors -> For accessing the FPGA therefore a struct km_bec_fpga is introduced. - no longer externs needed - to defines, that only select functions, don;t assign a numeric value - Codingstyle changes to prevent checkpatch errors/warnings

Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Holger Brunck holger.brunck@keymile.com cc: Wolfgang Denk wd@denx.de cc: Detlev Zundel dzu@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- Changes for v3: - new in this patchset, to prevent a lot of checkpatch errors/warnings

Changes for v4: - correct struct km_bec_fpga

board/keymile/common/common.c | 347 ++++++++++++++++++-------------------- board/keymile/common/common.h | 40 ++++- board/keymile/km_arm/km_arm.c | 25 ++-- board/keymile/kmeter1/kmeter1.c | 122 +++++++------- board/keymile/mgcoge/mgcoge.c | 82 +++++----- include/configs/keymile-common.h | 62 ++++---- include/configs/km_arm.h | 8 +- include/configs/kmeter1.h | 104 +++++++----- include/configs/mgcoge.h | 107 +++++++----- 9 files changed, 476 insertions(+), 421 deletions(-)

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 86be9c2..ea32028 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -39,9 +39,7 @@ #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) #include <i2c.h>

-extern int i2c_soft_read_pin (void); - -int ivm_calc_crc (unsigned char *buf, int len) +int ivm_calc_crc(unsigned char *buf, int len) { const unsigned short crc_tab[16] = { 0x0000, 0xCC01, 0xD801, 0x1400, @@ -71,20 +69,20 @@ int ivm_calc_crc (unsigned char *buf, int len) return crc; }

-static int ivm_set_value (char *name, char *value) +static int ivm_set_value(char *name, char *value) { char tempbuf[256];

if (value != NULL) { - sprintf (tempbuf, "%s=%s", name, value); - return set_local_var (tempbuf, 0); + sprintf(tempbuf, "%s=%s", name, value); + return set_local_var(tempbuf, 0); } else { - unset_local_var (name); + unset_local_var(name); } return 0; }

-static int ivm_get_value (unsigned char *buf, int len, char *name, int off, +static int ivm_get_value(unsigned char *buf, int len, char *name, int off, int check) { unsigned short val; @@ -92,21 +90,21 @@ static int ivm_get_value (unsigned char *buf, int len, char *name, int off,

if ((buf[off + 0] != buf[off + 2]) && (buf[off + 2] != buf[off + 4])) { - printf ("%s Error corrupted %s\n", __FUNCTION__, name); + printf("%s Error corrupted %s\n", __func__, name); val = -1; } else { val = buf[off + 0] + (buf[off + 1] << 8); if ((val == 0) && (check == 1)) val = -1; } - sprintf ((char *)valbuf, "%x", val); - ivm_set_value (name, (char *)valbuf); + sprintf((char *)valbuf, "%x", val); + ivm_set_value(name, (char *)valbuf); return val; }

-#define INVENTORYBLOCKSIZE 0x100 -#define INVENTORYDATAADDRESS 0x21 -#define INVENTORYDATASIZE (INVENTORYBLOCKSIZE - INVENTORYDATAADDRESS - 3) +#define INV_BLOCKSIZE 0x100 +#define INV_DATAADDRESS 0x21 +#define INVENTORYDATASIZE (INV_BLOCKSIZE - INV_DATAADDRESS - 3)

#define IVM_POS_SHORT_TEXT 0 #define IVM_POS_MANU_ID 1 @@ -121,19 +119,19 @@ static int ivm_get_value (unsigned char *buf, int len, char *name, int off, #define IVM_POS_HISTORY 10 #define IVM_POS_SYMBOL_ONLY 11

-static char convert_char (char c) +static char convert_char(char c) { return (c < ' ' || c > '~') ? '.' : c; }

-static int ivm_findinventorystring (int type, +static int ivm_findinventorystring(int type, unsigned char* const string, unsigned long maxlen, unsigned char *buf) { int xcode = 0; unsigned long cr = 0; - unsigned long addr = INVENTORYDATAADDRESS; + unsigned long addr = INV_DATAADDRESS; unsigned long size = 0; unsigned long nr = type; int stop = 0; /* stop on semicolon */ @@ -157,8 +155,10 @@ static int ivm_findinventorystring (int type, addr++; }

- /* the expected number of CR was found until the end of the IVM - * content --> fill string */ + /* + * the expected number of CR was found until the end of the IVM + * content --> fill string + */ if (addr < INVENTORYDATASIZE) { /* Copy the IVM string in the corresponding string */ for (; (buf[addr] != '\r') && @@ -170,64 +170,62 @@ static int ivm_findinventorystring (int type, convert_char (buf[addr])); }

- /* copy phase is done: check if everything is ok. If not, + /* + * copy phase is done: check if everything is ok. If not, * the inventory data is most probably corrupted: tell - * the world there is a problem! */ + * the world there is a problem! + */ if (addr == INVENTORYDATASIZE) { xcode = -1; - printf ("Error end of string not found\n"); + printf("Error end of string not found\n"); } else if ((size >= (maxlen - 1)) && (buf[addr] != '\r')) { xcode = -1; - printf ("string too long till next CR\n"); + printf("string too long till next CR\n"); } } else { - /* some CR are missing... - * the inventory data is most probably corrupted */ + /* + * some CR are missing... + * the inventory data is most probably corrupted + */ xcode = -1; - printf ("not enough cr found\n"); + printf("not enough cr found\n"); } return xcode; }

#define GET_STRING(name, which, len) \ - if (ivm_findinventorystring (which, valbuf, len, buf) == 0) { \ - ivm_set_value (name, (char *)valbuf); \ + if (ivm_findinventorystring(which, valbuf, len, buf) == 0) { \ + ivm_set_value(name, (char *)valbuf); \ }

-static int ivm_check_crc (unsigned char *buf, int block) +static int ivm_check_crc(unsigned char *buf, int block) { unsigned long crc; unsigned long crceeprom;

- crc = ivm_calc_crc (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2); + crc = ivm_calc_crc(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2); crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \ buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256); if (crc != crceeprom) { if (block == 0) - printf ("Error CRC Block: %d EEprom: calculated: \ + printf("Error CRC Block: %d EEprom: calculated: \ %lx EEprom: %lx\n", block, crc, crceeprom); return -1; } return 0; }

-static int ivm_analyze_block2 (unsigned char *buf, int len) +static int ivm_analyze_block2(unsigned char *buf, int len) { unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; unsigned long count;

/* IVM_MacAddress */ - sprintf ((char *)valbuf, "%02X:%02X:%02X:%02X:%02X:%02X", - buf[1], - buf[2], - buf[3], - buf[4], - buf[5], - buf[6]); - ivm_set_value ("IVM_MacAddress", (char *)valbuf); - if (getenv ("ethaddr") == NULL) - setenv ((char *)"ethaddr", (char *)valbuf); + sprintf((char *)valbuf, "%pM", buf); + ivm_set_value("IVM_MacAddress", (char *)valbuf); + if (getenv("ethaddr") == NULL) + setenv((char *)"ethaddr", (char *)valbuf); /* IVM_MacCount */ count = (buf[10] << 24) + (buf[11] << 16) + @@ -235,48 +233,52 @@ static int ivm_analyze_block2 (unsigned char *buf, int len) buf[13]; if (count == 0xffffffff) count = 1; - sprintf ((char *)valbuf, "%lx", count); - ivm_set_value ("IVM_MacCount", (char *)valbuf); + sprintf((char *)valbuf, "%lx", count); + ivm_set_value("IVM_MacCount", (char *)valbuf); return 0; }

-int ivm_analyze_eeprom (unsigned char *buf, int len) +int ivm_analyze_eeprom(unsigned char *buf, int len) { unsigned short val; unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; unsigned char *tmp;

- if (ivm_check_crc (buf, 0) != 0) + if (ivm_check_crc(buf, 0) != 0) return -1;

- ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_BoardId", 0, 1); - val = ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_HWKey", 6, 1); + ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, + "IVM_BoardId", 0, 1); + val = ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, + "IVM_HWKey", 6, 1); if (val != 0xffff) { - sprintf ((char *)valbuf, "%x", ((val /100) % 10)); - ivm_set_value ("IVM_HWVariant", (char *)valbuf); - sprintf ((char *)valbuf, "%x", (val % 100)); - ivm_set_value ("IVM_HWVersion", (char *)valbuf); + sprintf((char *)valbuf, "%x", ((val / 100) % 10)); + ivm_set_value("IVM_HWVariant", (char *)valbuf); + sprintf((char *)valbuf, "%x", (val % 100)); + ivm_set_value("IVM_HWVersion", (char *)valbuf); } - ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_Functions", 12, 0); + ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, + "IVM_Functions", 12, 0);

GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8) GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64) tmp = (unsigned char *) getenv("IVM_DeviceName"); if (tmp) { - int len = strlen ((char *)tmp); + int len = strlen((char *)tmp); int i = 0;

while (i < len) { if (tmp[i] == ';') { - ivm_set_value ("IVM_ShortText", (char *)&tmp[i + 1]); + ivm_set_value("IVM_ShortText", + (char *)&tmp[i + 1]); break; } i++; } if (i >= len) - ivm_set_value ("IVM_ShortText", NULL); + ivm_set_value("IVM_ShortText", NULL); } else { - ivm_set_value ("IVM_ShortText", NULL); + ivm_set_value("IVM_ShortText", NULL); } GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32) GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20) @@ -288,14 +290,15 @@ int ivm_analyze_eeprom (unsigned char *buf, int len) GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32) GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32)

- if (ivm_check_crc (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0) + if (ivm_check_crc(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0) return 0; - ivm_analyze_block2 (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], CONFIG_SYS_IVM_EEPROM_PAGE_LEN); + ivm_analyze_block2(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], + CONFIG_SYS_IVM_EEPROM_PAGE_LEN);

return 0; }

-int ivm_read_eeprom (void) +int ivm_read_eeprom(void) { #if defined(CONFIG_I2C_MUX) I2C_MUX_DEVICE *dev = NULL; @@ -303,33 +306,36 @@ int ivm_read_eeprom (void) uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; uchar *buf; unsigned dev_addr = CONFIG_SYS_IVM_EEPROM_ADR; + int ret;

#if defined(CONFIG_I2C_MUX) /* First init the Bus, select the Bus */ #if defined(CONFIG_SYS_I2C_IVM_BUS) - dev = i2c_mux_ident_muxstring ((uchar *)CONFIG_SYS_I2C_IVM_BUS); + dev = i2c_mux_ident_muxstring((uchar *)CONFIG_SYS_I2C_IVM_BUS); #else - buf = (unsigned char *) getenv ("EEprom_ivm"); + buf = (unsigned char *) getenv("EEprom_ivm"); if (buf != NULL) - dev = i2c_mux_ident_muxstring (buf); + dev = i2c_mux_ident_muxstring(buf); #endif if (dev == NULL) { - printf ("Error couldnt add Bus for IVM\n"); + printf("Error couldnt add Bus for IVM\n"); return -1; } - i2c_set_bus_num (dev->busid); + i2c_set_bus_num(dev->busid); #endif

- buf = (unsigned char *) getenv ("EEprom_ivm_addr"); + buf = (unsigned char *) getenv("EEprom_ivm_addr"); if (buf != NULL) - dev_addr = simple_strtoul ((char *)buf, NULL, 16); + dev_addr = simple_strtoul((char *)buf, NULL, 16);

- if (i2c_read(dev_addr, 0, 1, i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN) != 0) { + ret = i2c_read(dev_addr, 0, 1, i2c_buffer, + CONFIG_SYS_IVM_EEPROM_MAX_LEN); + if (ret != 0) { printf ("Error reading EEprom\n"); return -2; }

- return ivm_analyze_eeprom (i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN); + return ivm_analyze_eeprom(i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN); }

#if defined(CONFIG_SYS_I2C_INIT_BOARD) @@ -339,145 +345,117 @@ int ivm_read_eeprom (void) #if defined(CONFIG_MGCOGE) #define SDA_MASK 0x00010000 #define SCL_MASK 0x00020000 -static void set_pin (int state, unsigned long mask) +static void set_pin(int state, unsigned long mask) { - volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3); + ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);

if (state) - iop->pdat |= (mask); + setbits_be32(&iop->pdat, mask); else - iop->pdat &= ~(mask); + clrbits_be32(&iop->pdat, mask);

- iop->pdir |= (mask); + setbits_be32(&iop->pdir, mask); }

-static int get_pin (unsigned long mask) +static int get_pin(unsigned long mask) { - volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3); + ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);

- iop->pdir &= ~(mask); - return (0 != (iop->pdat & (mask))); + clrbits_be32(&iop->pdir, mask); + return 0 != (in_be32(&iop->pdat) & mask); }

-static void set_sda (int state) +static void set_sda(int state) { - set_pin (state, SDA_MASK); + set_pin(state, SDA_MASK); }

-static void set_scl (int state) +static void set_scl(int state) { - set_pin (state, SCL_MASK); + set_pin(state, SCL_MASK); }

-static int get_sda (void) +static int get_sda(void) { - return get_pin (SDA_MASK); + return get_pin(SDA_MASK); }

-static int get_scl (void) +static int get_scl(void) { - return get_pin (SCL_MASK); + return get_pin(SCL_MASK); }

#if defined(CONFIG_HARD_I2C) -static void setports (int gpio) +static void setports(int gpio) { - volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3); + ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);

if (gpio) { - iop->ppar &= ~(SDA_MASK | SCL_MASK); - iop->podr &= ~(SDA_MASK | SCL_MASK); + clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK)); + clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK)); } else { - iop->ppar |= (SDA_MASK | SCL_MASK); - iop->pdir &= ~(SDA_MASK | SCL_MASK); - iop->podr |= (SDA_MASK | SCL_MASK); + setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK)); + clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK)); + setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK)); } } #endif #endif

-#if defined(CONFIG_KM8XX) -static void set_sda (int state) -{ - I2C_SDA(state); -} - -static void set_scl (int state) -{ - I2C_SCL(state); -} - -static int get_sda (void) -{ - return I2C_READ; -} - -static int get_scl (void) -{ - int val; - - *(unsigned short *)(I2C_BASE_DIR) &= ~SCL_CONF; - udelay (1); - val = *(unsigned char *)(I2C_BASE_PORT); - - return ((val & SCL_BIT) == SCL_BIT); -} -#endif - #if !defined(CONFIG_KMETER1) -static void writeStartSeq (void) +static void writeStartSeq(void) { - set_sda (1); - udelay (DELAY_HALF_PERIOD); - set_scl (1); - udelay (DELAY_HALF_PERIOD); - set_sda (0); - udelay (DELAY_HALF_PERIOD); - set_scl (0); - udelay (DELAY_HALF_PERIOD); + set_sda(1); + udelay(DELAY_HALF_PERIOD); + set_scl(1); + udelay(DELAY_HALF_PERIOD); + set_sda(0); + udelay(DELAY_HALF_PERIOD); + set_scl(0); + udelay(DELAY_HALF_PERIOD); }

-/* I2C is a synchronous protocol and resets of the processor in the middle - of an access can block the I2C Bus until a powerdown of the full unit is - done. This function toggles the SCL until the SCL and SCA line are - released, but max. 16 times, after this a I2C start-sequence is sent. - This I2C Deblocking mechanism was developed by Keymile in association - with Anatech and Atmel in 1998. +/* + * I2C is a synchronous protocol and resets of the processor in the middle + * of an access can block the I2C Bus until a powerdown of the full unit is + * done. This function toggles the SCL until the SCL and SCA line are + * released, but max. 16 times, after this a I2C start-sequence is sent. + * This I2C Deblocking mechanism was developed by Keymile in association + * with Anatech and Atmel in 1998. */ -static int i2c_make_abort (void) +static int i2c_make_abort(void) { int scl_state = 0; int sda_state = 0; int i = 0; int ret = 0;

- if (!get_sda ()) { + if (!get_sda()) { ret = -1; while (i < 16) { i++; - set_scl (0); - udelay (DELAY_ABORT_SEQ); - set_scl (1); - udelay (DELAY_ABORT_SEQ); - scl_state = get_scl (); - sda_state = get_sda (); + set_scl(0); + udelay(DELAY_ABORT_SEQ); + set_scl(1); + udelay(DELAY_ABORT_SEQ); + scl_state = get_scl(); + sda_state = get_sda(); if (scl_state && sda_state) { ret = 0; break; } } } - if (ret == 0) { - for (i =0; i < 5; i++) { - writeStartSeq (); - } - } - get_sda (); + if (ret == 0) + for (i = 0; i < 5; i++) + writeStartSeq(); + + get_sda(); return ret; } #endif

-/** +/* * i2c_init_board - reset i2c bus. When the board is powercycled during a * bus transfer it might hang; for details see doc/I2C_Edge_Conditions. */ @@ -488,36 +466,37 @@ void i2c_init_board(void) dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); uchar dummy;

- out_8 (&dev->cr, (I2C_CR_MSTA)); - out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); + out_8(&dev->cr, (I2C_CR_MSTA)); + out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); dummy = in_8(&dev->dr); dummy = in_8(&dev->dr); if (dummy != 0xff) { dummy = in_8(&dev->dr); } - out_8 (&dev->cr, (I2C_CR_MEN)); - out_8 (&dev->cr, 0x00); - out_8 (&dev->cr, (I2C_CR_MEN)); - + out_8(&dev->cr, (I2C_CR_MEN)); + out_8(&dev->cr, 0x00); + out_8(&dev->cr, (I2C_CR_MEN)); #else #if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD) - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; - volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; + i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;

- /* disable I2C controller first, otherwhise it thinks we want to */ - /* talk to the slave port... */ - i2c->i2c_i2mod &= ~0x01; + /* + * disable I2C controller first, otherwhise it thinks we want to + * talk to the slave port... + */ + clrbits_8(&i2c->i2c_i2mod, 0x01);

/* Set the PortPins to GPIO */ - setports (1); + setports(1); #endif

/* Now run the AbortSequence() */ - i2c_make_abort (); + i2c_make_abort();

#if defined(CONFIG_HARD_I2C) /* Set the PortPins back to use for I2C */ - setports (0); + setports(0); #endif #endif } @@ -525,7 +504,7 @@ void i2c_init_board(void) #endif

#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -int fdt_set_node_and_value (void *blob, +int fdt_set_node_and_value(void *blob, char *nodename, char *regname, void *var, @@ -534,21 +513,22 @@ int fdt_set_node_and_value (void *blob, int ret = 0; int nodeoffset = 0;

- nodeoffset = fdt_path_offset (blob, nodename); + nodeoffset = fdt_path_offset(blob, nodename); if (nodeoffset >= 0) { - ret = fdt_setprop (blob, nodeoffset, regname, var, + ret = fdt_setprop(blob, nodeoffset, regname, var, size); if (ret < 0) printf("ft_blob_update(): cannot set %s/%s " "property err:%s\n", nodename, regname, - fdt_strerror (ret)); + fdt_strerror(ret)); } else { printf("ft_blob_update(): cannot find %s node " - "err:%s\n", nodename, fdt_strerror (nodeoffset)); + "err:%s\n", nodename, fdt_strerror(nodeoffset)); } return ret; } -int fdt_get_node_and_value (void *blob, + +int fdt_get_node_and_value(void *blob, char *nodename, char *propname, void **var) @@ -556,42 +536,43 @@ int fdt_get_node_and_value (void *blob, int len; int nodeoffset = 0;

- nodeoffset = fdt_path_offset (blob, nodename); + nodeoffset = fdt_path_offset(blob, nodename); if (nodeoffset >= 0) { - *var = (void *)fdt_getprop (blob, nodeoffset, propname, &len); + *var = (void *)fdt_getprop(blob, nodeoffset, propname, &len); if (len == 0) { /* no value */ - printf ("%s no value\n", __FUNCTION__); + printf("%s no value\n", __func__); return -1; } else if (len > 0) { return len; } else { - printf ("libfdt fdt_getprop(): %s\n", + printf("libfdt fdt_getprop(): %s\n", fdt_strerror(len)); return -2; } } else { - printf("%s: cannot find %s node err:%s\n", __FUNCTION__, - nodename, fdt_strerror (nodeoffset)); + printf("%s: cannot find %s node err:%s\n", __func__, + nodename, fdt_strerror(nodeoffset)); return -3; } } #endif

#if !defined(MACH_TYPE_KM_KIRKWOOD) -int ethernet_present (void) +int ethernet_present(void) { - return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80); + struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE; + + return in_8(&base->bprth) & PIGGY_PRESENT; } #endif

-int board_eth_init (bd_t *bis) +int board_eth_init(bd_t *bis) { #ifdef CONFIG_KEYMILE_HDLC_ENET - (void)keymile_hdlc_enet_initialize (bis); + (void)keymile_hdlc_enet_initialize(bis); #endif - if (ethernet_present ()) { + if (ethernet_present()) return -1; - } return 0; } diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index a38c727..8497ab6 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -11,20 +11,50 @@ #ifndef __KEYMILE_COMMON_H #define __KEYMILE_COMMON_H

-int ethernet_present (void); -int ivm_read_eeprom (void); +#define WRG_RESET 0x80 +#define H_OPORTS_14 0x40 +#define WRG_LED 0x02 +#define WRL_BOOT 0x01 + +#define H_OPORTS_SCC4_ENA 0x10 +#define H_OPORTS_SCC4_FD_ENA 0x04 +#define H_OPORTS_FCC1_PW_DWN 0x01 + +#define PIGGY_PRESENT 0x80 + +struct km_bec_fpga { + unsigned char id; + unsigned char rev; + unsigned char oprth; + unsigned char oprtl; + unsigned char res1[3]; + unsigned char bprth; + unsigned char bprtl; + unsigned char res2[6]; + unsigned char prst; + unsigned char res3[0xfff0]; + unsigned char pgy_id; + unsigned char pgy_rev; + unsigned char pgy_outputs; + unsigned char pgy_eth; +}; + +int ethernet_present(void); +int ivm_read_eeprom(void);

#ifdef CONFIG_KEYMILE_HDLC_ENET -int keymile_hdlc_enet_initialize (bd_t *bis); +int keymile_hdlc_enet_initialize(bd_t *bis); #endif

-int fdt_set_node_and_value (void *blob, +int fdt_set_node_and_value(void *blob, char *nodename, char *regname, void *var, int size); -int fdt_get_node_and_value (void *blob, +int fdt_get_node_and_value(void *blob, char *nodename, char *propname, void **var); + +int i2c_soft_read_pin(void); #endif /* __KEYMILE_COMMON_H */ diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 5c1e822..9d0892d 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -42,7 +42,6 @@ DECLARE_GLOBAL_DATA_PTR;

static int io_dev; -extern I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);

/* Multi-Purpose Pins Functionality configuration */ u32 kwmpp_config[] = { @@ -111,12 +110,12 @@ int ethernet_present(void) int ret = 0;

if (i2c_read(0x10, 2, 1, &buf, 1) != 0) { - printf ("%s: Error reading Boco\n", __FUNCTION__); + printf("%s: Error reading Boco\n", __func__); return -1; } - if ((buf & 0x40) == 0x40) { + if ((buf & 0x40) == 0x40) ret = 1; - } + return ret; }

@@ -265,15 +264,15 @@ void reset_phy(void) }

#if defined(CONFIG_HUSH_INIT_VAR) -int hush_init_var (void) +int hush_init_var(void) { - ivm_read_eeprom (); + ivm_read_eeprom(); return 0; } #endif

#if defined(CONFIG_BOOTCOUNT_LIMIT) -void bootcount_store (ulong a) +void bootcount_store(ulong a) { volatile ulong *save_addr; volatile ulong size = 0; @@ -286,7 +285,7 @@ void bootcount_store (ulong a) writel(BOOTCOUNT_MAGIC, &save_addr[1]); }

-ulong bootcount_load (void) +ulong bootcount_load(void) { volatile ulong *save_addr; volatile ulong size = 0; @@ -303,31 +302,31 @@ ulong bootcount_load (void) #endif

#if defined(CONFIG_SOFT_I2C) -void set_sda (int state) +void set_sda(int state) { I2C_ACTIVE; I2C_SDA(state); }

-void set_scl (int state) +void set_scl(int state) { I2C_SCL(state); }

-int get_sda (void) +int get_sda(void) { I2C_TRISTATE; return I2C_READ; }

-int get_scl (void) +int get_scl(void) { return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0); } #endif

#if defined(CONFIG_SYS_EEPROM_WREN) -int eeprom_write_enable (unsigned dev_addr, int state) +int eeprom_write_enable(unsigned dev_addr, int state) { kw_gpio_set_value(SUEN3_ENV_WP, !state);

diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/kmeter1/kmeter1.c index bbcaf5d..9c18168 100644 --- a/board/keymile/kmeter1/kmeter1.c +++ b/board/keymile/kmeter1/kmeter1.c @@ -30,8 +30,6 @@

#include "../common/common.h"

-extern void disable_addr_trans (void); -extern void enable_addr_trans (void); const qe_iop_conf_t qe_iop_conf_tab[] = { /* port pin dir open_drain assign */

@@ -62,131 +60,140 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, };

-static int board_init_i2c_busses (void) +static int board_init_i2c_busses(void) { I2C_MUX_DEVICE *dev = NULL; uchar *buf;

/* Set up the Bus for the DTTs */ - buf = (unsigned char *) getenv ("dtt_bus"); + buf = (unsigned char *) getenv("dtt_bus"); if (buf != NULL) - dev = i2c_mux_ident_muxstring (buf); + dev = i2c_mux_ident_muxstring(buf); if (dev == NULL) { - printf ("Error couldn't add Bus for DTT\n"); - printf ("please setup dtt_bus to where your\n"); - printf ("DTT is found.\n"); + printf("Error couldn't add Bus for DTT\n"); + printf("please setup dtt_bus to where your\n"); + printf("DTT is found.\n"); } return 0; }

-int board_early_init_r (void) +int board_early_init_r(void) { + struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE; unsigned short svid;

/* * Because of errata in the UCCs, we have to write to the reserved * registers to slow the clocks down. */ - svid = SVR_REV(mfspr (SVR)); + svid = SVR_REV(mfspr(SVR)); switch (svid) { case 0x0020: + /* + * MPC8360ECE.pdf QE_ENET10 table 4: + * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) + * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) + */ setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000); break; case 0x0021: + /* + * MPC8360ECE.pdf QE_ENET10 table 4: + * IMMR + 0x14AC[24:27] = 1010 + */ clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac), 0x00000050, 0x000000a0); break; } /* enable the PHY on the PIGGY */ - setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01); + setbits_8(&base->pgy_eth, 0x01); /* enable the Unit LED (green) */ - setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x00002), 0x01); + setbits_8(&base->oprth, WRL_BOOT); /* take FE/GbE PHYs out of reset */ - setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x0000f), 0x1c); + setbits_8(&base->prst, 0x1c);

return 0; }

-int misc_init_r (void) +int misc_init_r(void) { /* add board specific i2c busses */ - board_init_i2c_busses (); + board_init_i2c_busses(); return 0; }

int fixed_sdram(void) { - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2;

- im->sysconf.ddrlaw[0].ar = LAWAR_EN | 0x1e; - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; - udelay (200); - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); + out_be32(&im->ddr.csbnds[0].csbnds, CONFIG_SYS_DDR_CS0_BNDS); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); + udelay(200); + out_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);

msize = CONFIG_SYS_DDR_SIZE << 20; - disable_addr_trans (); - msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize); - enable_addr_trans (); + disable_addr_trans(); + msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); + enable_addr_trans(); msize /= (1024 * 1024); if (CONFIG_SYS_DDR_SIZE != msize) { for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) + (ddr_size > 1); + ddr_size = ddr_size >> 1, ddr_size_log2++) if (ddr_size & 1) return -1; - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->ddr.csbnds[0].csbnds = (((msize / 16) - 1) & 0xff); + out_be32(&im->sysconf.ddrlaw[0].ar, + (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE))); + out_be32(&im->ddr.csbnds[0].csbnds, + (((msize / 16) - 1) & 0xff)); }

return msize; }

-phys_size_t initdram (int board_type) +phys_size_t initdram(int board_type) { -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - extern void ddr_enable_ecc (unsigned int dram_size); -#endif - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0;

- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) return -1;

- /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; - msize = fixed_sdram (); + out_be32(&im->sysconf.ddrlaw[0].bar, + CONFIG_SYS_DDR_BASE & LAWBAR_BAR); + msize = fixed_sdram();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize DDR ECC byte */ - ddr_enable_ecc (msize * 1024 * 1024); + ddr_enable_ecc(msize * 1024 * 1024); #endif

/* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); }

-int checkboard (void) +int checkboard(void) { - puts ("Board: Keymile kmeter1"); - if (ethernet_present ()) - puts (" with PIGGY."); - puts ("\n"); + puts("Board: Keymile kmeter1"); + if (ethernet_present()) + puts(" with PIGGY."); + puts("\n"); return 0; }

@@ -194,13 +201,13 @@ int checkboard (void) /* * update property in the blob */ -void ft_blob_update (void *blob, bd_t *bd) +void ft_blob_update(void *blob, bd_t *bd) { /* no board specific update */ }

-void ft_board_setup (void *blob, bd_t *bd) +void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup (blob, bd); ft_blob_update (blob, bd); @@ -208,10 +215,9 @@ void ft_board_setup (void *blob, bd_t *bd) #endif

#if defined(CONFIG_HUSH_INIT_VAR) -extern int ivm_read_eeprom (void); -int hush_init_var (void) +int hush_init_var(void) { - ivm_read_eeprom (); + ivm_read_eeprom(); return 0; } #endif diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index 5c9496c..de80aa5 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -195,33 +195,30 @@ const iop_conf_t iop_conf_tab[4][32] = { } };

-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx +/* + * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx * * This routine performs standard 8260 initialization sequence * and calculates the available memory size. It may be called * several times to try different SDRAM configurations on both * 60x and local buses. */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) +static long int try_init(memctl8260_t *memctl, ulong sdmr, + ulong orx, uchar *base) { - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; + uchar c = 0xff; ulong maxsize, size; int i;

- /* We must be able to test a location outsize the maximum legal size + /* + * We must be able to test a location outsize the maximum legal size * to find out THAT we are outside; but this address still has to be * mapped by the controller. That means, that the initial mapping has * to be (at least) twice as large as the maximum expected size. */ maxsize = (1 + (~orx | 0x7fff))/* / 2*/;

- sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or1; - - *orx_ptr = orx; + out_be32(&memctl->memc_or1, orx);

/* * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): @@ -243,78 +240,83 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */

- *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; + out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA); + out_8(base, c);

- *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR); for (i = 0; i < 8; i++) - *base = c; + out_8(base, c);

- *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ + out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW); + /* setting MR on address lines */ + out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);

- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; + out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN); + out_8(base, c);

- size = get_ram_size ((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); + size = get_ram_size((long *)base, maxsize); + out_be32(&memctl->memc_or1, orx | ~(size - 1));

return (size); }

-phys_size_t initdram (int board_type) +phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + memctl8260_t *memctl = &immap->im_memctl;

long psize;

- memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; + out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT); + out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);

#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1, - (uchar *) CONFIG_SYS_SDRAM_BASE); + psize = try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1, + (uchar *) CONFIG_SYS_SDRAM_BASE); #endif /* CONFIG_SYS_RAMBOOT */

- icache_enable (); + icache_enable();

return (psize); }

int checkboard(void) { - puts ("Board: Keymile mgcoge"); - if (ethernet_present ()) - puts (" with PIGGY."); - puts ("\n"); + puts("Board: Keymile mgcoge"); + if (ethernet_present()) + puts(" with PIGGY."); + puts("\n"); return 0; }

/* * Early board initalization. */ -int board_early_init_r (void) +int board_early_init_r(void) { + struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE; + /* setup the UPIOx */ /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */ - out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc2); + out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED)); /* SCC4 enable, halfduplex, FCC1 powerdown */ - out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x15); + out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA | + H_OPORTS_FCC1_PW_DWN)); + return 0; }

-int hush_init_var (void) +int hush_init_var(void) { - ivm_read_eeprom (); + ivm_read_eeprom(); return 0; }

#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup (void *blob, bd_t *bd) +void ft_board_setup(void *blob, bd_t *bd) { - ft_cpu_setup (blob, bd); + ft_cpu_setup(blob, bd); } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index e3bd264..b934620 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008 + * (C) Copyright 2008-2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * See file CREDITS for list of people who contributed to this @@ -25,7 +25,7 @@ #define __CONFIG_KEYMILE_H

/* Do boardspecific init for all boards */ -#define CONFIG_BOARD_EARLY_INIT_R 1 +#define CONFIG_BOARD_EARLY_INIT_R

#define CONFIG_BOOTCOUNT_LIMIT

@@ -63,44 +63,44 @@ #define CONFIG_JFFS2_CMDLINE #define CONFIG_CMD_MTDPARTS

-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */

-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */

/* * Miscellaneous configurable options */ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE

-#define CONFIG_HUSH_INIT_VAR 1 +#define CONFIG_HUSH_INIT_VAR

#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */

-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x100000

-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decr. freq: 1 ms ticks */

-#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }

-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_LOADS_ECHO +#define CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */

/* @@ -108,28 +108,28 @@ * to modify in a centralized location. This is used in the HDLC * driver to set the MAC. */ -#define CONFIG_CHECK_ETHERNET_PRESENT 1 +#define CONFIG_CHECK_ETHERNET_PRESENT #define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE #define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ #define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */

-#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_MAX_I2C_BUS 1 -#define CONFIG_SYS_I2C_INIT_BOARD 1 -#define CONFIG_I2C_MUX 1 +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MUX

/* EEprom support */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 +#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

/* Support the IVM EEprom */ #define CONFIG_SYS_IVM_EEPROM_ADR 0x50 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100

-#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_PROTECTION

/* * BOOTP options @@ -141,7 +141,7 @@

#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */

-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)

/* UBI Support for all Keymile boards */ #define CONFIG_CMD_UBI diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 533da73..b3cd5a3 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -6,6 +6,9 @@ * (C) Copyright 2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * + * (C) Copyright 2010-2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * * See file CREDITS for list of people who contributed to this * project. * @@ -25,7 +28,10 @@ * MA 02110-1301 USA */

-/* for linking errors see http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ +/* + * for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html + */

#ifndef _CONFIG_KM_ARM_H #define _CONFIG_KM_ARM_H diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 8fcadfe..f288cb0 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -23,11 +23,9 @@ /* * High Level Configuration Options */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ -#define CONFIG_KMETER1 1 /* KMETER1 board specific */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_MPC8360 /* MPC8360 CPU specific */ +#define CONFIG_KMETER1 /* KMETER1 board specific */ #define CONFIG_HOSTNAME kmeter1

#define CONFIG_SYS_TEXT_BASE 0xF0000000 @@ -42,7 +40,7 @@ "mtdparts=boot:768k(u-boot),128k(env),128k(envred)," \ "-(" CONFIG_KM_UBI_PARTITION_NAME ")"

-#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MISC_INIT_R /* * System Clock Setup */ @@ -114,8 +112,9 @@ #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10 | \ + CSCONFIG_ODT_WR_ACS)

#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_SREN) @@ -137,14 +136,14 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT))

-#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_50) | \ - ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \ - ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - ( 3 << TIMING_CFG1_WRREC_SHIFT) | \ - ( 7 << TIMING_CFG1_REFREC_SHIFT) | \ - ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - ( 3 << TIMING_CFG1_PRETOACT_SHIFT)) +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT))

#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ @@ -172,7 +171,7 @@ #undef CONFIG_SYS_RAMBOOT #endif

-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve for Mon */

/* * Initial RAM Base Address Setup @@ -180,7 +179,8 @@ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE)

/* * Local Bus Configuration & Clock Setup @@ -208,7 +208,7 @@ #define CONFIG_SYS_FLASH_PROTECTION 1 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1

-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */

#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ @@ -220,8 +220,9 @@ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX | OR_GPCM_EAD)

-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +/* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }

#undef CONFIG_SYS_FLASH_CHECKSUM @@ -229,13 +230,13 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */

#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \ +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX | OR_GPCM_EAD) @@ -243,7 +244,7 @@ /* * PAXE on the local bus CS3 */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */

#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \ @@ -267,8 +268,8 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)

/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP #define CONFIG_OF_STDOUT_VIA_ALIAS

/* @@ -278,7 +279,7 @@ #undef CONFIG_PCI /* No PCI */

#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI #endif /* * QE UEC ethernet configuration @@ -291,7 +292,7 @@

#ifdef CONFIG_UEC_ETH1 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII */ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 @@ -305,17 +306,19 @@

#ifndef CONFIG_SYS_RAMBOOT #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)

/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)

#else /* CFG_RAMBOOT */ -#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ -#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 #endif /* CFG_RAMBOOT */ @@ -333,9 +336,9 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

-/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ #define CONFIG_SYS_DTT_MAX_TEMP 70 #define CONFIG_SYS_DTT_LOW_TEMP -30 #define CONFIG_SYS_DTT_HYSTERESIS 3 @@ -361,7 +364,7 @@ * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20)

/* * Core HID Setup @@ -375,45 +378,54 @@ * MMU Setup */

-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CONFIG_HIGH_BATS /* High BATs supported */

/* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U

/* IMMRBAR & PCI IO: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | \ + BATU_VP) #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U

/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U

/* Stack in dcache: cacheable, no memory coherence */ #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U

/* PAXE: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 6dec0ee..3a987ad 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -29,15 +29,12 @@ * (easy to change) */

-#define CONFIG_MPC8247 1 -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_MGCOGE 1 +#define CONFIG_MPC8247 +#define CONFIG_MGCOGE #define CONFIG_HOSTNAME mgcoge

#define CONFIG_SYS_TEXT_BASE 0xFE000000

-#define CONFIG_CPM2 1 /* Has a CPM2 */ - /* include common defines/options for all Keymile boards */ #include "keymile-common.h"

@@ -69,13 +66,13 @@ #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ #undef CONFIG_ETHER_NONE /* No external Ethernet */ -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI

#define CONFIG_ETHER_INDEX 4 #define CONFIG_HAS_ETH0 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000

-# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) +# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)

#ifndef CONFIG_8260_CLKIN #define CONFIG_8260_CLKIN 66000000 /* in Hz */ @@ -113,8 +110,9 @@ #define CONFIG_SYS_FLASH_SIZE 32 #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 3 +/* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 512

#define CONFIG_SYS_FLASH_BASE_1 0x50000000 #define CONFIG_SYS_FLASH_SIZE_1 32 @@ -130,24 +128,26 @@ #define CONFIG_SYS_RAMBOOT #endif

-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384KB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (384 << 10)

#define CONFIG_ENV_IS_IN_FLASH

#ifdef CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN

/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif /* CONFIG_ENV_IS_IN_FLASH */ -#define CONFIG_ENV_BUFFER_PRINT 1 +#define CONFIG_ENV_BUFFER_PRINT

/* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F

@@ -159,15 +159,23 @@ #define I2C_ACTIVE (iop->pdir |= 0x00010000) #define I2C_TRISTATE (iop->pdir &= ~0x00010000) #define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 +#define I2C_SDA(bit) do { \ + if (bit) \ + iop->pdat |= 0x00010000; \ + else \ + iop->pdat &= ~0x00010000; \ + } while (0) +#define I2C_SCL(bit) do { \ + if (bit) \ + iop->pdat |= 0x00020000; \ + else \ + iop->pdat &= ~0x00020000; \ + } while (0) #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */

-/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ #define CONFIG_SYS_DTT_MAX_TEMP 70 #define CONFIG_SYS_DTT_LOW_TEMP -30 #define CONFIG_SYS_DTT_HYSTERESIS 3 @@ -178,8 +186,9 @@ #define CONFIG_SYS_IMMR 0xF0000000

#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET

/* Hard reset configuration word */ @@ -194,11 +203,11 @@ #define CONFIG_SYS_HRCW_SLAVE6 0 #define CONFIG_SYS_HRCW_SLAVE7 0

-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20)

#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ #if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif

#define CONFIG_SYS_HID0_INIT 0 @@ -211,14 +220,16 @@ #define CONFIG_SYS_BCR 0x10000000 #define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)

-/*----------------------------------------------------------------------- +/* + *----------------------------------------------------------------------- * RMR - Reset Mode Register 5-5 *----------------------------------------------------------------------- * turn on Checkstop Reset Enable */ #define CONFIG_SYS_RMR 0

-/*----------------------------------------------------------------------- +/* + *----------------------------------------------------------------------- * TMCNTSC - Time Counter Status and Control 4-40 *----------------------------------------------------------------------- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, @@ -226,7 +237,8 @@ */ #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

-/*----------------------------------------------------------------------- +/* + *----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 4-42 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable @@ -234,7 +246,8 @@ */ #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)

-/*----------------------------------------------------------------------- +/* + *----------------------------------------------------------------------- * RCCR - RISC Controller Configuration 13-7 *----------------------------------------------------------------------- */ @@ -265,14 +278,16 @@ ORxG_TRLX )

-/* Bank 1 - 60x bus SDRAM +/* + * Bank 1 - 60x bus SDRAM */ #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ +#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20)

#define CONFIG_SYS_MPTPR 0x1800

-/*----------------------------------------------------------------------------- +/* + *----------------------------------------------------------------------------- * Address for Mode Register Set (MRS) command *----------------------------------------------------------------------------- */ @@ -286,8 +301,9 @@

#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1

-/* SDRAM initialization values -*/ +/* + * SDRAM initialization values + */

#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_8 |\ @@ -304,8 +320,9 @@ PSDMR_WRC_1C |\ PSDMR_CL_2)

-/* GPIO/PIGGY on CS3 initialization values -*/ +/* + * GPIO/PIGGY on CS3 initialization values + */ #define CONFIG_SYS_PIGGY_BASE 0x30000000 #define CONFIG_SYS_PIGGY_SIZE 128

@@ -316,8 +333,9 @@ ORxG_CSNT | ORxG_ACS_DIV2 |\ ORxG_SCY_3_CLK | ORxG_TRLX )

-/* Board FPGA on CS4 initialization values -*/ +/* + * Board FPGA on CS4 initialization values + */ #define CONFIG_SYS_FPGA_BASE 0x40000000 #define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/

@@ -328,8 +346,9 @@ ORxG_CSNT | ORxG_ACS_DIV2 |\ ORxG_SCY_3_CLK | ORxG_TRLX )

-/* CFG-Flash on CS5 initialization values -*/ +/* + * CFG-Flash on CS5 initialization values + */ #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)

@@ -338,12 +357,12 @@ ORxG_CSNT | ORxG_ACS_DIV2 |\ ORxG_SCY_5_CLK | ORxG_TRLX )

-#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ +#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */

/* pass open firmware flat tree */ -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_FIT +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP

#define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"

From: Holger Brunck holger.brunck@keymile.com

- adapt copyright string - change bootdelay to 2 seconds - set max number of command args to 32 - set I/O buffer size to 512

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Wolfgang Denk wd@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - new patch in v2, first patch in v1 was split up - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

include/configs/keymile-common.h | 13 ++++--------- include/configs/kmeter1.h | 4 ++-- include/configs/mgcoge.h | 7 +++---- 3 files changed, 9 insertions(+), 15 deletions(-)

diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index b934620..6f37f53 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -27,8 +27,6 @@ /* Do boardspecific init for all boards */ #define CONFIG_BOARD_EARLY_INIT_R

-#define CONFIG_BOOTCOUNT_LIMIT - /* * By default kwbimage.cfg from board specific folder is used * If for some board, different configuration file need to be used, @@ -56,16 +54,15 @@ #define CONFIG_CMD_IMMAP #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#define CONFIG_CMD_DTT #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C #define CONFIG_CMD_JFFS2 -#define CONFIG_JFFS2_CMDLINE #define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_SETEXPR

#undef CONFIG_WATCHDOG /* disable platform specific watchdog */

-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */

/* @@ -78,10 +75,10 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #endif #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE @@ -139,8 +136,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME

-#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */ - #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)

/* UBI Support for all Keymile boards */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index f288cb0..15042b9 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -8,7 +8,7 @@ * Copyright (C) 2007 MontaVista Software, Inc. * Anton Vorontsov avorontsov@ru.mvista.com * - * (C) Copyright 2008 + * (C) Copyright 2008-2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * This program is free software; you can redistribute it and/or @@ -171,7 +171,7 @@ #undef CONFIG_SYS_RAMBOOT #endif

-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve for Mon */

/* * Initial RAM Base Address Setup diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 3a987ad..662d885 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * See file CREDITS for list of people who contributed to this @@ -78,8 +78,7 @@ #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #endif

-#define BOOTFLASH_START FE000000 -#define CONFIG_PRAM 512 /* protected RAM [KBytes] */ +#define BOOTFLASH_START 0xFE000000

#define MTDIDS_DEFAULT "nor0=boot,nor1=app" #define MTDPARTS_DEFAULT \ @@ -128,7 +127,7 @@ #define CONFIG_SYS_RAMBOOT #endif

-#define CONFIG_SYS_MONITOR_LEN (384 << 10) +#define CONFIG_SYS_MONITOR_LEN (768 << 10)

#define CONFIG_ENV_IS_IN_FLASH

From: Holger Brunck holger.brunck@keymile.com

This patch reworks all headerfiles for keymile boards. Furthermore the environment variables are refactored.

Changes: - introduce km-powerpc.h file and extract ppc specific parts to it - move ARM specific options and vaiables to km_arm.h - sort the environment variables to logical groups - enhance the description of the environment variables - remove KM specific HW key and board id from kernel command line

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Wolfgang Denk wd@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - new patch in v2, first patch in v1 was split up - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

include/configs/keymile-common.h | 234 ++++++++++++++++++++++--------------- include/configs/km-powerpc.h | 92 +++++++++++++++ include/configs/km_arm.h | 25 ++++- include/configs/kmeter1.h | 36 +++---- include/configs/mgcoge.h | 31 +++--- 5 files changed, 286 insertions(+), 132 deletions(-) create mode 100644 include/configs/km-powerpc.h

diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 6f37f53..e952a19 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -86,10 +86,6 @@ #define CONFIG_HUSH_INIT_VAR

#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000

#define CONFIG_SYS_HZ 1000 /* decr. freq: 1 ms ticks */

@@ -142,7 +138,6 @@ #define CONFIG_CMD_UBI #define CONFIG_RBTREE #define CONFIG_MTD_PARTITIONS -#define CONFIG_FLASH_CFI_MTD #define CONFIG_MTD_DEVICE #define CONFIG_MTD_CONCAT

@@ -170,103 +165,152 @@ "kmprivate=empty\0" #endif

+#ifndef CONFIG_KM_DEF_NETDEV +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" +#endif + +#ifndef CONFIG_KM_UBI_PARTITION_NAME +#define CONFIG_KM_UBI_PARTITION_NAME "ubi0" +#endif +#ifndef CONFIG_KM_UBI_LINUX_MTD_NAME +#define CONFIG_KM_UBI_LINUX_MTD_NAME "ubi0" +#endif + #define xstr(s) str(s) #define str(s) #s

+/* + * bootargs + * - modify 'bootargs' + * + * - 'addip': add ip configuration + * - 'addpanic': add kernel panic options + * - 'addramfs': add phram device for the rootfilesysten in ram + * - 'addtty': add console=... + * - 'nfsargs': default arguments for nfs boot + * - 'flashargs': defaults arguments for flash base boot + * + * processor specific settings + * - 'addmtdparts': add mtd partition information + */ +#define CONFIG_KM_DEF_ENV_BOOTARGS \ + "addinit=" \ + "setenv bootargs ${bootargs} init=${init}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off\0" \ + "addpanic=" \ + "setenv bootargs ${bootargs} " \ + "panic=1 panic_on_oops=1\0" \ + "addramfs=" \ + "setenv bootargs "" \ + "${bootargs} phram.phram=" \ + "rootfs${actual_bank},${rootfsaddr},${rootfssize}"\0" \ + "addtty=" \ + "setenv bootargs ${bootargs}" \ + " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}\0" \ + "nfsargs=" \ + "setenv bootargs " \ + "ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \ + "root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "flashargs=" \ + "setenv bootargs " \ + "ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \ + "root=mtdblock:rootfs${actual_bank} " \ + "rootfstype=squashfs ro\0" \ + "" + +#define CONFIG_KM_DEF_ENV_COMPUTE_ADDR \ + "setboardid=" \ + "if test "x${boardId}" = "x"; then; " \ + "setenv boardId ${IVM_BoardId} && " \ + "setenv hwKey ${IVM_HWKey}; " \ + "else; " \ + "echo \\c; " \ + "fi\0" + +/* + * flash_boot + * - commands for booting from flash + * + * - 'cramfsaddr': address to the cramfs (in ram) + * - 'cramfsloadkernel': copy kernel from a cramfs to ram + * - 'ubiattach': attach ubi partition + * - 'ubicopy': copy ubi volume to ram + * - volume names: bootfs0, bootfs1, bootfs2, ... + * - 'ubiparition': mtd parition name for ubi + * + * processor specific settings + * - 'cramfsloadfdt': copy fdt from a cramfs to ram + */ +#define CONFIG_KM_DEF_ENV_FLASH_BOOT \ + "cramfsaddr="xstr(CONFIG_KM_CRAMFS_ADDR) "\0" \ + "cramfsloadkernel=" \ + "cramfsload ${kernel_addr_r} uImage && " \ + "setenv actual_kernel_addr ${kernel_addr_r}\0" \ + "ubiattach=ubi part ${ubipartition}\0" \ + "ubicopy=ubi read ${cramfsaddr} bootfs${actual_bank}\0" \ + "ubipartition=" CONFIG_KM_UBI_PARTITION_NAME "\0" \ + "" + +/* + * net_boot + * - commands for booting over the network + * + * - 'tftpkernel': load a kernel with tftp into ram + * + * processor specific settings + * - 'tftpfdt': load fdt with tftp into ram + */ +#define CONFIG_KM_DEF_ENV_NET_BOOT \ + "tftpkernel=" \ + "tftpboot ${kernel_addr_r} ${kernel_file} && " \ + "setenv actual_kernel_addr ${kernel_addr_r} \0" + +/* + * constants + * - KM specific constants and commands + * + * - 'default': setup default environment + */ +#define CONFIG_KM_DEF_ENV_CONSTANTS \ + "actual=setenv actual_bank ${initial_boot_bank}\0" \ + "actual0=setenv actual_bank 0\0" \ + "actual_bank=${initial_boot_bank}\0" \ + "default=" \ + "setenv default 'run newenv; reset' && " \ + "run release && saveenv; reset\0" \ + "checkboardid=" \ + "test "x${boardId}" = "x${IVM_BoardId}"\0" \ + "printbootargs=print bootargs\0" \ + "rootfsfile="xstr(CONFIG_HOSTNAME) "/rootfsImage\0" \ + "" + #ifndef CONFIG_KM_DEF_ENV #define CONFIG_KM_DEF_ENV \ - "netdev=eth0\0" \ - "u-boot_addr_r=100000\0" \ - "kernel_addr_r=200000\0" \ - "fdt_addr_r=600000\0" \ - "ram_ws=800000 \0" \ - "script_ws=780000 \0" \ - "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \ - xstr(CONFIG_HOSTNAME) ".dtb\0" \ - "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \ - "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off " xstr(BOOTFLASH_START) " +${filesize};" \ - "erase " xstr(BOOTFLASH_START) " +${filesize};" \ - "cp.b ${u-boot_addr_r} " xstr(BOOTFLASH_START) \ - " ${filesize};" \ - "protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \ - "load_fdt=tftp ${fdt_addr_r} ${fdt_file}; " \ - "setenv actual_fdt_addr ${fdt_addr_r} \0" \ - "load_kernel=tftp ${kernel_addr_r} ${kernel_file}; " \ - "setenv actual_kernel_addr ${kernel_addr_r} \0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "mtdargs=setenv bootargs root=${actual_rootfs} rw " \ - "rootfstype=jffs2 \0" \ - "altmtdargs=setenv bootargs root=${backup_rootfs} rw " \ - "rootfstype=jffs2 \0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addboardid=setenv bootargs ${bootargs} " \ - "hwKey=${IVM_HWKey} boardId=0x${IVM_BoardId} \0" \ - "addpram=setenv bootargs ${bootargs} " \ - "mem=${mem} pram=${pram}\0" \ - "pram=" xstr(CONFIG_PRAM) "k\0" \ - "net_nfs=tftp ${kernel_addr_r} ${kernel_file}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addcon addboardid addpram;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_self=tftp ${kernel_addr_r} ${kernel_file}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "tftp ${ramdisk_addr} ${ramdisk_file}; " \ - "run ramargs addip addboardid addpram; " \ - "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0"\ - "flash_nfs=run nfsargs addip addcon;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addcon addboardid addpram;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "bootcmd=run mtdargs addip addcon addboardid addpram; " \ - "bootm ${actual_kernel_addr} - ${actual_fdt_addr} \0" \ - "altbootcmd=run altmtdargs addip addcon addboardid addpram; " \ - "bootm ${backup_kernel_addr} - ${backup_fdt_addr} \0" \ - "actual0=setenv actual_bank 0; setenv actual_kernel_addr " \ - "${bank0_kernel_addr}; " \ - "setenv actual_fdt_addr ${bank0_fdt_addr}; " \ - "setenv actual_rootfs ${bank0_rootfs} \0" \ - "actual1=setenv actual_bank 1; setenv actual_kernel_addr " \ - "${bank1_kernel_addr}; " \ - "setenv actual_fdt_addr ${bank1_fdt_addr}; " \ - "setenv actual_rootfs ${bank1_rootfs} \0" \ - "backup0=setenv backup_bank 0; setenv backup_kernel_addr " \ - "${bank0_kernel_addr}; " \ - "setenv backup_fdt_addr ${bank0_fdt_addr}; " \ - "setenv backup_rootfs ${bank0_rootfs} \0" \ - "backup1=setenv backup_bank 1; setenv backup_kernel_addr " \ - "${bank1_kernel_addr}; " \ - "setenv backup_fdt_addr ${bank1_fdt_addr}; " \ - "setenv backup_rootfs ${bank1_rootfs} \0" \ - "setbank0=run actual0 backup1 \0" \ - "setbank1=run actual1 backup0 \0" \ - "release=setenv bootcmd " \ - "'run mtdargs addip addcon addboardid addpram;" \ - "bootm ${actual_kernel_addr} - ${actual_fdt_addr} '; " \ - "saveenv \0" \ - "develop=setenv bootcmd " \ - "'run nfsargs addip addcon addboardid addpram;" \ - "bootm ${actual_kernel_addr} - ${actual_fdt_addr} '; " \ - "saveenv \0" \ - "developall=setenv bootcmd " \ - "'run load_fdt load_kernel nfsargs " \ - "addip addcon addboardid addpram; " \ - "bootm ${actual_kernel_addr} - ${actual_fdt_addr} '; " \ - "saveenv \0" \ - "set_new_esw_script=setenv new_esw_script " \ - "new_esw_0x${IVM_BoardId}_0x${IVM_HWKey}.scr \0" \ - "new_esw=run set_new_esw_script; " \ - "tftp ${script_ws} ${new_esw_script}; " \ - "iminfo ${script_ws}; source ${script_ws} \0" \ - "bootlimit=0 \0" \ CONFIG_KM_DEF_ENV_IOMUX \ CONFIG_KM_DEF_ENV_PRIVATE \ + CONFIG_KM_DEF_NETDEV \ + CONFIG_KM_DEF_ENV_CPU \ + CONFIG_KM_DEF_ENV_BOOTARGS \ + CONFIG_KM_DEF_ENV_COMPUTE_ADDR \ + CONFIG_KM_DEF_ENV_FLASH_BOOT \ + CONFIG_KM_DEF_ENV_NET_BOOT \ + "altbootcmd=run bootcmd\0" \ + "bootcmd=run default\0" \ + "bootlimit=2\0" \ + "init=/sbin/init-overlay.sh\0" \ + "kernel_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \ + "kernel_file="xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "kernel_name=uImage\0" \ + "load=tftpboot ${u-boot_addr_r} ${u-boot}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "u-boot_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \ "" #endif /* CONFIG_KM_DEF_ENV */

diff --git a/include/configs/km-powerpc.h b/include/configs/km-powerpc.h new file mode 100644 index 0000000..3351609 --- /dev/null +++ b/include/configs/km-powerpc.h @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_KEYMILE_POWERPC_H +#define __CONFIG_KEYMILE_POWERPC_H + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_CMD_DTT +#define CONFIG_JFFS2_CMDLINE + +#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */ +#define CONFIG_FLASH_CFI_MTD + +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ + +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ + +/****************************************************************************** + * (PRAM usage) + * ... ------------------------------------------------------- + * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM + * ... |<------------------- pram -------------------------->| + * ... ------------------------------------------------------- + * @END_OF_RAM: + * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose + * @CONFIG_KM_PHRAM: address for /var + * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) + * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM + */ + +/* size of rootfs in RAM */ +#define CONFIG_KM_ROOTFSSIZE 0x0 +/* pseudo-non volatile RAM [hex] */ +#define CONFIG_KM_PNVRAM 0x80000 +/* physical RAM MTD size [hex] */ +#define CONFIG_KM_PHRAM 0x100000 +/* resereved pram area at the end of memroy [hex] */ +#define CONFIG_KM_RESERVED_PRAM 0x0 +/* enable protected RAM */ +#define CONFIG_PRAM 0 + +#define CONFIG_KM_CRAMFS_ADDR 0x800000 +#define CONFIG_KM_KERNEL_ADDR 0x400000 /* 3968Kbytes */ +#define CONFIG_KM_FDT_ADDR 0x7E0000 /* 128Kbytes */ + +#define CONFIG_KM_DEF_ENV_CPU \ + "addbootcount=echo \\c\0" \ + "addmtdparts=echo \\c\0" \ + "boot=bootm ${actual_kernel_addr} - ${actual_fdt_addr}\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb && " \ + "setenv actual_fdt_addr ${fdt_addr_r}\0" \ + "fdt_addr_r=" xstr(CONFIG_KM_FDT_ADDR) "\0" \ + "fdt_file=" \ + xstr(CONFIG_HOSTNAME) "/" \ + xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "tftpfdt=" \ + "tftpboot ${fdt_addr_r} ${fdt_file} && " \ + "setenv actual_fdt_addr ${fdt_addr_r} \0" \ + "update=" \ + "protect off " xstr(BOOTFLASH_START) " +${filesize} && "\ + "erase " xstr(BOOTFLASH_START) " +${filesize} && " \ + "cp.b ${u-boot_addr_r} " xstr(BOOTFLASH_START) \ + " ${filesize} && " \ + "protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \ + "" + +#endif /* __CONFIG_KEYMILE_POWERPC_H */ diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index b3cd5a3..a7c080b 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -48,8 +48,29 @@

/* include common defines/options for all Keymile boards */ #include "keymile-common.h" -#undef CONFIG_CMD_DTT -#undef CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_ENV_SIZE (128 << 10) /* NAND chip block size */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ + +/* pseudo-non volatile RAM [hex] */ +#define CONFIG_KM_PNVRAM 0x80000 +/* physical RAM MTD size [hex] */ +#define CONFIG_KM_PHRAM 0x17F000 + +#define CONFIG_KM_CRAMFS_ADDR 0x2400000 +#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */ + +#define CONFIG_KM_DEF_ENV_CPU \ + "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "boot=bootm ${actual_kernel_addr} - -\0" \ + "cramfsloadfdt=echo \\c\0" \ + "tftpfdt=echo \\c\0" \ + CONFIG_KM_DEF_ENV_UPDATE \ + "" + +

#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 15042b9..2fbc774 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -29,16 +29,20 @@ #define CONFIG_HOSTNAME kmeter1

#define CONFIG_SYS_TEXT_BASE 0xF0000000 +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth2\0" \

/* include common defines/options for all Keymile boards */ #include "keymile-common.h" - -#define CONFIG_KM_UBI_PARTITION_NAME "ubi0" +#include "km-powerpc.h"

#define MTDIDS_DEFAULT "nor0=boot" -#define MTDPARTS_DEFAULT \ - "mtdparts=boot:768k(u-boot),128k(env),128k(envred)," \ - "-(" CONFIG_KM_UBI_PARTITION_NAME ")" +#define MTDPARTS_DEFAULT "mtdparts=" \ + "boot:" \ + "768k(u-boot)," \ + "128k(env)," \ + "128k(envred)," \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")"

#define CONFIG_MISC_INIT_R /* @@ -455,7 +459,7 @@

#define BOOTFLASH_START F0000000

-#define CONFIG_PRAM 512 /* protected RAM [KBytes] */ +#define CONFIG_KM_CONSOLE_TTY "ttyS0"

/* * Environment Configuration @@ -467,22 +471,14 @@

#define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ + "dtt_bus=pca9547:70:a\0" \ + "EEprom_ivm=pca9547:70:9\0" \ + "newenv=" \ + "prot off 0xF00C0000 +0x40000 && " \ + "era 0xF00C0000 +0x40000\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ - "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \ - "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \ - "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ - "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0" \ "unlock=yes\0" \ - "fdt_addr=F0080000\0" \ - "kernel_addr=F00a0000\0" \ - "ramdisk_addr=F03a0000\0" \ - "ramdisk_addr_r=F10000\0" \ - "EEprom_ivm=pca9547:70:9\0" \ - "dtt_bus=pca9547:70:a\0" \ - "mtdids=nor0=app \0" \ - "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \ - "" + ""

#if defined(CONFIG_UEC_ETH) #define CONFIG_HAS_ETH0 diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 662d885..05ba433 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -37,6 +37,7 @@

/* include common defines/options for all Keymile boards */ #include "keymile-common.h" +#include "km-powerpc.h"

/* * Select serial console configuration @@ -80,28 +81,28 @@

#define BOOTFLASH_START 0xFE000000

-#define MTDIDS_DEFAULT "nor0=boot,nor1=app" -#define MTDPARTS_DEFAULT \ - "mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \ - "app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)" +#define CONFIG_KM_CONSOLE_TTY "ttyCPM0" + +#define MTDIDS_DEFAULT "nor3=app" +#define MTDPARTS_DEFAULT "mtdparts=" \ + "app:" \ + "768k(u-boot)," \ + "128k(env)," \ + "128k(envred)," \ + "3072k(free)," \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")"

-#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif /* * Default environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "addcon=setenv bootargs ${bootargs} " \ - "console=ttyCPM0,${baudrate}\0" \ - "mtdids=nor0=boot,nor1=app \0" \ - "partition=nor1,5 \0" \ - "new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0" \ "EEprom_ivm=pca9544a:70:4 \0" \ - "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \ "unlock=yes\0" \ + "newenv=" \ + "prot off 0xFE0C0000 +0x40000 && " \ + "era 0xFE0C0000 +0x40000\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ ""

#define CONFIG_SYS_SDRAM_BASE 0x00000000

- serial console on UART1 - Ethernet RMII over UCC4 - PHY SMSC LAN8700 - 64MB Flash - 128 MB DDR2 RAM - I2C - bootcount

This board is similiar to the kmeter1 (8360) board, so common config options are extracted into the include/configs/km83xx-common.h file.

Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Holger Brunck holger.brunck@keymile.com cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only Changes for v4: - addressed comments from Kim Phillips - replaced 832x and 8360 with just CONFIG_QE - used (SICRH_UC1EOBI | SICRH_UC2E1OBI) for CONFIG_SYS_SICRH - Coding Style changes

MAINTAINERS | 1 + arch/powerpc/cpu/mpc83xx/fdt.c | 3 +- arch/powerpc/lib/bootcount.c | 2 +- board/keymile/common/common.c | 10 +- board/keymile/{kmeter1 => km83xx}/Makefile | 0 .../keymile/{kmeter1/kmeter1.c => km83xx/km83xx.c} | 94 +++++- boards.cfg | 3 +- include/configs/km83xx-common.h | 324 +++++++++++++++++++ include/configs/kmeter1.h | 332 +------------------- include/configs/suvd3.h | 214 +++++++++++++ 10 files changed, 640 insertions(+), 343 deletions(-) rename board/keymile/{kmeter1 => km83xx}/Makefile (100%) rename board/keymile/{kmeter1/kmeter1.c => km83xx/km83xx.c} (67%) create mode 100644 include/configs/km83xx-common.h create mode 100644 include/configs/suvd3.h

diff --git a/MAINTAINERS b/MAINTAINERS index 4756f14..75b7343 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -433,6 +433,7 @@ Heiko Schocher hs@denx.de municse MPC5200 sc3 PPC405GP suen3 ARM926EJS (Kirkwood SoC) + suvd3 MPC8321 uc101 MPC5200 ve8313 MPC8313

diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index daf73a6..028c8f0 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -32,7 +32,8 @@ extern void ft_qe_setup(void *blob);

DECLARE_GLOBAL_DATA_PTR;

-#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360) +#if defined(CONFIG_BOOTCOUNT_LIMIT) && \ + (defined(CONFIG_QE)) #include <asm/immap_qe.h>

void fdt_fixup_muram (void *blob) diff --git a/arch/powerpc/lib/bootcount.c b/arch/powerpc/lib/bootcount.c index 07ef28d..f9ce539 100644 --- a/arch/powerpc/lib/bootcount.c +++ b/arch/powerpc/lib/bootcount.c @@ -51,7 +51,7 @@ #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR) #endif /* defined(CONFIG_MPC8260) */

-#if defined(CONFIG_MPC8360) +#if defined(CONFIG_QE) #include <asm/immap_qe.h>

#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \ diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index ea32028..85538d0 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -29,6 +29,7 @@ #include <malloc.h> #include <hush.h> #include <net.h> +#include <netdev.h> #include <asm/io.h>

#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) @@ -402,7 +403,7 @@ static void setports(int gpio) #endif #endif

-#if !defined(CONFIG_KMETER1) +#if !defined(CONFIG_MPC83xx) static void writeStartSeq(void) { set_sda(1); @@ -461,7 +462,7 @@ static int i2c_make_abort(void) */ void i2c_init_board(void) { -#if defined(CONFIG_KMETER1) +#if defined(CONFIG_MPC83xx) struct fsl_i2c *dev; dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); uchar dummy; @@ -573,6 +574,7 @@ int board_eth_init(bd_t *bis) (void)keymile_hdlc_enet_initialize(bis); #endif if (ethernet_present()) - return -1; - return 0; + return cpu_eth_init(bis); + + return -1; } diff --git a/board/keymile/kmeter1/Makefile b/board/keymile/km83xx/Makefile similarity index 100% rename from board/keymile/kmeter1/Makefile rename to board/keymile/km83xx/Makefile diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/km83xx/km83xx.c similarity index 67% rename from board/keymile/kmeter1/kmeter1.c rename to board/keymile/km83xx/km83xx.c index 9c18168..98aceef 100644 --- a/board/keymile/kmeter1/kmeter1.c +++ b/board/keymile/km83xx/km83xx.c @@ -8,7 +8,7 @@ * Copyright (C) 2007 MontaVista Software, Inc. * Anton Vorontsov avorontsov@ru.mvista.com * - * (C) Copyright 2008 + * (C) Copyright 2008 - 2010 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * This program is free software; you can redistribute it and/or @@ -32,7 +32,7 @@

const qe_iop_conf_t qe_iop_conf_tab[] = { /* port pin dir open_drain assign */ - +#if defined(CONFIG_KMETER1) /* MDIO */ {0, 1, 3, 0, 2}, /* MDIO */ {0, 2, 1, 0, 1}, /* MDC */ @@ -55,6 +55,40 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {5, 2, 1, 0, 1}, /* UART2_RTS */ {5, 3, 2, 0, 2}, /* UART2_SIN */ {5, 1, 2, 0, 3}, /* UART2_CTS */ +#else + /* Local Bus */ + {0, 16, 1, 0, 3}, /* LA00 */ + {0, 17, 1, 0, 3}, /* LA01 */ + {0, 18, 1, 0, 3}, /* LA02 */ + {0, 19, 1, 0, 3}, /* LA03 */ + {0, 20, 1, 0, 3}, /* LA04 */ + {0, 21, 1, 0, 3}, /* LA05 */ + {0, 22, 1, 0, 3}, /* LA06 */ + {0, 23, 1, 0, 3}, /* LA07 */ + {0, 24, 1, 0, 3}, /* LA08 */ + {0, 25, 1, 0, 3}, /* LA09 */ + {0, 26, 1, 0, 3}, /* LA10 */ + {0, 27, 1, 0, 3}, /* LA11 */ + {0, 28, 1, 0, 3}, /* LA12 */ + {0, 29, 1, 0, 3}, /* LA13 */ + {0, 30, 1, 0, 3}, /* LA14 */ + {0, 31, 1, 0, 3}, /* LA15 */ + + /* MDIO */ + {3, 4, 3, 0, 2}, /* MDIO */ + {3, 5, 1, 0, 2}, /* MDC */ + + /* UCC4 - UEC */ + {1, 18, 1, 0, 1}, /* TxD0 */ + {1, 19, 1, 0, 1}, /* TxD1 */ + {1, 22, 2, 0, 1}, /* RxD0 */ + {1, 23, 2, 0, 1}, /* RxD1 */ + {1, 26, 2, 0, 1}, /* RxER */ + {1, 28, 2, 0, 1}, /* Rx_DV */ + {1, 30, 1, 0, 1}, /* TxEN */ + {1, 31, 2, 0, 1}, /* CRS */ + {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */ +#endif

/* END of table */ {0, 0, 0, 0, QE_IOP_TAB_END}, @@ -77,11 +111,38 @@ static int board_init_i2c_busses(void) return 0; }

+#if defined(CONFIG_SUVD3) +const uint upma_table[] = { + 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */ + 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */ + 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */ + 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */ + 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */ +}; +#endif + int board_early_init_r(void) { struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE; - unsigned short svid; +#if defined(CONFIG_SUVD3) + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + fsl_lbc_t *lbc = &immap->im_lbc; + u32 *mxmr = &lbc->mamr; +#endif

+#if defined(CONFIG_MPC8360) + unsigned short svid; /* * Because of errata in the UCCs, we have to write to the reserved * registers to slow the clocks down. @@ -105,13 +166,19 @@ int board_early_init_r(void) 0x00000050, 0x000000a0); break; } +#endif + /* enable the PHY on the PIGGY */ setbits_8(&base->pgy_eth, 0x01); /* enable the Unit LED (green) */ setbits_8(&base->oprth, WRL_BOOT); - /* take FE/GbE PHYs out of reset */ - setbits_8(&base->prst, 0x1c);

+#if defined(CONFIG_SUVD3) + /* configure UPMA for APP1 */ + upmconfig(UPMA, (uint *) upma_table, + sizeof(upma_table) / sizeof(uint)); + out_be32(mxmr, CONFIG_SYS_MAMR); +#endif return 0; }

@@ -185,12 +252,13 @@ phys_size_t initdram(int board_type) #endif

/* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); + return msize * 1024 * 1024; }

int checkboard(void) { - puts("Board: Keymile kmeter1"); + puts("Board: Keymile " CONFIG_KM_BOARD_NAME); + if (ethernet_present()) puts(" with PIGGY."); puts("\n"); @@ -198,19 +266,9 @@ int checkboard(void) }

#if defined(CONFIG_OF_BOARD_SETUP) -/* - * update property in the blob - */ -void ft_blob_update(void *blob, bd_t *bd) -{ - /* no board specific update */ -} - - void ft_board_setup(void *blob, bd_t *bd) { - ft_cpu_setup (blob, bd); - ft_blob_update (blob, bd); + ft_cpu_setup(blob, bd); } #endif

diff --git a/boards.cfg b/boards.cfg index 45c3102..dc583ba 100644 --- a/boards.cfg +++ b/boards.cfg @@ -470,10 +470,11 @@ MPC8360ERDK_66 powerpc mpc83xx mpc8360erdk freesca MPC837XEMDS powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI MPC837XERDB powerpc mpc83xx mpc837xerdb freescale -kmeter1 powerpc mpc83xx kmeter1 keymile +kmeter1 powerpc mpc83xx km83xx keymile MVBLM7 powerpc mpc83xx mvblm7 matrix_vision SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP +suvd3 powerpc mpc83xx km83xx keymile TQM834x powerpc mpc83xx tqm834x tqc sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 diff --git a/include/configs/km83xx-common.h b/include/configs/km83xx-common.h new file mode 100644 index 0000000..8cfb854 --- /dev/null +++ b/include/configs/km83xx-common.h @@ -0,0 +1,324 @@ +/* + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_KM83XX_H +#define __CONFIG_KM83XX_H + +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" +#include "km-powerpc.h" + +#define MTDIDS_DEFAULT "nor0=boot" +#define MTDPARTS_DEFAULT "mtdparts=" \ + "boot:" \ + "768k(u-boot)," \ + "128k(env)," \ + "128k(envred)," \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")" + +#define CONFIG_MISC_INIT_R +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ + (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_FSL_I2C +#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 +#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE +#endif + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ROOTPATH +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ROOTPATH \ + "dtt_bus=pca9547:70:a\0" \ + "EEprom_ivm=pca9547:70:9\0" \ + "newenv=" \ + "prot off 0xF00C0000 +0x40000 && " \ + "era 0xF00C0000 +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + +#endif /* __CONFIG_KM83XX_H */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2fbc774..16278e1 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -27,30 +27,20 @@ #define CONFIG_MPC8360 /* MPC8360 CPU specific */ #define CONFIG_KMETER1 /* KMETER1 board specific */ #define CONFIG_HOSTNAME kmeter1 +#define CONFIG_KM_BOARD_NAME "kmeter1"

#define CONFIG_SYS_TEXT_BASE 0xF0000000 #define CONFIG_KM_DEF_NETDEV \ "netdev=eth2\0" \

-/* include common defines/options for all Keymile boards */ -#include "keymile-common.h" -#include "km-powerpc.h" - -#define MTDIDS_DEFAULT "nor0=boot" -#define MTDPARTS_DEFAULT "mtdparts=" \ - "boot:" \ - "768k(u-boot)," \ - "128k(env)," \ - "128k(envred)," \ - "-(" CONFIG_KM_UBI_PARTITION_NAME ")" +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h"

#define CONFIG_MISC_INIT_R /* - * System Clock Setup + * System IO Setup */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 +#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)

/* * Hardware Reset Configuration Word @@ -71,55 +61,7 @@ HRCWH_LALE_EARLY | \ HRCWH_LDP_CLEAR )

-/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000006 -#define CONFIG_SYS_SICRL 0x00000000 - -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -#undef CONFIG_DDR_ECC - -/* - * DDRCDR - DDR Control Driver Register - */ - -#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10 | \ - CSCONFIG_ODT_WR_ACS) - #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_SREN) #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 @@ -127,6 +69,11 @@ #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))

+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10 | \ + CSCONFIG_ODT_WR_ACS) + #define CONFIG_SYS_DDRCDR 0x40000001 #define CONFIG_SYS_DDR_MODE 0x47860452 #define CONFIG_SYS_DDR_MODE2 0x8080c000 @@ -159,32 +106,13 @@

#define CONFIG_SYS_DDR_TIMING_3 0x00000000

-/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 #define CONFIG_SYS_PIGGY_BASE 0xE8000000 #define CONFIG_SYS_PIGGY_SIZE 128 #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 512

-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve for Mon */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

/* * Local Bus Configuration & Clock Setup @@ -198,52 +126,9 @@ * * Bank Bus Machine PortSz Size Device * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY * 3 Local GPCM 8 bit 512MB PAXE * */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX | OR_GPCM_EAD) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -/* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * PRIO1/PIGGY on the local bus CS1 - */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ - (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX | OR_GPCM_EAD)

/* * PAXE on the local bus CS3 @@ -260,176 +145,14 @@ OR_GPCM_TRLX | OR_GPCM_EAD)

/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#undef CONFIG_PCI /* No PCI */ - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI -#endif -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_RAMBOOT */ -#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ -#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_RAMBOOT */ - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_FSL_I2C -#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_I2C_MUX 1 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 -#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE -#endif - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -#if defined(CFG_RAMBOOT) -#undef CONFIG_CMD_SAVEENV -#undef CONFIG_CMD_LOADS -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* * MMU Setup */

-#define CONFIG_HIGH_BATS /* High BATs supported */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* PAXE: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ - BATL_MEMCOHERENCE) + BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U @@ -457,31 +180,4 @@ #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #endif /* CONFIG_PCI */

-#define BOOTFLASH_START F0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - "dtt_bus=pca9547:70:a\0" \ - "EEprom_ivm=pca9547:70:9\0" \ - "newenv=" \ - "prot off 0xF00C0000 +0x40000 && " \ - "era 0xF00C0000 +0x40000\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h new file mode 100644 index 0000000..5552c51 --- /dev/null +++ b/include/configs/suvd3.h @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_MPC832x /* MPC832x CPU specific */ +#define CONFIG_SUVD3 /* SUVD3 board specific */ +#define CONFIG_HOSTNAME suvd3 +#define CONFIG_KM_BOARD_NAME "suvd3" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" + +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +#define CONFIG_MISC_INIT_R 1 + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN) +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860252 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (2 << TIMING_CFG1_WRREC_SHIFT) | \ + (6 << TIMING_CFG1_REFREC_SHIFT) | \ + (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_PIGGY_BASE 0xE8000000 +#define CONFIG_SYS_PIGGY_SIZE 128 +#define CONFIG_SYS_APP1_BASE 0xA0000000 +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local UPMA 16 bit 256MB APP1 + * 3 Local GPCM 16 bit 256MB APP2 + * + */ + +/* + * APP1 on the local bus CS2 + */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_16 | \ + BR_MS_UPMA | \ + BR_V) +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_16 | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_3 | \ + OR_GPCM_TRLX) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +/* + * MMU Setup + */ + + +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else /* CONFIG_PCI */ + +/* APP2: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif /* CONFIG_PCI */ + +#endif /* __CONFIG_H */

This board is similar to suvd3 board. So most initialisation topics are taken from suvd3 (UART1, Ethernet, piggy PHY, flash, ram) only the application specific chip selects differ.

Signed-off-by: Lukas Roggli lukas.roggli@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only Changes for v4: - addressed comment from Kim Phillips: - Codingsytle changes - removed CONFIG_SYS_SICRH define, as it not exists on 832x

MAINTAINERS | 1 + boards.cfg | 1 + include/configs/tuxa1.h | 233 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 235 insertions(+), 0 deletions(-) create mode 100644 include/configs/tuxa1.h

diff --git a/MAINTAINERS b/MAINTAINERS index 75b7343..801e4dd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -434,6 +434,7 @@ Heiko Schocher hs@denx.de sc3 PPC405GP suen3 ARM926EJS (Kirkwood SoC) suvd3 MPC8321 + tuxa1 MPC8321 uc101 MPC5200 ve8313 MPC8313

diff --git a/boards.cfg b/boards.cfg index dc583ba..ed5e0e7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -476,6 +476,7 @@ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP suvd3 powerpc mpc83xx km83xx keymile TQM834x powerpc mpc83xx tqm834x tqc +tuxa1 powerpc mpc83xx km83xx keymile sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540 diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h new file mode 100644 index 0000000..ba3570b --- /dev/null +++ b/include/configs/tuxa1.h @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010 + * Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_MPC832x /* MPC832x CPU specific */ +#define CONFIG_TUXA1 /* TUXA1 board specific */ +#define CONFIG_HOSTNAME tuxa1 +#define CONFIG_KM_BOARD_NAME "tuxa1" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" + +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +#define CONFIG_MISC_INIT_R + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_2T_EN | \ + SDRAM_CFG_SREN) +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860252 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (2 << TIMING_CFG1_WRREC_SHIFT) | \ + (6 << TIMING_CFG1_REFREC_SHIFT) | \ + (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_PIGGY_BASE 0xE8000000 +#define CONFIG_SYS_PIGGY_SIZE 128 +#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */ +#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_PINC2_BASE 0xB0000000 /* PINC2 */ +#define CONFIG_SYS_PINC2_SIZE 256 /* Megabytes */ + + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local GPCM 8 bit 256MB LPXF + * 3 Local GPCM 8 bit 256MB PINC2 + * + */ + +/* + * LPXF on the local bus CS2 + * Window base at flash base + * Window size: 256 MB + */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + (OR_GPCM_TRLX & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_EAD) +/* + * PINC2 on the local bus CS3 + * Access window base at PINC2 base + * Window size: 256 MB + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PINC2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PINC2_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \ + OR_GPCM_CSNT | \ + (OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \ + (~OR_GPCM_XACS)) | /* XACS = 0 */ \ + (OR_GPCM_SCY_2 & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_TRLX) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +/* + * MMU Setup + */ +/* LPXF: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else /* CONFIG_PCI */ + +/* PINC2: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif /* CONFIG_PCI */ + +#endif /* __CONFIG_H */

This board is similar to suvd3 board. So most initialisation topics are taken from suvd3 (UART1, Ethernet, piggy PHY, flash, ram) only the application specific chip selects differ.

Signed-off-by: Lukas Roggli lukas.roggli@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Kim Phillips kim.phillips@freescale.com cc: Valentin Longchamp valentin.longchamp@keymile.com --- changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only Changes for v4: - addressed comment from Kim Phillips: - Codingsytle changes - removed CONFIG_SYS_SICRH define, as it not exists on 832x

MAINTAINERS | 1 + boards.cfg | 1 + include/configs/tuda1.h | 248 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 250 insertions(+), 0 deletions(-) create mode 100644 include/configs/tuda1.h

diff --git a/MAINTAINERS b/MAINTAINERS index 801e4dd..cbc34af 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -434,6 +434,7 @@ Heiko Schocher hs@denx.de sc3 PPC405GP suen3 ARM926EJS (Kirkwood SoC) suvd3 MPC8321 + tuda1 MPC8321 tuxa1 MPC8321 uc101 MPC5200 ve8313 MPC8313 diff --git a/boards.cfg b/boards.cfg index ed5e0e7..b3a4e9e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -476,6 +476,7 @@ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP suvd3 powerpc mpc83xx km83xx keymile TQM834x powerpc mpc83xx tqm834x tqc +tuda1 powerpc mpc83xx km83xx keymile tuxa1 powerpc mpc83xx km83xx keymile sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h new file mode 100644 index 0000000..7ada9d5 --- /dev/null +++ b/include/configs/tuda1.h @@ -0,0 +1,248 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2011 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_MPC832x /* MPC832x CPU specific */ +#define CONFIG_TUDA1 /* TUDA1 board specific */ +#define CONFIG_HOSTNAME tuda1 +#define CONFIG_KM_BOARD_NAME "tuda1" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" + +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +#define CONFIG_MISC_INIT_R + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_2T_EN | \ + SDRAM_CFG_SREN) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860252 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (2 << TIMING_CFG1_WRREC_SHIFT) | \ + (6 << TIMING_CFG1_REFREC_SHIFT) | \ + (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + + +#define CONFIG_SYS_PIGGY_BASE 0xE8000000 +#define CONFIG_SYS_PIGGY_SIZE 128 +#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local GPCM 8 bit 256MB PAXG + * 3 Local GPCM 8 bit 256MB PINC3 + * + */ + +/* + * PAXG on the local bus CS2 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + (OR_GPCM_TRLX & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_EAD) +/* + * PINC3 on the local bus CS3 + */ +/* Access window base at PINC3 base */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_CSNT | \ + (OR_GPCM_ACS_DIV2 & /* ACS = 11 */\ + (~OR_GPCM_XACS)) | /* XACS = 0 */\ + (OR_GPCM_SCY_2 & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_TRLX) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +/* + * MMU Setup + */ +/* PAXG: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_10 | \ + BATL_MEMCOHERENCE) +/* 512M should also include APP2... */ +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | \ + BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else /* CONFIG_PCI */ + +/* PINC3: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif /* CONFIG_PCI */ + +#endif /* __CONFIG_H */

This board is similar to keymile suen3.

Signed-off-by: Clive Stubbings clive.stubbings@xentech.co.uk Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Prafulla Wadaskar prafulla@marvell.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

MAINTAINERS | 1 + boards.cfg | 1 + include/configs/km_arm.h | 41 ++++++++++++++++++++++++++++ include/configs/mgcoge2un.h | 63 +++++++++++++++++++++++++++++++++++++++++++ include/configs/suen3.h | 41 ---------------------------- 5 files changed, 106 insertions(+), 41 deletions(-) create mode 100644 include/configs/mgcoge2un.h

diff --git a/MAINTAINERS b/MAINTAINERS index cbc34af..4e7a8f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -428,6 +428,7 @@ Heiko Schocher hs@denx.de jupiter MPC5200 kmeter1 MPC8360 mgcoge MPC8247 + mgcoge2un ARM926EJS (Kirkwood SoC) mucmc52 MPC5200 muas3001 MPC8270 municse MPC5200 diff --git a/boards.cfg b/boards.cfg index b3a4e9e..1b45b5e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -94,6 +94,7 @@ davinci_schmoogie arm arm926ejs schmoogie davinci davinci_sffsdr arm arm926ejs sffsdr davinci davinci davinci_sonata arm arm926ejs sonata davinci davinci suen3 arm arm926ejs km_arm keymile kirkwood +mgcoge2un arm arm926ejs km_arm keymile kirkwood guruplug arm arm926ejs - Marvell kirkwood mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood openrd_base arm arm926ejs - Marvell kirkwood diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index a7c080b..2e38c12 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -200,6 +200,47 @@ int get_scl (void); #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

+/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ +#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_EEPROM_WREN +#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) +#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0" + +/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#define CONFIG_CMD_SF + +#define CONFIG_SPI_FLASH +#define CONFIG_HARD_SPI +#define CONFIG_KIRKWOOD_SPI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */ + +#define FLASH_GPIO_PIN 0x00010000 + +#define MTDIDS_DEFAULT "nand0=orion_nand" +/* test-only: partitioning needs some tuning, this is just for tests */ +#define MTDPARTS_DEFAULT "mtdparts=" \ + "orion_nand:" \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")" + +#define CONFIG_KM_DEF_ENV_UPDATE \ + "update=" \ + "spi on;sf probe 0;sf erase 0 50000;" \ + "sf write ${u-boot_addr_r} 0 ${filesize};" \ + "spi off\0" + #if defined(CONFIG_SYS_NO_FLASH) #define CONFIG_KM_UBI_PARTITION_NAME "ubi0" #undef CONFIG_FLASH_CFI_MTD diff --git a/include/configs/mgcoge2un.h b/include/configs/mgcoge2un.h new file mode 100644 index 0000000..9f5464b --- /dev/null +++ b/include/configs/mgcoge2un.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar prafulla@marvell.com + * + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2010-2011 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ + +#ifndef _CONFIG_MGCOGE2UN_H +#define _CONFIG_MGCOGE2UN_H + +/* include common defines/options for all arm based Keymile boards */ +#include "km_arm.h" + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nKeymile MGCOGE2UN" + +#define CONFIG_HOSTNAME mgcoge2un + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + "memsize=0x8000000\0" \ + "newenv=setenv addr 0x100000 && " \ + "i2c dev 1; mw.b ${addr} 0 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ + "rootpath=/opt/eldk/arm\0" \ + "EEprom_ivm=pca9547:70:9\0" \ + "" + +#endif /* _CONFIG_MGCOGE2UN_H */ diff --git a/include/configs/suen3.h b/include/configs/suen3.h index b2730a3..87f524a 100644 --- a/include/configs/suen3.h +++ b/include/configs/suen3.h @@ -44,47 +44,6 @@ #define CONFIG_HOSTNAME suen3

/* - * Environment variables configurations - */ -#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ -#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 -#define CONFIG_ENV_EEPROM_IS_ON_I2C 1 -#define CONFIG_SYS_EEPROM_WREN 1 -#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) -#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0" - -/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_CMD_SF - -#define CONFIG_SPI_FLASH -#define CONFIG_HARD_SPI -#define CONFIG_KIRKWOOD_SPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */ - -#define FLASH_GPIO_PIN 0x00010000 - -#define MTDIDS_DEFAULT "nand0=orion_nand" -/* test-only: partitioning needs some tuning, this is just for tests */ -#define MTDPARTS_DEFAULT "mtdparts=" \ - "orion_nand:" \ - "-(" CONFIG_KM_UBI_PARTITION_NAME ")" - -#define CONFIG_KM_DEF_ENV_UPDATE \ - "update=" \ - "spi on;sf probe 0;sf erase 0 50000;" \ - "sf write ${u-boot_addr_r} 0 ${filesize};" \ - "spi off\0" - -/* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \

The mgcoge2 board from keymile deploys two different processors. An ARM based Kirkwood for the "unit" part of the SW and a PPC for the "ne" part of the SW. Therefore in Linux and U-Boot the names for the board are mgcoge2un and mgcoge2ne. This patch adds the mgcoge2ne part of the board. The ppc part of mgboge2 is quite similar to mgcoge, therefore a generic header km82xx-common.h was introduced to collect all similiarities. Currently the only difference is that mgcoge2ne has a 64 MB numonyx NOR flash with a single die. The mgcoge has a dual die flash 2*32MB from spansion.

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Wolfgang Denk wd@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

MAINTAINERS | 1 + board/keymile/common/common.c | 4 +- board/keymile/mgcoge/mgcoge.c | 4 + boards.cfg | 1 + include/configs/km82xx-common.h | 336 +++++++++++++++++++++++++++++++++++++++ include/configs/mgcoge.h | 312 +----------------------------------- include/configs/mgcoge2ne.h | 64 ++++++++ 7 files changed, 411 insertions(+), 311 deletions(-) create mode 100644 include/configs/km82xx-common.h create mode 100644 include/configs/mgcoge2ne.h

diff --git a/MAINTAINERS b/MAINTAINERS index 9644d38..e4525e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -428,6 +428,7 @@ Heiko Schocher hs@denx.de jupiter MPC5200 kmeter1 MPC8360 mgcoge MPC8247 + mgcoge2ne MPC8247 mgcoge2un ARM926EJS (Kirkwood SoC) mucmc52 MPC5200 muas3001 MPC8270 diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 85538d0..8564b9c 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -22,7 +22,7 @@ */

#include <common.h> -#if defined(CONFIG_MGCOGE) +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGCOGE2NE) #include <mpc8260.h> #endif #include <ioports.h> @@ -343,7 +343,7 @@ int ivm_read_eeprom(void) #define DELAY_ABORT_SEQ 62 #define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))

-#if defined(CONFIG_MGCOGE) +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGCOGE2NE) #define SDA_MASK 0x00010000 #define SCL_MASK 0x00020000 static void set_pin(int state, unsigned long mask) diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index de80aa5..e32ff98 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -284,7 +284,11 @@ phys_size_t initdram(int board_type)

int checkboard(void) { +#if defined(CONFIG_MGCOGE) puts("Board: Keymile mgcoge"); +#else + puts("Board: Keymile mgcoge2ne"); +#endif if (ethernet_present()) puts(" with PIGGY."); puts("\n"); diff --git a/boards.cfg b/boards.cfg index 22cb509..3c45456 100644 --- a/boards.cfg +++ b/boards.cfg @@ -424,6 +424,7 @@ PQ2FADS-ZU_66MHz_lowboot powerpc mpc8260 mpc8260ads freesca PQ2FADS-ZU_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw funkwerk - VoVPN-GW:CLKIN_66MHz mgcoge powerpc mpc8260 - keymile +mgcoge2ne powerpc mpc8260 mgcoge keymile SCM powerpc mpc8260 - siemens TQM8255_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8255,300MHz TQM8260_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz diff --git a/include/configs/km82xx-common.h b/include/configs/km82xx-common.h new file mode 100644 index 0000000..f0a5893 --- /dev/null +++ b/include/configs/km82xx-common.h @@ -0,0 +1,336 @@ +/* + * (C) Copyright 2007-2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __KM82XX_COMMON +#define __KM82XX_COMMON + +/* + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#define CONFIG_CONS_ON_SMC /* Console is on SMC */ +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ +#undef CONFIG_CONS_NONE /* It's not on external UART */ +#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ +#define CONFIG_SYS_SMC_RXBUFLEN 128 +#define CONFIG_SYS_MAXIDLE 10 + +/* + * Select ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for + * SCC, 1-3 for FCC) + * + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines + * must be defined elsewhere (as for the console), or CONFIG_CMD_NET + * must be unset. + */ +#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ +#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ +#undef CONFIG_ETHER_NONE /* No external Ethernet */ +#define CONFIG_NET_MULTI + +#define CONFIG_ETHER_INDEX 4 +#define CONFIG_HAS_ETH0 +#define CONFIG_SYS_SCC_TOUT_LOOP 10000000 + +#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) + +#ifndef CONFIG_8260_CLKIN +#define CONFIG_8260_CLKIN 66000000 /* in Hz */ +#endif + +#define BOOTFLASH_START 0xFE000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyCPM0" + +#define MTDPARTS_DEFAULT "mtdparts=" \ + "app:" \ + "768k(u-boot)," \ + "128k(env)," \ + "128k(envred)," \ + "3072k(free)," \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")" + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + "EEprom_ivm=pca9544a:70:4 \0" \ + "unlock=yes\0" \ + "newenv=" \ + "prot off 0xFE0C0000 +0x40000 && " \ + "era 0xFE0C0000 +0x40000\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "" + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_LEN (768 << 10) + +#define CONFIG_ENV_IS_IN_FLASH + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed */ +#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ + +/* + * Software (bit-bang) I2C driver configuration + */ + +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) do { \ + if (bit) \ + iop->pdat |= 0x00010000; \ + else \ + iop->pdat &= ~0x00010000; \ + } while (0) +#define I2C_SCL(bit) do { \ + if (bit) \ + iop->pdat |= 0x00020000; \ + else \ + iop->pdat &= ~0x00020000; \ + } while (0) +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 +#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +#define CONFIG_SYS_IMMR 0xF0000000 + +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* Hard reset configuration word */ +#define CONFIG_SYS_HRCW_MASTER 0x0604b211 + +/* No slaves */ +#define CONFIG_SYS_HRCW_SLAVE1 0 +#define CONFIG_SYS_HRCW_SLAVE2 0 +#define CONFIG_SYS_HRCW_SLAVE3 0 +#define CONFIG_SYS_HRCW_SLAVE4 0 +#define CONFIG_SYS_HRCW_SLAVE5 0 +#define CONFIG_SYS_HRCW_SLAVE6 0 +#define CONFIG_SYS_HRCW_SLAVE7 0 + +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CONFIG_SYS_HID0_INIT 0 +#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) + +#define CONFIG_SYS_HID2 0 + +#define CONFIG_SYS_SIUMCR 0x4020c200 +#define CONFIG_SYS_SYPCR 0xFFFFFFC3 +#define CONFIG_SYS_BCR 0x10000000 +#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) + +/* + *----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CONFIG_SYS_RMR 0 + +/* + *----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/* + *----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/* + *----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CONFIG_SYS_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 8 bit FLASH + * 1 60x SDRAM 32 bit SDRAM + * 3 60x GPCM 8 bit GPIO/PIGGY + * 5 60x GPCM 16 bit CFG-Flash + * + */ +/* Bank 0 - FLASH + */ +#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV2 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX) + + +/* + * Bank 1 - 60x bus SDRAM + */ +#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ + +#define CONFIG_SYS_MPTPR 0x1800 + +/* + *----------------------------------------------------------------------------- + * Address for Mode Register Set (MRS) command + *----------------------------------------------------------------------------- + */ +#define CONFIG_SYS_MRS_OFFS 0x00000110 +#define CONFIG_SYS_PSRT 0x0e + +#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 + +/* + * SDRAM initialization values + */ + +#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_8 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + +#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_5_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + +/* + * GPIO/PIGGY on CS3 initialization values + */ +#define CONFIG_SYS_PIGGY_BASE 0x30000000 +#define CONFIG_SYS_PIGGY_SIZE 128 + +#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\ + BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\ + ORxG_CSNT | ORxG_ACS_DIV2 |\ + ORxG_SCY_3_CLK | ORxG_TRLX) + +/* + * Board FPGA on CS4 initialization values + */ +#define CONFIG_SYS_FPGA_BASE 0x40000000 +#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ + +#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\ + BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) + +#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\ + ORxG_CSNT | ORxG_ACS_DIV2 |\ + ORxG_SCY_3_CLK | ORxG_TRLX) + +/* + * CFG-Flash on CS5 initialization values + */ +#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ + BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) + +#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \ + CONFIG_SYS_FLASH_SIZE_2) |\ + ORxG_CSNT | ORxG_ACS_DIV2 |\ + ORxG_SCY_5_CLK | ORxG_TRLX) + +#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ + +/* pass open firmware flat tree */ +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" + +#endif /* __KM82XX_COMMON */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 05ba433..3d2ee24 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -39,72 +39,6 @@ #include "keymile-common.h" #include "km-powerpc.h"

-/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ -#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ -#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ -#define CONFIG_NET_MULTI - -#define CONFIG_ETHER_INDEX 4 -#define CONFIG_HAS_ETH0 -#define CONFIG_SYS_SCC_TOUT_LOOP 10000000 - -# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif - -#define BOOTFLASH_START 0xFE000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyCPM0" - -#define MTDIDS_DEFAULT "nor3=app" -#define MTDPARTS_DEFAULT "mtdparts=" \ - "app:" \ - "768k(u-boot)," \ - "128k(env)," \ - "128k(envred)," \ - "3072k(free)," \ - "-(" CONFIG_KM_UBI_PARTITION_NAME ")" - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - "EEprom_ivm=pca9544a:70:4 \0" \ - "unlock=yes\0" \ - "newenv=" \ - "prot off 0xFE0C0000 +0x40000 && " \ - "era 0xFE0C0000 +0x40000\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "" - #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE 0xFE000000 #define CONFIG_SYS_FLASH_SIZE 32 @@ -122,249 +56,9 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ CONFIG_SYS_FLASH_BASE_1, \ CONFIG_SYS_FLASH_BASE_2 } +#define MTDIDS_DEFAULT "nor3=app"

-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (768 << 10) - -#define CONFIG_ENV_IS_IN_FLASH - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ -#define CONFIG_ENV_BUFFER_PRINT - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) do { \ - if (bit) \ - iop->pdat |= 0x00010000; \ - else \ - iop->pdat &= ~0x00010000; \ - } while (0) -#define I2C_SCL(bit) do { \ - if (bit) \ - iop->pdat |= 0x00020000; \ - else \ - iop->pdat &= ~0x00020000; \ - } while (0) -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 -#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -#define CONFIG_SYS_IMMR 0xF0000000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CONFIG_SYS_HRCW_MASTER 0x0604b211 - -/* No slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SIUMCR 0x4020c200 -#define CONFIG_SYS_SYPCR 0xFFFFFFC3 -#define CONFIG_SYS_BCR 0x10000000 -#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) - -/* - *----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR 0 - -/* - *----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/* - *----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/* - *----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 8 bit FLASH - * 1 60x SDRAM 32 bit SDRAM - * 3 60x GPCM 8 bit GPIO/PIGGY - * 5 60x GPCM 16 bit CFG-Flash - * - */ -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX ) - - -/* - * Bank 1 - 60x bus SDRAM - */ -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) - -#define CONFIG_SYS_MPTPR 0x1800 - -/* - *----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 -#define CONFIG_SYS_PSRT 0x0e - -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 - -/* - * SDRAM initialization values - */ - -#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_8 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* - * GPIO/PIGGY on CS3 initialization values - */ -#define CONFIG_SYS_PIGGY_BASE 0x30000000 -#define CONFIG_SYS_PIGGY_SIZE 128 - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\ - BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_3_CLK | ORxG_TRLX ) - -/* - * Board FPGA on CS4 initialization values - */ -#define CONFIG_SYS_FPGA_BASE 0x40000000 -#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ - -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\ - BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_3_CLK | ORxG_TRLX ) - -/* - * CFG-Flash on CS5 initialization values - */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ - BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \ - CONFIG_SYS_FLASH_SIZE_2) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK | ORxG_TRLX ) - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* pass open firmware flat tree */ -#define CONFIG_FIT -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP - -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" +/* include further common stuff for all keymile 82xx boards */ +#include "km82xx-common.h"

#endif /* __CONFIG_H */ diff --git a/include/configs/mgcoge2ne.h b/include/configs/mgcoge2ne.h new file mode 100644 index 0000000..287b717 --- /dev/null +++ b/include/configs/mgcoge2ne.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2007-2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MGCOGE2NE +#define __MGCOGE2NE + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC8247 +#define CONFIG_MGCOGE +#define CONFIG_HOSTNAME mgcoge2ne + +#define CONFIG_SYS_TEXT_BASE 0xFE000000 + +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" +#include "km-powerpc.h" + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0xFE000000 +#define CONFIG_SYS_FLASH_SIZE 32 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* + * max num of sects on one + * chip + */ + +#define CONFIG_SYS_FLASH_BASE_1 0x50000000 +#define CONFIG_SYS_FLASH_SIZE_1 64 +#define CONFIG_SYS_FLASH_SIZE_2 0 + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_FLASH_BASE_1 } + +#define MTDIDS_DEFAULT "nor2=app" + +/* include further common stuff for all keymile 82xx boards */ +#include "km82xx-common.h" + +#endif /* __MGCOGE2NE */

These new values are: - enables UART0 and UART1 pins in MPP - define some L2 cache settings - changes a SDRAM timing to better fit the hardware - removed three writes that were the same as the reset values

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Holger Brunck holger.brunck@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- Changes for v2: - nothing Changes for v3: - nothing Changes for v4: - update commit message

board/keymile/km_arm/kwbimage.cfg | 32 ++++++++++++++++++-------------- 1 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg index 26d6aa0..b2f5193 100644 --- a/board/keymile/km_arm/kwbimage.cfg +++ b/board/keymile/km_arm/kwbimage.cfg @@ -27,16 +27,18 @@ # Boot Media configurations BOOT_FROM spi # Boot from SPI flash

-DATA 0xFFD10000 0x01111111 # MPP Control 0 Register -# bit 3-0: MPPSel0 1, NF_IO[2] -# bit 7-4: MPPSel1 1, NF_IO[3] -# bit 12-8: MPPSel2 1, NF_IO[4] -# bit 15-12: MPPSel3 1, NF_IO[5] +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: MPPSel0 2, NF_IO[2] +# bit 7-4: MPPSel1 2, NF_IO[3] +# bit 12-8: MPPSel2 2, NF_IO[4] +# bit 15-12: MPPSel3 2, NF_IO[5] # bit 19-16: MPPSel4 1, NF_IO[6] # bit 23-20: MPPSel5 1, NF_IO[7] # bit 27-24: MPPSel6 1, SYSRST_O # bit 31-28: MPPSel7 0, GPO[7]

+DATA 0xFFD10004 0x03303300 + DATA 0xFFD10008 0x00001100 # MPP Control 2 Register # bit 3-0: MPPSel16 0, GPIO[16] # bit 7-4: MPPSel17 0, GPIO[17] @@ -48,8 +50,8 @@ DATA 0xFFD10008 0x00001100 # MPP Control 2 Register # bit 31-28: MPPSel23 0, GPIO[23]

DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -DATA 0xFFD20134 0xBBBBBBBB # L2 RAM Timing 0 Register -DATA 0xFFD20138 0x00BBBBBB # L2 RAM Timing 1 Register +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register @@ -63,7 +65,7 @@ DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register # bit29-26: zero # bit31-30: 01

-DATA 0xFFD01404 0x36343000 # DDR Controller Control Low +DATA 0xFFD01404 0x39543000 # DDR Controller Control Low # bit 3-0: 0 reserved # bit 4: 0=addr/cmd in smame cycle # bit 5: 0=clk is driven during self refresh, we don't care for APX @@ -75,7 +77,7 @@ DATA 0xFFD01404 0x36343000 # DDR Controller Control Low # bit30-28: 3 required # bit31: 0=no additional STARTBURST delay

-DATA 0xFFD01408 0x2302544B # DDR Timing (Low) (active cycles value +1) +DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1) # bit3-0: TRAS lsbs # bit7-4: TRCD # bit11- 8: TRP @@ -86,7 +88,7 @@ DATA 0xFFD01408 0x2302544B # DDR Timing (Low) (active cycles value +1) # bit27-24: TRRD # bit31-28: TRTP

-DATA 0xFFD0140C 0x00000032 # DDR Timing (High) +DATA 0xFFD0140C 0x00000033 # DDR Timing (High) # bit6-0: TRFC # bit8-7: TR2R # bit10-9: TR2W @@ -116,8 +118,8 @@ DATA 0xFFD01418 0x00000000 # DDR Operation # bit3-0: 0x0, DDR cmd # bit31-4: 0 required

-DATA 0xFFD0141C 0x00000642 # DDR Mode -DATA 0xFFD01420 0x00000040 # DDR Extended Mode +DATA 0xFFD0141C 0x00000652 # DDR Mode +DATA 0xFFD01420 0x00000044 # DDR Extended Mode # bit0: 0, DDR DLL enabled # bit1: 0, DDR drive strenght normal # bit2: 1, DDR ODT control lsd disabled @@ -140,6 +142,8 @@ DATA 0xFFD01424 0x0000F07F # DDR Controller Control High # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh # bit15-12: 1111 required # bit31-16: 0 required +DATA 0xFFD01428 0x00074510 +DATA 0xFFD0147c 0x00007451

DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size @@ -153,7 +157,7 @@ DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled

-DATA 0xFFD01494 0x00000000 # DDR ODT Control (Low) +DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low) # bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0 # bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0

@@ -162,7 +166,7 @@ DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) # bit3-2: 00, ODT1 controlled by register # bit31-4: zero, required

-DATA 0xFFD0149C 0x0000E90F # CPU ODT Control +DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0 # bit9-8: 1, ODTEn, never active

define KM_IVM_BUS and KM_ENV_BUS macros KM_IVM_BUS is used to define the EEprom_ivm environment variable. These macros allow the reuse of these I2C addresses in other code locations.

remove unneeded code On first HW versions the BOCO FPGA was behind a MUX device. These HW versions are not supported anymore. And therefore this code can be removed.

added LED initialization for SUEN3 The bootstat LED required to be initialized so to have a green colour after start-up.

define CONFIG_SYS_TEXT_BASE This is needed by the relocation code and is not the same for our ARM BEC and thus needs to be defined.

remove memsize variable An environment variable for memsize is not needed. this can be get via the board info struct.

remove unneeded double access to bi_dram[i].size field

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Luca Haab luca.haab@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Prafulla Wadaskar prafulla@marvell.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

board/keymile/km_arm/km_arm.c | 38 +++++++++++++++++++++++++++++++------- include/configs/km_arm.h | 1 + include/configs/mgcoge2un.h | 6 ++++-- include/configs/suen3.h | 6 ++++-- include/configs/suen8.h | 6 ++++-- 5 files changed, 44 insertions(+), 13 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 9dafcef..cb999b2 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -41,8 +41,6 @@

DECLARE_GLOBAL_DATA_PTR;

-static int io_dev; - /* Multi-Purpose Pins Functionality configuration */ u32 kwmpp_config[] = { MPP0_NF_IO2, @@ -119,15 +117,39 @@ int ethernet_present(void) return ret; }

+int initialize_unit_leds(void) +{ + /* + * init the unit LEDs + * per default they all are + * ok apart from bootstat + * LED connected through BOCO + * BOCO lies at the address 0x10 + * LEDs are in the block CTRL_H (addr 0x02) + * BOOTSTAT LED is the first 0x01 + */ + #define BOCO 0x10 + #define CTRL_H 0x02 + #define APPLEDMASK 0x01 + uchar buf; + + if (i2c_read(BOCO, CTRL_H, 1, &buf, 1) != 0) { + printf("%s: Error reading Boco\n", __func__); + return -1; + } + buf |= APPLEDMASK; + if (i2c_write(BOCO, CTRL_H, 1, &buf, 1) != 0) { + printf("%s: Error writing Boco\n", __func__); + return -1; + } + return 0; +} + int misc_init_r(void) { - I2C_MUX_DEVICE *i2cdev; char *str; int mach_type;

- /* add I2C Bus for I/O Expander */ - i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a"); - io_dev = i2cdev->busid; puts("Piggy:"); if (ethernet_present() == 0) puts (" not"); @@ -139,6 +161,9 @@ int misc_init_r(void) printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); gd->bd->bi_arch_number = mach_type; } + + initialize_unit_leds(); + return 0; }

@@ -245,7 +270,6 @@ void dram_init_banksize(void)

for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), kw_sdram_bs(i)); } diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 5fa0153..8cb0fe8 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -49,6 +49,7 @@ /* include common defines/options for all Keymile boards */ #include "keymile-common.h"

+#define CONFIG_SYS_TEXT_BASE 0x04000000 /* code address after reloc */ #define CONFIG_ENV_SIZE (128 << 10) /* NAND chip block size */ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ diff --git a/include/configs/mgcoge2un.h b/include/configs/mgcoge2un.h index 9f5464b..d3c7bdc 100644 --- a/include/configs/mgcoge2un.h +++ b/include/configs/mgcoge2un.h @@ -44,12 +44,14 @@

#define CONFIG_HOSTNAME mgcoge2un

+#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/ + /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ - "memsize=0x8000000\0" \ "newenv=setenv addr 0x100000 && " \ "i2c dev 1; mw.b ${addr} 0 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ @@ -57,7 +59,7 @@ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ "rootpath=/opt/eldk/arm\0" \ - "EEprom_ivm=pca9547:70:9\0" \ + "EEprom_ivm=" KM_IVM_BUS "\0" \ ""

#endif /* _CONFIG_MGCOGE2UN_H */ diff --git a/include/configs/suen3.h b/include/configs/suen3.h index 87f524a..2b6f19e 100644 --- a/include/configs/suen3.h +++ b/include/configs/suen3.h @@ -43,12 +43,14 @@

#define CONFIG_HOSTNAME suen3

+#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ + /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ - "memsize=0x8000000\0" \ "newenv=setenv addr 0x100000 && " \ "i2c dev 1; mw.b ${addr} 0 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ @@ -56,7 +58,7 @@ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ "rootpath=/opt/eldk/arm\0" \ - "EEprom_ivm=pca9544a:70:9\0" \ + "EEprom_ivm=" KM_IVM_BUS "\0" \ ""

#endif /* _CONFIG_SUEN3_H */ diff --git a/include/configs/suen8.h b/include/configs/suen8.h index cdda4af..3f60bc3 100644 --- a/include/configs/suen8.h +++ b/include/configs/suen8.h @@ -44,12 +44,14 @@

#define CONFIG_HOSTNAME suen8

+#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ + /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ - "memsize=0x8000000\0" \ "newenv=setenv addr 0x100000 && " \ "i2c dev 1; mw.b ${addr} 0 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ @@ -57,7 +59,7 @@ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ "rootpath=/opt/eldk/arm\0" \ - "EEprom_ivm=pca9544a:70:9\0" \ + "EEprom_ivm=" KM_IVM_BUS "\0" \ ""

#endif /* _CONFIG_SUEN8_H */

This patch adds last_stage_init to all keymile boards. And in the last stage init some environment variables for u-boot were set. Currently these are pnvramaddr, pram and var address.

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Heiko Schocher hs@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com cc: Wolfgang Denk wd@denx.de cc: Kim Phillips kim.phillips@freescale.com --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

board/keymile/common/common.c | 38 +++++++++++++++++++++++++++++++++++++- board/keymile/common/common.h | 1 + board/keymile/km83xx/km83xx.c | 6 ++++++ board/keymile/km_arm/km_arm.c | 6 ++++++ board/keymile/mgcoge/mgcoge.c | 6 ++++++ include/configs/keymile-common.h | 3 +++ include/configs/km_arm.h | 7 +++++++ 7 files changed, 66 insertions(+), 1 deletions(-)

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 8392a64..3908e63 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -42,6 +42,7 @@

static void i2c_write_start_seq(void); static int i2c_make_abort(void); +DECLARE_GLOBAL_DATA_PTR;

int ivm_calc_crc(unsigned char *buf, int len) { @@ -73,7 +74,42 @@ int ivm_calc_crc(unsigned char *buf, int len) return crc; }

-static int ivm_set_value(char *name, char *value) +/* + * Set Keymile specific environment variables + * Currently only some memory layout variables are calculated here + * ... ------------------------------------------------ + * ... |@rootfsaddr |@pnvramaddr |@varaddr |@reserved |@END_OF_RAM + * ... |<------------------- pram ------------------->| + * ... ------------------------------------------------ + * @END_OF_RAM: denotes the RAM size + * @pnvramaddr: Startadress of pseudo non volatile RAM in hex + * @pram : preserved ram size in k + * @varaddr : startadress for /var mounted into RAM + */ +int set_km_env(void) +{ + uchar buf[32]; + unsigned int pnvramaddr; + unsigned int pram; + unsigned int varaddr; + + pnvramaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM + - CONFIG_KM_PNVRAM; + sprintf((char *)buf, "0x%x", pnvramaddr); + setenv("pnvramaddr", (char *)buf); + + pram = (CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM + CONFIG_KM_PNVRAM) / + 0x400; + sprintf((char *)buf, "0x%x", pram); + setenv("pram", (char *)buf); + + varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; + sprintf((char *)buf, "0x%x", varaddr); + setenv("varaddr", (char *)buf); + return 0; +} + +static int ivm_set_value(char *name, char *value) { char tempbuf[256];

diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index e32de8d..099de98 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -50,6 +50,7 @@ int ivm_read_eeprom(void); int keymile_hdlc_enet_initialize(bd_t *bis); #endif

+int set_km_env(void); int fdt_set_node_and_value(void *blob, char *nodename, char *regname, diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index f9186e8..17560c8 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -190,6 +190,12 @@ int misc_init_r(void) return 0; }

+int last_stage_init(void) +{ + set_km_env(); + return 0; +} + int fixed_sdram(void) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index cb999b2..c772ee2 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -212,6 +212,12 @@ int board_init(void) return 0; }

+int last_stage_init(void) +{ + set_km_env(); + return 0; +} + #if defined(CONFIG_CMD_SF) int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index a58256e..340016b 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -313,6 +313,12 @@ int board_early_init_r(void) return 0; }

+int last_stage_init(void) +{ + set_km_env(); + return 0; +} + int hush_init_var(void) { ivm_read_eeprom(); diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 77e2090..da5a447 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -26,6 +26,9 @@

/* Do boardspecific init for all boards */ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_LAST_STAGE_INIT + +#define CONFIG_BOOTCOUNT_LIMIT

/* * By default kwbimage.cfg from board specific folder is used diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 8cb0fe8..9c8d0e7 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -254,4 +254,11 @@ int get_scl (void); #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 /* Do early setups now in board_init_f() */ #define CONFIG_BOARD_EARLY_INIT_F + +/* + * resereved pram area at the end of memroy [hex] + * 8Mbytes for switch + 4Kbytes for bootcount + */ +#define CONFIG_KM_RESERVED_PRAM 0x801000 + #endif /* _CONFIG_KM_ARM_H */

From: Holger Brunck holger.brunck@keymile.com

Add: - introduce "bootrunner" environment variable This allows to execute consecutive different commands specified in the list "subbootcmd". If one command fails the command serie will stop. - introduce environment variable "develop", "ramfs" and "release" Each variable is one way to boot our linux. "develop" is for development purpose and boots the SW via NFS. "release" is for booting the linux image from flash, "ramfs" allows to load an SW image via tftp into ram and executes from there - introduce "addmem" variable, this command adds the used memory for linux to the bootargs - introduce "addvar" variable, this command adress for the /var directory to the kernel command line - introduce "setramfspram" and "setrootfsaddr" these calculation were done if "ramfs" was used (only for debugging) - introduce "tftpramfs" used for "ramfs" to load the image into RAM (only for debugging) Remove unneeded stuff: - CONFIG_IO_MUXING is obsolete for keymile boards - CONFIG_KM_DEF_ENV_PRIVATE is also obsolete - define CONFIG_SYS_TEXT_BASE in board configs only

Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Wolfgang Denk wd@denx.de cc: Prafulla Wadaskar prafulla@marvell.com cc: Valentin Longchamp valentin.longchamp@keymile.com cc: Heiko Schocher hs@denx.de --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

include/configs/keymile-common.h | 163 +++++++++++++++++++++++++++++++------ include/configs/km_arm.h | 2 + 2 files changed, 138 insertions(+), 27 deletions(-)

diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index da5a447..1344ca9 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -40,13 +40,6 @@ #endif /* CONFIG_SYS_KWD_CONFIG */

/* - * CONFIG_SYS_TEXT_BASE can be defined in board specific header file, if needed - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x00400000 -#endif /* CONFIG_SYS_TEXT_BASE */ - -/* * Command line configuration. */ #include <config_cmd_default.h> @@ -144,28 +137,16 @@ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_CONCAT

-/* define this to use the keymile's io muxing feature */ -/*#define CONFIG_IO_MUXING */ - -#ifdef CONFIG_IO_MUXING -#define CONFIG_KM_DEF_ENV_IOMUX \ - "nc=setenv ethact HDLC \0" \ - "nce=setenv ethact SCC \0" \ - "stderr=serial,nc \0" \ - "stdin=serial,nc \0" \ - "stdout=serial,nc \0" \ - "tftpsrcp=69 \0" \ - "tftpdstp=69 \0" -#else #define CONFIG_KM_DEF_ENV_IOMUX \ "stderr=serial \0" \ "stdin=serial \0" \ "stdout=serial \0" -#endif

-#ifndef CONFIG_KM_DEF_ENV_PRIVATE -#define CONFIG_KM_DEF_ENV_PRIVATE \ - "kmprivate=empty\0" +/* common powerpc specific env settings */ +#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS +#define CONFIG_KM_DEF_ENV_BOOTPARAMS \ + "bootparams=empty\0" \ + "initial_boot_bank=0\0" #endif

#ifndef CONFIG_KM_DEF_NETDEV @@ -184,17 +165,116 @@ #define str(s) #s

/* + * bootrunner + * - run all commands in 'subbootcmds' + * - on error, stop running the remaing commands + */ +#define CONFIG_KM_DEF_ENV_BOOTRUNNER \ + "bootrunner=" \ + "break=0; " \ + "for subbootcmd in ${subbootcmds}; do " \ + "if test ${break} -eq 0; then; " \ + "echo "[INFO] running \c"; " \ + "print ${subbootcmd}; " \ + "run ${subbootcmd} || break=1; " \ + "if test ${break} -eq 1; then; " \ + "echo "[ERR] failed \c"; " \ + "print ${subbootcmd}; " \ + "fi; " \ + "fi; " \ + "done\0" \ + "" + +/* + * boottargets + * - set 'subbootcmds' for the bootrunner + * - set 'bootcmd' and 'altbootcmd' + * available targets: + * - 'release': for a standalone system kernel/rootfs from flash + * - 'develop': for development kernel(tftp)/rootfs(NFS) + * - 'ramfs': rootfilesystem in RAM kernel(tftp)/rootfs(RAM) + * + * - 'commonargs': bootargs common to all targets + */ +#define CONFIG_KM_DEF_ENV_BOOTTARGETS \ + "commonargs=" \ + "addip " \ + "addtty " \ + "addmem " \ + "addinit " \ + "addvar " \ + "addmtdparts " \ + "addbootcount " \ + "\0" \ + "develop=" \ + "setenv subbootcmds "" \ + "tftpfdt tftpkernel " \ + "nfsargs ${commonargs} " \ + "printbootargs boot " \ + "" && " \ + "setenv bootcmd '" \ + "run bootrunner" \ + "' && " \ + "setenv altbootcmd '" \ + "run bootcmd" \ + "' && " \ + "run setboardid && " \ + "saveenv && " \ + "reset\0" \ + "ramfs=" \ + "setenv actual_bank -1 && " \ + "setenv subbootcmds "" \ + "tftpfdt tftpkernel " \ + "setrootfsaddr tftpramfs " \ + "flashargs ${commonargs} " \ + "addpanic addramfs " \ + "printbootargs boot " \ + "" && " \ + "setenv bootcmd '" \ + "run bootrunner" \ + "' && " \ + "setenv altbootcmd '" \ + "run bootcmd" \ + "' && " \ + "run setboardid && " \ + "run setramfspram && " \ + "saveenv && " \ + "reset\0" \ + "release=" \ + "setenv actual_bank ${initial_boot_bank} && " \ + "setenv subbootcmds "" \ + "checkboardid " \ + "ubiattach ubicopy " \ + "cramfsloadfdt cramfsloadkernel " \ + "flashargs ${commonargs} " \ + "addpanic " \ + "printbootargs boot " \ + "" && " \ + "setenv bootcmd '" \ + "run bootrunner; reset" \ + "' && " \ + "setenv altbootcmd '" \ + "run actual0 bootcmd; reset" \ + "' && " \ + "saveenv && " \ + "reset\0" \ + "" + +/* * bootargs * - modify 'bootargs' * * - 'addip': add ip configuration + * - 'addmem': limit kernel memory mem= * - 'addpanic': add kernel panic options * - 'addramfs': add phram device for the rootfilesysten in ram * - 'addtty': add console=... + * - 'addvar': add phram device for /var * - 'nfsargs': default arguments for nfs boot * - 'flashargs': defaults arguments for flash base boot * * processor specific settings + * - 'addbootcount': add boot counter * - 'addmtdparts': add mtd partition information */ #define CONFIG_KM_DEF_ENV_BOOTARGS \ @@ -204,6 +284,8 @@ "setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off\0" \ + "addmem=" \ + "setenv bootargs ${bootargs} mem=0x${pnvramaddr}\0" \ "addpanic=" \ "setenv bootargs ${bootargs} " \ "panic=1 panic_on_oops=1\0" \ @@ -214,6 +296,9 @@ "addtty=" \ "setenv bootargs ${bootargs}" \ " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}\0" \ + "addvar=" \ + "setenv bootargs ${bootargs} phram.phram=phvar," \ + "${varaddr},0x" xstr(CONFIG_KM_PHRAM) "\0" \ "nfsargs=" \ "setenv bootargs " \ "ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \ @@ -226,6 +311,14 @@ "rootfstype=squashfs ro\0" \ ""

+/* + * compute_addr + * - compute addresses and sizes + * - addresses are calculated form the end of memory 'memsize' + * + * - 'setramfspram': compute PRAM size for ramfs target + * - 'setrootfsaddr': compute rootfilesystem address for phram + */ #define CONFIG_KM_DEF_ENV_COMPUTE_ADDR \ "setboardid=" \ "if test "x${boardId}" = "x"; then; " \ @@ -233,7 +326,15 @@ "setenv hwKey ${IVM_HWKey}; " \ "else; " \ "echo \\c; " \ - "fi\0" + "fi\0" \ + "setramfspram=" \ + "setexpr value ${rootfssize} / 0x400 && " \ + "setexpr value 0x${value} + ${pram} && " \ + "setenv pram 0x${value}\0" \ + "setrootfsaddr=" \ + "setexpr value ${pnvramaddr} - ${rootfssize} && " \ + "setenv rootfsaddr 0x${value}\0" \ + ""

/* * flash_boot @@ -264,6 +365,7 @@ * - commands for booting over the network * * - 'tftpkernel': load a kernel with tftp into ram + * - 'tftpramfs': load rootfs with tftp into ram * * processor specific settings * - 'tftpfdt': load fdt with tftp into ram @@ -271,7 +373,11 @@ #define CONFIG_KM_DEF_ENV_NET_BOOT \ "tftpkernel=" \ "tftpboot ${kernel_addr_r} ${kernel_file} && " \ - "setenv actual_kernel_addr ${kernel_addr_r} \0" + "setenv actual_kernel_addr ${kernel_addr_r}\0" \ + "tftpramfs=" \ + "tftpboot ${rootfsaddr} "\"${rootfsfile}\"" && " \ + "setenv loadaddr\0" \ + ""

/* * constants @@ -294,14 +400,17 @@

#ifndef CONFIG_KM_DEF_ENV #define CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ENV_BOOTPARAMS \ CONFIG_KM_DEF_ENV_IOMUX \ - CONFIG_KM_DEF_ENV_PRIVATE \ CONFIG_KM_DEF_NETDEV \ CONFIG_KM_DEF_ENV_CPU \ + CONFIG_KM_DEF_ENV_BOOTRUNNER \ + CONFIG_KM_DEF_ENV_BOOTTARGETS \ CONFIG_KM_DEF_ENV_BOOTARGS \ CONFIG_KM_DEF_ENV_COMPUTE_ADDR \ CONFIG_KM_DEF_ENV_FLASH_BOOT \ CONFIG_KM_DEF_ENV_NET_BOOT \ + CONFIG_KM_DEF_ENV_CONSTANTS \ "altbootcmd=run bootcmd\0" \ "bootcmd=run default\0" \ "bootlimit=2\0" \ diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 9c8d0e7..70113d4 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -260,5 +260,7 @@ int get_scl (void); * 8Mbytes for switch + 4Kbytes for bootcount */ #define CONFIG_KM_RESERVED_PRAM 0x801000 +/* address for the bootcount (taken from end of RAM) */ +#define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM)

#endif /* _CONFIG_KM_ARM_H */

From: Holger Brunck holger.brunck@keymile.com

Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Wolfgang Denk wd@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com cc: Heiko Schocher hs@denx.de --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only

include/configs/keymile-common.h | 9 +++------ 1 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index e9a97b7..cb6d0fb 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -137,11 +137,6 @@ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_CONCAT

-#define CONFIG_KM_DEF_ENV_IOMUX \ - "stderr=serial \0" \ - "stdin=serial \0" \ - "stdout=serial \0" - /* common powerpc specific env settings */ #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS #define CONFIG_KM_DEF_ENV_BOOTPARAMS \ @@ -428,7 +423,6 @@ #ifndef CONFIG_KM_DEF_ENV #define CONFIG_KM_DEF_ENV \ CONFIG_KM_DEF_ENV_BOOTPARAMS \ - CONFIG_KM_DEF_ENV_IOMUX \ CONFIG_KM_DEF_NETDEV \ CONFIG_KM_DEF_ENV_CPU \ CONFIG_KM_DEF_ENV_BOOTRUNNER \ @@ -448,6 +442,9 @@ "load=tftpboot ${u-boot_addr_r} ${u-boot}\0" \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "u-boot_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \ ""