[U-Boot] [PATCH v2 0/10] split tegra20 arm7 code into separate SPL
This patch series fixes a long standing problem with the tegra20 u-boot build. Tegra20 contains an ARM7TDMI boot processor and a Cortex A9 main processor. Prior to this patch series this was accomplished by #ifdefing out any armv7 code from the early boot sequence and creating a single binary that runs on both both the ARM7TDMI and A9. This was very fragile as changes to compiler options or any additions or rearranging of the early boot code could add additional armv7 specific code causing it to fail on the ARM7TDMI.
This patch series pulls all the armv4t code out into a separate SPL that does nothing more than initialize the A9 and transfer control to it. The resultint SPL and armv7 u-boot are concatenated together into a single image.
Changes: v2: - renamed tegra2 to tegra20 to match kernel and devicetree naming policy - pulled all SPL related config overrides to a separate file to clean up ifdefs from seabard.h - rebased to TOT u-boot/master and fixed a bug related to init sequence changes between this patch series and new EMC code - made u-boot.t2 target work even if CONFIG_OF is disabled - added back USE_PRIVATE_LIBGCC
[PATCH 01/10] tegra20: rename tegra2 -> tegra20 [PATCH 02/10] tegra20: move tegra20 SoC code to [PATCH 03/10] mkconfig: add support for SPL CPU [PATCH 04/10] ARM: Fix arm720t SPL build [PATCH 05/10] tegra20: remove timer_init from SPL build [PATCH 06/10] ARM: add tegra20 support to arm720t [PATCH 07/10] tegra20: add SPL config options for seaboard [PATCH 08/10] tegra20: add u-boot.t2 target [PATCH 09/10] tegra20: Remove CPU init code from tegra20 u-boot [PATCH 10/10] tegra20: Remove armv4t build flags
.gitignore | 1 - Makefile | 14 - arch/arm/cpu/arm720t/cpu.c | 2 - arch/arm/cpu/arm720t/interrupts.c | 4 - arch/arm/cpu/arm720t/start.S | 19 +- arch/arm/cpu/arm720t/tegra20/Makefile | 48 - arch/arm/cpu/arm720t/tegra20/board.h | 25 - arch/arm/cpu/arm720t/tegra20/cpu.c | 259 ----- arch/arm/cpu/arm720t/tegra20/cpu.h | 99 -- arch/arm/cpu/arm720t/tegra20/spl.c | 133 --- arch/arm/cpu/armv7/start.S | 2 + arch/arm/cpu/armv7/tegra2/Makefile | 59 ++ arch/arm/cpu/armv7/tegra2/ap20.c | 366 +++++++ arch/arm/cpu/armv7/tegra2/board.c | 151 +++ arch/arm/cpu/armv7/tegra2/clock.c | 1087 ++++++++++++++++++++ arch/arm/cpu/armv7/tegra2/config.mk | 35 + arch/arm/cpu/armv7/tegra2/crypto.c | 230 +++++ arch/arm/cpu/armv7/tegra2/crypto.h | 36 + arch/arm/cpu/armv7/tegra2/emc.c | 286 +++++ arch/arm/cpu/armv7/tegra2/funcmux.c | 200 ++++ arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 42 + arch/arm/cpu/armv7/tegra2/pinmux.c | 572 ++++++++++ arch/arm/cpu/armv7/tegra2/pmu.c | 70 ++ arch/arm/cpu/armv7/tegra2/sys_info.c | 35 + arch/arm/cpu/armv7/tegra2/timer.c | 111 ++ arch/arm/cpu/armv7/tegra2/usb.c | 460 +++++++++ arch/arm/cpu/armv7/tegra2/warmboot.c | 386 +++++++ arch/arm/cpu/armv7/tegra2/warmboot_avp.c | 250 +++++ arch/arm/cpu/armv7/tegra2/warmboot_avp.h | 81 ++ arch/arm/cpu/armv7/tegra20/Makefile | 48 - arch/arm/cpu/armv7/tegra20/config.mk | 28 - arch/arm/cpu/armv7/tegra20/usb.c | 460 --------- arch/arm/cpu/tegra20-common/Makefile | 59 -- arch/arm/cpu/tegra20-common/ap20.c | 110 -- arch/arm/cpu/tegra20-common/board.c | 134 --- arch/arm/cpu/tegra20-common/clock.c | 1087 -------------------- arch/arm/cpu/tegra20-common/crypto.c | 230 ----- arch/arm/cpu/tegra20-common/crypto.h | 36 - arch/arm/cpu/tegra20-common/emc.c | 286 ----- arch/arm/cpu/tegra20-common/funcmux.c | 200 ---- arch/arm/cpu/tegra20-common/lowlevel_init.S | 42 - arch/arm/cpu/tegra20-common/pinmux.c | 572 ---------- arch/arm/cpu/tegra20-common/pmu.c | 70 -- arch/arm/cpu/tegra20-common/sys_info.c | 35 - arch/arm/cpu/tegra20-common/timer.c | 111 -- arch/arm/cpu/tegra20-common/warmboot.c | 386 ------- arch/arm/cpu/tegra20-common/warmboot_avp.c | 250 ----- arch/arm/cpu/tegra20-common/warmboot_avp.h | 81 -- arch/arm/include/asm/arch-tegra2/ap20.h | 109 ++ arch/arm/include/asm/arch-tegra2/apb_misc.h | 36 + arch/arm/include/asm/arch-tegra2/board.h | 30 + arch/arm/include/asm/arch-tegra2/clk_rst.h | 147 +++ arch/arm/include/asm/arch-tegra2/clock.h | 406 ++++++++ arch/arm/include/asm/arch-tegra2/emc.h | 113 ++ arch/arm/include/asm/arch-tegra2/flow.h | 36 + arch/arm/include/asm/arch-tegra2/funcmux.h | 69 ++ arch/arm/include/asm/arch-tegra2/fuse.h | 39 + arch/arm/include/asm/arch-tegra2/gp_padctrl.h | 73 ++ arch/arm/include/asm/arch-tegra2/gpio.h | 289 ++++++ arch/arm/include/asm/arch-tegra2/mmc.h | 27 + arch/arm/include/asm/arch-tegra2/pinmux.h | 354 +++++++ arch/arm/include/asm/arch-tegra2/pmc.h | 132 +++ arch/arm/include/asm/arch-tegra2/pmu.h | 30 + arch/arm/include/asm/arch-tegra2/scu.h | 43 + arch/arm/include/asm/arch-tegra2/sdram_param.h | 148 +++ arch/arm/include/asm/arch-tegra2/sys_proto.h | 35 + arch/arm/include/asm/arch-tegra2/tegra2.h | 86 ++ arch/arm/include/asm/arch-tegra2/tegra2_spi.h | 76 ++ arch/arm/include/asm/arch-tegra2/tegra_i2c.h | 164 +++ arch/arm/include/asm/arch-tegra2/timer.h | 30 + arch/arm/include/asm/arch-tegra2/uart-spi-switch.h | 46 + arch/arm/include/asm/arch-tegra2/uart.h | 47 + arch/arm/include/asm/arch-tegra2/usb.h | 252 +++++ arch/arm/include/asm/arch-tegra2/warmboot.h | 150 +++ arch/arm/include/asm/arch-tegra20/ap20.h | 109 -- arch/arm/include/asm/arch-tegra20/apb_misc.h | 36 - arch/arm/include/asm/arch-tegra20/board.h | 30 - arch/arm/include/asm/arch-tegra20/clk_rst.h | 147 --- arch/arm/include/asm/arch-tegra20/clock.h | 406 -------- arch/arm/include/asm/arch-tegra20/emc.h | 113 -- arch/arm/include/asm/arch-tegra20/flow.h | 36 - arch/arm/include/asm/arch-tegra20/funcmux.h | 69 -- arch/arm/include/asm/arch-tegra20/fuse.h | 39 - arch/arm/include/asm/arch-tegra20/gp_padctrl.h | 73 -- arch/arm/include/asm/arch-tegra20/gpio.h | 289 ------ arch/arm/include/asm/arch-tegra20/hardware.h | 29 - arch/arm/include/asm/arch-tegra20/mmc.h | 27 - arch/arm/include/asm/arch-tegra20/pinmux.h | 354 ------- arch/arm/include/asm/arch-tegra20/pmc.h | 132 --- arch/arm/include/asm/arch-tegra20/pmu.h | 30 - arch/arm/include/asm/arch-tegra20/scu.h | 43 - arch/arm/include/asm/arch-tegra20/sdram_param.h | 148 --- arch/arm/include/asm/arch-tegra20/sys_proto.h | 35 - arch/arm/include/asm/arch-tegra20/tegra2.h | 86 -- arch/arm/include/asm/arch-tegra20/tegra2_spi.h | 76 -- arch/arm/include/asm/arch-tegra20/tegra_i2c.h | 164 --- arch/arm/include/asm/arch-tegra20/timer.h | 30 - .../arm/include/asm/arch-tegra20/uart-spi-switch.h | 46 - arch/arm/include/asm/arch-tegra20/uart.h | 47 - arch/arm/include/asm/arch-tegra20/usb.h | 252 ----- arch/arm/include/asm/arch-tegra20/warmboot.h | 150 --- board/nvidia/common/board.c | 2 - board/nvidia/seaboard/config.mk | 1 - boards.cfg | 17 +- doc/README.SPL | 12 - include/configs/seaboard.h | 6 - include/configs/tegra2-common.h | 21 +- include/configs/tegra2-spl.h | 87 -- mkconfig | 15 +- spl/Makefile | 4 - 110 files changed, 7438 insertions(+), 7978 deletions(-)
-- nvpublic
This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code.
Signed-off-by: Allen Martin amartin@nvidia.com --- arch/arm/cpu/armv7/{tegra2 => tegra20}/Makefile | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/ap20.c | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/board.c | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/clock.c | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/config.mk | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/crypto.c | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/crypto.h | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/emc.c | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/funcmux.c | 0 .../cpu/armv7/{tegra2 => tegra20}/lowlevel_init.S | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/pinmux.c | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/pmu.c | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/sys_info.c | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/timer.c | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/usb.c | 0 arch/arm/cpu/armv7/{tegra2 => tegra20}/warmboot.c | 0 .../cpu/armv7/{tegra2 => tegra20}/warmboot_avp.c | 0 .../cpu/armv7/{tegra2 => tegra20}/warmboot_avp.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/ap20.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/apb_misc.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/board.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/clk_rst.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/clock.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/emc.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/flow.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/funcmux.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/fuse.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/gp_padctrl.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/gpio.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/mmc.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/pinmux.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/pmc.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/pmu.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/scu.h | 0 .../{arch-tegra2 => arch-tegra20}/sdram_param.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/sys_proto.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/tegra2.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/tegra2_spi.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/tegra_i2c.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/timer.h | 0 .../uart-spi-switch.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/uart.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/usb.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/warmboot.h | 0 boards.cfg | 12 ++++++------ 45 files changed, 6 insertions(+), 6 deletions(-) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/Makefile (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/ap20.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/board.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/clock.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/config.mk (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/crypto.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/crypto.h (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/emc.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/funcmux.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/lowlevel_init.S (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/pinmux.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/pmu.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/sys_info.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/timer.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/usb.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/warmboot.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/warmboot_avp.c (100%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/warmboot_avp.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/ap20.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/apb_misc.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/board.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/clk_rst.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/clock.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/emc.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/flow.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/funcmux.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/fuse.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/gp_padctrl.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/gpio.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/mmc.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/pinmux.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/pmc.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/pmu.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/scu.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/sdram_param.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/sys_proto.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/tegra2.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/tegra2_spi.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/tegra_i2c.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/timer.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/uart-spi-switch.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/uart.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/usb.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/warmboot.h (100%)
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra20/Makefile similarity index 100% rename from arch/arm/cpu/armv7/tegra2/Makefile rename to arch/arm/cpu/armv7/tegra20/Makefile diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra20/ap20.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/ap20.c rename to arch/arm/cpu/armv7/tegra20/ap20.c diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra20/board.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/board.c rename to arch/arm/cpu/armv7/tegra20/board.c diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra20/clock.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/clock.c rename to arch/arm/cpu/armv7/tegra20/clock.c diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra20/config.mk similarity index 100% rename from arch/arm/cpu/armv7/tegra2/config.mk rename to arch/arm/cpu/armv7/tegra20/config.mk diff --git a/arch/arm/cpu/armv7/tegra2/crypto.c b/arch/arm/cpu/armv7/tegra20/crypto.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/crypto.c rename to arch/arm/cpu/armv7/tegra20/crypto.c diff --git a/arch/arm/cpu/armv7/tegra2/crypto.h b/arch/arm/cpu/armv7/tegra20/crypto.h similarity index 100% rename from arch/arm/cpu/armv7/tegra2/crypto.h rename to arch/arm/cpu/armv7/tegra20/crypto.h diff --git a/arch/arm/cpu/armv7/tegra2/emc.c b/arch/arm/cpu/armv7/tegra20/emc.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/emc.c rename to arch/arm/cpu/armv7/tegra20/emc.c diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c b/arch/arm/cpu/armv7/tegra20/funcmux.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/funcmux.c rename to arch/arm/cpu/armv7/tegra20/funcmux.c diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra20/lowlevel_init.S similarity index 100% rename from arch/arm/cpu/armv7/tegra2/lowlevel_init.S rename to arch/arm/cpu/armv7/tegra20/lowlevel_init.S diff --git a/arch/arm/cpu/armv7/tegra2/pinmux.c b/arch/arm/cpu/armv7/tegra20/pinmux.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/pinmux.c rename to arch/arm/cpu/armv7/tegra20/pinmux.c diff --git a/arch/arm/cpu/armv7/tegra2/pmu.c b/arch/arm/cpu/armv7/tegra20/pmu.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/pmu.c rename to arch/arm/cpu/armv7/tegra20/pmu.c diff --git a/arch/arm/cpu/armv7/tegra2/sys_info.c b/arch/arm/cpu/armv7/tegra20/sys_info.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/sys_info.c rename to arch/arm/cpu/armv7/tegra20/sys_info.c diff --git a/arch/arm/cpu/armv7/tegra2/timer.c b/arch/arm/cpu/armv7/tegra20/timer.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/timer.c rename to arch/arm/cpu/armv7/tegra20/timer.c diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/usb.c rename to arch/arm/cpu/armv7/tegra20/usb.c diff --git a/arch/arm/cpu/armv7/tegra2/warmboot.c b/arch/arm/cpu/armv7/tegra20/warmboot.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/warmboot.c rename to arch/arm/cpu/armv7/tegra20/warmboot.c diff --git a/arch/arm/cpu/armv7/tegra2/warmboot_avp.c b/arch/arm/cpu/armv7/tegra20/warmboot_avp.c similarity index 100% rename from arch/arm/cpu/armv7/tegra2/warmboot_avp.c rename to arch/arm/cpu/armv7/tegra20/warmboot_avp.c diff --git a/arch/arm/cpu/armv7/tegra2/warmboot_avp.h b/arch/arm/cpu/armv7/tegra20/warmboot_avp.h similarity index 100% rename from arch/arm/cpu/armv7/tegra2/warmboot_avp.h rename to arch/arm/cpu/armv7/tegra20/warmboot_avp.h diff --git a/arch/arm/include/asm/arch-tegra2/ap20.h b/arch/arm/include/asm/arch-tegra20/ap20.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/ap20.h rename to arch/arm/include/asm/arch-tegra20/ap20.h diff --git a/arch/arm/include/asm/arch-tegra2/apb_misc.h b/arch/arm/include/asm/arch-tegra20/apb_misc.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/apb_misc.h rename to arch/arm/include/asm/arch-tegra20/apb_misc.h diff --git a/arch/arm/include/asm/arch-tegra2/board.h b/arch/arm/include/asm/arch-tegra20/board.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/board.h rename to arch/arm/include/asm/arch-tegra20/board.h diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra20/clk_rst.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/clk_rst.h rename to arch/arm/include/asm/arch-tegra20/clk_rst.h diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra20/clock.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/clock.h rename to arch/arm/include/asm/arch-tegra20/clock.h diff --git a/arch/arm/include/asm/arch-tegra2/emc.h b/arch/arm/include/asm/arch-tegra20/emc.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/emc.h rename to arch/arm/include/asm/arch-tegra20/emc.h diff --git a/arch/arm/include/asm/arch-tegra2/flow.h b/arch/arm/include/asm/arch-tegra20/flow.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/flow.h rename to arch/arm/include/asm/arch-tegra20/flow.h diff --git a/arch/arm/include/asm/arch-tegra2/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/funcmux.h rename to arch/arm/include/asm/arch-tegra20/funcmux.h diff --git a/arch/arm/include/asm/arch-tegra2/fuse.h b/arch/arm/include/asm/arch-tegra20/fuse.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/fuse.h rename to arch/arm/include/asm/arch-tegra20/fuse.h diff --git a/arch/arm/include/asm/arch-tegra2/gp_padctrl.h b/arch/arm/include/asm/arch-tegra20/gp_padctrl.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/gp_padctrl.h rename to arch/arm/include/asm/arch-tegra20/gp_padctrl.h diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/gpio.h rename to arch/arm/include/asm/arch-tegra20/gpio.h diff --git a/arch/arm/include/asm/arch-tegra2/mmc.h b/arch/arm/include/asm/arch-tegra20/mmc.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/mmc.h rename to arch/arm/include/asm/arch-tegra20/mmc.h diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/pinmux.h rename to arch/arm/include/asm/arch-tegra20/pinmux.h diff --git a/arch/arm/include/asm/arch-tegra2/pmc.h b/arch/arm/include/asm/arch-tegra20/pmc.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/pmc.h rename to arch/arm/include/asm/arch-tegra20/pmc.h diff --git a/arch/arm/include/asm/arch-tegra2/pmu.h b/arch/arm/include/asm/arch-tegra20/pmu.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/pmu.h rename to arch/arm/include/asm/arch-tegra20/pmu.h diff --git a/arch/arm/include/asm/arch-tegra2/scu.h b/arch/arm/include/asm/arch-tegra20/scu.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/scu.h rename to arch/arm/include/asm/arch-tegra20/scu.h diff --git a/arch/arm/include/asm/arch-tegra2/sdram_param.h b/arch/arm/include/asm/arch-tegra20/sdram_param.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/sdram_param.h rename to arch/arm/include/asm/arch-tegra20/sdram_param.h diff --git a/arch/arm/include/asm/arch-tegra2/sys_proto.h b/arch/arm/include/asm/arch-tegra20/sys_proto.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/sys_proto.h rename to arch/arm/include/asm/arch-tegra20/sys_proto.h diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra20/tegra2.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/tegra2.h rename to arch/arm/include/asm/arch-tegra20/tegra2.h diff --git a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h b/arch/arm/include/asm/arch-tegra20/tegra2_spi.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/tegra2_spi.h rename to arch/arm/include/asm/arch-tegra20/tegra2_spi.h diff --git a/arch/arm/include/asm/arch-tegra2/tegra_i2c.h b/arch/arm/include/asm/arch-tegra20/tegra_i2c.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/tegra_i2c.h rename to arch/arm/include/asm/arch-tegra20/tegra_i2c.h diff --git a/arch/arm/include/asm/arch-tegra2/timer.h b/arch/arm/include/asm/arch-tegra20/timer.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/timer.h rename to arch/arm/include/asm/arch-tegra20/timer.h diff --git a/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h b/arch/arm/include/asm/arch-tegra20/uart-spi-switch.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/uart-spi-switch.h rename to arch/arm/include/asm/arch-tegra20/uart-spi-switch.h diff --git a/arch/arm/include/asm/arch-tegra2/uart.h b/arch/arm/include/asm/arch-tegra20/uart.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/uart.h rename to arch/arm/include/asm/arch-tegra20/uart.h diff --git a/arch/arm/include/asm/arch-tegra2/usb.h b/arch/arm/include/asm/arch-tegra20/usb.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/usb.h rename to arch/arm/include/asm/arch-tegra20/usb.h diff --git a/arch/arm/include/asm/arch-tegra2/warmboot.h b/arch/arm/include/asm/arch-tegra20/warmboot.h similarity index 100% rename from arch/arm/include/asm/arch-tegra2/warmboot.h rename to arch/arm/include/asm/arch-tegra20/warmboot.h diff --git a/boards.cfg b/boards.cfg index 0dee43f..8e46d08 100644 --- a/boards.cfg +++ b/boards.cfg @@ -228,9 +228,9 @@ s5pc210_universal arm armv7 universal_c210 samsung smdk5250 arm armv7 smdk5250 samsung exynos smdkv310 arm armv7 smdkv310 samsung exynos trats arm armv7 trats samsung exynos -harmony arm armv7 harmony nvidia tegra2 -seaboard arm armv7 seaboard nvidia tegra2 -ventana arm armv7 ventana nvidia tegra2 +harmony arm armv7 harmony nvidia tegra20 +seaboard arm armv7 seaboard nvidia tegra20 +ventana arm armv7 ventana nvidia tegra20 u8500_href arm armv7 u8500 st-ericsson u8500 actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB @@ -256,9 +256,9 @@ xaeniax arm pxa zipitz2 arm pxa colibri_pxa270 arm pxa - toradex jornada arm sa1100 -plutux arm armv7 plutux avionic-design tegra2 -medcom arm armv7 medcom avionic-design tegra2 -paz00 arm armv7 paz00 compal tegra2 +plutux arm armv7 plutux avionic-design tegra20 +medcom arm armv7 medcom avionic-design tegra20 +paz00 arm armv7 paz00 compal tegra20 atngw100 avr32 at32ap - atmel at32ap700x atstk1002 avr32 at32ap atstk1000 atmel at32ap700x atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
On 06/05/2012 03:20 PM, Allen Martin wrote:
This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code.
diff --git a/boards.cfg b/boards.cfg
This misses a couple of recently added boards - whistler and trimslice.
On Wed, Jun 06, 2012 at 09:11:01AM -0700, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code.
diff --git a/boards.cfg b/boards.cfg
This misses a couple of recently added boards - whistler and trimslice.
I based the series off u-boot/master, I'll rebase against u-boot-tegra/next
In preparation for splitting out the armv4t code from tegra20, move the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
Signed-off-by: Allen Martin amartin@nvidia.com --- Makefile | 3 ++ arch/arm/cpu/armv7/tegra20/Makefile | 15 ++------- .../cpu/{armv7/tegra20 => tegra20-common}/Makefile | 32 ++++++++++---------- .../cpu/{armv7/tegra20 => tegra20-common}/ap20.c | 0 .../cpu/{armv7/tegra20 => tegra20-common}/board.c | 0 .../cpu/{armv7/tegra20 => tegra20-common}/clock.c | 0 .../cpu/{armv7/tegra20 => tegra20-common}/crypto.c | 0 .../cpu/{armv7/tegra20 => tegra20-common}/crypto.h | 0 .../cpu/{armv7/tegra20 => tegra20-common}/emc.c | 0 .../{armv7/tegra20 => tegra20-common}/funcmux.c | 0 .../tegra20 => tegra20-common}/lowlevel_init.S | 0 .../cpu/{armv7/tegra20 => tegra20-common}/pinmux.c | 0 .../cpu/{armv7/tegra20 => tegra20-common}/pmu.c | 0 .../{armv7/tegra20 => tegra20-common}/sys_info.c | 0 .../cpu/{armv7/tegra20 => tegra20-common}/timer.c | 0 .../{armv7/tegra20 => tegra20-common}/warmboot.c | 0 .../tegra20 => tegra20-common}/warmboot_avp.c | 0 .../tegra20 => tegra20-common}/warmboot_avp.h | 0 spl/Makefile | 4 +++ 19 files changed, 25 insertions(+), 29 deletions(-) copy arch/arm/cpu/{armv7/tegra20 => tegra20-common}/Makefile (68%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/ap20.c (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/board.c (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/clock.c (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/crypto.c (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/crypto.h (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/emc.c (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/funcmux.c (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/lowlevel_init.S (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/pinmux.c (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/pmu.c (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/sys_info.c (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/timer.c (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/warmboot.c (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/warmboot_avp.c (100%) rename arch/arm/cpu/{armv7/tegra20 => tegra20-common}/warmboot_avp.h (100%)
diff --git a/Makefile b/Makefile index 351a8f0..b2275ed 100644 --- a/Makefile +++ b/Makefile @@ -319,6 +319,9 @@ endif ifeq ($(SOC),exynos) LIBS += $(CPUDIR)/s5p-common/libs5p-common.o endif +ifeq ($(SOC),tegra20) +LIBS += $(OBJTREE)/arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o +endif
LIBS := $(addprefix $(obj),$(sort $(LIBS))) .PHONY : $(LIBS) diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/armv7/tegra20/Makefile index 08c4137..09a0314 100644 --- a/arch/arm/cpu/armv7/tegra20/Makefile +++ b/arch/arm/cpu/armv7/tegra20/Makefile @@ -23,26 +23,15 @@ # MA 02111-1307 USA #
-# The AVP is ARMv4T architecture so we must use special compiler -# flags for any startup files it might use. -CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t -CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t -CFLAGS_arch/arm/cpu/armv7/tegra2/warmboot_avp.o += -march=armv4t - include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
-SOBJS := lowlevel_init.o -COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o -COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o -COBJS-$(CONFIG_TEGRA_PMU) += pmu.o COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o -COBJS-$(CONFIG_TEGRA2_LP0) += crypto.o warmboot.o warmboot_avp.o
COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS))
all: $(obj).depend $(LIB)
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/tegra20-common/Makefile similarity index 68% copy from arch/arm/cpu/armv7/tegra20/Makefile copy to arch/arm/cpu/tegra20-common/Makefile index 08c4137..84a24ff 100644 --- a/arch/arm/cpu/armv7/tegra20/Makefile +++ b/arch/arm/cpu/tegra20-common/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2010,2011 Nvidia Corporation. # -# (C) Copyright 2000-2003 +# (C) Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -14,7 +14,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -23,32 +23,32 @@ # MA 02111-1307 USA #
+include $(TOPDIR)/config.mk + # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. -CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t -CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t -CFLAGS_arch/arm/cpu/armv7/tegra2/warmboot_avp.o += -march=armv4t +CFLAGS_arch/arm/cpu/tegra2-common/ap20.o += -march=armv4t +CFLAGS_arch/arm/cpu/tegra2-common/clock.o += -march=armv4t
-include $(TOPDIR)/config.mk +LIB = $(obj)lib$(SOC)-common.o
-LIB = $(obj)lib$(SOC).o - -SOBJS := lowlevel_init.o -COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +SOBJS += lowlevel_init.o +COBJS-y += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-$(CONFIG_TEGRA2_LP0) += warmboot.o crypto.o warmboot_avp.o COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o COBJS-$(CONFIG_TEGRA_PMU) += pmu.o -COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o -COBJS-$(CONFIG_TEGRA2_LP0) += crypto.o warmboot.o warmboot_avp.o
-COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-all: $(obj).depend $(LIB) +all: $(obj).depend $(LIB)
$(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS))
+$(obj).depend: + echo wtf + #########################################################################
# defines $(obj).depend target diff --git a/arch/arm/cpu/armv7/tegra20/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c similarity index 100% rename from arch/arm/cpu/armv7/tegra20/ap20.c rename to arch/arm/cpu/tegra20-common/ap20.c diff --git a/arch/arm/cpu/armv7/tegra20/board.c b/arch/arm/cpu/tegra20-common/board.c similarity index 100% rename from arch/arm/cpu/armv7/tegra20/board.c rename to arch/arm/cpu/tegra20-common/board.c diff --git a/arch/arm/cpu/armv7/tegra20/clock.c b/arch/arm/cpu/tegra20-common/clock.c similarity index 100% rename from arch/arm/cpu/armv7/tegra20/clock.c rename to arch/arm/cpu/tegra20-common/clock.c diff --git a/arch/arm/cpu/armv7/tegra20/crypto.c b/arch/arm/cpu/tegra20-common/crypto.c similarity index 100% rename from arch/arm/cpu/armv7/tegra20/crypto.c rename to arch/arm/cpu/tegra20-common/crypto.c diff --git a/arch/arm/cpu/armv7/tegra20/crypto.h b/arch/arm/cpu/tegra20-common/crypto.h similarity index 100% rename from arch/arm/cpu/armv7/tegra20/crypto.h rename to arch/arm/cpu/tegra20-common/crypto.h diff --git a/arch/arm/cpu/armv7/tegra20/emc.c b/arch/arm/cpu/tegra20-common/emc.c similarity index 100% rename from arch/arm/cpu/armv7/tegra20/emc.c rename to arch/arm/cpu/tegra20-common/emc.c diff --git a/arch/arm/cpu/armv7/tegra20/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c similarity index 100% rename from arch/arm/cpu/armv7/tegra20/funcmux.c rename to arch/arm/cpu/tegra20-common/funcmux.c diff --git a/arch/arm/cpu/armv7/tegra20/lowlevel_init.S b/arch/arm/cpu/tegra20-common/lowlevel_init.S similarity index 100% rename from arch/arm/cpu/armv7/tegra20/lowlevel_init.S rename to arch/arm/cpu/tegra20-common/lowlevel_init.S diff --git a/arch/arm/cpu/armv7/tegra20/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c similarity index 100% rename from arch/arm/cpu/armv7/tegra20/pinmux.c rename to arch/arm/cpu/tegra20-common/pinmux.c diff --git a/arch/arm/cpu/armv7/tegra20/pmu.c b/arch/arm/cpu/tegra20-common/pmu.c similarity index 100% rename from arch/arm/cpu/armv7/tegra20/pmu.c rename to arch/arm/cpu/tegra20-common/pmu.c diff --git a/arch/arm/cpu/armv7/tegra20/sys_info.c b/arch/arm/cpu/tegra20-common/sys_info.c similarity index 100% rename from arch/arm/cpu/armv7/tegra20/sys_info.c rename to arch/arm/cpu/tegra20-common/sys_info.c diff --git a/arch/arm/cpu/armv7/tegra20/timer.c b/arch/arm/cpu/tegra20-common/timer.c similarity index 100% rename from arch/arm/cpu/armv7/tegra20/timer.c rename to arch/arm/cpu/tegra20-common/timer.c diff --git a/arch/arm/cpu/armv7/tegra20/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c similarity index 100% rename from arch/arm/cpu/armv7/tegra20/warmboot.c rename to arch/arm/cpu/tegra20-common/warmboot.c diff --git a/arch/arm/cpu/armv7/tegra20/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c similarity index 100% rename from arch/arm/cpu/armv7/tegra20/warmboot_avp.c rename to arch/arm/cpu/tegra20-common/warmboot_avp.c diff --git a/arch/arm/cpu/armv7/tegra20/warmboot_avp.h b/arch/arm/cpu/tegra20-common/warmboot_avp.h similarity index 100% rename from arch/arm/cpu/armv7/tegra20/warmboot_avp.h rename to arch/arm/cpu/tegra20-common/warmboot_avp.h diff --git a/spl/Makefile b/spl/Makefile index ea7d475..6d3241f 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -62,6 +62,10 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif
+ifneq ($(CONFIG_TEGRA2),) +LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o +endif + START := $(addprefix $(SPLTREE)/,$(START)) LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y)))
On 06/05/2012 03:20 PM, Allen Martin wrote:
In preparation for splitting out the armv4t code from tegra20, move the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/tegra20-common/Makefile
# The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. -CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t -CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t -CFLAGS_arch/arm/cpu/armv7/tegra2/warmboot_avp.o += -march=armv4t +CFLAGS_arch/arm/cpu/tegra2-common/ap20.o += -march=armv4t +CFLAGS_arch/arm/cpu/tegra2-common/clock.o += -march=armv4t
Don't you still need the CFLAGS override for warmboot_avp.o here too? I assume that a later patch will just remove it, but it'd be nice if each patch along the way built and booted OK to, so that "git bisect" works through this series.
-COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
At least in this patch, I don't think SOBJS is set. Does using it here cause build issues?
diff --git a/spl/Makefile b/spl/Makefile
+ifneq ($(CONFIG_TEGRA2),) +LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o +endif
In another file in this patch, that first line was the non-inverted test:
+ifeq ($(SOC),tegra20)
That seems simpler. Can we use the same here?
On Wed, Jun 06, 2012 at 09:16:46AM -0700, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
In preparation for splitting out the armv4t code from tegra20, move the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/tegra20-common/Makefile
# The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. -CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t -CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t -CFLAGS_arch/arm/cpu/armv7/tegra2/warmboot_avp.o += -march=armv4t +CFLAGS_arch/arm/cpu/tegra2-common/ap20.o += -march=armv4t +CFLAGS_arch/arm/cpu/tegra2-common/clock.o += -march=armv4t
Don't you still need the CFLAGS override for warmboot_avp.o here too? I assume that a later patch will just remove it, but it'd be nice if each patch along the way built and booted OK to, so that "git bisect" works through this series.
When I first wrote the series I made sure it booted at each patch, but I didn't reconfirm with all the changes, so it's quite possible I broke that. I'll make sure I preserve that.
-COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
At least in this patch, I don't think SOBJS is set. Does using it here cause build issues?
I'll confirm.
diff --git a/spl/Makefile b/spl/Makefile
+ifneq ($(CONFIG_TEGRA2),) +LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o +endif
In another file in this patch, that first line was the non-inverted test:
+ifeq ($(SOC),tegra20)
That seems simpler. Can we use the same here?
Sure.
-Allen
Add support for specifying a differnt CPU for main u-boot and SPL u-boot builds. This is done by adding an optional SPL CPU after the main CPU in boards.cfg as follows:
normal_cpu:spl_cpu
This this case CPU will be set to "normal_cpu" during the main u-boot build and "spl_cpu" during the SPL build.
Signed-off-by: Allen Martin amartin@nvidia.com --- boards.cfg | 5 +++++ doc/README.SPL | 12 ++++++++++++ mkconfig | 15 ++++++++++++++- 3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/boards.cfg b/boards.cfg index 8e46d08..0e571aa 100644 --- a/boards.cfg +++ b/boards.cfg @@ -11,6 +11,11 @@ # Lines starting with '#' are comments. # Blank lines are ignored. # +# The CPU field takes the form: +# cpu[:spl_cpu] +# If spl_cpu is specified the make variable CPU will be set to this +# during the SPL build. +# # The options field takes the form: # <board config name>[:comma separated config options] # Each config option has the form (value defaults to "1"): diff --git a/doc/README.SPL b/doc/README.SPL index 0276953..e4a5ac3 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -66,3 +66,15 @@ CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o) CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o) CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o) CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o) + + +Normally CPU is assumed to be the same between the SPL and normal +u-boot build. However it is possible to specify a different CPU for +the SPL build for cases where the SPL is expected to run on a +different CPU model from the main u-boot. This is done by specifying +an SPL CPU in boards.cfg as follows: + + normal_cpu:spl_cpu + +This this case CPU will be set to "normal_cpu" during the main u-boot +build and "spl_cpu" during the SPL build. diff --git a/mkconfig b/mkconfig index 438530b..82660a6 100755 --- a/mkconfig +++ b/mkconfig @@ -60,6 +60,11 @@ CONFIG_NAME="${1%_config}"
arch="$2" cpu="$3" +tmp="${cpu#*:}" +if [ "$tmp" != "$cpu" ] ; then + spl_cpu=$tmp + cpu="${cpu%:*}" +fi if [ "$4" = "-" ] ; then board=${BOARD_NAME} else @@ -131,7 +136,15 @@ fi # Create include file for Make # echo "ARCH = ${arch}" > config.mk -echo "CPU = ${cpu}" >> config.mk +if [ ! -z "$spl_cpu" ] ; then + echo 'ifeq ($(CONFIG_SPL_BUILD),y)' >> config.mk + echo "CPU = ${spl_cpu}" >> config.mk + echo "else" >> config.mk + echo "CPU = ${cpu}" >> config.mk + echo "endif" >> config.mk +else + echo "CPU = ${cpu}" >> config.mk +fi echo "BOARD = ${board}" >> config.mk
[ "${vendor}" ] && echo "VENDOR = ${vendor}" >> config.mk
On 06/05/2012 03:20 PM, Allen Martin wrote:
Add support for specifying a differnt CPU for main u-boot and SPL
typo ^^
u-boot builds. This is done by adding an optional SPL CPU after the main CPU in boards.cfg as follows:
normal_cpu:spl_cpuThis this case CPU will be set to "normal_cpu" during the main u-boot build and "spl_cpu" during the SPL build.
diff --git a/mkconfig b/mkconfig
+tmp="${cpu#*:}" +if [ "$tmp" != "$cpu" ] ; then
- spl_cpu=$tmp
- cpu="${cpu%:*}"
+fi
Neat - I wasn't aware of those variable expansion techniques.
However, this script runs under /bin/sh - are they standard sh constructs, or are they bash-isms? I wonder if shelling out to awk or cut here would be more portable?
On Wed, Jun 06, 2012 at 09:20:22AM -0700, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
Add support for specifying a differnt CPU for main u-boot and SPL
typo ^^
Got it, thanks.
u-boot builds. This is done by adding an optional SPL CPU after the main CPU in boards.cfg as follows:
normal_cpu:spl_cpuThis this case CPU will be set to "normal_cpu" during the main u-boot build and "spl_cpu" during the SPL build.
diff --git a/mkconfig b/mkconfig
+tmp="${cpu#*:}" +if [ "$tmp" != "$cpu" ] ; then
- spl_cpu=$tmp
- cpu="${cpu%:*}"
+fi
Neat - I wasn't aware of those variable expansion techniques.
However, this script runs under /bin/sh - are they standard sh constructs, or are they bash-isms? I wonder if shelling out to awk or cut here would be more portable?
It's bash, I'll rewrite it with awk.
-Allen
Take a few SPL fixes from armv7 and apply them to arm720t: -Use dummy exception handlers for SPL build -Initialize relocation register r9 to 0 for the case of no relocation -ifdef out interrupt handler code
Signed-off-by: Allen Martin amartin@nvidia.com --- arch/arm/cpu/arm720t/start.S | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 540e3c2..df66946 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -51,6 +51,15 @@ _start: b reset ldr pc, _irq ldr pc, _fiq
+#ifdef CONFIG_SPL_BUILD +_undefined_instruction: .word _undefined_instruction +_software_interrupt: .word _software_interrupt +_prefetch_abort: .word _prefetch_abort +_data_abort: .word _data_abort +_not_used: .word _not_used +_irq: .word _irq +_fiq: .word _fiq +#else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort @@ -58,6 +67,7 @@ _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq +#endif /* CONFIG_SPL_BUILD */
.balignl 16,0xdeadbeef
@@ -167,6 +177,7 @@ stack_setup:
adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs @@ -425,6 +436,7 @@ lock_loop: mov pc, lr
+#ifndef CONFIG_SPL_BUILD /* ************************************************************************* * @@ -587,6 +599,7 @@ fiq: bl do_fiq
#endif +#endif /* CONFIG_SPL_BUILD */
#if defined(CONFIG_NETARM) .align 5
Don't use timer_init from tegra board.c. This comes out of arm720t for the SPL build.
Signed-off-by: Allen Martin amartin@nvidia.com --- board/nvidia/common/board.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 2e22133..4864949 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -49,6 +49,7 @@ const struct tegra2_sysinfo sysinfo = { CONFIG_TEGRA2_BOARD_STRING };
+#ifndef CONFIG_SPL_BUILD /* * Routine: timer_init * Description: init the timestamp and lastinc value @@ -57,6 +58,7 @@ int timer_init(void) { return 0; } +#endif
void __pin_mux_usb(void) {
Add support for tegra20 arm7 boot processor. This processor is used to power on the Cortex A9 and transfer control to it.
Signed-off-by: Allen Martin amartin@nvidia.com --- arch/arm/cpu/arm720t/cpu.c | 2 + arch/arm/cpu/arm720t/interrupts.c | 4 + arch/arm/cpu/arm720t/start.S | 6 +- arch/arm/cpu/arm720t/tegra20/Makefile | 48 +++++ arch/arm/cpu/arm720t/tegra20/board.h | 25 +++ arch/arm/cpu/arm720t/tegra20/cpu.c | 259 ++++++++++++++++++++++++++ arch/arm/cpu/arm720t/tegra20/cpu.h | 99 ++++++++++ arch/arm/cpu/arm720t/tegra20/spl.c | 133 +++++++++++++ arch/arm/include/asm/arch-tegra20/hardware.h | 29 +++ 9 files changed, 604 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/arm720t/tegra20/Makefile create mode 100644 arch/arm/cpu/arm720t/tegra20/board.h create mode 100644 arch/arm/cpu/arm720t/tegra20/cpu.c create mode 100644 arch/arm/cpu/arm720t/tegra20/cpu.h create mode 100644 arch/arm/cpu/arm720t/tegra20/spl.c create mode 100644 arch/arm/include/asm/arch-tegra20/hardware.h
diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index 974f288..dd46809 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -51,6 +51,8 @@ int cleanup_before_linux (void) /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No cleanup before linux for IntegratorAP/CM720T as yet */ +#elif defined (CONFIG_MACH_TEGRA_GENERIC) + /* No cleanup before linux for tegra as yet */ #else #error No cleanup_before_linux() defined for this CPU type #endif diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 464dd30..6473f0e 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -180,6 +180,8 @@ int timer_init (void) PUT32(T0TC, 0); PUT32(T0TCR, 1); /* enable timer0 */
+#elif defined(CONFIG_MACH_TEGRA_GENERIC) + /* No timer routines for tegra as yet */ #else #error No timer_init() defined for this CPU type #endif @@ -282,6 +284,8 @@ void __udelay (unsigned long usec)
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No timer routines for IntegratorAP/CM720T as yet */ +#elif defined(CONFIG_MACH_TEGRA_GENERIC) + /* No timer routines for tegra as yet */ #else #error Timer routines not defined for this CPU type #endif diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index df66946..e79b1be 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -407,6 +407,8 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] +#elif defined(CONFIG_MACH_TEGRA_GENERIC) + /* No cpu_init_crit for tegra as yet */ #else #error No cpu_init_crit() defined for current CPU type #endif @@ -422,7 +424,7 @@ lock_loop: str r1, [r0] #endif
-#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2292) && !defined(CONFIG_MACH_TEGRA_GENERIC) mov ip, lr /* * before relocating, we have to setup RAM timing @@ -631,6 +633,8 @@ reset_cpu: .globl reset_cpu reset_cpu: mov pc, r0 +#elif defined(CONFIG_MACH_TEGRA_GENERIC) + /* No specific reset actions for tegra as yet */ #else #error No reset_cpu() defined for current CPU type #endif diff --git a/arch/arm/cpu/arm720t/tegra20/Makefile b/arch/arm/cpu/arm720t/tegra20/Makefile new file mode 100644 index 0000000..6e48475 --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra20/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2010,2011 Nvidia Corporation. +# +# (C) Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS-y += cpu.o +COBJS-$(CONFIG_SPL_BUILD) += spl.o + +SRCS := $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm720t/tegra20/board.h b/arch/arm/cpu/arm720t/tegra20/board.h new file mode 100644 index 0000000..61b91c0 --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra20/board.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2010-2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +void board_init_uart_f(void); +void gpio_config_uart(void); diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/cpu/arm720t/tegra20/cpu.c new file mode 100644 index 0000000..00a82b1 --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra20/cpu.c @@ -0,0 +1,259 @@ +/* +* (C) Copyright 2010-2011 +* NVIDIA Corporation <www.nvidia.com> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <asm/io.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/pmc.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/scu.h> +#include <common.h> +#include "cpu.h" + +/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */ +int ap20_cpu_is_cortexa9(void) +{ + u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0); + return id == (PG_UP_TAG_0_PID_CPU & 0xff); +} + +void init_pllx(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU]; + u32 reg; + + /* If PLLX is already enabled, just return */ + if (readl(&pll->pll_base) & PLL_ENABLE_MASK) + return; + + /* Set PLLX_MISC */ + writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc); + + /* Use 12MHz clock here */ + reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT); + reg |= 1000 << PLL_DIVN_SHIFT; + writel(reg, &pll->pll_base); + + reg |= PLL_ENABLE_MASK; + writel(reg, &pll->pll_base); + + reg &= ~PLL_BYPASS_MASK; + writel(reg, &pll->pll_base); +} + +static void enable_cpu_clock(int enable) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 clk; + + /* + * NOTE: + * Regardless of whether the request is to enable or disable the CPU + * clock, every processor in the CPU complex except the master (CPU 0) + * will have it's clock stopped because the AVP only talks to the + * master. The AVP does not know (nor does it need to know) that there + * are multiple processors in the CPU complex. + */ + + if (enable) { + /* Initialize PLLX */ + init_pllx(); + + /* Wait until all clocks are stable */ + udelay(PLL_STABILIZATION_DELAY); + + writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); + writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); + } + + /* + * Read the register containing the individual CPU clock enables and + * always stop the clock to CPU 1. + */ + clk = readl(&clkrst->crc_clk_cpu_cmplx); + clk |= 1 << CPU1_CLK_STP_SHIFT; + + /* Stop/Unstop the CPU clock */ + clk &= ~CPU0_CLK_STP_MASK; + clk |= !enable << CPU0_CLK_STP_SHIFT; + writel(clk, &clkrst->crc_clk_cpu_cmplx); + + clock_enable(PERIPH_ID_CPU); +} + +static int is_cpu_powered(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + + return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; +} + +static void remove_cpu_io_clamps(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + u32 reg; + + /* Remove the clamps on the CPU I/O signals */ + reg = readl(&pmc->pmc_remove_clamping); + reg |= CPU_CLMP; + writel(reg, &pmc->pmc_remove_clamping); + + /* Give I/O signals time to stabilize */ + udelay(IO_STABILIZATION_DELAY); +} + +static void powerup_cpu(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + u32 reg; + int timeout = IO_STABILIZATION_DELAY; + + if (!is_cpu_powered()) { + /* Toggle the CPU power state (OFF -> ON) */ + reg = readl(&pmc->pmc_pwrgate_toggle); + reg &= PARTID_CP; + reg |= START_CP; + writel(reg, &pmc->pmc_pwrgate_toggle); + + /* Wait for the power to come up */ + while (!is_cpu_powered()) { + if (timeout-- == 0) + printf("CPU failed to power up!\n"); + else + udelay(10); + } + + /* + * Remove the I/O clamps from CPU power partition. + * Recommended only on a Warm boot, if the CPU partition gets + * power gated. Shouldn't cause any harm when called after a + * cold boot according to HW, probably just redundant. + */ + remove_cpu_io_clamps(); + } +} + +static void enable_cpu_power_rail(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + u32 reg; + + reg = readl(&pmc->pmc_cntrl); + reg |= CPUPWRREQ_OE; + writel(reg, &pmc->pmc_cntrl); + + /* + * The TI PMU65861C needs a 3.75ms delay between enabling + * the power rail and enabling the CPU clock. This delay + * between SM1EN and SM1 is for switching time + the ramp + * up of the voltage to the CPU (VDD_CPU from PMU). + */ + udelay(3750); +} + +static void reset_A9_cpu(int reset) +{ + /* + * NOTE: Regardless of whether the request is to hold the CPU in reset + * or take it out of reset, every processor in the CPU complex + * except the master (CPU 0) will be held in reset because the + * AVP only talks to the master. The AVP does not know that there + * are multiple processors in the CPU complex. + */ + + /* Hold CPU 1 in reset, and CPU 0 if asked */ + reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1); + reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug, + reset); + + /* Enable/Disable master CPU reset */ + reset_set_enable(PERIPH_ID_CPU, reset); +} + +static void clock_enable_coresight(int enable) +{ + u32 rst, src; + + clock_set_enable(PERIPH_ID_CORESIGHT, enable); + reset_set_enable(PERIPH_ID_CORESIGHT, !enable); + + if (enable) { + /* + * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by + * 1.5, giving an effective frequency of 144MHz. + * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor + * (bits 7:0), so 00000001b == 1.5 (n+1 + .5) + */ + src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); + clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src); + + /* Unlock the CPU CoreSight interfaces */ + rst = 0xC5ACCE55; + writel(rst, CSITE_CPU_DBG0_LAR); + writel(rst, CSITE_CPU_DBG1_LAR); + } +} + +void start_cpu(u32 reset_vector) +{ + /* Enable VDD_CPU */ + enable_cpu_power_rail(); + + /* Hold the CPUs in reset */ + reset_A9_cpu(1); + + /* Disable the CPU clock */ + enable_cpu_clock(0); + + /* Enable CoreSight */ + clock_enable_coresight(1); + + /* + * Set the entry point for CPU execution from reset, + * if it's a non-zero value. + */ + if (reset_vector) + writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); + + /* Enable the CPU clock */ + enable_cpu_clock(1); + + /* If the CPU doesn't already have power, power it up */ + powerup_cpu(); + + /* Take the CPU out of reset */ + reset_A9_cpu(0); +} + + +void halt_avp(void) +{ + for (;;) { + writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \ + | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)), + FLOW_CTLR_HALT_COP_EVENTS); + } +} + diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.h b/arch/arm/cpu/arm720t/tegra20/cpu.h new file mode 100644 index 0000000..90857a8 --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra20/cpu.h @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2010-2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <asm/types.h> + +/* Stabilization delays, in usec */ +#define PLL_STABILIZATION_DELAY (300) +#define IO_STABILIZATION_DELAY (1000) + +#define NVBL_PLLP_KHZ (216000) + +#define PLLX_ENABLED (1 << 30) +#define CCLK_BURST_POLICY 0x20008888 +#define SUPER_CCLK_DIVIDER 0x80000000 + +/* Calculate clock fractional divider value from ref and target frequencies */ +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) + +/* Calculate clock frequency value from reference and clock divider value */ +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) + +/* AVP/CPU ID */ +#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ +#define PG_UP_TAG_0 0x0 + +#define CORESIGHT_UNLOCK 0xC5ACCE55; + +/* AP20-Specific Base Addresses */ + +/* AP20 Base physical address of SDRAM. */ +#define AP20_BASE_PA_SDRAM 0x00000000 +/* AP20 Base physical address of internal SRAM. */ +#define AP20_BASE_PA_SRAM 0x40000000 +/* AP20 Size of internal SRAM (256KB). */ +#define AP20_BASE_PA_SRAM_SIZE 0x00040000 +/* AP20 Base physical address of flash. */ +#define AP20_BASE_PA_NOR_FLASH 0xD0000000 +/* AP20 Base physical address of boot information table. */ +#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM + +/* + * Super-temporary stacks for EXTREMELY early startup. The values chosen for + * these addresses must be valid on ALL SOCs because this value is used before + * we are able to differentiate between the SOC types. + * + * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its + * stack is placed below the AVP stack. Once the CPU stack has been moved, + * the AVP is free to use the IRAM the CPU stack previously occupied if + * it should need to do so. + * + * NOTE: In multi-processor CPU complex configurations, each processor will have + * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a + * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a + * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous + * CPU. + */ + +/* Common AVP early boot stack limit */ +#define AVP_EARLY_BOOT_STACK_LIMIT \ + (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2)) +/* Common AVP early boot stack size */ +#define AVP_EARLY_BOOT_STACK_SIZE 0x1000 +/* Common CPU early boot stack limit */ +#define CPU_EARLY_BOOT_STACK_LIMIT \ + (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE) +/* Common CPU early boot stack size */ +#define CPU_EARLY_BOOT_STACK_SIZE 0x1000 + +#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) +#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) +#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) + +#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) +#define FLOW_MODE_STOP 2 +#define HALT_COP_EVENT_JTAG (1 << 28) +#define HALT_COP_EVENT_IRQ_1 (1 << 11) +#define HALT_COP_EVENT_FIQ_1 (1 << 9) + +void start_cpu(u32 reset_vector); +int ap20_cpu_is_cortexa9(void); diff --git a/arch/arm/cpu/arm720t/tegra20/spl.c b/arch/arm/cpu/arm720t/tegra20/spl.c new file mode 100644 index 0000000..d467ab2 --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra20/spl.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2012 + * NVIDIA Inc, <www.nvidia.com> + * + * Allen Martin amartin@nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <nand.h> +#include <mmc.h> +#include <fat.h> +#include <version.h> +#include <i2c.h> +#include <image.h> +#include <malloc.h> +#include <linux/compiler.h> +#include "board.h" +#include "cpu.h" + +#include <asm/io.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/pmc.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/scu.h> +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Define global data structure pointer to it*/ +static gd_t gdata __attribute__ ((section(".data"))); +static bd_t bdata __attribute__ ((section(".data"))); + +inline void hang(void) +{ + puts("### ERROR ### Please RESET the board ###\n"); + for (;;) + ; +} + +void board_init_f(ulong dummy) +{ + board_init_uart_f(); + + /* Initialize periph GPIOs */ +#ifdef CONFIG_SPI_UART_SWITCH + gpio_early_init_uart(); +#else + gpio_config_uart(); +#endif + + /* + * We call relocate_code() with relocation target same as the + * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting + * skipped. Instead, only .bss initialization will happen. That's + * all we need + */ + debug(">>board_init_f()\n"); + relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE); +} + +/* This requires UART clocks to be enabled */ +static void preloader_console_init(void) +{ + const char *u_boot_rev = U_BOOT_VERSION; + + gd = &gdata; + gd->bd = &bdata; + gd->flags |= GD_FLG_RELOC; + gd->baudrate = CONFIG_BAUDRATE; + + serial_init(); /* serial communications setup */ + + gd->have_console = 1; + + /* Avoid a second "U-Boot" coming from this string */ + u_boot_rev = &u_boot_rev[7]; + + printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE, + U_BOOT_TIME); +} + +void board_init_r(gd_t *id, ulong dummy) +{ + u32 boot_device; + struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + debug(">>spl:board_init_r()\n"); + + mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, + CONFIG_SYS_SPL_MALLOC_SIZE); + +#ifdef CONFIG_SPL_BOARD_INIT + spl_board_init(); +#endif + + clock_early_init(); + serial_init(); + preloader_console_init(); + + /* enable JTAG */ + writel(0xC0, &pmt->pmt_cfg_ctl); + + start_cpu((u32)CONFIG_SYS_TEXT_BASE); + halt_avp(); + /* not reached */ +} + +int board_usb_init(const void *blob) +{ + return 0; +} diff --git a/arch/arm/include/asm/arch-tegra20/hardware.h b/arch/arm/include/asm/arch-tegra20/hardware.h new file mode 100644 index 0000000..8c47578 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/hardware.h @@ -0,0 +1,29 @@ +/* +* (C) Copyright 2010-2011 +* NVIDIA Corporation <www.nvidia.com> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#ifndef __TEGRA2_HW_H +#define __TEGRA2_HW_H + +/* include tegra specific hardware definitions */ + +#endif /* __TEGRA2_HW_H */
On 06/05/2012 03:20 PM, Allen Martin wrote:
Add support for tegra20 arm7 boot processor. This processor is used to power on the Cortex A9 and transfer control to it.
diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No cleanup before linux for IntegratorAP/CM720T as yet */ +#elif defined (CONFIG_MACH_TEGRA_GENERIC)
- /* No cleanup before linux for tegra as yet */
#else #error No cleanup_before_linux() defined for this CPU type #endif
Wouldn't CONFIG_TEGRA2 be a better define to use? Same comment throughout.
diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/cpu/arm720t/tegra20/cpu.c
+/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */ +int ap20_cpu_is_cortexa9(void) +{
- u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
- return id == (PG_UP_TAG_0_PID_CPU & 0xff);
+}
Doesn't the SPL always run on the AVP, and the regular U-Boot build always run on the main CPUs - I'm not sure why this runtime API would be needed.
+void init_pllx(void)
I assume a lot of the code in this file is copied from the armv7/tegra20/*.c files. Shouldn't this patch remove the ARMv7 versions since presumably it's no longer needed - doesn't the non-SPL U-Boot rely on the SPL U-Boot always having run first in order to start the main U-Boot executing?
If not, then shouldn't this code be in tegra20-common so it can be shared?
diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.h b/arch/arm/cpu/arm720t/tegra20/cpu.h
Similarly, this file seems like it'd be in tegra20-common/include or somewhere like that.
On Wed, Jun 06, 2012 at 09:39:57AM -0700, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
Add support for tegra20 arm7 boot processor. This processor is used to power on the Cortex A9 and transfer control to it.
diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No cleanup before linux for IntegratorAP/CM720T as yet */ +#elif defined (CONFIG_MACH_TEGRA_GENERIC)
- /* No cleanup before linux for tegra as yet */
#else #error No cleanup_before_linux() defined for this CPU type #endif
Wouldn't CONFIG_TEGRA2 be a better define to use? Same comment throughout.
The SPL *should* work on tegra30 with only minor changes, so just trying to look forward.
diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/cpu/arm720t/tegra20/cpu.c
+/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */ +int ap20_cpu_is_cortexa9(void) +{
- u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
- return id == (PG_UP_TAG_0_PID_CPU & 0xff);
+}
Doesn't the SPL always run on the AVP, and the regular U-Boot build always run on the main CPUs - I'm not sure why this runtime API would be needed.
I think this is just a holdover from the old code, I'll look at purging it.
+void init_pllx(void)
I assume a lot of the code in this file is copied from the armv7/tegra20/*.c files. Shouldn't this patch remove the ARMv7 versions since presumably it's no longer needed - doesn't the non-SPL U-Boot rely on the SPL U-Boot always having run first in order to start the main U-Boot executing?
Yes, I remove some of it in "tegra20: Remove CPU init code from tegra20 u-boot". I'll look at rolling that patch into this one, but I originally made it two patches to try to preserve building and booting at every patch.
If not, then shouldn't this code be in tegra20-common so it can be shared?
diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.h b/arch/arm/cpu/arm720t/tegra20/cpu.h
Similarly, this file seems like it'd be in tegra20-common/include or somewhere like that.
Those defines are only used for the Cortex A9 init, so it should only be needed from the SPL.
-Allen
On 06/06/2012 12:25 PM, Allen Martin wrote:
On Wed, Jun 06, 2012 at 09:39:57AM -0700, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
Add support for tegra20 arm7 boot processor. This processor is used to power on the Cortex A9 and transfer control to it.
diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No cleanup before linux for IntegratorAP/CM720T as yet */ +#elif defined (CONFIG_MACH_TEGRA_GENERIC)
- /* No cleanup before linux for tegra as yet */
#else #error No cleanup_before_linux() defined for this CPU type #endif
Wouldn't CONFIG_TEGRA2 be a better define to use? Same comment throughout.
The SPL *should* work on tegra30 with only minor changes, so just trying to look forward.
Oh, I see. MACH_TEGRA_GENERIC means "some Tegra SoC", and CONFIG_TEGRA* indicate which one. Coming from my kernel background, MACH_* is a define for a particular board, and we do have a GENERIC Tegra board, so I got the wrong end of the stick.
I wonder if it's worth renaming CONFIG_MACH_TEGRA_GENERIC to CONFIG_TEGRA. There don't appear to be any users of it currently.
On Wed, Jun 06, 2012 at 12:17:53PM -0700, Stephen Warren wrote:
Oh, I see. MACH_TEGRA_GENERIC means "some Tegra SoC", and CONFIG_TEGRA* indicate which one. Coming from my kernel background, MACH_* is a define for a particular board, and we do have a GENERIC Tegra board, so I got the wrong end of the stick.
I wonder if it's worth renaming CONFIG_MACH_TEGRA_GENERIC to CONFIG_TEGRA. There don't appear to be any users of it currently.
Fine by me, maybe CONFIG_TEGRA2 should go to CONFIG_TEGRA20 also to keep with the new naming?
-Allen
On 06/06/2012 04:18 PM, Allen Martin wrote:
On Wed, Jun 06, 2012 at 12:17:53PM -0700, Stephen Warren wrote:
Oh, I see. MACH_TEGRA_GENERIC means "some Tegra SoC", and CONFIG_TEGRA* indicate which one. Coming from my kernel background, MACH_* is a define for a particular board, and we do have a GENERIC Tegra board, so I got the wrong end of the stick.
I wonder if it's worth renaming CONFIG_MACH_TEGRA_GENERIC to CONFIG_TEGRA. There don't appear to be any users of it currently.
Fine by me, maybe CONFIG_TEGRA2 should go to CONFIG_TEGRA20 also to keep with the new naming?
Sounds reasonable to me.
Add SPL options to tegra20 config files and enable SPL build for seaboard in boards.cfg
Signed-off-by: Allen Martin amartin@nvidia.com --- boards.cfg | 2 +- include/configs/seaboard.h | 6 +++ include/configs/tegra2-common.h | 17 ++++++++ include/configs/tegra2-spl.h | 87 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 include/configs/tegra2-spl.h
diff --git a/boards.cfg b/boards.cfg index 0e571aa..056a022 100644 --- a/boards.cfg +++ b/boards.cfg @@ -234,7 +234,7 @@ smdk5250 arm armv7 smdk5250 samsung exynos smdkv310 arm armv7 smdkv310 samsung exynos trats arm armv7 trats samsung exynos harmony arm armv7 harmony nvidia tegra20 -seaboard arm armv7 seaboard nvidia tegra20 +seaboard arm armv7:arm720t seaboard nvidia tegra20 ventana arm armv7 ventana nvidia tegra20 u8500_href arm armv7 u8500 st-ericsson u8500 actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 46d4228..826483d 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -108,4 +108,10 @@ #define TEGRA2_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \ "stdout=serial\0" \ "stderr=serial\0" + +/* include overrides for SPL build */ +#ifdef CONFIG_SPL_BUILD +#include "tegra2-spl.h" +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 068ce88..8e2732a 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -199,4 +199,21 @@
#define CONFIG_TEGRA2_GPIO #define CONFIG_CMD_GPIO + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x00008000 +#define CONFIG_SPL_MAX_SIZE 0x00078000 +#define CONFIG_SYS_SPL_MALLOC_START 0x00080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 +#define CONFIG_SPL_STACK 0x0009fffc + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra2/u-boot-spl.lds" + #endif /* __TEGRA2_COMMON_H */ diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h new file mode 100644 index 0000000..e1afa78 --- /dev/null +++ b/include/configs/tegra2-spl.h @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2012 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __TEGRA2_SPL_H +#define __TEGRA2_SPL_H + +/* remove devicetree support */ +#ifdef CONFIG_OF_CONTROL +#undef CONFIG_OF_CONTROL +#endif + +/* remove SERIAL_MULTI */ +#ifdef CONFIG_SERIAL_MULTI +#undef CONFIG_SERIAL_MULTI +#endif + +/* remove I2C support */ +#ifdef CONFIG_TEGRA_I2C +#undef CONFIG_TEGRA_I2C +#endif +#ifdef CONFIG_CMD_I2C +#undef CONFIG_CMD_I2C +#endif + +/* remove MMC support */ +#ifdef CONFIG_MMC +#undef CONFIG_MMC +#endif +#ifdef CONFIG_GENERIC_MMC +#undef CONFIG_GENERIC_MMC +#endif +#ifdef CONFIG_TEGRA2_MMC +#undef CONFIG_TEGRA2_MMC +#endif +#ifdef CONFIG_CMD_MMC +#undef CONFIG_CMD_MMC +#endif + +/* remove partitions/filesystems */ +#ifdef CONFIG_DOS_PARTITION +#undef CONFIG_DOS_PARTITION +#endif +#ifdef CONFIG_EFI_PARTITION +#undef CONFIG_EFI_PARTITION +#endif +#ifdef CONFIG_CMD_EXT2 +#undef CONFIG_CMD_EXT2 +#endif +#ifdef CONFIG_CMD_FAT +#undef CONFIG_CMD_FAT +#endif + +/* remove USB */ +#ifdef CONFIG_USB_EHCI +#undef CONFIG_USB_EHCI +#endif +#ifdef CONFIG_USB_EHCI_TEGRA +#undef CONFIG_USB_EHCI_TEGRA +#endif +#ifdef CONFIG_USB_STORAGE +#undef CONFIG_USB_STORAGE +#endif +#ifdef CONFIG_CMD_USB +#undef CONFIG_CMD_USB +#endif + +#endif /* __TEGRA2_SPL_H */
On 06/05/2012 03:20 PM, Allen Martin wrote:
Add SPL options to tegra20 config files and enable SPL build for seaboard in boards.cfg
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
+/* include overrides for SPL build */ +#ifdef CONFIG_SPL_BUILD +#include "tegra2-spl.h" +#endif
Perhaps we should add that to include/configs/tegra2-common-post.h, which I think all Tegra config headers now include at the end.
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
+/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x00008000 +#define CONFIG_SPL_MAX_SIZE 0x00078000 +#define CONFIG_SYS_SPL_MALLOC_START 0x00080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 +#define CONFIG_SPL_STACK 0x0009fffc
+#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
I'm not sure what that's for?
+#define CONFIG_SPL_GPIO_SUPPORT
I believe only Seaboard needs that, not all boards. It'd be nice if we could just ignore the crufy SPI/GPIO switch on Seaboard too and punt this. Does anyone actually boot Seaboard using SPI? I use NAND and Tom uses eMMC...
diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
Being a new file, this should be GPLv2 not GPLv2+.
+/* remove devicetree support */ +#ifdef CONFIG_OF_CONTROL +#undef CONFIG_OF_CONTROL +#endif
I don't /think/ #undef complains if the define isn't defined?
Perhaps this (and the others) are better approached by not defining all these if building SPL though - what if a particular board's SPL actually wanted any of these?
On Wed, Jun 06, 2012 at 09:44:59AM -0700, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
Add SPL options to tegra20 config files and enable SPL build for seaboard in boards.cfg
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
+/* include overrides for SPL build */ +#ifdef CONFIG_SPL_BUILD +#include "tegra2-spl.h" +#endif
Perhaps we should add that to include/configs/tegra2-common-post.h, which I think all Tegra config headers now include at the end.
Ok.
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
+/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x00008000 +#define CONFIG_SPL_MAX_SIZE 0x00078000 +#define CONFIG_SYS_SPL_MALLOC_START 0x00080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 +#define CONFIG_SPL_STACK 0x0009fffc
+#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
I'm not sure what that's for?
Hm, I put it in for the PMU driver, but maybe that's not actually needed in the SPL. I'll take a look.
+#define CONFIG_SPL_GPIO_SUPPORT
I believe only Seaboard needs that, not all boards. It'd be nice if we could just ignore the crufy SPI/GPIO switch on Seaboard too and punt this. Does anyone actually boot Seaboard using SPI? I use NAND and Tom uses eMMC...
Well I use SPI on my Springbank, but maybe I'm in the minority :^)
diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
Being a new file, this should be GPLv2 not GPLv2+.
Ok.
+/* remove devicetree support */ +#ifdef CONFIG_OF_CONTROL +#undef CONFIG_OF_CONTROL +#endif
I don't /think/ #undef complains if the define isn't defined?
I've seen compilers that do, so I was just trying to play it safe.
Perhaps this (and the others) are better approached by not defining all these if building SPL though - what if a particular board's SPL actually wanted any of these?
That's what I had in v1 of the patch series, but it ends up adding a lot of #ifdefs sprinkled through each board config file. I'd like to keep the SPL as small and minimal as possible such that it doesn't need a lot of board specific configuration, just unavoidable things like UART.
-Allen
On Wed Jun 06, 2012 at 10:44:59AM -0600, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
<snip>
diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
Being a new file, this should be GPLv2 not GPLv2+.
u-boot uses GPLv2+.
http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign http://www.mail-archive.com/u-boot@lists.denx.de/msg26569.html
-sughosh
On 06/07/2012 01:15 AM, Sughosh Ganu wrote:
On Wed Jun 06, 2012 at 10:44:59AM -0600, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
<snip>
diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
Being a new file, this should be GPLv2 not GPLv2+.
u-boot uses GPLv2+.
http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign http://www.mail-archive.com/u-boot@lists.denx.de/msg26569.html
Sughosh,
I guess I'm a little confused here.
COPYING in the U-Boot source tree states the following:
U-Boot is Free Software. It is copyrighted by Wolfgang Denk and many others who contributed code (see the actual source code for details). You can redistribute U-Boot and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. Most of it can also be distributed, at your option, under any later version of the GNU General Public License -- see individual files for exceptions.
... which explicitly allows for either GPLv2 or GPLv2+ code. There is certainly GPLv2-only code already in U-Boot. Why do you say that GPLv2-only code isn't allowed?
On Thu Jun 07, 2012 at 10:36:53AM -0600, Stephen Warren wrote:
On 06/07/2012 01:15 AM, Sughosh Ganu wrote:
On Wed Jun 06, 2012 at 10:44:59AM -0600, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
<snip>
diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
Being a new file, this should be GPLv2 not GPLv2+.
u-boot uses GPLv2+.
http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign http://www.mail-archive.com/u-boot@lists.denx.de/msg26569.html
Sughosh,
I guess I'm a little confused here.
COPYING in the U-Boot source tree states the following:
U-Boot is Free Software. It is copyrighted by Wolfgang Denk and many others who contributed code (see the actual source code for details). You can redistribute U-Boot and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. Most of it can also be distributed, at your option, under any later version of the GNU General Public License -- see individual files for exceptions.
... which explicitly allows for either GPLv2 or GPLv2+ code. There is certainly GPLv2-only code already in U-Boot. Why do you say that GPLv2-only code isn't allowed?
I guess that could be because some of the existing files in u-boot are released under GPLv2 only license -- hence a separate mention that most of the files can be distributed under any later version too . Both Wolfgang and Detlev have stated many a times on the mailing list earlier that all new files need to be released under GPLv2+, and not GPLv2 only.
-sughosh
On 06/07/2012 11:04 AM, Sughosh Ganu wrote:
On Thu Jun 07, 2012 at 10:36:53AM -0600, Stephen Warren wrote:
On 06/07/2012 01:15 AM, Sughosh Ganu wrote:
On Wed Jun 06, 2012 at 10:44:59AM -0600, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
<snip>
diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
Being a new file, this should be GPLv2 not GPLv2+.
u-boot uses GPLv2+.
http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign http://www.mail-archive.com/u-boot@lists.denx.de/msg26569.html
Sughosh,
I guess I'm a little confused here.
COPYING in the U-Boot source tree states the following:
U-Boot is Free Software. It is copyrighted by Wolfgang Denk and many others who contributed code (see the actual source code for details). You can redistribute U-Boot and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. Most of it can also be distributed, at your option, under any later version of the GNU General Public License -- see individual files for exceptions.
... which explicitly allows for either GPLv2 or GPLv2+ code. There is certainly GPLv2-only code already in U-Boot. Why do you say that GPLv2-only code isn't allowed?
I guess that could be because some of the existing files in u-boot are released under GPLv2 only license -- hence a separate mention that most of the files can be distributed under any later version too . Both Wolfgang and Detlev have stated many a times on the mailing list earlier that all new files need to be released under GPLv2+, and not GPLv2 only.
Hmmm. It seems like a good idea for COPYING to be updated to be explicit re: why that exemption is there, to avoid future confusion.
I assume the requirement for GPLv2+ only applies to new code written for U-Boot, not existing code that's being taken from or derived from some other GPLv2-only project?
Add target for tegra20 u-boot image. This is a concatenation of tegra spl and normal u-boot binaries.
Signed-off-by: Allen Martin amartin@nvidia.com --- .gitignore | 1 + Makefile | 11 +++++++++++ board/nvidia/seaboard/config.mk | 1 + 3 files changed, 13 insertions(+) create mode 100644 board/nvidia/seaboard/config.mk
diff --git a/.gitignore b/.gitignore index 0f32fd8..b9192bf 100644 --- a/.gitignore +++ b/.gitignore @@ -39,6 +39,7 @@ /u-boot.ais /u-boot.dtb /u-boot.sb +/u-boot.t2
# # Generated files diff --git a/Makefile b/Makefile index b2275ed..6f4abc6 100644 --- a/Makefile +++ b/Makefile @@ -456,6 +456,16 @@ $(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \ -o $(obj)u-boot.sb
+ifeq ($(CONFIG_OF_SEPARATE),y) +T2_UBOOT=$(obj)u-boot-dtb.bin +else +T2_UBOOT=$(obj)u-boot.bin +endif +$(obj)u-boot.t2: $(obj)spl/u-boot-spl.bin $(T2_UBOOT) + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin + cat $(obj)spl/u-boot-spl-pad.bin $(T2_UBOOT) > $(obj)u-boot.t2 + rm $(obj)spl/u-boot-spl-pad.bin + ifeq ($(CONFIG_SANDBOX),y) GEN_UBOOT = \ cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \ @@ -775,6 +785,7 @@ clobber: tidy @rm -f $(obj)u-boot.ais @rm -f $(obj)u-boot.dtb @rm -f $(obj)u-boot.sb + @rm -f $(obj)u-boot.t2 @rm -f $(obj)tools/inca-swap-bytes @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c @rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c diff --git a/board/nvidia/seaboard/config.mk b/board/nvidia/seaboard/config.mk new file mode 100644 index 0000000..1d6e878 --- /dev/null +++ b/board/nvidia/seaboard/config.mk @@ -0,0 +1 @@ +PAD_TO=0x00108000
On 06/05/2012 03:20 PM, Allen Martin wrote:
Add target for tegra20 u-boot image. This is a concatenation of tegra spl and normal u-boot binaries.
diff --git a/board/nvidia/seaboard/config.mk b/board/nvidia/seaboard/config.mk
+PAD_TO=0x00108000
Oh crap, does this mean that we have to start flashing the combined u-boot.t2 at 0x8000 (IIRC the start address of the SPL in an earlier patch) instead of 0x108000? That would cause all kinds of problems. If that is the case, can we move the SPL to the existing 0x108000, and bump the regular U-Boot up a bit to make space? If that isn't the case, could you please explain exactly how the SPL memory layout etc. works for me? Thanks.
On Wed, Jun 06, 2012 at 09:48:23AM -0700, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
Add target for tegra20 u-boot image. This is a concatenation of tegra spl and normal u-boot binaries.
diff --git a/board/nvidia/seaboard/config.mk b/board/nvidia/seaboard/config.mk
+PAD_TO=0x00108000
Oh crap, does this mean that we have to start flashing the combined u-boot.t2 at 0x8000 (IIRC the start address of the SPL in an earlier patch) instead of 0x108000? That would cause all kinds of problems. If that is the case, can we move the SPL to the existing 0x108000, and bump the regular U-Boot up a bit to make space? If that isn't the case, could you please explain exactly how the SPL memory layout etc. works for me? Thanks.
The addresses are arbitrary, I picked 0x8000 for the SPL to preserve the existing 0x108000 for the normal u-boot but it doesn't have to be that way. The only requirement is that the SPL needs to know the address of the normal u-boot at compile time because it doesn't have any smarts to look for it.
I'll move the SPL to 0x108000 and the normal u-boot to 0x208000 if that sounds more acceptable.
-Allen
Allen,
-----Original Message----- From: Allen Martin [mailto:amartin@nvidia.com] Sent: Wednesday, June 06, 2012 12:37 PM To: Stephen Warren Cc: Tom Warren; sjg@chromium.org; u-boot@lists.denx.de Subject: Re: [PATCH v2 08/10] tegra20: add u-boot.t2 target
On Wed, Jun 06, 2012 at 09:48:23AM -0700, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
Add target for tegra20 u-boot image. This is a concatenation of tegra spl and normal u-boot binaries.
diff --git a/board/nvidia/seaboard/config.mk b/board/nvidia/seaboard/config.mk
+PAD_TO=0x00108000
Oh crap, does this mean that we have to start flashing the combined u-boot.t2 at 0x8000 (IIRC the start address of the SPL in an earlier patch) instead of 0x108000? That would cause all kinds of problems. If that is the case, can we move the SPL to the existing 0x108000, and bump the regular U-Boot up a bit to make space? If that isn't the case, could you please explain exactly how the SPL memory layout etc.
works for me?
Thanks.
The addresses are arbitrary, I picked 0x8000 for the SPL to preserve the existing 0x108000 for the normal u-boot but it doesn't have to be that way. The only requirement is that the SPL needs to know the address of the normal u-boot at compile time because it doesn't have any smarts to look for it.
I'll move the SPL to 0x108000 and the normal u-boot to 0x208000 if that sounds more acceptable.
The current flash tools everyone is using expect to flash U-Boot to 0x0108000 (on T20). This works with the non-SPL (current) upstream U-Boot for Tegra, and should continue to work for any new SPL Tegra U-Boot, so that people can use the same flash tools for either build.
Note that the above statement assumes we'll still be able to build either a 'normal' non-SPL build of Tegra U-Boot and a SPL build with your patchset, at least in the interim while we're testing/reviewing these major changes.
Thanks,
Tom
-Allen
On 06/06/2012 01:53 PM, Tom Warren wrote:
Allen,
-----Original Message----- From: Allen Martin [mailto:amartin@nvidia.com] Sent: Wednesday, June 06, 2012 12:37 PM To: Stephen Warren Cc: Tom Warren; sjg@chromium.org; u-boot@lists.denx.de Subject: Re: [PATCH v2 08/10] tegra20: add u-boot.t2 target
On Wed, Jun 06, 2012 at 09:48:23AM -0700, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
Add target for tegra20 u-boot image. This is a concatenation of tegra spl and normal u-boot binaries.
diff --git a/board/nvidia/seaboard/config.mk b/board/nvidia/seaboard/config.mk
+PAD_TO=0x00108000
Oh crap, does this mean that we have to start flashing the combined u-boot.t2 at 0x8000 (IIRC the start address of the SPL in an earlier patch) instead of 0x108000? That would cause all kinds of problems. If that is the case, can we move the SPL to the existing 0x108000, and bump the regular U-Boot up a bit to make space? If that isn't the case, could you please explain exactly how the SPL memory layout etc.
works for me?
Thanks.
The addresses are arbitrary, I picked 0x8000 for the SPL to preserve the existing 0x108000 for the normal u-boot but it doesn't have to be that way. The only requirement is that the SPL needs to know the address of the normal u-boot at compile time because it doesn't have any smarts to look for it.
I'll move the SPL to 0x108000 and the normal u-boot to 0x208000 if that sounds more acceptable.
The current flash tools everyone is using expect to flash U-Boot to 0x0108000 (on T20). This works with the non-SPL (current) upstream U-Boot for Tegra, and should continue to work for any new SPL Tegra U-Boot, so that people can use the same flash tools for either build.
Note that the above statement assumes we'll still be able to build either a 'normal' non-SPL build of Tegra U-Boot and a SPL build with your patchset, at least in the interim while we're testing/reviewing these major changes.
I assume that once a board is converted to SPL, you always use a matched/concatenated pair of SPL+non-SPL, i.e. never SPL on its own or non-SPL on its own?
But that does bring up one point - boards which haven't yet converted to SPL need to still build/link for the original 00108000 address, so the addresses need to depend on config data.
Either that, or just convert all boards at once?
On Wed, Jun 06, 2012 at 12:57:05PM -0700, Stephen Warren wrote:
On 06/06/2012 01:53 PM, Tom Warren wrote:
I'll move the SPL to 0x108000 and the normal u-boot to 0x208000 if that sounds more acceptable.
The current flash tools everyone is using expect to flash U-Boot to 0x0108000 (on T20). This works with the non-SPL (current) upstream U-Boot for Tegra, and should continue to work for any new SPL Tegra U-Boot, so that people can use the same flash tools for either build.
Note that the above statement assumes we'll still be able to build either a 'normal' non-SPL build of Tegra U-Boot and a SPL build with your patchset, at least in the interim while we're testing/reviewing these major changes.
I assume that once a board is converted to SPL, you always use a matched/concatenated pair of SPL+non-SPL, i.e. never SPL on its own or non-SPL on its own?
Yes, that's the intention. Although I do have plans down the road for adding memory initialization to the SPL so I can use it for boot/flashing when in recovery mode and there's no BCT. In the normal case they have to be used together.
But that does bring up one point - boards which haven't yet converted to SPL need to still build/link for the original 00108000 address, so the addresses need to depend on config data.
Either that, or just convert all boards at once?
I'll need to convert all the boards. Since I removed the Cortex A9 init from the normal u-boot it will no longer work for non SPL boot. I think that's what we want anyway, I just may need some help testing some of the boards I don't have.
-Allen
On 06/06/2012 04:00 PM, Allen Martin wrote:
On Wed, Jun 06, 2012 at 12:57:05PM -0700, Stephen Warren wrote:
On 06/06/2012 01:53 PM, Tom Warren wrote:
I'll move the SPL to 0x108000 and the normal u-boot to 0x208000 if that sounds more acceptable.
The current flash tools everyone is using expect to flash U-Boot to 0x0108000 (on T20). This works with the non-SPL (current) upstream U-Boot for Tegra, and should continue to work for any new SPL Tegra U-Boot, so that people can use the same flash tools for either build.
Note that the above statement assumes we'll still be able to build either a 'normal' non-SPL build of Tegra U-Boot and a SPL build with your patchset, at least in the interim while we're testing/reviewing these major changes.
I assume that once a board is converted to SPL, you always use a matched/concatenated pair of SPL+non-SPL, i.e. never SPL on its own or non-SPL on its own?
Yes, that's the intention. Although I do have plans down the road for adding memory initialization to the SPL so I can use it for boot/flashing when in recovery mode and there's no BCT. In the normal case they have to be used together.
How would that work; in the regular boot process, SPL would be linked to e.g. 00108000 since the boot ROM will put it into SDRAM. However, in recovery mode, code will be downloaded to the IRAM, so would have to be linked to a different address, and hence the same SPL binary couldn't be used. At that point, aren't we looking at:
* Regular boot SPL, which just sets up a few PLLs and jump-starts the A9s. * Regular boot full-blown U-Boot to run on the A9s. * Some third build t run from IRAM.
Or am I missing something?
On Wed, Jun 06, 2012 at 07:02:45PM -0700, Stephen Warren wrote:
On 06/06/2012 04:00 PM, Allen Martin wrote:
Yes, that's the intention. Although I do have plans down the road for adding memory initialization to the SPL so I can use it for boot/flashing when in recovery mode and there's no BCT. In the normal case they have to be used together.
How would that work; in the regular boot process, SPL would be linked to e.g. 00108000 since the boot ROM will put it into SDRAM. However, in recovery mode, code will be downloaded to the IRAM, so would have to be linked to a different address, and hence the same SPL binary couldn't be used. At that point, aren't we looking at:
- Regular boot SPL, which just sets up a few PLLs and jump-starts the A9s.
- Regular boot full-blown U-Boot to run on the A9s.
- Some third build t run from IRAM.
Or am I missing something?
No, that's spot on, it's just that #3 and #1 above are very similar, only a few build/config tweaks should separate them. I've already hacked up an SPL to boot from IRAM as proof of concept and loaded it in recovery mode. But you're right, it has to be a separate build.
-Allen
This code is now included in the tegra20 SPL
Signed-off-by: Allen Martin amartin@nvidia.com --- arch/arm/cpu/armv7/start.S | 2 - arch/arm/cpu/tegra20-common/ap20.c | 262 +---------------------------------- arch/arm/cpu/tegra20-common/board.c | 27 +--- include/configs/tegra2-common.h | 4 - 4 files changed, 8 insertions(+), 287 deletions(-)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 261835b..786152f 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -133,7 +133,6 @@ reset: orr r0, r0, #0xd3 msr cpsr,r0
-#if !defined(CONFIG_TEGRA2) /* * Setup vector: * (OMAP4 spl TEXT_BASE is not 32 byte aligned. @@ -149,7 +148,6 @@ reset: ldr r0, =_start mcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif -#endif /* !Tegra2 */
/* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT diff --git a/arch/arm/cpu/tegra20-common/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c index 698bfd0..299f698 100644 --- a/arch/arm/cpu/tegra20-common/ap20.c +++ b/arch/arm/cpu/tegra20-common/ap20.c @@ -20,16 +20,10 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - #include <asm/io.h> -#include <asm/arch/tegra2.h> -#include <asm/arch/ap20.h> -#include <asm/arch/clk_rst.h> -#include <asm/arch/clock.h> #include <asm/arch/fuse.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/pmc.h> -#include <asm/arch/pinmux.h> #include <asm/arch/scu.h> #include <asm/arch/warmboot.h> #include <common.h> @@ -68,233 +62,7 @@ int tegra_get_chip_type(void) return TEGRA_SOC_UNKNOWN; }
-/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */ -static int ap20_cpu_is_cortexa9(void) -{ - u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0); - return id == (PG_UP_TAG_0_PID_CPU & 0xff); -} - -void init_pllx(void) -{ - struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU]; - u32 reg; - - /* If PLLX is already enabled, just return */ - if (readl(&pll->pll_base) & PLL_ENABLE_MASK) - return; - - /* Set PLLX_MISC */ - writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc); - - /* Use 12MHz clock here */ - reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT); - reg |= 1000 << PLL_DIVN_SHIFT; - writel(reg, &pll->pll_base); - - reg |= PLL_ENABLE_MASK; - writel(reg, &pll->pll_base); - - reg &= ~PLL_BYPASS_MASK; - writel(reg, &pll->pll_base); -} - -static void enable_cpu_clock(int enable) -{ - struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - u32 clk; - - /* - * NOTE: - * Regardless of whether the request is to enable or disable the CPU - * clock, every processor in the CPU complex except the master (CPU 0) - * will have it's clock stopped because the AVP only talks to the - * master. The AVP does not know (nor does it need to know) that there - * are multiple processors in the CPU complex. - */ - - if (enable) { - /* Initialize PLLX */ - init_pllx(); - - /* Wait until all clocks are stable */ - udelay(PLL_STABILIZATION_DELAY); - - writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); - writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); - } - - /* - * Read the register containing the individual CPU clock enables and - * always stop the clock to CPU 1. - */ - clk = readl(&clkrst->crc_clk_cpu_cmplx); - clk |= 1 << CPU1_CLK_STP_SHIFT; - - /* Stop/Unstop the CPU clock */ - clk &= ~CPU0_CLK_STP_MASK; - clk |= !enable << CPU0_CLK_STP_SHIFT; - writel(clk, &clkrst->crc_clk_cpu_cmplx); - - clock_enable(PERIPH_ID_CPU); -} - -static int is_cpu_powered(void) -{ - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; - - return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; -} - -static void remove_cpu_io_clamps(void) -{ - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; - u32 reg; - - /* Remove the clamps on the CPU I/O signals */ - reg = readl(&pmc->pmc_remove_clamping); - reg |= CPU_CLMP; - writel(reg, &pmc->pmc_remove_clamping); - - /* Give I/O signals time to stabilize */ - udelay(IO_STABILIZATION_DELAY); -} - -static void powerup_cpu(void) -{ - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; - u32 reg; - int timeout = IO_STABILIZATION_DELAY; - - if (!is_cpu_powered()) { - /* Toggle the CPU power state (OFF -> ON) */ - reg = readl(&pmc->pmc_pwrgate_toggle); - reg &= PARTID_CP; - reg |= START_CP; - writel(reg, &pmc->pmc_pwrgate_toggle); - - /* Wait for the power to come up */ - while (!is_cpu_powered()) { - if (timeout-- == 0) - printf("CPU failed to power up!\n"); - else - udelay(10); - } - - /* - * Remove the I/O clamps from CPU power partition. - * Recommended only on a Warm boot, if the CPU partition gets - * power gated. Shouldn't cause any harm when called after a - * cold boot according to HW, probably just redundant. - */ - remove_cpu_io_clamps(); - } -} - -static void enable_cpu_power_rail(void) -{ - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; - u32 reg; - - reg = readl(&pmc->pmc_cntrl); - reg |= CPUPWRREQ_OE; - writel(reg, &pmc->pmc_cntrl); - - /* - * The TI PMU65861C needs a 3.75ms delay between enabling - * the power rail and enabling the CPU clock. This delay - * between SM1EN and SM1 is for switching time + the ramp - * up of the voltage to the CPU (VDD_CPU from PMU). - */ - udelay(3750); -} - -static void reset_A9_cpu(int reset) -{ - /* - * NOTE: Regardless of whether the request is to hold the CPU in reset - * or take it out of reset, every processor in the CPU complex - * except the master (CPU 0) will be held in reset because the - * AVP only talks to the master. The AVP does not know that there - * are multiple processors in the CPU complex. - */ - - /* Hold CPU 1 in reset, and CPU 0 if asked */ - reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1); - reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug, - reset); - - /* Enable/Disable master CPU reset */ - reset_set_enable(PERIPH_ID_CPU, reset); -} - -static void clock_enable_coresight(int enable) -{ - u32 rst, src; - - clock_set_enable(PERIPH_ID_CORESIGHT, enable); - reset_set_enable(PERIPH_ID_CORESIGHT, !enable); - - if (enable) { - /* - * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by - * 1.5, giving an effective frequency of 144MHz. - * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor - * (bits 7:0), so 00000001b == 1.5 (n+1 + .5) - */ - src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); - clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src); - - /* Unlock the CPU CoreSight interfaces */ - rst = 0xC5ACCE55; - writel(rst, CSITE_CPU_DBG0_LAR); - writel(rst, CSITE_CPU_DBG1_LAR); - } -} - -void start_cpu(u32 reset_vector) -{ - /* Enable VDD_CPU */ - enable_cpu_power_rail(); - - /* Hold the CPUs in reset */ - reset_A9_cpu(1); - - /* Disable the CPU clock */ - enable_cpu_clock(0); - - /* Enable CoreSight */ - clock_enable_coresight(1); - - /* - * Set the entry point for CPU execution from reset, - * if it's a non-zero value. - */ - if (reset_vector) - writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); - - /* Enable the CPU clock */ - enable_cpu_clock(1); - - /* If the CPU doesn't already have power, power it up */ - powerup_cpu(); - - /* Take the CPU out of reset */ - reset_A9_cpu(0); -} - - -void halt_avp(void) -{ - for (;;) { - writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \ - | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)), - FLOW_CTLR_HALT_COP_EVENTS); - } -} - -void enable_scu(void) +static void enable_scu(void) { struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; u32 reg; @@ -312,7 +80,7 @@ void enable_scu(void) writel(reg, &scu->scu_ctrl); }
-void init_pmc_scratch(void) +static void init_pmc_scratch(void) { struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; int i; @@ -323,34 +91,10 @@ void init_pmc_scratch(void)
/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20); - -#ifdef CONFIG_TEGRA2_LP0 - /* save Sdram params to PMC 2, 4, and 24 for WB0 */ - warmboot_save_sdram_params(); -#endif }
-void tegra2_start(void) +void lowlevel_init(void) { - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - - /* If we are the AVP, start up the first Cortex-A9 */ - if (!ap20_cpu_is_cortexa9()) { - /* enable JTAG */ - writel(0xC0, &pmt->pmt_cfg_ctl); - - /* - * If we are ARM7 - give it a different stack. We are about to - * start up the A9 which will want to use this one. - */ - asm volatile("mov sp, %0\n" - : : "r"(AVP_EARLY_BOOT_STACK_LIMIT)); - - start_cpu((u32)_start); - halt_avp(); - /* not reached */ - } - /* Init PMC scratch memory */ init_pmc_scratch();
diff --git a/arch/arm/cpu/tegra20-common/board.c b/arch/arm/cpu/tegra20-common/board.c index a50b1b9..458a928 100644 --- a/arch/arm/cpu/tegra20-common/board.c +++ b/arch/arm/cpu/tegra20-common/board.c @@ -23,7 +23,6 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/ap20.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pmc.h> @@ -69,6 +68,11 @@ int dram_init(void) { /* We do not initialise DRAM here. We just query the size */ gd->ram_size = query_sdram_size(); + +#ifdef CONFIG_TEGRA2_LP0 + /* save Sdram params to PMC 2, 4, and 24 for WB0 */ + warmboot_save_sdram_params(); +#endif return 0; }
@@ -80,27 +84,6 @@ int checkboard(void) } #endif /* CONFIG_DISPLAY_BOARDINFO */
-#ifdef CONFIG_ARCH_CPU_INIT -/* - * Note this function is executed by the ARM7TDMI AVP. It does not return - * in this case. It is also called once the A9 starts up, but does nothing in - * that case. - */ -int arch_cpu_init(void) -{ - /* Fire up the Cortex A9 */ - tegra2_start(); - - /* We didn't do this init in start.S, so do it now */ - cpu_init_cp15(); - - /* Initialize essential common plls */ - clock_early_init(); - - return 0; -} -#endif - /** * Set up the specified uarts * diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 8e2732a..28a9082 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -43,8 +43,6 @@
#define CONFIG_SYS_CACHELINE_SIZE 32
-#define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */ - #include <asm/arch/tegra2.h> /* get chip and board defs */
/* @@ -53,8 +51,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_OF_LIBFDT /* enable passing of devicetree */
On 06/05/2012 03:20 PM, Allen Martin wrote:
This code is now included in the tegra20 SPL
@@ -323,34 +91,10 @@ void init_pmc_scratch(void)
/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
-#ifdef CONFIG_TEGRA2_LP0
- /* save Sdram params to PMC 2, 4, and 24 for WB0 */
- warmboot_save_sdram_params();
-#endif }
Is that change intended, or was it a rebase mistake?
diff --git a/arch/arm/cpu/tegra20-common/board.c b/arch/arm/cpu/tegra20-common/board.c
@@ -69,6 +68,11 @@ int dram_init(void) { /* We do not initialise DRAM here. We just query the size */ gd->ram_size = query_sdram_size();
+#ifdef CONFIG_TEGRA2_LP0
- /* save Sdram params to PMC 2, 4, and 24 for WB0 */
- warmboot_save_sdram_params();
+#endif
Hmmm. That's more than just removing the code that's now in the AVP directory. Separate patch? The patch description also doesn't say why this change is necessary.
On Wed, Jun 06, 2012 at 09:51:09AM -0700, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
This code is now included in the tegra20 SPL
@@ -323,34 +91,10 @@ void init_pmc_scratch(void)
/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
-#ifdef CONFIG_TEGRA2_LP0
- /* save Sdram params to PMC 2, 4, and 24 for WB0 */
- warmboot_save_sdram_params();
-#endif }
Is that change intended, or was it a rebase mistake?
diff --git a/arch/arm/cpu/tegra20-common/board.c b/arch/arm/cpu/tegra20-common/board.c
@@ -69,6 +68,11 @@ int dram_init(void) { /* We do not initialise DRAM here. We just query the size */ gd->ram_size = query_sdram_size();
+#ifdef CONFIG_TEGRA2_LP0
- /* save Sdram params to PMC 2, 4, and 24 for WB0 */
- warmboot_save_sdram_params();
+#endif
Hmmm. That's more than just removing the code that's now in the AVP directory. Separate patch? The patch description also doesn't say why this change is necessary.
This code was added since v1 of the patch series, and I had to move it because when I fixed it so we could use the normal lowlevel_init it gets called before the devicetree is initialized.
I rolled it into this patch, but you're probably right, it would make more sense to be in it's own patch with a proper description.
-Allen
These flags were necessary when building tegra20 as a single binary that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support is split into a separate SPL, this is no longer necessary.
Signed-off-by: Allen Martin amartin@nvidia.com --- arch/arm/cpu/armv7/tegra20/config.mk | 7 ------- 1 file changed, 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra20/config.mk b/arch/arm/cpu/armv7/tegra20/config.mk index fe9ef5b..e666f6b 100644 --- a/arch/arm/cpu/armv7/tegra20/config.mk +++ b/arch/arm/cpu/armv7/tegra20/config.mk @@ -23,13 +23,6 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - -# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this -# file with compatible flags -ifdef CONFIG_TEGRA2 -CFLAGS_arch/arm/lib/board.o += -march=armv4t -endif - USE_PRIVATE_LIBGCC = yes
CONFIG_ARCH_DEVICE_TREE := tegra20
On 06/05/2012 03:20 PM, Allen Martin wrote:
These flags were necessary when building tegra20 as a single binary that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support is split into a separate SPL, this is no longer necessary.
Can we also (probably in a separate patch) remove USE_PRIVATE_LIBGCC from the makefiles/... wherever we define it for Tegra? At least for the non-SPL build; presumably the SPL build will still need it.
Allen,
-----Original Message----- From: Allen Martin [mailto:amartin@nvidia.com] Sent: Tuesday, June 05, 2012 2:20 PM To: Tom Warren; swarren@wwwdotorg.org; sjg@chromium.org Cc: u-boot@lists.denx.de Subject: [PATCH v2 0/10] split tegra20 arm7 code into separate SPL
This patch series fixes a long standing problem with the tegra20 u-boot build. Tegra20 contains an ARM7TDMI boot processor and a Cortex A9 main processor. Prior to this patch series this was accomplished by #ifdefing out any armv7 code from the early boot sequence and creating a single binary that runs on both both the ARM7TDMI and A9. This was very fragile as changes to compiler options or any additions or rearranging of the early boot code could add additional armv7 specific code causing it to fail on the ARM7TDMI.
This patch series pulls all the armv4t code out into a separate SPL that does nothing more than initialize the A9 and transfer control to it. The resultint SPL and armv7 u-boot are concatenated together into a single image.
Changes: v2:
- renamed tegra2 to tegra20 to match kernel and devicetree naming policy
- pulled all SPL related config overrides to a separate file to clean up
ifdefs from seabard.h
- rebased to TOT u-boot/master and fixed a bug related to init sequence
changes between this patch series and new EMC code
- made u-boot.t2 target work even if CONFIG_OF is disabled
- added back USE_PRIVATE_LIBGCC
[PATCH 01/10] tegra20: rename tegra2 -> tegra20 [PATCH 02/10] tegra20: move tegra20 SoC code to [PATCH 03/10] mkconfig: add support for SPL CPU [PATCH 04/10] ARM: Fix arm720t SPL build [PATCH 05/10] tegra20: remove timer_init from SPL build [PATCH 06/10] ARM: add tegra20 support to arm720t [PATCH 07/10] tegra20: add SPL config options for seaboard [PATCH 08/10] tegra20: add u-boot.t2 target [PATCH 09/10] tegra20: Remove CPU init code from tegra20 u-boot [PATCH 10/10] tegra20: Remove armv4t build flags
Did you use the -C option for format-patch? I'd expect a lot of these file moves to show up as simple renames.
Tom
.gitignore | 1 - Makefile | 14 - arch/arm/cpu/arm720t/cpu.c | 2 - arch/arm/cpu/arm720t/interrupts.c | 4 - arch/arm/cpu/arm720t/start.S | 19 +- arch/arm/cpu/arm720t/tegra20/Makefile | 48 - arch/arm/cpu/arm720t/tegra20/board.h | 25 - arch/arm/cpu/arm720t/tegra20/cpu.c | 259 ----- arch/arm/cpu/arm720t/tegra20/cpu.h | 99 -- arch/arm/cpu/arm720t/tegra20/spl.c | 133 --- arch/arm/cpu/armv7/start.S | 2 + arch/arm/cpu/armv7/tegra2/Makefile | 59 ++ arch/arm/cpu/armv7/tegra2/ap20.c | 366 +++++++ arch/arm/cpu/armv7/tegra2/board.c | 151 +++ arch/arm/cpu/armv7/tegra2/clock.c | 1087 ++++++++++++++++++++ arch/arm/cpu/armv7/tegra2/config.mk | 35 + arch/arm/cpu/armv7/tegra2/crypto.c | 230 +++++ arch/arm/cpu/armv7/tegra2/crypto.h | 36 + arch/arm/cpu/armv7/tegra2/emc.c | 286 +++++ arch/arm/cpu/armv7/tegra2/funcmux.c | 200 ++++ arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 42 + arch/arm/cpu/armv7/tegra2/pinmux.c | 572 ++++++++++ arch/arm/cpu/armv7/tegra2/pmu.c | 70 ++ arch/arm/cpu/armv7/tegra2/sys_info.c | 35 + arch/arm/cpu/armv7/tegra2/timer.c | 111 ++ arch/arm/cpu/armv7/tegra2/usb.c | 460 +++++++++ arch/arm/cpu/armv7/tegra2/warmboot.c | 386 +++++++ arch/arm/cpu/armv7/tegra2/warmboot_avp.c | 250 +++++ arch/arm/cpu/armv7/tegra2/warmboot_avp.h | 81 ++ arch/arm/cpu/armv7/tegra20/Makefile | 48 - arch/arm/cpu/armv7/tegra20/config.mk | 28 - arch/arm/cpu/armv7/tegra20/usb.c | 460 --------- arch/arm/cpu/tegra20-common/Makefile | 59 -- arch/arm/cpu/tegra20-common/ap20.c | 110 -- arch/arm/cpu/tegra20-common/board.c | 134 --- arch/arm/cpu/tegra20-common/clock.c | 1087 -----------------
arch/arm/cpu/tegra20-common/crypto.c | 230 ----- arch/arm/cpu/tegra20-common/crypto.h | 36 - arch/arm/cpu/tegra20-common/emc.c | 286 ----- arch/arm/cpu/tegra20-common/funcmux.c | 200 ---- arch/arm/cpu/tegra20-common/lowlevel_init.S | 42 - arch/arm/cpu/tegra20-common/pinmux.c | 572 ---------- arch/arm/cpu/tegra20-common/pmu.c | 70 -- arch/arm/cpu/tegra20-common/sys_info.c | 35 - arch/arm/cpu/tegra20-common/timer.c | 111 -- arch/arm/cpu/tegra20-common/warmboot.c | 386 ------- arch/arm/cpu/tegra20-common/warmboot_avp.c | 250 ----- arch/arm/cpu/tegra20-common/warmboot_avp.h | 81 -- arch/arm/include/asm/arch-tegra2/ap20.h | 109 ++ arch/arm/include/asm/arch-tegra2/apb_misc.h | 36 + arch/arm/include/asm/arch-tegra2/board.h | 30 + arch/arm/include/asm/arch-tegra2/clk_rst.h | 147 +++ arch/arm/include/asm/arch-tegra2/clock.h | 406 ++++++++ arch/arm/include/asm/arch-tegra2/emc.h | 113 ++ arch/arm/include/asm/arch-tegra2/flow.h | 36 + arch/arm/include/asm/arch-tegra2/funcmux.h | 69 ++ arch/arm/include/asm/arch-tegra2/fuse.h | 39 + arch/arm/include/asm/arch-tegra2/gp_padctrl.h | 73 ++ arch/arm/include/asm/arch-tegra2/gpio.h | 289 ++++++ arch/arm/include/asm/arch-tegra2/mmc.h | 27 + arch/arm/include/asm/arch-tegra2/pinmux.h | 354 +++++++ arch/arm/include/asm/arch-tegra2/pmc.h | 132 +++ arch/arm/include/asm/arch-tegra2/pmu.h | 30 + arch/arm/include/asm/arch-tegra2/scu.h | 43 + arch/arm/include/asm/arch-tegra2/sdram_param.h | 148 +++ arch/arm/include/asm/arch-tegra2/sys_proto.h | 35 + arch/arm/include/asm/arch-tegra2/tegra2.h | 86 ++ arch/arm/include/asm/arch-tegra2/tegra2_spi.h | 76 ++ arch/arm/include/asm/arch-tegra2/tegra_i2c.h | 164 +++ arch/arm/include/asm/arch-tegra2/timer.h | 30 + arch/arm/include/asm/arch-tegra2/uart-spi-switch.h | 46 + arch/arm/include/asm/arch-tegra2/uart.h | 47 + arch/arm/include/asm/arch-tegra2/usb.h | 252 +++++ arch/arm/include/asm/arch-tegra2/warmboot.h | 150 +++ arch/arm/include/asm/arch-tegra20/ap20.h | 109 -- arch/arm/include/asm/arch-tegra20/apb_misc.h | 36 - arch/arm/include/asm/arch-tegra20/board.h | 30 - arch/arm/include/asm/arch-tegra20/clk_rst.h | 147 --- arch/arm/include/asm/arch-tegra20/clock.h | 406 -------- arch/arm/include/asm/arch-tegra20/emc.h | 113 -- arch/arm/include/asm/arch-tegra20/flow.h | 36 - arch/arm/include/asm/arch-tegra20/funcmux.h | 69 -- arch/arm/include/asm/arch-tegra20/fuse.h | 39 - arch/arm/include/asm/arch-tegra20/gp_padctrl.h | 73 -- arch/arm/include/asm/arch-tegra20/gpio.h | 289 ------ arch/arm/include/asm/arch-tegra20/hardware.h | 29 - arch/arm/include/asm/arch-tegra20/mmc.h | 27 - arch/arm/include/asm/arch-tegra20/pinmux.h | 354 ------- arch/arm/include/asm/arch-tegra20/pmc.h | 132 --- arch/arm/include/asm/arch-tegra20/pmu.h | 30 - arch/arm/include/asm/arch-tegra20/scu.h | 43 - arch/arm/include/asm/arch-tegra20/sdram_param.h | 148 --- arch/arm/include/asm/arch-tegra20/sys_proto.h | 35 - arch/arm/include/asm/arch-tegra20/tegra2.h | 86 -- arch/arm/include/asm/arch-tegra20/tegra2_spi.h | 76 -- arch/arm/include/asm/arch-tegra20/tegra_i2c.h | 164 --- arch/arm/include/asm/arch-tegra20/timer.h | 30 - .../arm/include/asm/arch-tegra20/uart-spi-switch.h | 46 - arch/arm/include/asm/arch-tegra20/uart.h | 47 - arch/arm/include/asm/arch-tegra20/usb.h | 252 ----- arch/arm/include/asm/arch-tegra20/warmboot.h | 150 --- board/nvidia/common/board.c | 2 - board/nvidia/seaboard/config.mk | 1 - boards.cfg | 17 +- doc/README.SPL | 12 - include/configs/seaboard.h | 6 - include/configs/tegra2-common.h | 21 +- include/configs/tegra2-spl.h | 87 -- mkconfig | 15 +- spl/Makefile | 4 - 110 files changed, 7438 insertions(+), 7978 deletions(-)
-- nvpublic
On Tue, Jun 05, 2012 at 02:25:12PM -0700, Tom Warren wrote:
Did you use the -C option for format-patch? I'd expect a lot of these file moves to show up as simple renames.
Yes, if you look inside "[PATCH v2 01/10] tegra20: rename tegra2 -> tegra20" for example, all the renames came out ok, I think it's just the diff stats in the summary that are wrong.
-Allen
participants (4)
-
Allen Martin -
Stephen Warren -
Sughosh Ganu -
Tom Warren