This patch adds a configurable spi clockdivider. In the original version, the divider is set to /4 to mimic the BROMs behaviour. However, in many cases this can be changed to /2 or no divider at all to speed up the booting process.

Signed-off-by: Benedikt-Alexander Mokroß u-boot@bamkrs.de --- arch/arm/mach-sunxi/spl/spi/Kconfig | 18 ++++++++++++++++++ arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi.c | 10 +++++++++- 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/spl/spi/Kconfig b/arch/arm/mach-sunxi/spl/spi/Kconfig index f92b80583f..2edc7c0917 100644 --- a/arch/arm/mach-sunxi/spl/spi/Kconfig +++ b/arch/arm/mach-sunxi/spl/spi/Kconfig @@ -9,4 +9,22 @@ config SPL_SPI_SUNXI_NOR sunxi SPI-NOR Flash. It uses the same method as the boot ROM, so does not need any extra configuration.

+choice + prompt "SPI Clockdivider of Allwinner SoCs in SPL" + depends on SPL_SPI_SUNXI + ---help--- + Select which clock divider should be used for spi clock + +config SPL_SPI_SUNXI_DIV_4 + bool "Clock / 4" + default y + +config SPL_SPI_SUNXI_DIV_2 + bool "Clock / 2" + +config SPL_SPI_SUNXI_DIV_NONE + bool "No clock divider" + +endchoice + endif diff --git a/arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi.c index 2f1d40dcfe..fd5f84a90c 100644 --- a/arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi.c @@ -69,8 +69,16 @@ void sunxi_spi0_enable_clock(void) setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));

/* Clock divider */ - writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ? + if (IS_ENABLED(CONFIG_SPL_SPI_SUNXI_DIV_4)) + writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ? SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); + else if (IS_ENABLED(CONFIG_SPL_SPI_SUNXI_DIV_2)) + writel(SPI0_CLK_DIV_BY_2, base + (is_sun6i_gen_spi() ? + SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); + else + writel(SPI0_CLK_DIV_NONE, base + (is_sun6i_gen_spi() ? + SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); + /* 24MHz from OSC24M */ writel((1 << 31), CCM_SPI0_CLK);