AVS is enabled at R5 SPL stage, on few platforms like J721E and J7200 clk-k3 is used instead if clk-sci driver.

Add support in clk-k3 driver as well to notify AVS driver on setting clock rate so that voltage is changed accordingly.

Cc: Keerthy j-keerthy@ti.com Signed-off-by: Udit Kumar u-kumar1@ti.com --- Boot logs with v4: https://gist.github.com/uditkumarti/bab0ec09eadb4b167ec1ab93e08637a8

Change log: Change in v4: - changed if condition order as per review feedback - splitted patch into two - v3 link https://lore.kernel.org/all/20230920120256.2901860-1-u-kumar1@ti.com/

Change in v3: - Updated AVS notification before/after clock setting based upon new and current rate - Added modifed notification in clk-sci driver as well - v2 link https://lore.kernel.org/all/20230919140408.2608521-1-u-kumar1@ti.com/

Changes in v2: - Kept clk-sci.c as is because this is used by AM64 and AM65 platforms - v1 link https://lore.kernel.org/all/20230919060649.2518147-1-u-kumar1@ti.com

drivers/clk/ti/clk-k3.c | 9 +++++++++ 1 file changed, 9 insertions(+)

diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index ba925fa3c4..10f7240f77 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -11,6 +11,7 @@ #include <errno.h> #include <soc.h> #include <clk-uclass.h> +#include <k3-avs.h> #include "k3-clk.h"

#define PLL_MIN_FREQ 800000000 @@ -242,7 +243,11 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate) const struct clk_ops *ops; ulong new_rate, rem; ulong diff, new_diff; + int freq_scale_up = rate >= ti_clk_get_rate(clk) ? 1 : 0;

+ if (IS_ENABLED(CONFIG_K3_AVS0) && freq_scale_up) + k3_avs_notify_freq(data->map[clk->id].dev_id, + data->map[clk->id].clk_id, rate); /* * We must propagate rate change to parent if current clock type * does not allow setting it. @@ -339,6 +344,10 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate) } }

+ if (IS_ENABLED(CONFIG_K3_AVS0) && !freq_scale_up) + k3_avs_notify_freq(data->map[clk->id].dev_id, + data->map[clk->id].clk_id, rate); + return new_rate; }