[U-Boot] [PATCH] net: ravb: Avoid unsupported internal delay mode for R-Car E3/D3
According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3 (r8a77995).
Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM when the DT explicitly specifies RGMII ID or TXID mode instead of setting it unconditionally when the PHY link speed is 1000 Mbit/s.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Joe Hershberger joe.hershberger@ni.com --- drivers/net/ravb.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 749562db96..11abe5e0c9 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -46,6 +46,8 @@ #define CSR_OPS 0x0000000F #define CSR_OPS_CONFIG BIT(1)
+#define APSR_TDM BIT(14) + #define TCCR_TSRQ0 BIT(0)
#define RFLR_RFL_MIN 0x05EE @@ -389,9 +391,14 @@ static int ravb_dmac_init(struct udevice *dev) /* FIFO size set */ writel(0x00222210, eth->iobase + RAVB_REG_TGC);
- /* Delay CLK: 2ns */ - if (pdata->max_speed == 1000) - writel(BIT(14), eth->iobase + RAVB_REG_APSR); + /* Delay CLK: 2ns (not applicable on R-Car E3/D3) */ + if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) || + (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995)) + return 0; + + if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || + (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)) + writel(APSR_TDM, eth->iobase + RAVB_REG_APSR);
return 0; }
On Wed, May 1, 2019 at 5:36 PM Marek Vasut marek.vasut@gmail.com wrote:
According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3 (r8a77995).
Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM when the DT explicitly specifies RGMII ID or TXID mode instead of setting it unconditionally when the PHY link speed is 1000 Mbit/s.
We just ran into an issue with a very similar patch. It blocked my tree being merged for a few months. Finally got to the bottom of it. https://patchwork.ozlabs.org/patch/1096572/
Are you sure there are no boards depending on the broken DT, like the 335-evm was?
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Joe Hershberger joe.hershberger@ni.com
drivers/net/ravb.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 749562db96..11abe5e0c9 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -46,6 +46,8 @@ #define CSR_OPS 0x0000000F #define CSR_OPS_CONFIG BIT(1)
+#define APSR_TDM BIT(14)
#define TCCR_TSRQ0 BIT(0)
#define RFLR_RFL_MIN 0x05EE @@ -389,9 +391,14 @@ static int ravb_dmac_init(struct udevice *dev) /* FIFO size set */ writel(0x00222210, eth->iobase + RAVB_REG_TGC);
/* Delay CLK: 2ns */if (pdata->max_speed == 1000)writel(BIT(14), eth->iobase + RAVB_REG_APSR);
/* Delay CLK: 2ns (not applicable on R-Car E3/D3) */if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) ||(rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))return 0;if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||(pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID))writel(APSR_TDM, eth->iobase + RAVB_REG_APSR); return 0;}
2.20.1
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On 5/9/19 8:56 PM, Joe Hershberger wrote:
On Wed, May 1, 2019 at 5:36 PM Marek Vasut marek.vasut@gmail.com wrote:
According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3 (r8a77995).
Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM when the DT explicitly specifies RGMII ID or TXID mode instead of setting it unconditionally when the PHY link speed is 1000 Mbit/s.
We just ran into an issue with a very similar patch. It blocked my tree being merged for a few months. Finally got to the bottom of it. https://patchwork.ozlabs.org/patch/1096572/
Are you sure there are no boards depending on the broken DT, like the 335-evm was?
I cannot be sure, but the boards which are supported and tested work fine. If someone runs into any issue. they can raise them, and we'll solve the problem when we come to that bridge.
On Thu, May 9, 2019 at 3:01 PM Marek Vasut marek.vasut@gmail.com wrote:
On 5/9/19 8:56 PM, Joe Hershberger wrote:
On Wed, May 1, 2019 at 5:36 PM Marek Vasut marek.vasut@gmail.com wrote:
According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3 (r8a77995).
Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM when the DT explicitly specifies RGMII ID or TXID mode instead of setting it unconditionally when the PHY link speed is 1000 Mbit/s.
We just ran into an issue with a very similar patch. It blocked my tree being merged for a few months. Finally got to the bottom of it. https://patchwork.ozlabs.org/patch/1096572/
Are you sure there are no boards depending on the broken DT, like the 335-evm was?
I cannot be sure, but the boards which are supported and tested work fine. If someone runs into any issue. they can raise them, and we'll solve the problem when we come to that bridge.
The point that came up is that the DT is considered the ABI, so it shouldn't break / change behavior. Just wanted to make sure you were aware.
Thanks, -Joe
On 5/9/19 10:18 PM, Joe Hershberger wrote:
On Thu, May 9, 2019 at 3:01 PM Marek Vasut marek.vasut@gmail.com wrote:
On 5/9/19 8:56 PM, Joe Hershberger wrote:
On Wed, May 1, 2019 at 5:36 PM Marek Vasut marek.vasut@gmail.com wrote:
According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3 (r8a77995).
Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM when the DT explicitly specifies RGMII ID or TXID mode instead of setting it unconditionally when the PHY link speed is 1000 Mbit/s.
We just ran into an issue with a very similar patch. It blocked my tree being merged for a few months. Finally got to the bottom of it. https://patchwork.ozlabs.org/patch/1096572/
Are you sure there are no boards depending on the broken DT, like the 335-evm was?
I cannot be sure, but the boards which are supported and tested work fine. If someone runs into any issue. they can raise them, and we'll solve the problem when we come to that bridge.
The point that came up is that the DT is considered the ABI, so it shouldn't break / change behavior. Just wanted to make sure you were aware.
I am, but I still prefer for the ethernet to work correctly.
On Thu, May 9, 2019 at 3:24 PM Marek Vasut marek.vasut@gmail.com wrote:
On 5/9/19 10:18 PM, Joe Hershberger wrote:
On Thu, May 9, 2019 at 3:01 PM Marek Vasut marek.vasut@gmail.com wrote:
On 5/9/19 8:56 PM, Joe Hershberger wrote:
On Wed, May 1, 2019 at 5:36 PM Marek Vasut marek.vasut@gmail.com wrote:
According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3 (r8a77995).
Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM when the DT explicitly specifies RGMII ID or TXID mode instead of setting it unconditionally when the PHY link speed is 1000 Mbit/s.
We just ran into an issue with a very similar patch. It blocked my tree being merged for a few months. Finally got to the bottom of it. https://patchwork.ozlabs.org/patch/1096572/
Are you sure there are no boards depending on the broken DT, like the 335-evm was?
I cannot be sure, but the boards which are supported and tested work fine. If someone runs into any issue. they can raise them, and we'll solve the problem when we come to that bridge.
The point that came up is that the DT is considered the ABI, so it shouldn't break / change behavior. Just wanted to make sure you were aware.
I am, but I still prefer for the ethernet to work correctly.
Is the whole patch required to fix it? The commit log doesn't make that clear. "Moreover, only set APSR:TDM when the DT explicitly specifies RGMII ID or TXID mode instead of setting it unconditionally when the PHY link speed is 1000 Mbit/s."
Thanks, -Joe
-- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On 5/9/19 10:26 PM, Joe Hershberger wrote:
On Thu, May 9, 2019 at 3:24 PM Marek Vasut marek.vasut@gmail.com wrote:
On 5/9/19 10:18 PM, Joe Hershberger wrote:
On Thu, May 9, 2019 at 3:01 PM Marek Vasut marek.vasut@gmail.com wrote:
On 5/9/19 8:56 PM, Joe Hershberger wrote:
On Wed, May 1, 2019 at 5:36 PM Marek Vasut marek.vasut@gmail.com wrote:
According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3 (r8a77995).
Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM when the DT explicitly specifies RGMII ID or TXID mode instead of setting it unconditionally when the PHY link speed is 1000 Mbit/s.
We just ran into an issue with a very similar patch. It blocked my tree being merged for a few months. Finally got to the bottom of it. https://patchwork.ozlabs.org/patch/1096572/
Are you sure there are no boards depending on the broken DT, like the 335-evm was?
I cannot be sure, but the boards which are supported and tested work fine. If someone runs into any issue. they can raise them, and we'll solve the problem when we come to that bridge.
The point that came up is that the DT is considered the ABI, so it shouldn't break / change behavior. Just wanted to make sure you were aware.
I am, but I still prefer for the ethernet to work correctly.
Is the whole patch required to fix it? The commit log doesn't make that clear. "Moreover, only set APSR:TDM when the DT explicitly specifies RGMII ID or TXID mode instead of setting it unconditionally when the PHY link speed is 1000 Mbit/s."
Yep, it's a port of similar patch from Linux.
On Wed, May 1, 2019 at 5:36 PM Marek Vasut marek.vasut@gmail.com wrote:
According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3 (r8a77995).
Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM when the DT explicitly specifies RGMII ID or TXID mode instead of setting it unconditionally when the PHY link speed is 1000 Mbit/s.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Joe Hershberger joe.hershberger@ni.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
participants (2)
-
Joe Hershberger -
Marek Vasut