[Patchv4 0/3] Odroid n2 using eMMC would fail to boot up
Here are some small changes to fix booting of Odroid N2 using eMMC. Fixed the clk tunnig during mmc initialization. Added two new patches to fix warning
Build and tested on top of below patches [0] https://patchwork.ozlabs.org/patch/1213648/ [1] https://patchwork.ozlabs.org/patch/1213650/
Tested on below eMMC module on Odroid N2 and C2 new orange - eMMC AJNB4R 14.6 GiB MMC 5.1 old back - eMMC CGND3R 58.2 GiB MMC 5.0
Prevoius changes: Fixed the clk tuning as per mainline kernel
[3]v1 https://patchwork.ozlabs.org/cover/1201206/ [4]v2 https://patchwork.ozlabs.org/cover/1215217/ [5]v3 https://www.mail-archive.com/u-boot@lists.denx.de/msg351859.html
-Anand
Anand Moon (3): mmc: meson-gx: Fix clk phase tuning for MMC arm: dts: Add mmc alias to avoid warning arm: dts: Add cd-gpio for eMMC
arch/arm/dts/meson-axg-s400.dts | 2 + arch/arm/dts/meson-g12a-sei510.dts | 3 ++ arch/arm/dts/meson-g12a-u200.dts | 3 ++ arch/arm/dts/meson-g12b-odroid-n2.dts | 4 ++ arch/arm/dts/meson-gxbb-odroidc2.dts | 3 ++ arch/arm/dts/meson-gxbb-p20x.dtsi | 3 ++ arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 3 ++ arch/arm/dts/meson-gxl-s905x-p212.dtsi | 3 ++ arch/arm/dts/meson-gxm-khadas-vim2.dts | 3 ++ arch/arm/dts/meson-sm1-sei610.dts | 3 ++ arch/arm/include/asm/arch-meson/sd_emmc.h | 11 ++---- drivers/mmc/meson_gx_mmc.c | 38 ++++++++++++++++--- 12 files changed, 65 insertions(+), 14 deletions(-)
As per mainline line kernel fix the clk tunig phase for mmc, set Core=180, Tx=180, Rx=0 clk phase for mmc initialization. As per S905X and S922X datasheet set the default values for clk tuning.
Signed-off-by: Anand Moon linux.amoon@gmail.com --- Changes from previous v3 Fix the initialization of core clk tunning phase as per datasheet. Fix the commit message.
v2: Fix the clk phase macro to support PHASE_180 drop the wrong CLK_CORE_PHASE_MASK macro.
v1: use the mainline kernel tuning for clk tuning.
Fixed the commmit messages. Patch v1: https://patchwork.ozlabs.org/patch/1201208/
Before these changes. clock is enabled (380953Hz) clock is enabled (25000000Hz) After these changes clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) Test on Odroid N2 and Odroid C2 with eMMC and microSD cards --- arch/arm/include/asm/arch-meson/sd_emmc.h | 11 ++----- drivers/mmc/meson_gx_mmc.c | 38 +++++++++++++++++++---- 2 files changed, 35 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h index e3a72c8b66..c193547aad 100644 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h @@ -7,6 +7,7 @@ #define __SD_EMMC_H__
#include <mmc.h> +#include <linux/bitops.h>
#define SDIO_PORT_A 0 #define SDIO_PORT_B 1 @@ -19,14 +20,8 @@ #define CLK_MAX_DIV 63 #define CLK_SRC_24M (0 << 6) #define CLK_SRC_DIV2 (1 << 6) -#define CLK_CO_PHASE_000 (0 << 8) -#define CLK_CO_PHASE_090 (1 << 8) -#define CLK_CO_PHASE_180 (2 << 8) -#define CLK_CO_PHASE_270 (3 << 8) -#define CLK_TX_PHASE_000 (0 << 10) -#define CLK_TX_PHASE_090 (1 << 10) -#define CLK_TX_PHASE_180 (2 << 10) -#define CLK_TX_PHASE_270 (3 << 10) +#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) + #define CLK_ALWAYS_ON BIT(24)
#define MESON_SD_EMMC_CFG 0x44 diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 86c1a7164a..67b1b075ab 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -51,12 +51,38 @@ static void meson_mmc_config_clock(struct mmc *mmc) } clk_div = DIV_ROUND_UP(clk, mmc->clock);
- /* 180 phase core clock */ - meson_mmc_clk |= CLK_CO_PHASE_180; - - /* 180 phase tx clock */ - meson_mmc_clk |= CLK_TX_PHASE_000; - + /* Clock divider */ + meson_mmc_clk = GENMASK(5, 0); + /* Clock source 1: Fix PLL, 1000MHz */ + meson_mmc_clk |= UPDATE(1, 7, 6); + /* Core clock phase 2:180 */ + meson_mmc_clk |= UPDATE(2, 9, 8); + /* TX clock phase 2:180 */ + meson_mmc_clk |= UPDATE(2, 11, 10); + /* RX clock phase 0:180 */ + meson_mmc_clk |= UPDATE(0, 13, 12); +#ifdef CONFIG_MESON_GX + /* TX clock delay line */ + meson_mmc_clk |= GENMASK(19, 16); + /* RX clock delay line */ + meson_mmc_clk |= GENMASK(23, 20); + /* clk always on */ + meson_mmc_clk |= BIT(20); + /* clk irq sdio sleep */ + meson_mmc_clk |= BIT(25); +#endif +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A)) + /* TX clock delay line */ + meson_mmc_clk |= GENMASK(21, 16); + /* RX clock delay line */ + meson_mmc_clk |= GENMASK(27, 22); + /* clk always on */ + meson_mmc_clk |= BIT(28); + /* clk irq sdio sleep */ + meson_mmc_clk |= BIT(29); + /* clk irq sdio sleep_ds */ + meson_mmc_clk |= BIT(30); +#endif /* clock settings */ meson_mmc_clk |= clk_src; meson_mmc_clk |= clk_div;
Dear Anand,
On 1/22/20 9:06 PM, Anand Moon wrote:
As per mainline line kernel fix the clk tunig phase for mmc, set Core=180, Tx=180, Rx=0 clk phase for mmc initialization. As per S905X and S922X datasheet set the default values for clk tuning.
Signed-off-by: Anand Moon linux.amoon@gmail.com
Changes from previous v3 Fix the initialization of core clk tunning phase as per datasheet. Fix the commit message.
v2: Fix the clk phase macro to support PHASE_180 drop the wrong CLK_CORE_PHASE_MASK macro.
v1: use the mainline kernel tuning for clk tuning.
Fixed the commmit messages. Patch v1: https://protect2.fireeye.com/url?k=c4a34ac1-9973420d-c4a2c18e-000babff3793-f...
Before these changes. clock is enabled (380953Hz) clock is enabled (25000000Hz) After these changes clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
arch/arm/include/asm/arch-meson/sd_emmc.h | 11 ++----- drivers/mmc/meson_gx_mmc.c | 38 +++++++++++++++++++---- 2 files changed, 35 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h index e3a72c8b66..c193547aad 100644 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h @@ -7,6 +7,7 @@ #define __SD_EMMC_H__
#include <mmc.h> +#include <linux/bitops.h>
#define SDIO_PORT_A 0 #define SDIO_PORT_B 1 @@ -19,14 +20,8 @@ #define CLK_MAX_DIV 63 #define CLK_SRC_24M (0 << 6) #define CLK_SRC_DIV2 (1 << 6) -#define CLK_CO_PHASE_000 (0 << 8) -#define CLK_CO_PHASE_090 (1 << 8) -#define CLK_CO_PHASE_180 (2 << 8) -#define CLK_CO_PHASE_270 (3 << 8) -#define CLK_TX_PHASE_000 (0 << 10) -#define CLK_TX_PHASE_090 (1 << 10) -#define CLK_TX_PHASE_180 (2 << 10) -#define CLK_TX_PHASE_270 (3 << 10) +#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
#define CLK_ALWAYS_ON BIT(24)
#define MESON_SD_EMMC_CFG 0x44 diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 86c1a7164a..67b1b075ab 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -51,12 +51,38 @@ static void meson_mmc_config_clock(struct mmc *mmc) } clk_div = DIV_ROUND_UP(clk, mmc->clock);
- /* 180 phase core clock */
- meson_mmc_clk |= CLK_CO_PHASE_180;
- /* 180 phase tx clock */
- meson_mmc_clk |= CLK_TX_PHASE_000;
- /* Clock divider */
- meson_mmc_clk = GENMASK(5, 0);
- /* Clock source 1: Fix PLL, 1000MHz */
- meson_mmc_clk |= UPDATE(1, 7, 6);
- /* Core clock phase 2:180 */
- meson_mmc_clk |= UPDATE(2, 9, 8);
- /* TX clock phase 2:180 */
- meson_mmc_clk |= UPDATE(2, 11, 10);
- /* RX clock phase 0:180 */
- meson_mmc_clk |= UPDATE(0, 13, 12);
+#ifdef CONFIG_MESON_GX
- /* TX clock delay line */
- meson_mmc_clk |= GENMASK(19, 16);
- /* RX clock delay line */
- meson_mmc_clk |= GENMASK(23, 20);
- /* clk always on */
- meson_mmc_clk |= BIT(20);
- /* clk irq sdio sleep */
- meson_mmc_clk |= BIT(25);
Could you define the macro instead of BIT(x)? It's helpful to know what its bit is used.
e.g) #define CLK_ALWAYS_ON BIT(20)
i didn't know that BIT(20)/(25) are defined as what purpose has.
Best Regards, Jaehoon Chung
+#endif +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
- /* TX clock delay line */
- meson_mmc_clk |= GENMASK(21, 16);
- /* RX clock delay line */
- meson_mmc_clk |= GENMASK(27, 22);
- /* clk always on */
- meson_mmc_clk |= BIT(28);
- /* clk irq sdio sleep */
- meson_mmc_clk |= BIT(29);
- /* clk irq sdio sleep_ds */
- meson_mmc_clk |= BIT(30);
+#endif /* clock settings */ meson_mmc_clk |= clk_src; meson_mmc_clk |= clk_div;
Hi Jaehoon,
On Thu, 23 Jan 2020 at 05:09, Jaehoon Chung jh80.chung@samsung.com wrote:
Dear Anand,
On 1/22/20 9:06 PM, Anand Moon wrote:
As per mainline line kernel fix the clk tunig phase for mmc, set Core=180, Tx=180, Rx=0 clk phase for mmc initialization. As per S905X and S922X datasheet set the default values for clk tuning.
Signed-off-by: Anand Moon linux.amoon@gmail.com
Changes from previous v3 Fix the initialization of core clk tunning phase as per datasheet. Fix the commit message.
v2: Fix the clk phase macro to support PHASE_180 drop the wrong CLK_CORE_PHASE_MASK macro.
v1: use the mainline kernel tuning for clk tuning.
Fixed the commmit messages. Patch v1: https://protect2.fireeye.com/url?k=c4a34ac1-9973420d-c4a2c18e-000babff3793-f...
Before these changes. clock is enabled (380953Hz) clock is enabled (25000000Hz) After these changes clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
arch/arm/include/asm/arch-meson/sd_emmc.h | 11 ++----- drivers/mmc/meson_gx_mmc.c | 38 +++++++++++++++++++---- 2 files changed, 35 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h index e3a72c8b66..c193547aad 100644 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h @@ -7,6 +7,7 @@ #define __SD_EMMC_H__
#include <mmc.h> +#include <linux/bitops.h>
#define SDIO_PORT_A 0 #define SDIO_PORT_B 1 @@ -19,14 +20,8 @@ #define CLK_MAX_DIV 63 #define CLK_SRC_24M (0 << 6) #define CLK_SRC_DIV2 (1 << 6) -#define CLK_CO_PHASE_000 (0 << 8) -#define CLK_CO_PHASE_090 (1 << 8) -#define CLK_CO_PHASE_180 (2 << 8) -#define CLK_CO_PHASE_270 (3 << 8) -#define CLK_TX_PHASE_000 (0 << 10) -#define CLK_TX_PHASE_090 (1 << 10) -#define CLK_TX_PHASE_180 (2 << 10) -#define CLK_TX_PHASE_270 (3 << 10) +#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
#define CLK_ALWAYS_ON BIT(24)
#define MESON_SD_EMMC_CFG 0x44 diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 86c1a7164a..67b1b075ab 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -51,12 +51,38 @@ static void meson_mmc_config_clock(struct mmc *mmc) } clk_div = DIV_ROUND_UP(clk, mmc->clock);
/* 180 phase core clock */meson_mmc_clk |= CLK_CO_PHASE_180;/* 180 phase tx clock */meson_mmc_clk |= CLK_TX_PHASE_000;
/* Clock divider */meson_mmc_clk = GENMASK(5, 0);/* Clock source 1: Fix PLL, 1000MHz */meson_mmc_clk |= UPDATE(1, 7, 6);/* Core clock phase 2:180 */meson_mmc_clk |= UPDATE(2, 9, 8);/* TX clock phase 2:180 */meson_mmc_clk |= UPDATE(2, 11, 10);/* RX clock phase 0:180 */meson_mmc_clk |= UPDATE(0, 13, 12);+#ifdef CONFIG_MESON_GX
/* TX clock delay line */meson_mmc_clk |= GENMASK(19, 16);/* RX clock delay line */meson_mmc_clk |= GENMASK(23, 20);/* clk always on */
Opps Typo this should be BIT(24)
meson_mmc_clk |= BIT(20);/* clk irq sdio sleep */meson_mmc_clk |= BIT(25);Could you define the macro instead of BIT(x)? It's helpful to know what its bit is used.
e.g) #define CLK_ALWAYS_ON BIT(20)
i didn't know that BIT(20)/(25) are defined as what purpose has.
Best Regards, Jaehoon Chung
Thanks for your review. Their are different bit setting for CLK_ALWAYS_ON on BIT(24) for (S905. S905X) and BIT(28) for S922X. I will change this as per your suggestion in the next version Lets wait for more comments on this patch.
-Anand
+#endif +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
/* TX clock delay line */meson_mmc_clk |= GENMASK(21, 16);/* RX clock delay line */meson_mmc_clk |= GENMASK(27, 22);/* clk always on */meson_mmc_clk |= BIT(28);/* clk irq sdio sleep */meson_mmc_clk |= BIT(29);/* clk irq sdio sleep_ds */meson_mmc_clk |= BIT(30);+#endif /* clock settings */ meson_mmc_clk |= clk_src; meson_mmc_clk |= clk_div;
Le 22/01/2020 à 13:06, Anand Moon a écrit :
As per mainline line kernel fix the clk tunig phase for mmc, set Core=180, Tx=180, Rx=0 clk phase for mmc initialization. As per S905X and S922X datasheet set the default values for clk tuning.
Please add you also add AXG/G12 setup.
Signed-off-by: Anand Moon linux.amoon@gmail.com
Changes from previous v3 Fix the initialization of core clk tunning phase as per datasheet. Fix the commit message.
v2: Fix the clk phase macro to support PHASE_180 drop the wrong CLK_CORE_PHASE_MASK macro.
v1: use the mainline kernel tuning for clk tuning.
Fixed the commmit messages. Patch v1: https://patchwork.ozlabs.org/patch/1201208/
Before these changes. clock is enabled (380953Hz) clock is enabled (25000000Hz) After these changes clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
arch/arm/include/asm/arch-meson/sd_emmc.h | 11 ++----- drivers/mmc/meson_gx_mmc.c | 38 +++++++++++++++++++---- 2 files changed, 35 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h index e3a72c8b66..c193547aad 100644 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h @@ -7,6 +7,7 @@ #define __SD_EMMC_H__
#include <mmc.h> +#include <linux/bitops.h>
#define SDIO_PORT_A 0 #define SDIO_PORT_B 1 @@ -19,14 +20,8 @@ #define CLK_MAX_DIV 63 #define CLK_SRC_24M (0 << 6) #define CLK_SRC_DIV2 (1 << 6) -#define CLK_CO_PHASE_000 (0 << 8) -#define CLK_CO_PHASE_090 (1 << 8) -#define CLK_CO_PHASE_180 (2 << 8) -#define CLK_CO_PHASE_270 (3 << 8) -#define CLK_TX_PHASE_000 (0 << 10) -#define CLK_TX_PHASE_090 (1 << 10) -#define CLK_TX_PHASE_180 (2 << 10) -#define CLK_TX_PHASE_270 (3 << 10) +#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
A macro already exists for that: FIELD_PREP(), please use it with proper BIT and GENMASK defines.
#define CLK_ALWAYS_ON BIT(24)
#define MESON_SD_EMMC_CFG 0x44 diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 86c1a7164a..67b1b075ab 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -51,12 +51,38 @@ static void meson_mmc_config_clock(struct mmc *mmc) } clk_div = DIV_ROUND_UP(clk, mmc->clock);
- /* 180 phase core clock */
- meson_mmc_clk |= CLK_CO_PHASE_180;
- /* 180 phase tx clock */
- meson_mmc_clk |= CLK_TX_PHASE_000;
- /* Clock divider */
- meson_mmc_clk = GENMASK(5, 0);
- /* Clock source 1: Fix PLL, 1000MHz */
- meson_mmc_clk |= UPDATE(1, 7, 6);
- /* Core clock phase 2:180 */
- meson_mmc_clk |= UPDATE(2, 9, 8);
- /* TX clock phase 2:180 */
- meson_mmc_clk |= UPDATE(2, 11, 10);
- /* RX clock phase 0:180 */
- meson_mmc_clk |= UPDATE(0, 13, 12);
+#ifdef CONFIG_MESON_GX
- /* TX clock delay line */
- meson_mmc_clk |= GENMASK(19, 16);
- /* RX clock delay line */
- meson_mmc_clk |= GENMASK(23, 20);
- /* clk always on */
- meson_mmc_clk |= BIT(20);
- /* clk irq sdio sleep */
- meson_mmc_clk |= BIT(25);
+#endif +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
- /* TX clock delay line */
- meson_mmc_clk |= GENMASK(21, 16);
- /* RX clock delay line */
- meson_mmc_clk |= GENMASK(27, 22);
- /* clk always on */
- meson_mmc_clk |= BIT(28);
- /* clk irq sdio sleep */
- meson_mmc_clk |= BIT(29);
- /* clk irq sdio sleep_ds */
- meson_mmc_clk |= BIT(30);
As Jaehoon wrote, please define these MASKs and BITs
+#endif
Instead of ifdef, please add a data in the compatible list and use thez fact we use amlogic,meson-axg-mmc on AXG & G12/SM1.
Example: https://github.com/u-boot/u-boot/blob/master/drivers/video/meson/meson_vpu.c... and https://github.com/u-boot/u-boot/blob/master/drivers/video/meson/meson_vpu.c...
/* clock settings */ meson_mmc_clk |= clk_src; meson_mmc_clk |= clk_div;
Thanks, Neil
Hi Neil,
On Sat, 1 Feb 2020 at 12:54, Neil Armstrong narmstrong@baylibre.com wrote:
Le 22/01/2020 à 13:06, Anand Moon a écrit :
As per mainline line kernel fix the clk tunig phase for mmc, set Core=180, Tx=180, Rx=0 clk phase for mmc initialization. As per S905X and S922X datasheet set the default values for clk tuning.
Please add you also add AXG/G12 setup.
Ok.
Signed-off-by: Anand Moon linux.amoon@gmail.com
Changes from previous v3 Fix the initialization of core clk tunning phase as per datasheet. Fix the commit message.
v2: Fix the clk phase macro to support PHASE_180 drop the wrong CLK_CORE_PHASE_MASK macro.
v1: use the mainline kernel tuning for clk tuning.
Fixed the commmit messages. Patch v1: https://patchwork.ozlabs.org/patch/1201208/
Before these changes. clock is enabled (380953Hz) clock is enabled (25000000Hz) After these changes clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
arch/arm/include/asm/arch-meson/sd_emmc.h | 11 ++----- drivers/mmc/meson_gx_mmc.c | 38 +++++++++++++++++++---- 2 files changed, 35 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h index e3a72c8b66..c193547aad 100644 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h @@ -7,6 +7,7 @@ #define __SD_EMMC_H__
#include <mmc.h> +#include <linux/bitops.h>
#define SDIO_PORT_A 0 #define SDIO_PORT_B 1 @@ -19,14 +20,8 @@ #define CLK_MAX_DIV 63 #define CLK_SRC_24M (0 << 6) #define CLK_SRC_DIV2 (1 << 6) -#define CLK_CO_PHASE_000 (0 << 8) -#define CLK_CO_PHASE_090 (1 << 8) -#define CLK_CO_PHASE_180 (2 << 8) -#define CLK_CO_PHASE_270 (3 << 8) -#define CLK_TX_PHASE_000 (0 << 10) -#define CLK_TX_PHASE_090 (1 << 10) -#define CLK_TX_PHASE_180 (2 << 10) -#define CLK_TX_PHASE_270 (3 << 10) +#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
A macro already exists for that: FIELD_PREP(), please use it with proper BIT and GENMASK defines.
Thanks for this input.
#define CLK_ALWAYS_ON BIT(24)
#define MESON_SD_EMMC_CFG 0x44 diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 86c1a7164a..67b1b075ab 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -51,12 +51,38 @@ static void meson_mmc_config_clock(struct mmc *mmc) } clk_div = DIV_ROUND_UP(clk, mmc->clock);
/* 180 phase core clock */meson_mmc_clk |= CLK_CO_PHASE_180;/* 180 phase tx clock */meson_mmc_clk |= CLK_TX_PHASE_000;
/* Clock divider */meson_mmc_clk = GENMASK(5, 0);/* Clock source 1: Fix PLL, 1000MHz */meson_mmc_clk |= UPDATE(1, 7, 6);/* Core clock phase 2:180 */meson_mmc_clk |= UPDATE(2, 9, 8);/* TX clock phase 2:180 */meson_mmc_clk |= UPDATE(2, 11, 10);/* RX clock phase 0:180 */meson_mmc_clk |= UPDATE(0, 13, 12);+#ifdef CONFIG_MESON_GX
/* TX clock delay line */meson_mmc_clk |= GENMASK(19, 16);/* RX clock delay line */meson_mmc_clk |= GENMASK(23, 20);/* clk always on */meson_mmc_clk |= BIT(20);/* clk irq sdio sleep */meson_mmc_clk |= BIT(25);+#endif +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
/* TX clock delay line */meson_mmc_clk |= GENMASK(21, 16);/* RX clock delay line */meson_mmc_clk |= GENMASK(27, 22);/* clk always on */meson_mmc_clk |= BIT(28);/* clk irq sdio sleep */meson_mmc_clk |= BIT(29);/* clk irq sdio sleep_ds */meson_mmc_clk |= BIT(30);As Jaehoon wrote, please define these MASKs and BITs
+#endif
Instead of ifdef, please add a data in the compatible list and use thez fact we use amlogic,meson-axg-mmc on AXG & G12/SM1.
Example: https://github.com/u-boot/u-boot/blob/master/drivers/video/meson/meson_vpu.c... and https://github.com/u-boot/u-boot/blob/master/drivers/video/meson/meson_vpu.c...
Ok, Thanks for the input.
/* clock settings */ meson_mmc_clk |= clk_src; meson_mmc_clk |= clk_div;Thanks, Neil
-Anand
Add missing mmc alias to dts nodes to avoid below debug warning.
mmc_bind: alias ret=-2, devnum=-1 mmc_bind: alias ret=-2, devnum=-1
Signed-off-by: Anand Moon linux.amoon@gmail.com --- arch/arm/dts/meson-axg-s400.dts | 2 ++ arch/arm/dts/meson-g12a-sei510.dts | 3 +++ arch/arm/dts/meson-g12a-u200.dts | 3 +++ arch/arm/dts/meson-g12b-odroid-n2.dts | 3 +++ arch/arm/dts/meson-gxbb-odroidc2.dts | 3 +++ arch/arm/dts/meson-gxbb-p20x.dtsi | 3 +++ arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 3 +++ arch/arm/dts/meson-gxl-s905x-p212.dtsi | 3 +++ arch/arm/dts/meson-gxm-khadas-vim2.dts | 3 +++ arch/arm/dts/meson-sm1-sei610.dts | 3 +++ 10 files changed, 29 insertions(+)
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts index 18778ada7b..b0192a9720 100644 --- a/arch/arm/dts/meson-axg-s400.dts +++ b/arch/arm/dts/meson-axg-s400.dts @@ -58,6 +58,8 @@ aliases { serial0 = &uart_AO; serial1 = &uart_A; + mmc1 = &sd_emmc_b; + mmc2 = &sd_emmc_c; };
linein: audio-codec@0 { diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts index c7a8736885..0e6378a320 100644 --- a/arch/arm/dts/meson-g12a-sei510.dts +++ b/arch/arm/dts/meson-g12a-sei510.dts @@ -31,6 +31,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac; + mmc0 = &sd_emmc_a; + mmc1 = &sd_emmc_b; + mmc2 = &sd_emmc_c; };
mono_dac: audio-codec-0 { diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts index 8551fbd4a4..88b4d365f8 100644 --- a/arch/arm/dts/meson-g12a-u200.dts +++ b/arch/arm/dts/meson-g12a-u200.dts @@ -16,6 +16,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac; + mmc0 = &sd_emmc_a; + mmc1 = &sd_emmc_b; + mmc2 = &sd_emmc_c; };
chosen { diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts index 42f1540575..888429b1cc 100644 --- a/arch/arm/dts/meson-g12b-odroid-n2.dts +++ b/arch/arm/dts/meson-g12b-odroid-n2.dts @@ -18,6 +18,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac; + mmc0 = &sd_emmc_a; + mmc1 = &sd_emmc_b; + mmc2 = &sd_emmc_c; };
chosen { diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts index 54954b314a..1436002013 100644 --- a/arch/arm/dts/meson-gxbb-odroidc2.dts +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts @@ -17,6 +17,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac; + mmc0 = &sd_emmc_a; + mmc1 = &sd_emmc_b; + mmc2 = &sd_emmc_c; };
chosen { diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi index 0be0f2a5d2..d55f5e1abb 100644 --- a/arch/arm/dts/meson-gxbb-p20x.dtsi +++ b/arch/arm/dts/meson-gxbb-p20x.dtsi @@ -11,6 +11,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac; + mmc0 = &sd_emmc_a; + mmc1 = &sd_emmc_b; + mmc2 = &sd_emmc_c; };
chosen { diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts index 82b1c48511..6422e11e5e 100644 --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts @@ -20,6 +20,9 @@ serial0 = &uart_AO; ethernet0 = ðmac; spi0 = &spifc; + mmc0 = &sd_emmc_a; + mmc1 = &sd_emmc_b; + mmc2 = &sd_emmc_c; };
chosen { diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi index a1b31013ab..d712e9fa1d 100644 --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi @@ -17,6 +17,9 @@ serial0 = &uart_AO; serial1 = &uart_A; ethernet0 = ðmac; + mmc0 = &sd_emmc_a; + mmc1 = &sd_emmc_b; + mmc2 = &sd_emmc_c; };
chosen { diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts index 782e9edac8..723061f0e2 100644 --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts @@ -20,6 +20,9 @@ serial0 = &uart_AO; serial1 = &uart_A; serial2 = &uart_AO_B; + mmc0 = &sd_emmc_a; + mmc1 = &sd_emmc_b; + mmc2 = &sd_emmc_c; };
chosen { diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts index 3435aaa4e8..3aafc20ccd 100644 --- a/arch/arm/dts/meson-sm1-sei610.dts +++ b/arch/arm/dts/meson-sm1-sei610.dts @@ -17,6 +17,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac; + mmc0 = &sd_emmc_a; + mmc1 = &sd_emmc_b; + mmc2 = &sd_emmc_c; };
chosen {
Hi,
On 22/01/2020 13:06, Anand Moon wrote:
Add missing mmc alias to dts nodes to avoid below debug warning.
mmc_bind: alias ret=-2, devnum=-1 mmc_bind: alias ret=-2, devnum=-1
Signed-off-by: Anand Moon linux.amoon@gmail.com
arch/arm/dts/meson-axg-s400.dts | 2 ++ arch/arm/dts/meson-g12a-sei510.dts | 3 +++ arch/arm/dts/meson-g12a-u200.dts | 3 +++ arch/arm/dts/meson-g12b-odroid-n2.dts | 3 +++ arch/arm/dts/meson-gxbb-odroidc2.dts | 3 +++ arch/arm/dts/meson-gxbb-p20x.dtsi | 3 +++ arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 3 +++ arch/arm/dts/meson-gxl-s905x-p212.dtsi | 3 +++ arch/arm/dts/meson-gxm-khadas-vim2.dts | 3 +++ arch/arm/dts/meson-sm1-sei610.dts | 3 +++ 10 files changed, 29 insertions(+)
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts index 18778ada7b..b0192a9720 100644 --- a/arch/arm/dts/meson-axg-s400.dts +++ b/arch/arm/dts/meson-axg-s400.dts @@ -58,6 +58,8 @@ aliases { serial0 = &uart_AO; serial1 = &uart_A;
mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c;};
linein: audio-codec@0 {
diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts index c7a8736885..0e6378a320 100644 --- a/arch/arm/dts/meson-g12a-sei510.dts +++ b/arch/arm/dts/meson-g12a-sei510.dts @@ -31,6 +31,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c;};
mono_dac: audio-codec-0 {
diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts index 8551fbd4a4..88b4d365f8 100644 --- a/arch/arm/dts/meson-g12a-u200.dts +++ b/arch/arm/dts/meson-g12a-u200.dts @@ -16,6 +16,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c;};
chosen {
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts index 42f1540575..888429b1cc 100644 --- a/arch/arm/dts/meson-g12b-odroid-n2.dts +++ b/arch/arm/dts/meson-g12b-odroid-n2.dts @@ -18,6 +18,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c;};
chosen {
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts index 54954b314a..1436002013 100644 --- a/arch/arm/dts/meson-gxbb-odroidc2.dts +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts @@ -17,6 +17,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c;};
chosen {
diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi index 0be0f2a5d2..d55f5e1abb 100644 --- a/arch/arm/dts/meson-gxbb-p20x.dtsi +++ b/arch/arm/dts/meson-gxbb-p20x.dtsi @@ -11,6 +11,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c;};
chosen {
diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts index 82b1c48511..6422e11e5e 100644 --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts @@ -20,6 +20,9 @@ serial0 = &uart_AO; ethernet0 = ðmac; spi0 = &spifc;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c;};
chosen {
diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi index a1b31013ab..d712e9fa1d 100644 --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi @@ -17,6 +17,9 @@ serial0 = &uart_AO; serial1 = &uart_A; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c;};
chosen {
diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts index 782e9edac8..723061f0e2 100644 --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts @@ -20,6 +20,9 @@ serial0 = &uart_AO; serial1 = &uart_A; serial2 = &uart_AO_B;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c;};
chosen {
diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts index 3435aaa4e8..3aafc20ccd 100644 --- a/arch/arm/dts/meson-sm1-sei610.dts +++ b/arch/arm/dts/meson-sm1-sei610.dts @@ -17,6 +17,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c;};
chosen {
Since it's not a linux binding but u-boot specific, please move these to the -u-boot.dtsi instead
Neil
Hi Neil,
On Wed, 22 Jan 2020 at 17:44, Neil Armstrong narmstrong@baylibre.com wrote:
Hi,
On 22/01/2020 13:06, Anand Moon wrote:
Add missing mmc alias to dts nodes to avoid below debug warning.
mmc_bind: alias ret=-2, devnum=-1 mmc_bind: alias ret=-2, devnum=-1
Signed-off-by: Anand Moon linux.amoon@gmail.com
arch/arm/dts/meson-axg-s400.dts | 2 ++ arch/arm/dts/meson-g12a-sei510.dts | 3 +++ arch/arm/dts/meson-g12a-u200.dts | 3 +++ arch/arm/dts/meson-g12b-odroid-n2.dts | 3 +++ arch/arm/dts/meson-gxbb-odroidc2.dts | 3 +++ arch/arm/dts/meson-gxbb-p20x.dtsi | 3 +++ arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 3 +++ arch/arm/dts/meson-gxl-s905x-p212.dtsi | 3 +++ arch/arm/dts/meson-gxm-khadas-vim2.dts | 3 +++ arch/arm/dts/meson-sm1-sei610.dts | 3 +++ 10 files changed, 29 insertions(+)
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts index 18778ada7b..b0192a9720 100644 --- a/arch/arm/dts/meson-axg-s400.dts +++ b/arch/arm/dts/meson-axg-s400.dts @@ -58,6 +58,8 @@ aliases { serial0 = &uart_AO; serial1 = &uart_A;
mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c; }; linein: audio-codec@0 {diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts index c7a8736885..0e6378a320 100644 --- a/arch/arm/dts/meson-g12a-sei510.dts +++ b/arch/arm/dts/meson-g12a-sei510.dts @@ -31,6 +31,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c; }; mono_dac: audio-codec-0 {diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts index 8551fbd4a4..88b4d365f8 100644 --- a/arch/arm/dts/meson-g12a-u200.dts +++ b/arch/arm/dts/meson-g12a-u200.dts @@ -16,6 +16,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c; }; chosen {diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts index 42f1540575..888429b1cc 100644 --- a/arch/arm/dts/meson-g12b-odroid-n2.dts +++ b/arch/arm/dts/meson-g12b-odroid-n2.dts @@ -18,6 +18,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c; }; chosen {diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts index 54954b314a..1436002013 100644 --- a/arch/arm/dts/meson-gxbb-odroidc2.dts +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts @@ -17,6 +17,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c; }; chosen {diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi index 0be0f2a5d2..d55f5e1abb 100644 --- a/arch/arm/dts/meson-gxbb-p20x.dtsi +++ b/arch/arm/dts/meson-gxbb-p20x.dtsi @@ -11,6 +11,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c; }; chosen {diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts index 82b1c48511..6422e11e5e 100644 --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts @@ -20,6 +20,9 @@ serial0 = &uart_AO; ethernet0 = ðmac; spi0 = &spifc;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c; }; chosen {diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi index a1b31013ab..d712e9fa1d 100644 --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi @@ -17,6 +17,9 @@ serial0 = &uart_AO; serial1 = &uart_A; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c; }; chosen {diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts index 782e9edac8..723061f0e2 100644 --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts @@ -20,6 +20,9 @@ serial0 = &uart_AO; serial1 = &uart_A; serial2 = &uart_AO_B;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c; }; chosen {diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts index 3435aaa4e8..3aafc20ccd 100644 --- a/arch/arm/dts/meson-sm1-sei610.dts +++ b/arch/arm/dts/meson-sm1-sei610.dts @@ -17,6 +17,9 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac;
mmc0 = &sd_emmc_a;mmc1 = &sd_emmc_b;mmc2 = &sd_emmc_c; }; chosen {Since it's not a linux binding but u-boot specific, please move these to the -u-boot.dtsi instead
Neil
Thanks for your review.
Ok I will move all the aliase to common meson-gx-u-boot.dtsi file..
-Anand
Add cd-gpio property for eMMC node.
Signed-off-by: Anand Moon linux.amoon@gmail.com --- New patch in this series --- arch/arm/dts/meson-g12b-odroid-n2.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts index 888429b1cc..23ec14abe7 100644 --- a/arch/arm/dts/meson-g12b-odroid-n2.dts +++ b/arch/arm/dts/meson-g12b-odroid-n2.dts @@ -449,6 +449,7 @@ max-frequency = <200000000>; disable-wp;
+ cd-gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; /* eMMC_nDET */ mmc-pwrseq = <&emmc_pwrseq>; vmmc-supply = <&vcc_3v3>; vqmmc-supply = <&flash_1v8>;
Hi,
On 22/01/2020 13:06, Anand Moon wrote:
Add cd-gpio property for eMMC node.
Signed-off-by: Anand Moon linux.amoon@gmail.com
New patch in this series
arch/arm/dts/meson-g12b-odroid-n2.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts index 888429b1cc..23ec14abe7 100644 --- a/arch/arm/dts/meson-g12b-odroid-n2.dts +++ b/arch/arm/dts/meson-g12b-odroid-n2.dts @@ -449,6 +449,7 @@ max-frequency = <200000000>; disable-wp;
- cd-gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; /* eMMC_nDET */ mmc-pwrseq = <&emmc_pwrseq>; vmmc-supply = <&vcc_3v3>; vqmmc-supply = <&flash_1v8>;
If it's missing, submit it to linux-amlogic and move it to the -u-boot.dtsi file.
Neil
Hi Neil,
On Wed, 22 Jan 2020 at 17:45, Neil Armstrong narmstrong@baylibre.com wrote:
Hi,
On 22/01/2020 13:06, Anand Moon wrote:
Add cd-gpio property for eMMC node.
Signed-off-by: Anand Moon linux.amoon@gmail.com
New patch in this series
arch/arm/dts/meson-g12b-odroid-n2.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts index 888429b1cc..23ec14abe7 100644 --- a/arch/arm/dts/meson-g12b-odroid-n2.dts +++ b/arch/arm/dts/meson-g12b-odroid-n2.dts @@ -449,6 +449,7 @@ max-frequency = <200000000>; disable-wp;
cd-gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; /* eMMC_nDET */ mmc-pwrseq = <&emmc_pwrseq>; vmmc-supply = <&vcc_3v3>; vqmmc-supply = <&flash_1v8>;If it's missing, submit it to linux-amlogic and move it to the -u-boot.dtsi file.
Neil
Thanks for your review. Ok I will submit this patch to linux-amlogic
-Anand
participants (3)
-
Anand Moon -
Jaehoon Chung -
Neil Armstrong