This driver works in "new" Data Mover UART mode, so will be compatible with modern Qualcomm chips only.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: - Add msm_serial_fetch that tries to fetch characters from FIFO - Decrease no of characters requested in RX transaction - Try to fetch characters from FIFO when tstc()/pending() is called

Changes in v2: - Added newline before return... (globally) - Renamed p to priv (priv data) - it required some rewrapping - Added Reviewed-by

Changes in v1: - Added (better) help to KConfig - Added dt binding documentation - Fixed include ordering - Reworked msm_serial_getc - Added error handling to msm_uart_clk_init (that is ignored later for now) - Dropped unneeded DM_FLAG_PRE_RELOC

doc/device-tree-bindings/serial/msm-serial.txt | 6 + drivers/serial/Kconfig | 8 + drivers/serial/Makefile | 1 + drivers/serial/serial_msm.c | 217 +++++++++++++++++++++++++ 4 files changed, 232 insertions(+) create mode 100644 doc/device-tree-bindings/serial/msm-serial.txt create mode 100644 drivers/serial/serial_msm.c

diff --git a/doc/device-tree-bindings/serial/msm-serial.txt b/doc/device-tree-bindings/serial/msm-serial.txt new file mode 100644 index 0000000..48b8428 --- /dev/null +++ b/doc/device-tree-bindings/serial/msm-serial.txt @@ -0,0 +1,6 @@ +Qualcomm UART (Data Mover mode) + +Required properties: +- compatible: must be "qcom,msm-uartdm-v1.4" +- reg: start address and size of the registers +- clock: interface clock (must accept baudrate as a frequency) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 2a770a1..a9a5d47 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -320,4 +320,12 @@ config XILINX_UARTLITE If you have a Xilinx based board and want to use the uartlite serial ports, say Y to this option. If unsure, say N.

+config MSM_SERIAL + bool "Qualcomm on-chip UART" + depends on DM_SERIAL + help + Support Data Mover UART used on Qualcomm Snapdragon SoCs. + It should support all Qualcomm devices with UARTDM version 1.4, + for example APQ8016 and MSM8916. + Single baudrate is supported in current implementation (115200). endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index ee7147a..b0ac9d8 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o +obj-$(CONFIG_MSM_SERIAL) += serial_msm.o

ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c new file mode 100644 index 0000000..80fb89e --- /dev/null +++ b/drivers/serial/serial_msm.c @@ -0,0 +1,217 @@ +/* + * Qualcomm UART driver + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * UART will work in Data Mover mode. + * Based on Linux driver. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <serial.h> +#include <watchdog.h> +#include <asm/io.h> +#include <linux/compiler.h> + +/* Serial registers - this driver works in uartdm mode*/ + +#define UARTDM_DMRX 0x34 /* Max RX transfer length */ +#define UARTDM_NCF_TX 0x40 /* Number of chars to TX */ + +#define UARTDM_RXFS 0x50 /* RX channel status register */ +#define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */ +#define UARTDM_RXFS_BUF_MASK 0x7 + +#define UARTDM_SR 0xA4 /* Status register */ +#define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */ +#define UARTDM_SR_TX_EMPTY (1 << 3) /* Transmitter underrun */ +#define UARTDM_SR_UART_OVERRUN (1 << 4) /* Receive overrun */ + +#define UARTDM_CR 0xA8 /* Command register */ +#define UARTDM_CR_CMD_RESET_ERR (3 << 4) /* Clear overrun error */ +#define UARTDM_CR_CMD_RESET_STALE_INT (8 << 4) /* Clears stale irq */ +#define UARTDM_CR_CMD_RESET_TX_READY (3 << 8) /* Clears TX Ready irq*/ +#define UARTDM_CR_CMD_FORCE_STALE (4 << 8) /* Causes stale event */ +#define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */ + +#define UARTDM_IMR 0xB0 /* Interrupt mask register */ +#define UARTDM_ISR 0xB4 /* Interrupt status register */ +#define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */ + +#define UARTDM_TF 0x100 /* UART Transmit FIFO register */ +#define UARTDM_RF 0x140 /* UART Receive FIFO register */ + + +DECLARE_GLOBAL_DATA_PTR; + +struct msm_serial_data { + phys_addr_t base; + unsigned chars_cnt; /* number of buffered chars */ + uint32_t chars_buf; /* buffered chars */ +}; + +static int msm_serial_fetch(struct udevice *dev) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + unsigned sr; + + if (priv->chars_cnt) + return priv->chars_cnt; + + /* Clear error in case of buffer overrun */ + if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN) + writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR); + + /* We need to fetch new character */ + sr = readl(priv->base + UARTDM_SR); + + if (sr & UARTDM_SR_RX_READY) { + /* There are at least 4 bytes in fifo */ + priv->chars_buf = readl(priv->base + UARTDM_RF); + priv->chars_cnt = 4; + } else { + /* Check if there is anything in fifo */ + priv->chars_cnt = readl(priv->base + UARTDM_RXFS); + /* Extract number of characters in UART packing buffer*/ + priv->chars_cnt = (priv->chars_cnt >> + UARTDM_RXFS_BUF_SHIFT) & + UARTDM_RXFS_BUF_MASK; + if (!priv->chars_cnt) + return 0; + + /* There is at least one charcter, move it to fifo */ + writel(UARTDM_CR_CMD_FORCE_STALE, + priv->base + UARTDM_CR); + + priv->chars_buf = readl(priv->base + UARTDM_RF); + writel(UARTDM_CR_CMD_RESET_STALE_INT, + priv->base + UARTDM_CR); + writel(0x7, priv->base + UARTDM_DMRX); + } + + return priv->chars_cnt; +} + +static int msm_serial_getc(struct udevice *dev) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + char c; + + if (!msm_serial_fetch(dev)) + return -EAGAIN; + + c = priv->chars_buf & 0xFF; + priv->chars_buf >>= 8; + priv->chars_cnt--; + + return c; +} + +static int msm_serial_putc(struct udevice *dev, const char ch) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + + if (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) && + !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY)) + return -EAGAIN; + + writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR); + + writel(1, priv->base + UARTDM_NCF_TX); + writel(ch, priv->base + UARTDM_TF); + + return 0; +} + +static int msm_serial_pending(struct udevice *dev, bool input) +{ + if (input) { + if (msm_serial_fetch(dev)) + return 1; + } + + return 0; +} + +static const struct dm_serial_ops msm_serial_ops = { + .putc = msm_serial_putc, + .pending = msm_serial_pending, + .getc = msm_serial_getc, +}; + +static int msm_uart_clk_init(struct udevice *dev) +{ + uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "clock-frequency", 115200); + uint clkd[2]; /* clk_id and clk_no */ + int clk_offset; + struct udevice *clk; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd, + 2); + if (ret) + return ret; + + clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]); + if (clk_offset < 0) + return clk_offset; + + ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk); + if (ret) + return ret; + + ret = clk_set_periph_rate(clk, clkd[1], clk_rate); + if (ret < 0) + return ret; + + return 0; +} + +static int msm_serial_probe(struct udevice *dev) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + + msm_uart_clk_init(dev); /* Ignore return value and hope clock was + properly initialized by earlier loaders */ + + if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN) + writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR); + + writel(0, priv->base + UARTDM_IMR); + writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, priv->base + UARTDM_CR); + msm_serial_fetch(dev); + + return 0; +} + +static int msm_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + + priv->base = dev_get_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static const struct udevice_id msm_serial_ids[] = { + { .compatible = "qcom,msm-uartdm-v1.4" }, + { } +}; + +U_BOOT_DRIVER(serial_msm) = { + .name = "serial_msm", + .id = UCLASS_SERIAL, + .of_match = msm_serial_ids, + .ofdata_to_platdata = msm_serial_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct msm_serial_data), + .probe = msm_serial_probe, + .ops = &msm_serial_ops, +};

Add support for gpio controllers on Qualcomm Snapdragon devices. This devices are usually called Top Level Mode Multiplexing in Qualcomm documentation.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: - Reordered includes (again) - Added newlines between returns - Fixed error handling in msm_gpio_probe - Added reviewed-by

Changes in v1: - Added dt binding documentation - Added help to KConfig - Use clrsetbits() to switch direction - Fixed include order - Added #defines for registers/register fields - Added secondary compatible string

doc/device-tree-bindings/gpio/gpio-msm.txt | 22 +++++ drivers/gpio/Kconfig | 14 +++ drivers/gpio/Makefile | 1 + drivers/gpio/msm_gpio.c | 135 +++++++++++++++++++++++++++++ 4 files changed, 172 insertions(+) create mode 100644 doc/device-tree-bindings/gpio/gpio-msm.txt create mode 100644 drivers/gpio/msm_gpio.c

diff --git a/doc/device-tree-bindings/gpio/gpio-msm.txt b/doc/device-tree-bindings/gpio/gpio-msm.txt new file mode 100644 index 0000000..966ce0a --- /dev/null +++ b/doc/device-tree-bindings/gpio/gpio-msm.txt @@ -0,0 +1,22 @@ +Qualcomm Snapdragon GPIO controller + +Required properties: +- compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl" +- reg : Physical base address and length of the controller's registers. + This controller is called "Top Level Mode Multiplexing" in + Qualcomm documentation. +- #gpio-cells : Should be one (pin number). +- gpio-controller : Marks the device node as a GPIO controller. +- gpio-count: Number of GPIO pins. +- gpio-bank-name: (optional) name of gpio bank. As default "soc" is used. + +Example: + +soc_gpios: pinctrl@1000000 { + compatible = "qcom,msm8916-pinctrl"; + reg = <0x1000000 0x300000>; + gpio-controller; + gpio-count = <122>; + gpio-bank-name="soc"; + #gpio-cells = <1>; +}; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 2311309..4d9e74c 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -55,6 +55,20 @@ config LPC32XX_GPIO help Support for the LPC32XX GPIO driver.

+config MSM_GPIO + bool "Qualcomm GPIO driver" + depends on DM_GPIO + default n + help + Support GPIO controllers on Qualcomm Snapdragon family of SoCs. + This controller have single bank (default name "soc"), every + gpio has it's own set of registers. + Only simple GPIO operations are supported (get/set, change of + direction and checking pin function). + Supported devices: + - APQ8016 + - MSM8916 + config ROCKCHIP_GPIO bool "Rockchip GPIO driver" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index ea6e2ed..4162c3c 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -50,3 +50,4 @@ obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o +obj-$(CONFIG_MSM_GPIO) += msm_gpio.o diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c new file mode 100644 index 0000000..950f309 --- /dev/null +++ b/drivers/gpio/msm_gpio.c @@ -0,0 +1,135 @@ +/* + * Qualcomm GPIO driver + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <asm/gpio.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Register offsets */ +#define GPIO_CONFIG_OFF(no) ((no) * 0x1000) +#define GPIO_IN_OUT_OFF(no) ((no) * 0x1000 + 0x4) + +/* OE */ +#define GPIO_OE_DISABLE (0x0 << 9) +#define GPIO_OE_ENABLE (0x1 << 9) +#define GPIO_OE_MASK (0x1 << 9) + +/* GPIO_IN_OUT register shifts. */ +#define GPIO_IN 0 +#define GPIO_OUT 1 + +struct msm_gpio_bank { + phys_addr_t base; +}; + +static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) +{ + struct msm_gpio_bank *priv = dev_get_priv(dev); + phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio); + + /* Disable OE bit */ + clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE); + + return 0; +} + +static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value) +{ + struct msm_gpio_bank *priv = dev_get_priv(dev); + + value = !!value; + /* set value */ + writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio)); + + return 0; +} + +static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) +{ + struct msm_gpio_bank *priv = dev_get_priv(dev); + phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio); + + value = !!value; + /* set value */ + writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio)); + /* switch direction */ + clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_ENABLE); + + return 0; +} + +static int msm_gpio_get_value(struct udevice *dev, unsigned gpio) +{ + struct msm_gpio_bank *priv = dev_get_priv(dev); + + return !!(readl(priv->base + GPIO_IN_OUT_OFF(gpio)) >> GPIO_IN); +} + +static int msm_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct msm_gpio_bank *priv = dev_get_priv(dev); + + if (readl(priv->base + GPIO_CONFIG_OFF(offset)) & GPIO_OE_ENABLE) + return GPIOF_OUTPUT; + + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops gpio_msm_ops = { + .direction_input = msm_gpio_direction_input, + .direction_output = msm_gpio_direction_output, + .get_value = msm_gpio_get_value, + .set_value = msm_gpio_set_value, + .get_function = msm_gpio_get_function, +}; + +static int msm_gpio_probe(struct udevice *dev) +{ + struct msm_gpio_bank *priv = dev_get_priv(dev); + + priv->base = dev_get_addr(dev); + + return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; +} + +static int msm_gpio_ofdata_to_platdata(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "gpio-count", 0); + uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, + "gpio-bank-name", NULL); + if (uc_priv->bank_name == NULL) + uc_priv->bank_name = "soc"; + + return 0; +} + +static const struct udevice_id msm_gpio_ids[] = { + { .compatible = "qcom,msm8916-pinctrl" }, + { .compatible = "qcom,apq8016-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(gpio_msm) = { + .name = "gpio_msm", + .id = UCLASS_GPIO, + .of_match = msm_gpio_ids, + .ofdata_to_platdata = msm_gpio_ofdata_to_platdata, + .probe = msm_gpio_probe, + .ops = &gpio_msm_ops, + .priv_auto_alloc_size = sizeof(struct msm_gpio_bank), +}; + +

Add support for SD/eMMC controller present on some Qualcomm Snapdragon devices. This controller implements SDHCI 2.0 interface but requires vendor-specific initialization. Driver works in PIO mode as ADMA is not supported by U-Boot (yet).

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: - Add reviewed-by

Changes in v1: - Added commit message - Added DT binding documentation - Added Kconfig help - Reordered includes - Dropped redundant fields from msm_sdhc - Cleaned up clock init code (+ added error handling) - Dropped mdelay - use wait_for_bit instead in reset code - Added missing newline after declarations - Added error handling if "reg" is missing - Converted base address to pointer

doc/device-tree-bindings/mmc/msm_sdhci.txt | 25 ++++ drivers/mmc/Kconfig | 9 ++ drivers/mmc/Makefile | 1 + drivers/mmc/msm_sdhci.c | 180 +++++++++++++++++++++++++++++ 4 files changed, 215 insertions(+) create mode 100644 doc/device-tree-bindings/mmc/msm_sdhci.txt create mode 100644 drivers/mmc/msm_sdhci.c

diff --git a/doc/device-tree-bindings/mmc/msm_sdhci.txt b/doc/device-tree-bindings/mmc/msm_sdhci.txt new file mode 100644 index 0000000..08a290c --- /dev/null +++ b/doc/device-tree-bindings/mmc/msm_sdhci.txt @@ -0,0 +1,25 @@ +Qualcomm Snapdragon SDHCI controller + +Required properties: +- compatible : "qcom,sdhci-msm-v4" +- reg: Base address and length of registers: + - Host controller registers (SDHCI) + - SD Core registers +- clock: interface clock (must accept SD bus clock as a frequency) + +Optional properties: +- index: If there is more than one controller - controller index (required + by generic SDHCI code). +- bus_width: Width of SD/eMMC bus (default 4) +- clock-frequency: Frequency of SD/eMMC bus (default 400 kHz) + +Example: + +sdhci@07864000 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x7864900 0x11c 0x7864000 0x800>; + index = <0x1>; + bus-width = <0x4>; + clock = <&clkc 1>; + clock-frequency = <200000000>; +}; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index dc8532f..4d3df11 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -16,6 +16,15 @@ config DM_MMC appear as block devices in U-Boot and can support filesystems such as EXT4 and FAT.

+config MSM_SDHCI + bool "Qualcomm SDHCI controller" + depends on DM_MMC + help + Enables support for SDHCI 2.0 controller present on some Qualcomm + Snapdragon devices. This device is compatible with eMMC v4.5 and + SD 3.0 specifications. Both SD and eMMC devices are supported. + Card-detect gpios are not supported. + config ROCKCHIP_DWMMC bool "Rockchip SD/MMC controller support" depends on DM_MMC && OF_CONTROL diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index b85e4bf..585aaf3 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -50,3 +50,4 @@ else obj-$(CONFIG_GENERIC_MMC) += mmc_write.o endif obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o +obj-$(CONFIG_MSM_SDHCI) += msm_sdhci.o diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c new file mode 100644 index 0000000..1e2a29b --- /dev/null +++ b/drivers/mmc/msm_sdhci.c @@ -0,0 +1,180 @@ +/* + * Qualcomm SDHCI driver - SD/eMMC controller + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * Based on Linux driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <sdhci.h> +#include <wait_bit.h> +#include <asm/io.h> +#include <linux/bitops.h> + +/* Non-standard registers needed for SDHCI startup */ +#define SDCC_MCI_POWER 0x0 +#define SDCC_MCI_POWER_SW_RST BIT(7) + +/* This is undocumented register */ +#define SDCC_MCI_VERSION 0x50 +#define SDCC_MCI_VERSION_MAJOR_SHIFT 28 +#define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT) +#define SDCC_MCI_VERSION_MINOR_MASK 0xff + +#define SDCC_MCI_STATUS2 0x6C +#define SDCC_MCI_STATUS2_MCI_ACT 0x1 +#define SDCC_MCI_HC_MODE 0x78 + +/* Offset to SDHCI registers */ +#define SDCC_SDHCI_OFFSET 0x900 + +/* Non standard (?) SDHCI register */ +#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c + +struct msm_sdhc { + struct sdhci_host host; + void *base; +}; + +DECLARE_GLOBAL_DATA_PTR; + +static int msm_sdc_clk_init(struct udevice *dev) +{ + uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "clock-frequency", 400000); + uint clkd[2]; /* clk_id and clk_no */ + int clk_offset; + struct udevice *clk; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd, + 2); + if (ret) + return ret; + + clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]); + if (clk_offset < 0) + return clk_offset; + + ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk); + if (ret) + return ret; + + ret = clk_set_periph_rate(clk, clkd[1], clk_rate); + if (ret < 0) + return ret; + + return 0; +} + +static int msm_sdc_probe(struct udevice *dev) +{ + struct msm_sdhc *prv = dev_get_priv(dev); + struct sdhci_host *host = &prv->host; + u32 core_version, core_minor, core_major; + int ret; + + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; + + /* Init clocks */ + ret = msm_sdc_clk_init(dev); + if (ret) + return ret; + + /* Reset the core and Enable SDHC mode */ + writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST, + prv->base + SDCC_MCI_POWER); + + + /* Wait for reset to be written to register */ + if (wait_for_bit(__func__, prv->base + SDCC_MCI_STATUS2, + SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) { + printf("msm_sdhci: reset request failed\n"); + return -EIO; + } + + /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */ + if (wait_for_bit(__func__, prv->base + SDCC_MCI_POWER, + SDCC_MCI_POWER_SW_RST, false, 2, false)) { + printf("msm_sdhci: stuck in reset\n"); + return -ETIMEDOUT; + } + + /* Enable host-controller mode */ + writel(1, prv->base + SDCC_MCI_HC_MODE); + + core_version = readl(prv->base + SDCC_MCI_VERSION); + + core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK); + core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT; + + core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK; + + /* + * Support for some capabilities is not advertised by newer + * controller versions and must be explicitly enabled. + */ + if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { + u32 caps = readl(host->ioaddr + SDHCI_CAPABILITIES); + caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; + writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0); + } + + /* Set host controller version */ + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + + /* automatically detect max and min speed */ + return add_sdhci(host, 0, 0); +} + +static int msm_sdc_remove(struct udevice *dev) +{ + struct msm_sdhc *priv = dev_get_priv(dev); + + /* Disable host-controller mode */ + writel(0, priv->base + SDCC_MCI_HC_MODE); + + return 0; +} + +static int msm_ofdata_to_platdata(struct udevice *dev) +{ + struct udevice *parent = dev->parent; + struct msm_sdhc *priv = dev_get_priv(dev); + struct sdhci_host *host = &priv->host; + + host->name = strdup(dev->name); + host->ioaddr = (void *)dev_get_addr(dev); + host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "bus-width", 4); + host->index = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "index", 0); + priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob, + parent->of_offset, + dev->of_offset, + "reg", 1, NULL); + if (priv->base == (void *)FDT_ADDR_T_NONE || + host->ioaddr == (void *)FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static const struct udevice_id msm_mmc_ids[] = { + { .compatible = "qcom,sdhci-msm-v4" }, + { } +}; + +U_BOOT_DRIVER(msm_sdc_drv) = { + .name = "msm_sdc", + .id = UCLASS_MMC, + .of_match = msm_mmc_ids, + .ofdata_to_platdata = msm_ofdata_to_platdata, + .probe = msm_sdc_probe, + .remove = msm_sdc_remove, + .priv_auto_alloc_size = sizeof(struct msm_sdhc), +};

Some host controllers need addidional initialization after ehci_reset() In non-dm implementation it is possible to use CONFIG_EHCI_HCD_INIT_AFTER_RESET. This patch adds similar option to ehci drivers using dm.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Acked-by: Marek Vasut marex@denx.de Reviewed-by: Tom Rini trini@konsulko.com Reviewed-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: - Add Reviewed-by (sjg)

Changes in v1: - No changes, just added Acked-by, Reviewed-by

drivers/usb/host/ehci-hcd.c | 6 ++++++ drivers/usb/host/ehci.h | 1 + 2 files changed, 7 insertions(+)

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 0113c6c..598f444 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1615,6 +1615,12 @@ int ehci_register(struct udevice *dev, struct ehci_hccr *hccr, if (ret) goto err;

+ if (ops->init_after_reset) { + ret = ops->init_after_reset(ctrl); + if (ret) + goto err; + } + ret = ehci_common_init(ctrl, tweaks); if (ret) goto err; diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 826b3fe..734d7f0 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -240,6 +240,7 @@ struct ehci_ops { void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg, uint32_t *reg); uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port); + int (*init_after_reset)(struct ehci_ctrl *ctrl); };

struct ehci_ctrl {

The following options can be now enabled via defconfig: - CONFIG_USB_ULPI - CONFIG_USB_ULPI_VIEWPORT - CONFIG_USB_ULPI_VIEWPORT_OMAP

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Acked-by: Marek Vasut marex@denx.de ---

Changes in v4: - Add Ack from Marek

Changes in v3: None Changes in v2: - Add better (any) descriptions for Kconfig items.

Changes in v1: None

drivers/usb/Kconfig | 2 ++ drivers/usb/ulpi/Kconfig | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 drivers/usb/ulpi/Kconfig

diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 7fa99c6..bccf43e 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -53,6 +53,8 @@ source "drivers/usb/musb-new/Kconfig"

source "drivers/usb/emul/Kconfig"

+source "drivers/usb/ulpi/Kconfig" + comment "USB peripherals"

config USB_STORAGE diff --git a/drivers/usb/ulpi/Kconfig b/drivers/usb/ulpi/Kconfig new file mode 100644 index 0000000..329d2df --- /dev/null +++ b/drivers/usb/ulpi/Kconfig @@ -0,0 +1,33 @@ +comment "ULPI drivers" + +choice + prompt "ULPI Viewport type" + optional + default n + help + Select ULPI viewport (SoC-side interface to ULPI) implementation + appropriate for the device if you want to communicate with + UTMI (USB PHY) via ULPI interface. + +config USB_ULPI_VIEWPORT + bool "Generic ULPI Viewport" + help + Support generic ULPI Viewport implementation that is used on + some Tegra and Snapdragon devices. + +config USB_ULPI_VIEWPORT_OMAP + bool "OMAP ULPI Viewport" + help + Support ULPI Viewport implementation that is used on OMAP devices. + +endchoice + +config USB_ULPI + bool "ULPI support" + depends on (USB_ULPI_VIEWPORT || USB_ULPI_VIEWPORT_OMAP) + help + Select to commnicate with USB PHY via ULPI interface. + ULPI is wrapper on UTMI+ core that is used as + PHY Transreceiver for USB controllers. + + This driver uses ULPI viewports that are specific for each SoC.

Move CONFIG_USB_ULPI* from headers to defconfigs for boards that use it. Also - add CONFIG_USB where necesarry - all boards use it, but some are not defining it explicitly.

Affected boards: colibri_t20, harmony, mcx, mt_ventoux, twister, zynq_(picozed, zc702, zc706, zed, zybo)

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: - New patch, independent of the rest - Should compile cleanly on all affected platforms - Is orthogonal to series (i.e. if get's NAK will not break rest of series)

Changes in v1: None

configs/colibri_t20_defconfig | 2 ++ configs/harmony_defconfig | 2 ++ configs/mcx_defconfig | 3 +++ configs/mt_ventoux_defconfig | 3 +++ configs/twister_defconfig | 3 +++ configs/zynq_picozed_defconfig | 2 ++ configs/zynq_zc702_defconfig | 2 ++ configs/zynq_zc706_defconfig | 2 ++ configs/zynq_zed_defconfig | 2 ++ configs/zynq_zybo_defconfig | 2 ++ include/configs/colibri_t20.h | 3 +-- include/configs/harmony.h | 2 -- include/configs/mcx.h | 2 -- include/configs/tam3517-common.h | 2 -- include/configs/zynq-common.h | 2 -- 15 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index c36967d..3813e96 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -21,4 +21,6 @@ CONFIG_DM_USB=y CONFIG_USB_GADGET=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index c150f6e..d4aafe9 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -21,4 +21,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig index a25ffcf..9c9d51a 100644 --- a/configs/mcx_defconfig +++ b/configs/mcx_defconfig @@ -12,3 +12,6 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT_OMAP=y diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig index c537440..45913d4 100644 --- a/configs/mt_ventoux_defconfig +++ b/configs/mt_ventoux_defconfig @@ -10,3 +10,6 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT_OMAP=y diff --git a/configs/twister_defconfig b/configs/twister_defconfig index 06c98eb..064cf91 100644 --- a/configs/twister_defconfig +++ b/configs/twister_defconfig @@ -10,3 +10,6 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT_OMAP=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 67e38e5..c730f3c 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -14,3 +14,5 @@ CONFIG_ZYNQ_SDHCI=y CONFIG_ZYNQ_GEM=y CONFIG_USB=y CONFIG_USB_GADGET=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index d1740a7..e8d28e4 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -26,3 +26,5 @@ CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_ZYNQ_QSPI=y CONFIG_USB=y CONFIG_USB_GADGET=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index d3ae438..d19108f 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -23,3 +23,5 @@ CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_QSPI=y CONFIG_USB=y CONFIG_USB_GADGET=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 9ad33ff..b13de10 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -23,3 +23,5 @@ CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_QSPI=y CONFIG_USB=y CONFIG_USB_GADGET=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 470c9cb..4a59890 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -24,3 +24,5 @@ CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_ZYNQ_QSPI=y CONFIG_USB=y CONFIG_USB_GADGET=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index b7ad189..e97e5a1 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -36,8 +36,7 @@ /* USB host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_ULPI -#define CONFIG_USB_ULPI_VIEWPORT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB

diff --git a/include/configs/harmony.h b/include/configs/harmony.h index f66ac70..0a3cb18 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -44,8 +44,6 @@ /* USB Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_ULPI -#define CONFIG_USB_ULPI_VIEWPORT #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB

diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 174cb5c..9a4f638 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -102,8 +102,6 @@ #define CONFIG_OMAP3_GPIO_5 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP -#define CONFIG_USB_ULPI -#define CONFIG_USB_ULPI_VIEWPORT_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_HOST_ETHER diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index a532417..59b6c5f 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -91,8 +91,6 @@ #define CONFIG_OMAP3_GPIO_5 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP -#define CONFIG_USB_ULPI -#define CONFIG_USB_ULPI_VIEWPORT_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_STORAGE diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 9ff3df2..c2ed28a 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -96,8 +96,6 @@ # define CONFIG_CMD_USB # define CONFIG_USB_STORAGE # define CONFIG_USB_EHCI_ZYNQ -# define CONFIG_USB_ULPI_VIEWPORT -# define CONFIG_USB_ULPI # define CONFIG_EHCI_IS_TDI # define CONFIG_USB_MAX_CONTROLLER_COUNT 2

viewport_addr is address of memory mapped ULPI viewport. It is used only as argument to readl/writel later causing compile warnings on 64-bit devices.

This fix changes its type to match pointer size.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Acked-by: Marek Vasut marex@denx.de ---

Changes in v4: - Add Ack from Marek

Changes in v3: - New patch

Changes in v2: None Changes in v1: None

include/usb/ulpi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/usb/ulpi.h b/include/usb/ulpi.h index 4fa765b..dfea395 100644 --- a/include/usb/ulpi.h +++ b/include/usb/ulpi.h @@ -32,7 +32,7 @@ * be extended from this structure */ struct ulpi_viewport { - u32 viewport_addr; + uintptr_t viewport_addr; u32 port_num; };

ulpi_read and ulpi_write are used to read/write registers via ULPI bus. Code generates compilation warnings on 64-bit machines where pointer is cast to u32.

This patch drops all but last 8 bits of register address. It is possible, because addresses on ULPI bus are 6- or 8-bit.

It is not possible (according to ULPI 1.1 spec) to have more than 8-bit addressing.

This patch should not cause regressions as all calls to ulpi_read/write use either structure pointer (@ address 0) or integer offsets cast to pointer - addresses requested are way below 8-bit range.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Acked-by: Marek Vasut marex@denx.de ---

Changes in v4: - Add Ack from Marek

Changes in v3: - New patch

Changes in v2: None Changes in v1: None

drivers/usb/ulpi/ulpi-viewport.c | 5 +++-- include/usb/ulpi.h | 2 ++ 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/ulpi/ulpi-viewport.c b/drivers/usb/ulpi/ulpi-viewport.c index 72a06de..d111680 100644 --- a/drivers/usb/ulpi/ulpi-viewport.c +++ b/drivers/usb/ulpi/ulpi-viewport.c @@ -92,7 +92,8 @@ static int ulpi_request(struct ulpi_viewport *ulpi_vp, u32 value)

int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value) { - u32 val = ULPI_RWRUN | ULPI_RWCTRL | ((u32)reg << 16) | (value & 0xff); + u32 addr = (uintptr_t)reg & 0xFF; + u32 val = ULPI_RWRUN | ULPI_RWCTRL | addr << 16 | (value & 0xff);

val |= (ulpi_vp->port_num & 0x7) << 24; return ulpi_request(ulpi_vp, val); @@ -101,7 +102,7 @@ int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value) u32 ulpi_read(struct ulpi_viewport *ulpi_vp, u8 *reg) { int err; - u32 val = ULPI_RWRUN | ((u32)reg << 16); + u32 val = ULPI_RWRUN | ((uintptr_t)reg & 0xFF) << 16;

val |= (ulpi_vp->port_num & 0x7) << 24; err = ulpi_request(ulpi_vp, val); diff --git a/include/usb/ulpi.h b/include/usb/ulpi.h index dfea395..747fb0a 100644 --- a/include/usb/ulpi.h +++ b/include/usb/ulpi.h @@ -123,6 +123,7 @@ int ulpi_reset(struct ulpi_viewport *ulpi_vp); /* * Write to the ULPI PHY register via the viewport. * @reg - the ULPI register (one of the fields in struct ulpi_regs). + * Due to ULPI design, only 8 lsb of address are used. * @value - the value - only 8 lower bits are used, others ignored. * * returns 0 on success, ULPI_ERROR on failure. @@ -132,6 +133,7 @@ int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value); /* * Read the ULPI PHY register content via the viewport. * @reg - the ULPI register (one of the fields in struct ulpi_regs). + * Due to ULPI design, only 8 lsb of address are used. * * returns register content on success, ULPI_ERROR on failure. */

Debug printf used '%u' to print size_t variable. This caused warnings on 64-bit machines.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Acked-by: Marek Vasut marex@denx.de Acked-by: Joe Hershberger joe.hershberger@ni.com ---

Changes in v4: - Add Ack from Marek and Joe

Changes in v3: - New patch

Changes in v2: None Changes in v1: None

drivers/usb/eth/asix88179.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c index cf4085d..5e1ea86 100644 --- a/drivers/usb/eth/asix88179.c +++ b/drivers/usb/eth/asix88179.c @@ -497,7 +497,7 @@ static int asix_send(struct eth_device *eth, void *packet, int length) length + sizeof(packet_len) + sizeof(tx_hdr2), &actual_len, USB_BULK_SEND_TIMEOUT); - debug("Tx: len = %u, actual = %u, err = %d\n", + debug("Tx: len = %zu, actual = %u, err = %d\n", length + sizeof(packet_len), actual_len, err);

return err;

Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors.

This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs).

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Acked-by: Marek Vasut marex@denx.de Tested-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Add missing renames (arch/* and board/*)

Changes in v3: None Changes in v2: - Add acked-by

Changes in v1: None

arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 +- board/boundary/nitrogen6x/nitrogen6x.c | 2 +- board/denx/m53evk/m53evk.c | 2 +- board/freescale/mx51evk/mx51evk.c | 2 +- board/freescale/mx6slevk/mx6slevk.c | 2 +- board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 2 +- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +- board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 2 +- board/freescale/mx7dsabresd/mx7dsabresd.c | 2 +- board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 +- drivers/usb/host/ehci-fsl.c | 2 +- drivers/usb/host/ehci-mpc512x.c | 2 +- drivers/usb/host/ehci-mx5.c | 2 +- drivers/usb/host/ehci-mx6.c | 2 +- drivers/usb/host/ehci-mxc.c | 2 +- drivers/usb/host/ehci-vf.c | 2 +- drivers/usb/host/ehci-zynq.c | 2 +- include/usb/{ehci-fsl.h => ehci-ci.h} | 6 +++--- 18 files changed, 20 insertions(+), 20 deletions(-) rename include/usb/{ehci-fsl.h => ehci-ci.h} (99%)

diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 00572de..0791043 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -9,7 +9,7 @@ #include <ioports.h> #include <asm/io.h> #ifdef CONFIG_USB_EHCI_FSL -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> #endif

DECLARE_GLOBAL_DATA_PTR; diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 104d71f..a3a56ca 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -31,7 +31,7 @@ #include <i2c.h> #include <input.h> #include <netdev.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR; #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c index 5dd6cdd..934f009 100644 --- a/board/denx/m53evk/m53evk.c +++ b/board/denx/m53evk/m53evk.c @@ -22,7 +22,7 @@ #include <spl.h> #include <fsl_esdhc.h> #include <asm/gpio.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> #include <linux/fb.h> #include <ipu_pixfmt.h>

diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index c7c21f3..2ea5346 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -20,7 +20,7 @@ #include <power/pmic.h> #include <fsl_pmic.h> #include <mc13892.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index f440ce6..f1915a8 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -28,7 +28,7 @@ #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index a240982..886373c 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -28,7 +28,7 @@ #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> #include <pca953x.h>

DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 41319c6..25e009e 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -27,7 +27,7 @@ #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 98d5675..88d3fbd 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -27,7 +27,7 @@ #include <power/pfuze3000_pmic.h> #include "../common/pfuze.h" #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 4d0b195..c3062f1 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -24,7 +24,7 @@ #include <asm/imx-common/mxc_i2c.h> #include <asm/arch/crm_regs.h> #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 823b70f..bcc9729 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -33,7 +33,7 @@ #include <asm/arch/sys_proto.h> #include <spl.h> #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 97b7f14..4bcea9d 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -12,7 +12,7 @@ #include <pci.h> #include <usb.h> #include <asm/io.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> #include <hwconfig.h> #include <fsl_usb.h> #include <fdt_support.h> diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c index b320c4a..4b50ac8 100644 --- a/drivers/usb/host/ehci-mpc512x.c +++ b/drivers/usb/host/ehci-mpc512x.c @@ -17,7 +17,7 @@ #include <pci.h> #include <usb.h> #include <asm/io.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h>

#include "ehci.h"

diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index d319962..2b36ceb 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -9,7 +9,7 @@ #include <usb.h> #include <errno.h> #include <linux/compiler.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index e1c67f7..a981b50 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -10,7 +10,7 @@ #include <errno.h> #include <wait_bit.h> #include <linux/compiler.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index f09c75a..f8324ee 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -9,7 +9,7 @@ #include <usb.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> #include <errno.h>

#include "ehci.h" diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 335e303..61789dd 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -17,7 +17,7 @@ #include <asm/arch/crm_regs.h> #include <asm/imx-common/iomux-v3.h> #include <asm/imx-common/regs-usbphy.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h>

#include "ehci.h"

diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c index 7770d05..37a7935 100644 --- a/drivers/usb/host/ehci-zynq.c +++ b/drivers/usb/host/ehci-zynq.c @@ -11,7 +11,7 @@ #include <asm/arch/sys_proto.h> #include <asm/io.h> #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> #include <usb/ulpi.h>

#include "ehci.h" diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-ci.h similarity index 99% rename from include/usb/ehci-fsl.h rename to include/usb/ehci-ci.h index e9349b5..725aec5 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-ci.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: GPL-2.0+ */

-#ifndef _EHCI_FSL_H -#define _EHCI_FSL_H +#ifndef _EHCI_CI_H +#define _EHCI_CI_H

#include <asm/processor.h>

@@ -285,4 +285,4 @@ int usb_phy_mode(int port); int board_ehci_hcd_init(int port); int board_usb_phy_mode(int port);

-#endif /* _EHCI_FSL_H */ +#endif /* _EHCI_CI_H */

Some registers of usb_ehci were marked as reserved. This may be true for some variants of Chipidea USB core, but they have meaning on other devices.

The following registers were added: sbusstatus/sbusmode: AHB-related registers genconfig*: Auxiluary IP core configuration registers.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Reviewed-by: Marek Vasut marex@denx.de Tested-by: Simon Glass sjg@chromium.org

---

Changes in v4: None Changes in v3: None Changes in v2: - Add reviewed-by

Changes in v1: None

include/usb/ehci-ci.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 725aec5..305b180 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -191,7 +191,11 @@ struct usb_ehci { u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */ u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */ u32 sbuscfg; /* 0x090 - System Bus Interface Control */ - u8 res2[0x6C]; + u32 sbusstatus; /* 0x094 - System Bus Interface Status */ + u32 sbusmode; /* 0x098 - System Bus Interface Mode */ + u32 genconfig; /* 0x09C - USB Core Configuration */ + u32 genconfig2; /* 0x0A0 - USB Core Configuration 2 */ + u8 res2[0x5c]; u8 caplength; /* 0x100 - Capability Register Length */ u8 res3[0x1]; u16 hciversion; /* 0x102 - Host Interface Version */

Use definitions from ehci.h instead.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Acked-by: Marek Vasut marex@denx.de Tested-by: Simon Glass sjg@chromium.org

---

Changes in v4: None Changes in v3: None Changes in v2: - Add Acked-by

Changes in v1: None

drivers/usb/host/ehci-mpc512x.c | 4 ++-- include/usb/ehci-ci.h | 4 ---- 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c index 4b50ac8..bb4f461 100644 --- a/drivers/usb/host/ehci-mpc512x.c +++ b/drivers/usb/host/ehci-mpc512x.c @@ -93,7 +93,7 @@ static int reset_usb_controller(volatile struct usb_ehci *ehci) unsigned int i;

/* Command a reset of the USB Controller */ - out_be32(&(ehci->usbcmd), EHCI_FSL_USBCMD_RST); + out_be32(&(ehci->usbcmd), CMD_RESET);

/* Wait for the reset process to finish */ for (i = 65535 ; i > 0 ; i--) { @@ -101,7 +101,7 @@ static int reset_usb_controller(volatile struct usb_ehci *ehci) * The host will set this bit to zero once the * reset process is complete */ - if ((in_be32(&(ehci->usbcmd)) & EHCI_FSL_USBCMD_RST) == 0) + if ((in_be32(&(ehci->usbcmd)) & CMD_RESET) == 0) return 0; }

diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 305b180..586d32a 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -97,10 +97,6 @@ #define INTR_DATA_PULSING_EN (0x1<<30) #define INTSTS_MASK (0x00ff0000)

-/* USBCMD Bits of interest */ -#define EHCI_FSL_USBCMD_RST (1 << 1) -#define EHCI_FSL_USBCMD_RS (1 << 0) - #define INTERRUPT_ENABLE_BITS_MASK \ (INTR_USB_ID_EN | \ INTR_1MS_TIMER_EN | \

This driver is able to reconfigure OTG controller into HOST mode. Board can add board-specific initialization as board_prepare_usb(). It requires USB_ULPI_VIEWPORT enabled in board configuration.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Acked-by: Marek Vasut marex@denx.de Tested-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: - Use PORT_... macro to write to portsc - Remove extra whitespace in probe() - Add acked-by

Changes in v1: - Reordered header files - Removed braces around constant - Added more verbose help to KConfig - Added ULPI dependency to Kconfig - Drop register #defines - use ehci-ci.h instead - Create fixed ulpi viewport for device - Use setbits/clearbits where possible - Use wait_for_bit to reset controller - Add dt binding documents

doc/device-tree-bindings/usb/ehci-msm.txt | 10 ++ drivers/usb/host/Kconfig | 11 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-msm.c | 178 ++++++++++++++++++++++++++++++ 4 files changed, 200 insertions(+) create mode 100644 doc/device-tree-bindings/usb/ehci-msm.txt create mode 100644 drivers/usb/host/ehci-msm.c

diff --git a/doc/device-tree-bindings/usb/ehci-msm.txt b/doc/device-tree-bindings/usb/ehci-msm.txt new file mode 100644 index 0000000..205bb07 --- /dev/null +++ b/doc/device-tree-bindings/usb/ehci-msm.txt @@ -0,0 +1,10 @@ +Chipidea EHCI controller (part of OTG controller) used on Qualcomm devices. + +Required properties: +- compatible: must be "qcom,ehci-host" +- reg: start address and size of the registers + +ehci@78d9000 { + compatible = "qcom,ehci-host"; + reg = <0x78d9000 0x400>; +}; diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 9332374..d2363c8 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -74,6 +74,17 @@ config USB_EHCI_MX6 ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs.

+config USB_EHCI_MSM + bool "Support for Qualcomm on-chip EHCI USB controller" + depends on DM_USB + select USB_ULPI_VIEWPORT + default n + ---help--- + Enables support for the on-chip EHCI controller on Qualcomm + Snapdragon SoCs. + This driver supports combination of Chipidea USB controller + and Synapsys USB PHY in host mode only. + config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on OF_CONTROL diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 9a87d2b..507519e 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_USB_EHCI_MX7) += ehci-mx6.o obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o +obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c new file mode 100644 index 0000000..6484c1c --- /dev/null +++ b/drivers/usb/host/ehci-msm.c @@ -0,0 +1,178 @@ +/* + * Qualcomm EHCI driver + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * Based on Linux driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <usb.h> +#include <usb/ehci-ci.h> +#include <usb/ulpi.h> +#include <wait_bit.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <linux/compat.h> +#include "ehci.h" + +/* PHY viewport regs */ +#define ULPI_MISC_A_READ 0x96 +#define ULPI_MISC_A_SET 0x97 +#define ULPI_MISC_A_CLEAR 0x98 +#define ULPI_MISC_A_VBUSVLDEXTSEL (1 << 1) +#define ULPI_MISC_A_VBUSVLDEXT (1 << 0) + +#define GEN2_SESS_VLD_CTRL_EN (1 << 7) + +#define SESS_VLD_CTRL (1 << 25) + +struct msm_ehci_priv { + struct ehci_ctrl ctrl; /* Needed by EHCI */ + struct usb_ehci *ehci; /* Start of IP core*/ + struct ulpi_viewport ulpi_vp; /* ULPI Viewport */ +}; + +int __weak board_prepare_usb(enum usb_init_type type) +{ + return 0; +} + +static void setup_usb_phy(struct msm_ehci_priv *priv) +{ + /* Select and enable external configuration with USB PHY */ + ulpi_write(&priv->ulpi_vp, (u8 *)ULPI_MISC_A_SET, + ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT); +} + +static void reset_usb_phy(struct msm_ehci_priv *priv) +{ + /* Disable VBUS mimicing in the controller. */ + ulpi_write(&priv->ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR, + ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT); +} + + +static int msm_init_after_reset(struct ehci_ctrl *dev) +{ + struct msm_ehci_priv *p = container_of(dev, struct msm_ehci_priv, ctrl); + struct usb_ehci *ehci = p->ehci; + + /* select ULPI phy */ + writel(PORT_PTS_ULPI, &ehci->portsc); + setup_usb_phy(p); + + /* Enable sess_vld */ + setbits_le32(&ehci->genconfig2, GEN2_SESS_VLD_CTRL_EN); + + /* Enable external vbus configuration in the LINK */ + setbits_le32(&ehci->usbcmd, SESS_VLD_CTRL); + + /* USB_OTG_HS_AHB_BURST */ + writel(0x0, &ehci->sbuscfg); + + /* USB_OTG_HS_AHB_MODE: HPROT_MODE */ + /* Bus access related config. */ + writel(0x08, &ehci->sbusmode); + + /* set mode to host controller */ + writel(CM_HOST, &ehci->usbmode); + + return 0; +} + +static const struct ehci_ops msm_ehci_ops = { + .init_after_reset = msm_init_after_reset +}; + +static int ehci_usb_probe(struct udevice *dev) +{ + struct msm_ehci_priv *p = dev_get_priv(dev); + struct usb_ehci *ehci = p->ehci; + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; + int ret; + + hccr = (struct ehci_hccr *)((phys_addr_t)&ehci->caplength); + hcor = (struct ehci_hcor *)((phys_addr_t)hccr + + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); + + ret = board_prepare_usb(USB_INIT_HOST); + if (ret < 0) + return ret; + + return ehci_register(dev, hccr, hcor, &msm_ehci_ops, 0, USB_INIT_HOST); +} + +static int ehci_usb_remove(struct udevice *dev) +{ + struct msm_ehci_priv *p = dev_get_priv(dev); + struct usb_ehci *ehci = p->ehci; + int ret; + + ret = ehci_deregister(dev); + if (ret) + return ret; + + /* Stop controller. */ + clrbits_le32(&ehci->usbcmd, CMD_RUN); + + reset_usb_phy(p); + + ret = board_prepare_usb(USB_INIT_DEVICE); /* Board specific hook */ + if (ret < 0) + return ret; + + /* Reset controller */ + setbits_le32(&ehci->usbcmd, CMD_RESET); + + /* Wait for reset */ + if (wait_for_bit(__func__, &ehci->usbcmd, CMD_RESET, false, 30, + false)) { + printf("Stuck on USB reset.\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int ehci_usb_ofdata_to_platdata(struct udevice *dev) +{ + struct msm_ehci_priv *priv = dev_get_priv(dev); + + priv->ulpi_vp.port_num = 0; + priv->ehci = (void *)dev_get_addr(dev); + + if (priv->ehci == (void *)FDT_ADDR_T_NONE) + return -EINVAL; + + /* Warning: this will not work if viewport address is > 64 bit due to + * ULPI design. + */ + priv->ulpi_vp.viewport_addr = (phys_addr_t)&priv->ehci->ulpi_viewpoint; + + return 0; +} + +static const struct udevice_id ehci_usb_ids[] = { + { .compatible = "qcom,ehci-host", }, + { } +}; + +U_BOOT_DRIVER(usb_ehci) = { + .name = "ehci_msm", + .id = UCLASS_USB, + .of_match = ehci_usb_ids, + .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, + .probe = ehci_usb_probe, + .remove = ehci_usb_remove, + .ops = &ehci_usb_ops, + .priv_auto_alloc_size = sizeof(struct msm_ehci_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +};

Qualcom processors use proprietary bus to talk with PMIC devices - SPMI (System Power Management Interface). On wiring level it is similar to I2C, but on protocol level, it's multi-master and has simple autodetection capabilities. This commit adds simple uclass that provides bus read/write interface.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: - Use proper entry order in Kconfig - Rename CONFIG_DM_SPMI -> CONFIG_SPMI - Fix header ordering - Add reviewed-by

Changes in v1: - Reorder includes - Add read/write arguments documentation

drivers/Kconfig | 2 ++ drivers/Makefile | 1 + drivers/spmi/Kconfig | 10 ++++++++++ drivers/spmi/Makefile | 7 +++++++ drivers/spmi/spmi-uclass.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + include/spmi/spmi.h | 47 +++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 116 insertions(+) create mode 100644 drivers/spmi/Kconfig create mode 100644 drivers/spmi/Makefile create mode 100644 drivers/spmi/spmi-uclass.c create mode 100644 include/spmi/spmi.h

diff --git a/drivers/Kconfig b/drivers/Kconfig index 70993fd..c82a94b 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -60,6 +60,8 @@ source "drivers/sound/Kconfig"

source "drivers/spi/Kconfig"

+source "drivers/spmi/Kconfig" + source "drivers/thermal/Kconfig"

source "drivers/timer/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index e7eab66..6900097 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -54,6 +54,7 @@ obj-y += dfu/ obj-$(CONFIG_X86) += pch/ obj-y += rtc/ obj-y += sound/ +obj-y += spmi/ obj-y += timer/ obj-y += tpm/ obj-y += twserial/ diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig new file mode 100644 index 0000000..0b9bd31 --- /dev/null +++ b/drivers/spmi/Kconfig @@ -0,0 +1,10 @@ +menu "SPMI support" + +config SPMI + bool "Enable SPMI bus support" + depends on DM + ---help--- + Select this to enable to support SPMI bus. + SPMI (System Power Management Interface) bus is used + to connect PMIC devices on various SoCs. +endmenu diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile new file mode 100644 index 0000000..99092eb --- /dev/null +++ b/drivers/spmi/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_SPMI) += spmi-uclass.o diff --git a/drivers/spmi/spmi-uclass.c b/drivers/spmi/spmi-uclass.c new file mode 100644 index 0000000..4ddd51b --- /dev/null +++ b/drivers/spmi/spmi-uclass.c @@ -0,0 +1,48 @@ +/* + * SPMI bus uclass driver + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <dm/root.h> +#include <spmi/spmi.h> +#include <linux/ctype.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spmi_reg_read(struct udevice *dev, int usid, int pid, int reg) +{ + const struct dm_spmi_ops *ops = dev_get_driver_ops(dev); + + if (!ops || !ops->read) + return -ENOSYS; + + return ops->read(dev, usid, pid, reg); +} + +int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg, + uint8_t value) +{ + const struct dm_spmi_ops *ops = dev_get_driver_ops(dev); + + if (!ops || !ops->write) + return -ENOSYS; + + return ops->write(dev, usid, pid, reg, value); +} + +static int spmi_post_bind(struct udevice *dev) +{ + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +} + +UCLASS_DRIVER(spmi) = { + .id = UCLASS_SPMI, + .name = "spmi", + .post_bind = spmi_post_bind, +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 37c4176..cbf9b2c 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -66,6 +66,7 @@ enum uclass_id { UCLASS_RTC, /* Real time clock device */ UCLASS_SERIAL, /* Serial UART */ UCLASS_SPI, /* SPI bus */ + UCLASS_SPMI, /* System Power Management Interface bus */ UCLASS_SPI_FLASH, /* SPI flash */ UCLASS_SPI_GENERIC, /* Generic SPI flash target */ UCLASS_SYSCON, /* System configuration device */ diff --git a/include/spmi/spmi.h b/include/spmi/spmi.h new file mode 100644 index 0000000..65a49bd --- /dev/null +++ b/include/spmi/spmi.h @@ -0,0 +1,47 @@ +#ifndef _SPMI_SPMI_H +#define _SPMI_SPMI_H + +/** + * struct dm_spmi_ops - SPMI device I/O interface + * + * Should be implemented by UCLASS_SPMI device drivers. The standard + * device operations provides the I/O interface for it's childs. + * + * @read: read register 'reg' of slave 'usid' and peripheral 'pid' + * @write: write register 'reg' of slave 'usid' and peripheral 'pid' + * + * Each register is 8-bit, both read and write can return negative values + * on error. + */ +struct dm_spmi_ops { + int (*read)(struct udevice *dev, int usid, int pid, int reg); + int (*write)(struct udevice *dev, int usid, int pid, int reg, + uint8_t value); +}; + +/** + * spmi_reg_read() - read a register from specific slave/peripheral + * + * @dev: SPMI bus to read + * @usid SlaveID + * @pid Peripheral ID + * @reg: Register to read + * @return value read on success or negative value of errno. + */ +int spmi_reg_read(struct udevice *dev, int usid, int pid, int reg); + +/** + * spmi_reg_write() - write a register of specific slave/peripheral + * + * @dev: SPMI bus to write + * @usid SlaveID + * @pid Peripheral ID + * @reg: Register to write + * @value: Value to write + * @return 0 on success or negative value of errno. + */ +int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg, + uint8_t value); + +#endif +

This patch adds emulated spmi bus controller with part of pm8916 pmic on it to sandbox and tests validating SPMI uclass.

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: - Updated test.dts to include SPMI like sandbox.dts does

Changes in v2: - Rename CONFIG_DM_SPMI -> CONFIG_SPMI - Rename r -> regs, p -> priv - Add reviewed-by - Update binding doc (drop unused bindig)

Changes in v1: None

arch/sandbox/dts/sandbox.dts | 20 ++++ arch/sandbox/dts/test.dts | 20 ++++ configs/sandbox_defconfig | 4 + doc/device-tree-bindings/spmi/spmi-sandbox.txt | 31 +++++ drivers/spmi/Kconfig | 8 ++ drivers/spmi/Makefile | 1 + drivers/spmi/spmi-sandbox.c | 157 +++++++++++++++++++++++++ test/dm/Makefile | 1 + test/dm/spmi.c | 115 ++++++++++++++++++ 9 files changed, 357 insertions(+) create mode 100644 doc/device-tree-bindings/spmi/spmi-sandbox.txt create mode 100644 drivers/spmi/spmi-sandbox.c create mode 100644 test/dm/spmi.c

diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index e3f02bf..2ae4014 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -240,6 +240,26 @@ status = "disabled"; };

+ spmi: spmi@0 { + compatible = "sandbox,spmi"; + #address-cells = <0x1>; + #size-cells = <0x1>; + pm8916@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x1>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + spmi_gpios: gpios@c000 { + compatible = "qcom,pm8916-gpio"; + reg = <0xc000 0x400>; + gpio-controller; + gpio-count = <4>; + #gpio-cells = <2>; + gpio-bank-name="spmi"; + }; + }; + }; };

#include "cros-ec-keyboard.dtsi" diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 9b8d658..8930009 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -351,6 +351,26 @@ status = "disabled"; };

+ spmi: spmi@0 { + compatible = "sandbox,spmi"; + #address-cells = <0x1>; + #size-cells = <0x1>; + pm8916@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x1>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + spmi_gpios: gpios@c000 { + compatible = "qcom,pm8916-gpio"; + reg = <0xc000 0x400>; + gpio-controller; + gpio-count = <4>; + #gpio-cells = <2>; + gpio-bank-name="spmi"; + }; + }; + }; };

#include "sandbox_pmic.dtsi" diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index d69c9fc..bfc8b61 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -31,6 +31,7 @@ CONFIG_ADC_SANDBOX=y CONFIG_BLK=y CONFIG_CLK=y CONFIG_SANDBOX_GPIO=y +CONFIG_PM8916_GPIO=y CONFIG_SYS_I2C_SANDBOX=y CONFIG_CROS_EC_KEYB=y CONFIG_LED=y @@ -59,6 +60,9 @@ CONFIG_PINCONF=y CONFIG_PINCTRL_SANDBOX=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_SANDBOX=y +CONFIG_PMIC_PM8916=y +CONFIG_SPMI=y +CONFIG_SPMI_SANDBOX=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_SANDBOX=y CONFIG_RAM=y diff --git a/doc/device-tree-bindings/spmi/spmi-sandbox.txt b/doc/device-tree-bindings/spmi/spmi-sandbox.txt new file mode 100644 index 0000000..8569a1a --- /dev/null +++ b/doc/device-tree-bindings/spmi/spmi-sandbox.txt @@ -0,0 +1,31 @@ +Sandbox SPMI emulated arbiter. + +This is bus driver for Sandbox. It includes part of emulated pm8916 pmic. + +Required properties: +- compatible: "sandbox,spmi" +- #address-cells: 0x1 - childs slave ID address +- #size-cells: 0x1 + +Example: + +spmi: spmi@0 { + compatible = "sandbox,spmi"; + #address-cells = <0x1>; + #size-cells = <0x1>; + pm8916@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x1>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + spmi_gpios: gpios@c000 { + compatible = "qcom,pm8916-gpio"; + reg = <0xc000 0x400>; + gpio-controller; + gpio-count = <4>; + #gpio-cells = <2>; + gpio-bank-name="spmi"; + }; + }; +}; diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig index 0b9bd31..c70d675 100644 --- a/drivers/spmi/Kconfig +++ b/drivers/spmi/Kconfig @@ -7,4 +7,12 @@ config SPMI Select this to enable to support SPMI bus. SPMI (System Power Management Interface) bus is used to connect PMIC devices on various SoCs. + +config SPMI_SANDBOX + boolean "Support for Sandbox SPMI bus" + depends on SPMI + ---help--- + Demo SPMI bus implementation. Emulates part of PM8916 as single + slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3. + endmenu diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile index 99092eb..4ca65a9 100644 --- a/drivers/spmi/Makefile +++ b/drivers/spmi/Makefile @@ -5,3 +5,4 @@ #

obj-$(CONFIG_SPMI) += spmi-uclass.o +obj-$(CONFIG_SPMI_SANDBOX) += spmi-sandbox.o diff --git a/drivers/spmi/spmi-sandbox.c b/drivers/spmi/spmi-sandbox.c new file mode 100644 index 0000000..2f0fea0 --- /dev/null +++ b/drivers/spmi/spmi-sandbox.c @@ -0,0 +1,157 @@ +/* + * Sample SPMI bus driver + * + * It emulates bus with single pm8916-like pmic that has only GPIO reigsters. + * + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <spmi/spmi.h> +#include <asm/gpio.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define EMUL_GPIO_PID_START 0xC0 +#define EMUL_GPIO_PID_END 0xC3 + +#define EMUL_GPIO_COUNT 4 + +#define EMUL_GPIO_REG_END 0x46 /* Last valid register */ + +#define EMUL_PERM_R 0x1 +#define EMUL_PERM_W 0x2 +#define EMUL_PERM_RW (EMUL_PERM_R | EMUL_PERM_W) + +struct sandbox_emul_fake_regs { + u8 value; + u8 access_mask; + u8 perms; /* Access permissions */ +}; + +struct sandbox_emul_gpio { + struct sandbox_emul_fake_regs r[EMUL_GPIO_REG_END]; /* Fake registers */ +}; + +struct sandbox_spmi_priv { + struct sandbox_emul_gpio gpios[EMUL_GPIO_COUNT]; +}; + +/* Check if valid register was requested */ +static bool check_address_valid(int usid, int pid, int off) +{ + if (usid != 0) + return false; + if (pid < EMUL_GPIO_PID_START || pid > EMUL_GPIO_PID_END) + return false; + if (off > EMUL_GPIO_REG_END) + return false; + return true; +} + +static int sandbox_spmi_write(struct udevice *dev, int usid, int pid, int off, + uint8_t val) +{ + struct sandbox_spmi_priv *priv = dev_get_priv(dev); + struct sandbox_emul_fake_regs *regs; + + if (!check_address_valid(usid, pid, off)) + return -EIO; + + regs = priv->gpios[pid & 0x3].r; /* Last 3 bits of pid are gpio # */ + + switch (off) { + case 0x40: /* Control */ + val &= regs[off].access_mask; + if (((val & 0x30) == 0x10) || ((val & 0x30) == 0x20)) { + /* out/inout - set status register */ + regs[0x8].value &= ~0x1; + regs[0x8].value |= val & 0x1; + } + break; + default: + if (regs[off].perms & EMUL_PERM_W) + regs[off].value = val & regs[off].access_mask; + } + return 0; +} + +static int sandbox_spmi_read(struct udevice *dev, int usid, int pid, int off) +{ + struct sandbox_spmi_priv *priv = dev_get_priv(dev); + struct sandbox_emul_fake_regs *regs; + + if (!check_address_valid(usid, pid, off)) + return -EIO; + + regs = priv->gpios[pid & 0x3].r; /* Last 3 bits of pid are gpio # */ + + if (regs[0x46].value == 0) /* Block disabled */ + return 0; + + switch (off) { + case 0x8: /* Status */ + if (regs[0x46].value == 0) /* Block disabled */ + return 0; + return regs[off].value; + default: + if (regs[off].perms & EMUL_PERM_R) + return regs[off].value; + else + return 0; + } +} + +static struct dm_spmi_ops sandbox_spmi_ops = { + .read = sandbox_spmi_read, + .write = sandbox_spmi_write, +}; + +static int sandbox_spmi_probe(struct udevice *dev) +{ + struct sandbox_spmi_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < EMUL_GPIO_COUNT; ++i) { + struct sandbox_emul_fake_regs *regs = priv->gpios[i].r; + regs[4].perms = EMUL_PERM_R; + regs[4].value = 0x10; + regs[5].perms = EMUL_PERM_R; + regs[5].value = 0x5; + regs[8].access_mask = 0x81; + regs[8].perms = EMUL_PERM_RW; + regs[0x40].access_mask = 0x7F; + regs[0x40].perms = EMUL_PERM_RW; + regs[0x41].access_mask = 7; + regs[0x41].perms = EMUL_PERM_RW; + regs[0x42].access_mask = 7; + regs[0x42].perms = EMUL_PERM_RW; + regs[0x42].value = 0x4; + regs[0x45].access_mask = 0x3F; + regs[0x45].perms = EMUL_PERM_RW; + regs[0x45].value = 0x1; + regs[0x46].access_mask = 0x80; + regs[0x46].perms = EMUL_PERM_RW; + regs[0x46].value = 0x80; + } + return 0; +} + +static const struct udevice_id sandbox_spmi_ids[] = { + { .compatible = "sandbox,spmi" }, + { } +}; + +U_BOOT_DRIVER(msm_spmi) = { + .name = "sandbox_spmi", + .id = UCLASS_SPMI, + .of_match = sandbox_spmi_ids, + .ops = &sandbox_spmi_ops, + .probe = sandbox_spmi_probe, + .priv_auto_alloc_size = sizeof(struct sandbox_spmi_priv), +}; diff --git a/test/dm/Makefile b/test/dm/Makefile index df2d71f..9a11ae0 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -37,4 +37,5 @@ obj-$(CONFIG_DM_REGULATOR) += regulator.o obj-$(CONFIG_TIMER) += timer.o obj-$(CONFIG_DM_VIDEO) += video.o obj-$(CONFIG_ADC) += adc.o +obj-$(CONFIG_SPMI) += spmi.o endif diff --git a/test/dm/spmi.c b/test/dm/spmi.c new file mode 100644 index 0000000..81767f6 --- /dev/null +++ b/test/dm/spmi.c @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <dm.h> +#include <dm/device.h> +#include <dm/root.h> +#include <dm/test.h> +#include <dm/util.h> +#include <power/pmic.h> +#include <spmi/spmi.h> +#include <asm/gpio.h> +#include <test/ut.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Test if bus childs got probed propperly*/ +static int dm_test_spmi_probe(struct unit_test_state *uts) +{ + const char *name = "spmi@0"; + struct udevice *bus, *dev; + + ut_assertok(uclass_get_device(UCLASS_SPMI, 0, &bus)); + + /* Check bus name */ + ut_asserteq_str(name, bus->name); + + /* Check that it has some devices */ + ut_asserteq(device_has_children(bus), true); + + ut_assertok(device_find_first_child(bus, &dev)); + + /* There should be at least one child */ + ut_assertnonnull(dev); + + /* Check that only PMICs are connected to the bus */ + while (dev) { + ut_asserteq(device_get_uclass_id(dev), UCLASS_PMIC); + device_find_next_child(&dev); + } + + return 0; +} +DM_TEST(dm_test_spmi_probe, DM_TESTF_SCAN_FDT); + +/* Test if it's possible to read bus directly and indirectly */ +static int dm_test_spmi_access(struct unit_test_state *uts) +{ + const char *pmic_name = "pm8916@0"; + struct udevice *bus, *pmic; + + ut_assertok(uclass_get_device(UCLASS_SPMI, 0, &bus)); + + ut_assertok(device_get_child(bus, 0, &pmic)); + + /* Sanity check if it's proper PMIC */ + ut_asserteq_str(pmic_name, pmic->name); + + /* Read PMIC ID reg using SPMI bus - it assumes it has slaveID == 0*/ + ut_asserteq(spmi_reg_read(bus, 0, 0xC0, 0x4), 0x10); + ut_asserteq(spmi_reg_read(bus, 0, 0xC0, 0x5), 0x5); + + /* Read ID reg via pmic interface */ + ut_asserteq(pmic_reg_read(pmic, 0xC004), 0x10); + ut_asserteq(pmic_reg_read(pmic, 0xC005), 0x5); + + return 0; +} +DM_TEST(dm_test_spmi_access, DM_TESTF_SCAN_FDT); + + +/* Test if it's possible to access GPIO that should be in pmic */ +static int dm_test_spmi_access_peripheral(struct unit_test_state *uts) +{ + struct udevice *dev; + unsigned int offset, gpio; + const char *name; + int offset_count; + + /* Get second pin of PMIC GPIO */ + ut_assertok(gpio_lookup_name("spmi1", &dev, &offset, &gpio)); + + /* Check if PMIC is parent */ + ut_asserteq(device_get_uclass_id(dev->parent), UCLASS_PMIC); + + /* This should be second gpio */ + ut_asserteq(1, offset); + + name = gpio_get_bank_info(dev, &offset_count); + + /* Check bank name */ + ut_asserteq_str("spmi", name); + /* Check pin count */ + ut_asserteq(4, offset_count); + + ut_assertok(gpio_request(gpio, "testing")); + + /* Try to set/clear gpio */ + ut_assertok(gpio_direction_output(gpio, 0)); + ut_asserteq(gpio_get_value(gpio), 0); + ut_assertok(gpio_direction_output(gpio, 1)); + ut_asserteq(gpio_get_value(gpio), 1); + ut_assertok(gpio_direction_input(gpio)); + ut_asserteq(gpio_get_value(gpio), 1); + + ut_assertok(gpio_free(gpio)); + + return 0; +} +DM_TEST(dm_test_spmi_access_peripheral, DM_TESTF_SCAN_FDT); +

- Update MAINTAINERS - Update git-mailrc

Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com Reviewed-by: Simon Glass sjg@chromium.org

---

Changes in v4: None Changes in v3: None Changes in v2: - New patch

Changes in v1: None

MAINTAINERS | 11 +++++++++++ doc/git-mailrc | 3 +++ 2 files changed, 14 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS index 32f97b2..6061139 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -125,6 +125,11 @@ F: arch/arm/mach-s5pc1xx/ F: arch/arm/cpu/armv7/s5p-common/ F: arch/arm/include/asm/arch-s3c24x0/

+ARM SNAPDRAGON +M: Mateusz Kulikowski mateusz.kulikowski@gmail.com +S: Maintained +F: arch/arm/mach-snapdragon/ + ARM STM SPEAR #M: Vipin Kumar vipin.kumar@st.com S: Orphaned (Since 2016-02) @@ -396,6 +401,12 @@ F: drivers/mtd/spi/ F: drivers/spi/ F: include/spi*

+SPMI +M: Mateusz Kulikowski mateusz.kulikowski@gmail.com +S: Maintained +F: drivers/spmi/ +F: include/spmi/ + TQ GROUP #M: Martin Krause martin.krause@tq-systems.de S: Orphaned (Since 2016-02) diff --git a/doc/git-mailrc b/doc/git-mailrc index ced7085..1201d4a 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -33,6 +33,7 @@ alias lukma Lukasz Majewski l.majewski@samsung.com alias macpaul Macpaul Lin macpaul@andestech.com alias marex Marek Vasut marex@denx.de alias masahiro Masahiro Yamada yamada.masahiro@socionext.com +alias mateusz Mateusz Kulikowski mateusz.kulikowski@gmail.com alias monstr Michal Simek monstr@monstr.eu alias panto Pantelis Antoniou panto@antoniou-consulting.com alias prafulla Prafulla Wadaskar prafulla@marvell.com @@ -67,6 +68,7 @@ alias rmobile uboot, iwamatsu alias s3c samsung alias s5pc samsung alias samsung uboot, prom +alias snapdragon uboot, mateusz alias socfpga uboot, marex, Dinh Nguyen dinguyen@opensource.altera.com alias sunxi uboot, ijc, jwrdegoede alias tegra uboot, sjg, Tom Warren twarren@nvidia.com, Stephen Warren swarren@nvidia.com @@ -127,6 +129,7 @@ alias nand uboot, scottwood alias net uboot, jhersh alias phy uboot, jhersh alias spi uboot, jagan +alias spmi uboot, mateusz alias ubi uboot, hs alias usb uboot, marex alias video uboot, ag