From: Vaibhav Hiremath hvaibhav@ti.com

Consolidated SDRC related functions into one file - sdrc.c

And also replaced sdrc_init with generic memory init function (mem_init), this generalization of omap memory setup is necessary to support the new emif4 interface introduced in AM3517.

Signed-off-by: Vaibhav Hiremath hvaibhav@ti.com Signed-off-by: Sanjeev Premi premi@ti.com --- arch/arm/cpu/arm_cortexa8/omap3/Makefile | 3 + arch/arm/cpu/arm_cortexa8/omap3/board.c | 35 +----- arch/arm/cpu/arm_cortexa8/omap3/mem.c | 90 ------------ arch/arm/cpu/arm_cortexa8/omap3/sdrc.c | 202 +++++++++++++++++++++++++++ arch/arm/cpu/arm_cortexa8/omap3/sys_info.c | 41 ------ arch/arm/include/asm/arch-omap3/cpu.h | 3 + arch/arm/include/asm/arch-omap3/mem.h | 13 ++ arch/arm/include/asm/arch-omap3/sys_proto.h | 4 +- include/configs/devkit8000.h | 2 + include/configs/omap3_beagle.h | 2 + include/configs/omap3_evm.h | 2 + include/configs/omap3_overo.h | 2 + include/configs/omap3_pandora.h | 2 + include/configs/omap3_sdp3430.h | 2 + include/configs/omap3_zoom1.h | 2 + include/configs/omap3_zoom2.h | 2 + 16 files changed, 240 insertions(+), 167 deletions(-) create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c

diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/arm_cortexa8/omap3/Makefile index 136b163..8cc7802 100644 --- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile +++ b/arch/arm/cpu/arm_cortexa8/omap3/Makefile @@ -33,6 +33,9 @@ COBJS += board.o COBJS += clock.o COBJS += gpio.o COBJS += mem.o +ifdef CONFIG_SDRC +COBJS += sdrc.o +endif COBJS += syslib.o COBJS += sys_info.o COBJS += timer.o diff --git a/arch/arm/cpu/arm_cortexa8/omap3/board.c b/arch/arm/cpu/arm_cortexa8/omap3/board.c index 69a08fd..d2500ca 100644 --- a/arch/arm/cpu/arm_cortexa8/omap3/board.c +++ b/arch/arm/cpu/arm_cortexa8/omap3/board.c @@ -40,8 +40,6 @@

extern omap3_sysinfo sysinfo;

-extern u32 is_mem_sdr(void); - /****************************************************************************** * Routine: delay * Description: spinning delay to use before udelay works @@ -233,7 +231,7 @@ void s_init(void) per_clocks_enable();

if (!in_sdram) - sdrc_init(); + mem_init(); }

/****************************************************************************** @@ -274,37 +272,6 @@ void watchdog_init(void) }

/****************************************************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - *****************************************************************************/ -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int size0 = 0, size1 = 0; - - size0 = get_sdr_cs_size(CS0); - - /* - * If a second bank of DDR is attached to CS1 this is - * where it can be started. Early init code will init - * memory on CS0. - */ - if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) { - do_sdrc_init(CS1, NOT_EARLY); - make_cs1_contiguous(); - - size1 = get_sdr_cs_size(CS1); - } - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; - - return 0; -} - -/****************************************************************************** * Dummy function to handle errors for EABI incompatibility *****************************************************************************/ void abort(void) diff --git a/arch/arm/cpu/arm_cortexa8/omap3/mem.c b/arch/arm/cpu/arm_cortexa8/omap3/mem.c index dfb7e4c..bd914b0 100644 --- a/arch/arm/cpu/arm_cortexa8/omap3/mem.c +++ b/arch/arm/cpu/arm_cortexa8/omap3/mem.c @@ -79,26 +79,6 @@ static const u32 gpmc_onenand[GPMC_MAX_REG] = {

#endif

-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; - -/************************************************************************** - * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow - * command line mem=xyz use all memory with out discontinuous support - * compiled in. Could do it at the ATAG, but there really is two banks... - * Called as part of 2nd phase DDR init. - **************************************************************************/ -void make_cs1_contiguous(void) -{ - u32 size, a_add_low, a_add_high; - - size = get_sdr_cs_size(CS0); - size >>= 25; /* divide by 32 MiB to find size to offset CS1 */ - a_add_high = (size & 3) << 8; /* set up low field */ - a_add_low = (size & 0x3C) >> 2; /* set up high field */ - writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); - -} - /******************************************************** * mem_ok() - test used to see if timings are correct * for a part. Helps in guessing which part @@ -123,76 +103,6 @@ u32 mem_ok(u32 cs) return 1; }

-/******************************************************** - * sdrc_init() - init the sdrc chip selects CS0 and CS1 - * - early init routines, called from flash or - * SRAM. - *******************************************************/ -void sdrc_init(void) -{ - /* only init up first bank here */ - do_sdrc_init(CS0, EARLY_INIT); -} - -/************************************************************************* - * do_sdrc_init(): initialize the SDRAM for use. - * -code sets up SDRAM basic SDRC timings for CS0 - * -optimal settings can be placed here, or redone after i2c - * inspection of board info - * - * - code called once in C-Stack only context for CS0 and a possible 2nd - * time depending on memory configuration from stack+global context - **************************************************************************/ - -void do_sdrc_init(u32 cs, u32 early) -{ - struct sdrc_actim *sdrc_actim_base; - - if(cs) - sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; - else - sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; - - if (early) { - /* reset sdrc controller */ - writel(SOFTRESET, &sdrc_base->sysconfig); - wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status, - 12000000); - writel(0, &sdrc_base->sysconfig); - - /* setup sdrc to ball mux */ - writel(SDRC_SHARING, &sdrc_base->sharing); - - /* Disable Power Down of CKE cuz of 1 CKE on combo part */ - writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH, - &sdrc_base->power); - - writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); - sdelay(0x20000); - } - - writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY | - RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 | - DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg); - writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl); - writel(V_ACTIMA_165, &sdrc_actim_base->ctrla); - writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb); - - writel(CMD_NOP, &sdrc_base ->cs[cs].manual); - writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - - /* - * CAS latency 3, Write Burst = Read Burst, Serial Mode, - * Burst length = 4 - */ - writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr); - - if (!mem_ok(cs)) - writel(0, &sdrc_base->cs[cs].mcfg); -} - void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size) { diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c b/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c new file mode 100644 index 0000000..96fd990 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c @@ -0,0 +1,202 @@ +/* + * Functions related to OMAP3 SDRC. + * + * This file has been created after exctracting and consolidating + * the SDRC related content from mem.c and board.c, also created + * generic init function (mem_init). + * + * Copyright (C) 2004-2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * Author : + * Vaibhav Hiremath hvaibhav@ti.com + * + * Original implementation by (mem.c, board.c) : + * Sunil Kumar sunilsaini05@gmail.com + * Shashi Ranjan shashiranjanmca05@gmail.com + * Manikandan Pillai mani.pillai@ti.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> + +extern omap3_sysinfo sysinfo; + +static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; + +/* + * is_mem_sdr - + * - Return 1 if mem type in use is SDR + */ +u32 is_mem_sdr(void) +{ + if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) + return 1; + return 0; +} + +/* + * make_cs1_contiguous - + * - For es2 and above remap cs1 behind cs0 to allow command line + * mem=xyz use all memory with out discontinuous support compiled in. + * Could do it at the ATAG, but there really is two banks... + * - Called as part of 2nd phase DDR init. + */ +void make_cs1_contiguous(void) +{ + u32 size, a_add_low, a_add_high; + + size = get_sdr_cs_size(CS0); + size >>= 25; /* divide by 32 MiB to find size to offset CS1 */ + a_add_high = (size & 3) << 8; /* set up low field */ + a_add_low = (size & 0x3C) >> 2; /* set up high field */ + writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); + +} + + +/* + * get_sdr_cs_size - + * - Get size of chip select 0/1 + */ +u32 get_sdr_cs_size(u32 cs) +{ + u32 size; + + /* get ram size field */ + size = readl(&sdrc_base->cs[cs].mcfg) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size <<= 21; /* multiply by 2 MiB to find size in MB */ + return size; +} + +/* + * get_sdr_cs_offset - + * - Get offset of cs from cs0 start + */ +u32 get_sdr_cs_offset(u32 cs) +{ + u32 offset; + + if (!cs) + return 0; + + offset = readl(&sdrc_base->cs_cfg); + offset = (offset & 15) << 27 | (offset & 0x30) >> 17; + + return offset; +} + +/* + * do_sdrc_init - + * - Initialize the SDRAM for use. + * - Sets up SDRC timings for CS0 + * - code called once in C-Stack only context for CS0 and a possible 2nd + * time depending on memory configuration from stack+global context + */ +void do_sdrc_init(u32 cs, u32 early) +{ + struct sdrc_actim *sdrc_actim_base; + + if (cs) + sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; + else + sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; + + if (early) { + /* reset sdrc controller */ + writel(SOFTRESET, &sdrc_base->sysconfig); + wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status, + 12000000); + writel(0, &sdrc_base->sysconfig); + + /* setup sdrc to ball mux */ + writel(SDRC_SHARING, &sdrc_base->sharing); + + /* Disable Power Down of CKE cuz of 1 CKE on combo part */ + writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH, + &sdrc_base->power); + + writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); + sdelay(0x20000); + } + + writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY | + RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 | + DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg); + writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl); + writel(V_ACTIMA_165, &sdrc_actim_base->ctrla); + writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb); + + writel(CMD_NOP, &sdrc_base->cs[cs].manual); + writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + + /* + * CAS latency 3, Write Burst = Read Burst, Serial Mode, + * Burst length = 4 + */ + writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr); + + if (!mem_ok(cs)) + writel(0, &sdrc_base->cs[cs].mcfg); +} + +/* + * dram_init - + * - Sets uboots idea of sdram size + */ +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + /* + * If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) { + do_sdrc_init(CS1, NOT_EARLY); + make_cs1_contiguous(); + + size1 = get_sdr_cs_size(CS1); + } + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->bd->bi_dram[1].size = size1; + + return 0; +} + +/* + * mem_init - + * - Init the sdrc chip, + * - Selects CS0 and CS1, + */ +void mem_init(void) +{ + /* only init up first bank here */ + do_sdrc_init(CS0, EARLY_INIT); +} diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c b/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c index 08fb32e..1df4401 100644 --- a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c +++ b/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c @@ -32,7 +32,6 @@ #include <i2c.h>

extern omap3_sysinfo sysinfo; -static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; static char *rev_s[CPU_3XX_MAX_REV] = { "1.0", @@ -104,46 +103,6 @@ u32 get_cpu_rev(void) } }

-/**************************************************** - * is_mem_sdr() - return 1 if mem type in use is SDR - ****************************************************/ -u32 is_mem_sdr(void) -{ - if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) - return 1; - return 0; -} - -/*********************************************************************** - * get_cs0_size() - get size of chip select 0/1 - ************************************************************************/ -u32 get_sdr_cs_size(u32 cs) -{ - u32 size; - - /* get ram size field */ - size = readl(&sdrc_base->cs[cs].mcfg) >> 8; - size &= 0x3FF; /* remove unwanted bits */ - size <<= 21; /* multiply by 2 MiB to find size in MB */ - return size; -} - -/*********************************************************************** - * get_sdr_cs_offset() - get offset of cs from cs0 start - ************************************************************************/ -u32 get_sdr_cs_offset(u32 cs) -{ - u32 offset; - - if (!cs) - return 0; - - offset = readl(&sdrc_base->cs_cfg); - offset = (offset & 15) << 27 | (offset & 0x30) >> 17; - - return offset; -} - /*************************************************************************** * get_gpmc0_base() - Return current address hardware will be * fetching from. The below effectively gives what is correct, its a bit diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index aa8de32..a49af10 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -183,6 +183,7 @@ struct sms { /* SDRC */ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ +#if defined(CONFIG_SDRC) struct sdrc_cs { u32 mcfg; /* 0x80 || 0xB0 */ u32 mr; /* 0x84 || 0xB4 */ @@ -215,6 +216,8 @@ struct sdrc { u8 res4[0xC]; struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ }; + +#endif /* CONFIG_SDRC */ #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */

diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 9439758..a78cf9f 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -270,4 +270,17 @@ enum { #define PISMO1_ONEN_BASE ONENAND_MAP #define DBG_MPDB_BASE DEBUG_BASE

+#ifndef __ASSEMBLY__ + +/* Function prototypes */ +void mem_init(void); + +u32 is_mem_sdr(void); +u32 mem_ok(u32 cs); + +u32 get_sdr_cs_size(u32); +u32 get_sdr_cs_offset(u32); + +#endif /* __ASSEMBLY__ */ + #endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 34bd515..34e4e0d 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -31,8 +31,10 @@ void prcm_init(void); void per_clocks_enable(void);

void memif_init(void); +#if defined(CONFIG_SDRC) void sdrc_init(void); void do_sdrc_init(u32, u32); +#endif void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size); @@ -46,8 +48,6 @@ u32 get_sysboot_value(void); u32 is_gpmc_muxed(void); u32 get_gpmc0_type(void); u32 get_gpmc0_width(void); -u32 get_sdr_cs_size(u32); -u32 get_sdr_cs_offset(u32); u32 is_running_in_sdram(void); u32 is_running_in_sram(void); u32 is_running_in_flash(void); diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 7d1332f..1798bc6 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -38,6 +38,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */

+#define CONFIG_SDRC 1 /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 08d79ac..7584063 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -37,6 +37,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */

+#define CONFIG_SDRC 1 /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 1d31731..8c17388 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -42,6 +42,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_EVM 1 /* working with EVM */

+#define CONFIG_SDRC 1 /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index a43500b..5ca9f3a 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -29,6 +29,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_OVERO 1 /* working with overo */

+#define CONFIG_SDRC 1 /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 945c053..7c62685 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -32,6 +32,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */

+#define CONFIG_SDRC 1 /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index b4919db..f751592 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -42,6 +42,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */

+#define CONFIG_SDRC 1 /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index ae7ebf9..30515b0 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -38,6 +38,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */

+#define CONFIG_SDRC 1 /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index c88c732..2861608 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -39,6 +39,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */

+#define CONFIG_SDRC 1 /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h>

-- 1.6.2.4