[PATCH 0/6] sunxi: improve F1C200s support
The Allwinner F1C200s is reportedly the same chip as the F1C100s, just with twice the amount of co-packaged DRAM: 64MB instead of just 32MB. U-Boot's F1C100 platform supported this quite naturally (since the DRAM size is auto-detected), but those better chips do not need to suffer from the same memory constraints as their smaller siblings.
Patch 1/6 adds a notion of "minimum DRAM size" to Kconfig, so that we can select those smaller sizes independently from the actual SoC. This makes it easy to let the F1C200s use a more generous memory map, but also paves the way for the T113-S3 and D1s, later. Patch 2/6 uses the opportunity to improve the 32MB memory map, which was not really practical, and arguably also somewhat buggy. Patch 3/6 helps to keep the _defconfig files small, while patch 4+5 add support for the console on UART1. The final patch then adds a defconfig and .dts file for the CherryPi F1C200s board, which is used as an example for a F1C200s board.
Please have a look and test, if possible.
Cheers, Andre
Andre Przywara (6): sunxi: Kconfig: introduce SUNXI_MINIMUM_DRAM_MB sunxi: fix 32MB load address layout sunxi: f1c100: move SKIP_LOWLEVEL_INIT_ONLY into Kconfig sunxi: f1c100: add UART1 support sunxi: f1c100: dtsi: add UART1 pins sunxi: add CherryPi-F1C200s support
Kconfig | 6 +-- .../dts/suniv-f1c100s-cherrypi-f1c200s.dts | 45 +++++++++++++++++ arch/arm/dts/suniv-f1c100s.dtsi | 5 ++ arch/arm/mach-sunxi/Kconfig | 14 ++++++ arch/arm/mach-sunxi/board.c | 4 ++ boot/Kconfig | 4 +- configs/cherrypi_f1c200s_defconfig | 11 +++++ configs/licheepi_nano_defconfig | 2 - drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 + include/configs/sunxi-common.h | 49 ++++++++++--------- 10 files changed, 111 insertions(+), 30 deletions(-) create mode 100644 arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts create mode 100644 configs/cherrypi_f1c200s_defconfig
Traditionally we assumed that every Allwinner board would come with at least 256 MB of DRAM, and set our DRAM layout accordingly. This affected both the default load addresses, but also U-Boot's own address expectations (like being loaded at 160 MB).
Some SoCs come with co-packaged DRAM, but only provide 32 or 64MB. So far we special-cased those *chips*, as there was only one chip per DRAM size. However new chips force us to take a more general approach.
Introduce a Kconfig symbol, which provides the minimum DRAM size of the board. If nothing else is specified, we use 256 MB, and default to smaller values for those co-packaged SoCs. Then select the different DRAM maps according to this new symbol, so that different SoCs with the same DRAM size can share those definitions.
Inspired by an idea from Icenowy.
This is just refactoring: compiled for all boards before and after this patch: the binaries were identical.
Signed-off-by: Andre Przywara andre.przywara@arm.com --- Kconfig | 6 +++--- arch/arm/mach-sunxi/Kconfig | 12 ++++++++++++ boot/Kconfig | 4 ++-- include/configs/sunxi-common.h | 31 +++++++++++++++++-------------- 4 files changed, 34 insertions(+), 19 deletions(-)
diff --git a/Kconfig b/Kconfig index 2ea735d38e4..d297513bac6 100644 --- a/Kconfig +++ b/Kconfig @@ -312,9 +312,9 @@ config SYS_MALLOC_LEN default 0x4000000 if SANDBOX default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON default 0x200000 if ARCH_BMIPS || X86 - default 0x120000 if MACH_SUNIV - default 0x220000 if MACH_SUN8I_V3S - default 0x4020000 if ARCH_SUNXI + default 0x4020000 if SUNXI_MINIMUM_DRAM_MB >= 256 + default 0x220000 if SUNXI_MINIMUM_DRAM_MB >= 64 + default 0x120000 if SUNXI_MINIMUM_DRAM_MB >= 32 default 0x400000 help This defines memory to be allocated for Dynamic allocation diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 6b16f43494f..9aa66deb9fd 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -615,6 +615,18 @@ config SYS_BOARD config SYS_SOC default "sunxi"
+config SUNXI_MINIMUM_DRAM_MB + int "minimum DRAM size" + default 32 if MACH_SUNIV + default 64 if MACH_SUN8I_V3S + default 256 + ---help--- + Minimum DRAM size expected on the board. Traditionally we assumed + 256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM + we have smaller sizes, though, so that U-Boot's own load address and + the default payload addresses must be shifted down. + This is expected to be fixed by the SoC selection. + config UART0_PORT_F bool "UART0 on MicroSD breakout board" ---help--- diff --git a/boot/Kconfig b/boot/Kconfig index 6b3b8f072cb..45f86e946cd 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -499,8 +499,8 @@ config SYS_TEXT_BASE default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3 default 0x81700000 if MACH_SUNIV default 0x2a000000 if MACH_SUN9I - default 0x42e00000 if MACH_SUN8I_V3S - default 0x4a000000 if ARCH_SUNXI + default 0x4a000000 if SUNXI_MINIMUM_DRAM_MB >= 256 + default 0x42e00000 if SUNXI_MINIMUM_DRAM_MB >= 64 hex "Text Base" help The address in memory that U-Boot will be running from, initially. diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 0f0ef4f64bb..416a0422861 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -135,7 +135,21 @@ #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FF00000))
-#elif defined(CONFIG_MACH_SUN8I_V3S) +#elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 256) +/* + * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. + * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, + * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. + */ +#define BOOTM_SIZE __stringify(0xa000000) +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000)) + +#elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 64) /* * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc. * 16M uncompressed kernel, 8M compressed kernel, 1M fdt, @@ -149,7 +163,7 @@ #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1B00000)) #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1C00000))
-#elif defined(CONFIG_MACH_SUNIV) +#elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 32) /* * 32M RAM minus 1MB heap + 8MB for u-boot, stack, fb, etc. * 8M uncompressed kernel, 4M compressed kernel, 512K fdt, @@ -164,18 +178,7 @@ #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(0D60000))
#else -/* - * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. - * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, - * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. - */ -#define BOOTM_SIZE __stringify(0xa000000) -#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) -#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) -#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) -#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) -#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000)) -#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000)) +#error Need at least 32MB of DRAM. Please adjust load addresses. #endif
#define MEM_LAYOUT_ENV_SETTINGS \
Hi Andre,
Dne sreda, 12. oktober 2022 ob 18:34:53 CEST je Andre Przywara napisal(a):
Traditionally we assumed that every Allwinner board would come with at least 256 MB of DRAM, and set our DRAM layout accordingly. This affected both the default load addresses, but also U-Boot's own address expectations (like being loaded at 160 MB).
Some SoCs come with co-packaged DRAM, but only provide 32 or 64MB. So far we special-cased those *chips*, as there was only one chip per DRAM size. However new chips force us to take a more general approach.
Introduce a Kconfig symbol, which provides the minimum DRAM size of the board. If nothing else is specified, we use 256 MB, and default to smaller values for those co-packaged SoCs. Then select the different DRAM maps according to this new symbol, so that different SoCs with the same DRAM size can share those definitions.
Inspired by an idea from Icenowy.
This is just refactoring: compiled for all boards before and after this patch: the binaries were identical.
Signed-off-by: Andre Przywara andre.przywara@arm.com
Nice approach.
Reviewed-by: Jernej Skrabec jernej.skrabec@gmail.com
Best regards, Jernej
Kconfig | 6 +++--- arch/arm/mach-sunxi/Kconfig | 12 ++++++++++++ boot/Kconfig | 4 ++-- include/configs/sunxi-common.h | 31 +++++++++++++++++-------------- 4 files changed, 34 insertions(+), 19 deletions(-)
diff --git a/Kconfig b/Kconfig index 2ea735d38e4..d297513bac6 100644 --- a/Kconfig +++ b/Kconfig @@ -312,9 +312,9 @@ config SYS_MALLOC_LEN default 0x4000000 if SANDBOX default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON default 0x200000 if ARCH_BMIPS || X86
- default 0x120000 if MACH_SUNIV
- default 0x220000 if MACH_SUN8I_V3S
- default 0x4020000 if ARCH_SUNXI
- default 0x4020000 if SUNXI_MINIMUM_DRAM_MB >= 256
- default 0x220000 if SUNXI_MINIMUM_DRAM_MB >= 64
- default 0x120000 if SUNXI_MINIMUM_DRAM_MB >= 32 default 0x400000 help This defines memory to be allocated for Dynamic allocation
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 6b16f43494f..9aa66deb9fd 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -615,6 +615,18 @@ config SYS_BOARD config SYS_SOC default "sunxi"
+config SUNXI_MINIMUM_DRAM_MB
- int "minimum DRAM size"
- default 32 if MACH_SUNIV
- default 64 if MACH_SUN8I_V3S
- default 256
- ---help---
- Minimum DRAM size expected on the board. Traditionally we assumed
- 256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM
- we have smaller sizes, though, so that U-Boot's own load address
and
- the default payload addresses must be shifted down.
- This is expected to be fixed by the SoC selection.
config UART0_PORT_F bool "UART0 on MicroSD breakout board" ---help--- diff --git a/boot/Kconfig b/boot/Kconfig index 6b3b8f072cb..45f86e946cd 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -499,8 +499,8 @@ config SYS_TEXT_BASE default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3 default 0x81700000 if MACH_SUNIV default 0x2a000000 if MACH_SUN9I
- default 0x42e00000 if MACH_SUN8I_V3S
- default 0x4a000000 if ARCH_SUNXI
- default 0x4a000000 if SUNXI_MINIMUM_DRAM_MB >= 256
- default 0x42e00000 if SUNXI_MINIMUM_DRAM_MB >= 64 hex "Text Base" help The address in memory that U-Boot will be running from,
initially.
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 0f0ef4f64bb..416a0422861 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -135,7 +135,21 @@ #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FF00000))
-#elif defined(CONFIG_MACH_SUN8I_V3S) +#elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 256) +/*
- 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb,
etc. + * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
- 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end.
- */
+#define BOOTM_SIZE __stringify(0xa000000) +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000))
+#elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 64) /*
- 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc.
- 16M uncompressed kernel, 8M compressed kernel, 1M fdt,
@@ -149,7 +163,7 @@ #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1B00000)) #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1C00000))
-#elif defined(CONFIG_MACH_SUNIV) +#elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 32) /*
- 32M RAM minus 1MB heap + 8MB for u-boot, stack, fb, etc.
- 8M uncompressed kernel, 4M compressed kernel, 512K fdt,
@@ -164,18 +178,7 @@ #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(0D60000))
#else -/*
- 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb,
etc. - * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
- 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end.
- */
-#define BOOTM_SIZE __stringify(0xa000000) -#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) -#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) -#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) -#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) -#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000)) -#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000)) +#error Need at least 32MB of DRAM. Please adjust load addresses. #endif
#define MEM_LAYOUT_ENV_SETTINGS \
2.25.1
The default load addresses for the various payloads (kernel, DT, ramdisk) on systems with just 32MB of DRAM have some issues: For a start the preceding comment doesn't match the actual values: apparently they were copied from the 64MB S3 layout, then halved, but since 0x5 is NOT the half of 0x10, they don't match up. Also those projected maximum sizes are quite restrictive: it's not easy to build a compressed kernel image with just 4MB. The only defconfig in mainline Linux that supports the F1C100s (the only 32MB user so far) creates a 6MB compressed / 15MB uncompressed kernel. Rearrange the default load addresses to accommodate such a kernel: we allow an 7MB/16MB kernel, and up to 5MB of ramdisk, stuffing the smaller binaries like the DTB towards the end, just before the relocated U-Boot. Shrink the size for DTB and scripts on the way, there is no need for allowing up to 512K for them.
Signed-off-by: Andre Przywara andre.przywara@arm.com --- include/configs/sunxi-common.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 416a0422861..fe90d55bd45 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -165,17 +165,17 @@
#elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 32) /* - * 32M RAM minus 1MB heap + 8MB for u-boot, stack, fb, etc. - * 8M uncompressed kernel, 4M compressed kernel, 512K fdt, - * 512K script, 512K pxe and the ramdisk at the end. + * 32M RAM minus 2.5MB for u-boot, heap, stack, etc. + * 16M uncompressed kernel, 7M compressed kernel, 128K fdt, 64K script, + * 128K DT overlay, 128K PXE and the ramdisk in the rest (max. 5MB) */ #define BOOTM_SIZE __stringify(0x1700000) -#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0500000)) -#define FDT_ADDR_R __stringify(SDRAM_OFFSET(0C00000)) -#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(0C50000)) -#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(0D00000)) -#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(0D50000)) -#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(0D60000)) +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1d50000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1d40000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1d00000)) +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1d20000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1800000))
#else #error Need at least 32MB of DRAM. Please adjust load addresses.
Hi Andre,
Dne sreda, 12. oktober 2022 ob 18:34:54 CEST je Andre Przywara napisal(a):
The default load addresses for the various payloads (kernel, DT, ramdisk) on systems with just 32MB of DRAM have some issues: For a start the preceding comment doesn't match the actual values: apparently they were copied from the 64MB S3 layout, then halved, but since 0x5 is NOT the half of 0x10, they don't match up. Also those projected maximum sizes are quite restrictive: it's not easy to build a compressed kernel image with just 4MB. The only defconfig in mainline Linux that supports the F1C100s (the only 32MB user so far) creates a 6MB compressed / 15MB uncompressed kernel. Rearrange the default load addresses to accommodate such a kernel: we allow an 7MB/16MB kernel, and up to 5MB of ramdisk, stuffing the smaller binaries like the DTB towards the end, just before the relocated U-Boot. Shrink the size for DTB and scripts on the way, there is no need for allowing up to 512K for them.
Signed-off-by: Andre Przywara andre.przywara@arm.com
include/configs/sunxi-common.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 416a0422861..fe90d55bd45 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -165,17 +165,17 @@
#elif (CONFIG_SUNXI_MINIMUM_DRAM_MB >= 32) /*
- 32M RAM minus 1MB heap + 8MB for u-boot, stack, fb, etc.
- 8M uncompressed kernel, 4M compressed kernel, 512K fdt,
- 512K script, 512K pxe and the ramdisk at the end.
- 32M RAM minus 2.5MB for u-boot, heap, stack, etc.
- 16M uncompressed kernel, 7M compressed kernel, 128K fdt, 64K script,
- 128K DT overlay, 128K PXE and the ramdisk in the rest (max. 5MB)
DT overlays and PXE could be even much smaller, but I guess it doesn't make much of a difference.
Reviewed-by: Jernej Skrabec jernej.skrabec@gmail.com
Best regards, Jernej
*/ #define BOOTM_SIZE __stringify(0x1700000) -#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0500000)) -#define FDT_ADDR_R __stringify(SDRAM_OFFSET(0C00000)) -#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(0C50000)) -#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(0D00000)) -#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(0D50000)) -#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(0D60000)) +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1d50000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1d40000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1d00000)) +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1d20000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1800000))
#else
#error Need at least 32MB of DRAM. Please adjust load addresses.
2.25.1
So far we stated the lack of a lowlevel() init function for the F1C100s board by defining the respective SKIP_* symbol in the board's defconfig. However we don't expect any *board* to employ such low level code, so expect this to be never used for the ARMv5 Allwinner SoCs.
Select the appropriate symbols in the Kconfig, so that we can remove them from the defconfig, and avoid putting them in future defconfigs for other boards.
Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/mach-sunxi/Kconfig | 2 ++ configs/licheepi_nano_defconfig | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 9aa66deb9fd..fc5d8bb3c19 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -185,6 +185,8 @@ config MACH_SUNIV select CPU_ARM926EJS select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SKIP_LOWLEVEL_INIT_ONLY + select SPL_SKIP_LOWLEVEL_INIT_ONLY
config MACH_SUN4I bool "sun4i (Allwinner A10)" diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index 14e6bcda927..09f1a19cdbe 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -1,6 +1,4 @@ CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
Hi Andre,
Dne sreda, 12. oktober 2022 ob 18:34:55 CEST je Andre Przywara napisal(a):
So far we stated the lack of a lowlevel() init function for the F1C100s board by defining the respective SKIP_* symbol in the board's defconfig. However we don't expect any *board* to employ such low level code, so expect this to be never used for the ARMv5 Allwinner SoCs.
Select the appropriate symbols in the Kconfig, so that we can remove them from the defconfig, and avoid putting them in future defconfigs for other boards.
Signed-off-by: Andre Przywara andre.przywara@arm.com
Reviewed-by: Jernej Skrabec jernej.skrabec@gmail.com
Best regards, Jernej
arch/arm/mach-sunxi/Kconfig | 2 ++ configs/licheepi_nano_defconfig | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 9aa66deb9fd..fc5d8bb3c19 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -185,6 +185,8 @@ config MACH_SUNIV select CPU_ARM926EJS select SUNXI_GEN_SUN6I select SUPPORT_SPL
- select SKIP_LOWLEVEL_INIT_ONLY
- select SPL_SKIP_LOWLEVEL_INIT_ONLY
config MACH_SUN4I bool "sun4i (Allwinner A10)" diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index 14e6bcda927..09f1a19cdbe 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -1,6 +1,4 @@ CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano" -- 2.25.1
I am against using "f1c100" in commit message, because there is a chip called F1C100 that is part of legacy sun3i instead of suniv.
Using "suniv" or "f1c100s" is better.
在 2022-10-12星期三的 17:34 +0100，Andre Przywara写道：
So far we stated the lack of a lowlevel() init function for the F1C100s board by defining the respective SKIP_* symbol in the board's defconfig. However we don't expect any *board* to employ such low level code, so expect this to be never used for the ARMv5 Allwinner SoCs.
Select the appropriate symbols in the Kconfig, so that we can remove them from the defconfig, and avoid putting them in future defconfigs for other boards.
Signed-off-by: Andre Przywara andre.przywara@arm.com
arch/arm/mach-sunxi/Kconfig | 2 ++ configs/licheepi_nano_defconfig | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach- sunxi/Kconfig index 9aa66deb9fd..fc5d8bb3c19 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -185,6 +185,8 @@ config MACH_SUNIV select CPU_ARM926EJS select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SKIP_LOWLEVEL_INIT_ONLY + select SPL_SKIP_LOWLEVEL_INIT_ONLY config MACH_SUN4I bool "sun4i (Allwinner A10)" diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index 14e6bcda927..09f1a19cdbe 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -1,6 +1,4 @@ CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
Some boards use UART1 for its debug UART, so define the pins for the SPL and the pinmux name and mux value for U-Boot proper.
Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/mach-sunxi/board.c | 4 ++++ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 + 2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 62bb40b8c89..77216157908 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -147,6 +147,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV) + sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); + sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 9ce2bc1b3af..061104be056 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -245,6 +245,7 @@ static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = { #else { "uart0", 5 }, /* PE0-PE1 */ #endif + { "uart1", 5 }, /* PA0-PA3 */ };
static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = {
Hi Andre,
Dne sreda, 12. oktober 2022 ob 18:34:56 CEST je Andre Przywara napisal(a):
Some boards use UART1 for its debug UART, so define the pins for the SPL and the pinmux name and mux value for U-Boot proper.
Signed-off-by: Andre Przywara andre.przywara@arm.com
arch/arm/mach-sunxi/board.c | 4 ++++ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 + 2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 62bb40b8c89..77216157908 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -147,6 +147,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
- sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
- sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 9ce2bc1b3af..061104be056 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -245,6 +245,7 @@ static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = { #else { "uart0", 5 }, /* PE0-PE1 */ #endif
- { "uart1", 5 }, /* PA0-PA3 */
Comment should be PA2-PA3. With that fixed: Reviewed-by: Jernej Skrabec jernej.skrabec@gmail.com
Best regards, Jernej
};
static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = { -- 2.25.1
On 12/10/2022 22:42, Jernej Škrabec wrote:
Hi Jernej,
many thanks for the review of this series, that's much appreciated!
Dne sreda, 12. oktober 2022 ob 18:34:56 CEST je Andre Przywara napisal(a):
Some boards use UART1 for its debug UART, so define the pins for the SPL and the pinmux name and mux value for U-Boot proper.
Signed-off-by: Andre Przywara andre.przywara@arm.com
arch/arm/mach-sunxi/board.c | 4 ++++ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 + 2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 62bb40b8c89..77216157908 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -147,6 +147,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
- sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
- sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 9ce2bc1b3af..061104be056 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -245,6 +245,7 @@ static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = { #else { "uart0", 5 }, /* PE0-PE1 */ #endif
- { "uart1", 5 }, /* PA0-PA3 */
Comment should be PA2-PA3. With that fixed:
Well, PA0 and PA1 are RTS and CTS for UART1, so if you don't mind, I will keep it like this. Not that the comment really matters anyway ;-)
Cheers, Andre
Reviewed-by: Jernej Skrabec jernej.skrabec@gmail.com
Best regards, Jernej
};
static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = { -- 2.25.1
Dne torek, 18. oktober 2022 ob 11:23:41 CEST je Andre Przywara napisal(a):
On 12/10/2022 22:42, Jernej Škrabec wrote:
Hi Jernej,
many thanks for the review of this series, that's much appreciated!
Dne sreda, 12. oktober 2022 ob 18:34:56 CEST je Andre Przywara napisal(a):
Some boards use UART1 for its debug UART, so define the pins for the SPL and the pinmux name and mux value for U-Boot proper.
Signed-off-by: Andre Przywara andre.przywara@arm.com
arch/arm/mach-sunxi/board.c | 4 ++++ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 + 2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 62bb40b8c89..77216157908 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -147,6 +147,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 9ce2bc1b3af..061104be056 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -245,6 +245,7 @@ static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = { #else
{ "uart0", 5 }, /* PE0-PE1 */
#endif
- { "uart1", 5 }, /* PA0-PA3 */
Comment should be PA2-PA3. With that fixed:
Well, PA0 and PA1 are RTS and CTS for UART1, so if you don't mind, I will keep it like this. Not that the comment really matters anyway ;-)
Ok.
Best regards, Jernej
Cheers, Andre
Reviewed-by: Jernej Skrabec jernej.skrabec@gmail.com
Best regards, Jernej
};
static const struct sunxi_pinctrl_desc __maybe_unused
suniv_f1c100s_pinctrl_desc = { -- 2.25.1
The F1Cx00 SoCs connect the first PortA pins to UART1.
Add this to the SoC .dtsi, so boards can reference UART1 pins.
Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/dts/suniv-f1c100s.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi index 0edc1724407..bc563c12e95 100644 --- a/arch/arm/dts/suniv-f1c100s.dtsi +++ b/arch/arm/dts/suniv-f1c100s.dtsi @@ -175,6 +175,11 @@ pins = "PE0", "PE1"; function = "uart0"; }; + + uart1_pa_pins: uart1-pa-pins { + pins = "PA2", "PA3"; + function = "uart1"; + }; };
timer@1c20c00 {
Hi Andre,
Dne sreda, 12. oktober 2022 ob 18:34:57 CEST je Andre Przywara napisal(a):
The F1Cx00 SoCs connect the first PortA pins to UART1.
Add this to the SoC .dtsi, so boards can reference UART1 pins.
Signed-off-by: Andre Przywara andre.przywara@arm.com
Reviewed-by: Jernej Skrabec jernej.skrabec@gmail.com
Best regards, Jernej
arch/arm/dts/suniv-f1c100s.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi index 0edc1724407..bc563c12e95 100644 --- a/arch/arm/dts/suniv-f1c100s.dtsi +++ b/arch/arm/dts/suniv-f1c100s.dtsi @@ -175,6 +175,11 @@ pins = "PE0", "PE1"; function = "uart0"; };
uart1_pa_pins: uart1-pa-pins {pins = "PA2", "PA3";function = "uart1";};};
timer@1c20c00 {
-- 2.25.1
The CherryPi F1C200s board is a small development board, featuring the F1C200s with 64MB of co-packaged DRAM. It comes with two USB-C sockets, of which one is connected to a USB-UART chip, that provides easy access to UART1. Beside the usual micro-SD card slot, the board comes with a SPI NAND flash chip, which is not yet supported.
Signed-off-by: Andre Przywara andre.przywara@arm.com --- .../dts/suniv-f1c100s-cherrypi-f1c200s.dts | 45 +++++++++++++++++++ configs/cherrypi_f1c200s_defconfig | 11 +++++ 2 files changed, 56 insertions(+) create mode 100644 arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts create mode 100644 configs/cherrypi_f1c200s_defconfig
diff --git a/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts new file mode 100644 index 00000000000..f0ebcb6d893 --- /dev/null +++ b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2022 Arm Ltd. + * based on another DT, which is: + * Copyright 2018 Icenowy Zheng icenowy@aosc.io + */ + +/dts-v1/; +#include "suniv-f1c100s.dtsi" + +/ { + model = "Cherry Pi F1C200s"; + compatible = "lctech,cherrypi-f1c200s", "allwinner,suniv-f1c100s"; + + aliases { + mmc0 = &mmc0; + serial0 = &uart1; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + status = "okay"; + vmmc-supply = <®_vcc3v3>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pa_pins>; + status = "okay"; +}; diff --git a/configs/cherrypi_f1c200s_defconfig b/configs/cherrypi_f1c200s_defconfig new file mode 100644 index 00000000000..306d363f485 --- /dev/null +++ b/configs/cherrypi_f1c200s_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-cherrypi-f1c200s" +CONFIG_SPL=y +CONFIG_MACH_SUNIV=y +CONFIG_DRAM_CLK=156 +CONFIG_DRAM_ZQ=0 +CONFIG_SUNXI_MINIMUM_DRAM_MB=64 +# CONFIG_VIDEO_SUNXI is not set +CONFIG_CONS_INDEX=2
Hi Andre,
On Wed, 12 Oct 2022 at 18:35, Andre Przywara andre.przywara@arm.com wrote:
The CherryPi F1C200s board is a small development board, featuring the F1C200s with 64MB of co-packaged DRAM. It comes with two USB-C sockets, of which one is connected to a USB-UART chip, that provides easy access to UART1.
A similar board is trying to been upstreamed by Icenowy:
see : https://lore.kernel.org/lkml/20221012055602.1544944-11-uwu@icenowy.me/ [PATCH v2 10/10] ARM: dts: suniv: add device tree for PopStick v1.1
Maybe we should take into account the remarks that Krzysztof Kozlowski made to follow the same device-tree rules on U-boot.
Regards, Clement
Beside the usual micro-SD card slot, the board comes with a SPI NAND flash chip, which is not yet supported.
Signed-off-by: Andre Przywara andre.przywara@arm.com
.../dts/suniv-f1c100s-cherrypi-f1c200s.dts | 45 +++++++++++++++++++ configs/cherrypi_f1c200s_defconfig | 11 +++++ 2 files changed, 56 insertions(+) create mode 100644 arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts create mode 100644 configs/cherrypi_f1c200s_defconfig
diff --git a/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts new file mode 100644 index 00000000000..f0ebcb6d893 --- /dev/null +++ b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/*
- Copyright 2022 Arm Ltd.
- based on another DT, which is:
- Copyright 2018 Icenowy Zheng icenowy@aosc.io
- */
+/dts-v1/; +#include "suniv-f1c100s.dtsi"
+/ {
model = "Cherry Pi F1C200s";compatible = "lctech,cherrypi-f1c200s", "allwinner,suniv-f1c100s";aliases {mmc0 = &mmc0;serial0 = &uart1;spi0 = &spi0;};chosen {stdout-path = "serial0:115200n8";};reg_vcc3v3: vcc3v3 {compatible = "regulator-fixed";regulator-name = "vcc3v3";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;};+};
+&mmc0 {
broken-cd;bus-width = <4>;disable-wp;status = "okay";vmmc-supply = <®_vcc3v3>;+};
+&uart1 {
pinctrl-names = "default";pinctrl-0 = <&uart1_pa_pins>;status = "okay";+}; diff --git a/configs/cherrypi_f1c200s_defconfig b/configs/cherrypi_f1c200s_defconfig new file mode 100644 index 00000000000..306d363f485 --- /dev/null +++ b/configs/cherrypi_f1c200s_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-cherrypi-f1c200s" +CONFIG_SPL=y +CONFIG_MACH_SUNIV=y +CONFIG_DRAM_CLK=156 +CONFIG_DRAM_ZQ=0 +CONFIG_SUNXI_MINIMUM_DRAM_MB=64 +# CONFIG_VIDEO_SUNXI is not set
+CONFIG_CONS_INDEX=2
2.25.1
On 13/10/2022 09:33, Clément Péron wrote:
Hi Clément,
On Wed, 12 Oct 2022 at 18:35, Andre Przywara andre.przywara@arm.com wrote:
The CherryPi F1C200s board is a small development board, featuring the F1C200s with 64MB of co-packaged DRAM. It comes with two USB-C sockets, of which one is connected to a USB-UART chip, that provides easy access to UART1.
A similar board is trying to been upstreamed by Icenowy:
see : https://lore.kernel.org/lkml/20221012055602.1544944-11-uwu@icenowy.me/ [PATCH v2 10/10] ARM: dts: suniv: add device tree for PopStick v1.1
Maybe we should take into account the remarks that Krzysztof Kozlowski made to follow the same device-tree rules on U-boot.
Yeah, thanks for the heads up, I saw that. I just wanted to post this to demonstrate what needs to be done. I will be sending a Linux DT patch anyway, since DTs need to go via Linux anyway.
Thanks, Andre
Regards, Clement
Beside the usual micro-SD card slot, the board comes with a SPI NAND flash chip, which is not yet supported.
Signed-off-by: Andre Przywara andre.przywara@arm.com
.../dts/suniv-f1c100s-cherrypi-f1c200s.dts | 45 +++++++++++++++++++ configs/cherrypi_f1c200s_defconfig | 11 +++++ 2 files changed, 56 insertions(+) create mode 100644 arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts create mode 100644 configs/cherrypi_f1c200s_defconfig
diff --git a/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts new file mode 100644 index 00000000000..f0ebcb6d893 --- /dev/null +++ b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/*
- Copyright 2022 Arm Ltd.
- based on another DT, which is:
- Copyright 2018 Icenowy Zheng icenowy@aosc.io
- */
+/dts-v1/; +#include "suniv-f1c100s.dtsi"
+/ {
model = "Cherry Pi F1C200s";compatible = "lctech,cherrypi-f1c200s", "allwinner,suniv-f1c100s";aliases {mmc0 = &mmc0;serial0 = &uart1;spi0 = &spi0;};chosen {stdout-path = "serial0:115200n8";};reg_vcc3v3: vcc3v3 {compatible = "regulator-fixed";regulator-name = "vcc3v3";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;};+};
+&mmc0 {
broken-cd;bus-width = <4>;disable-wp;status = "okay";vmmc-supply = <®_vcc3v3>;+};
+&uart1 {
pinctrl-names = "default";pinctrl-0 = <&uart1_pa_pins>;status = "okay";+}; diff --git a/configs/cherrypi_f1c200s_defconfig b/configs/cherrypi_f1c200s_defconfig new file mode 100644 index 00000000000..306d363f485 --- /dev/null +++ b/configs/cherrypi_f1c200s_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-cherrypi-f1c200s" +CONFIG_SPL=y +CONFIG_MACH_SUNIV=y +CONFIG_DRAM_CLK=156 +CONFIG_DRAM_ZQ=0 +CONFIG_SUNXI_MINIMUM_DRAM_MB=64 +# CONFIG_VIDEO_SUNXI is not set
+CONFIG_CONS_INDEX=2
2.25.1
On 10/13/22 05:53, Andre Przywara wrote:
On 13/10/2022 09:33, Clément Péron wrote:
Hi Clément,
On Wed, 12 Oct 2022 at 18:35, Andre Przywara andre.przywara@arm.com wrote:
The CherryPi F1C200s board is a small development board, featuring the F1C200s with 64MB of co-packaged DRAM. It comes with two USB-C sockets, of which one is connected to a USB-UART chip, that provides easy access to UART1.
A similar board is trying to been upstreamed by Icenowy:
see : https://lore.kernel.org/lkml/20221012055602.1544944-11-uwu@icenowy.me/ [PATCH v2 10/10] ARM: dts: suniv: add device tree for PopStick v1.1
Maybe we should take into account the remarks that Krzysztof Kozlowski made to follow the same device-tree rules on U-boot.
Yeah, thanks for the heads up, I saw that. I just wanted to post this to demonstrate what needs to be done. I will be sending a Linux DT patch anyway, since DTs need to go via Linux anyway.
Thanks, Andre
Regards, Clement
Beside the usual micro-SD card slot, the board comes with a SPI NAND flash chip, which is not yet supported.
Signed-off-by: Andre Przywara andre.przywara@arm.com
.../dts/suniv-f1c100s-cherrypi-f1c200s.dts | 45 +++++++++++++++++++ configs/cherrypi_f1c200s_defconfig | 11 +++++ 2 files changed, 56 insertions(+) create mode 100644 arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts create mode 100644 configs/cherrypi_f1c200s_defconfig
diff --git a/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts new file mode 100644 index 00000000000..f0ebcb6d893 --- /dev/null +++ b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/*
- Copyright 2022 Arm Ltd.
- based on another DT, which is:
- Copyright 2018 Icenowy Zheng icenowy@aosc.io
Her email changed IDK if it is proper to change here.
- */
+/dts-v1/; +#include "suniv-f1c100s.dtsi"
+/ {
model = "Cherry Pi F1C200s";compatible = "lctech,cherrypi-f1c200s", "allwinner,suniv-f1c100s";aliases {mmc0 = &mmc0;serial0 = &uart1;spi0 = &spi0;
no need for spi.
};chosen {stdout-path = "serial0:115200n8";};reg_vcc3v3: vcc3v3 {compatible = "regulator-fixed";regulator-name = "vcc3v3";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;};+};
+&mmc0 {
broken-cd;bus-width = <4>;disable-wp;status = "okay";vmmc-supply = <®_vcc3v3>;+};
+&uart1 {
pinctrl-names = "default";pinctrl-0 = <&uart1_pa_pins>;status = "okay";+}; diff --git a/configs/cherrypi_f1c200s_defconfig b/configs/cherrypi_f1c200s_defconfig new file mode 100644 index 00000000000..306d363f485 --- /dev/null +++ b/configs/cherrypi_f1c200s_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-cherrypi-f1c200s" +CONFIG_SPL=y +CONFIG_MACH_SUNIV=y +CONFIG_DRAM_CLK=156 +CONFIG_DRAM_ZQ=0
You need +CONFIG_SPL_STACK=0x8000
I will test this on both 100s and 200s. Thanks, Jesse Taube
+CONFIG_SUNXI_MINIMUM_DRAM_MB=64 +# CONFIG_VIDEO_SUNXI is not set
+CONFIG_CONS_INDEX=2
2.25.1
On Fri, 14 Oct 2022 01:04:18 -0400 Jesse Taube mr.bossman075@gmail.com wrote:
Hi Jesse, Giulio,
thanks for having a look and for the testing!
On 10/13/22 05:53, Andre Przywara wrote:
On 13/10/2022 09:33, Clément Péron wrote:
Hi Clément,
On Wed, 12 Oct 2022 at 18:35, Andre Przywara andre.przywara@arm.com wrote:
The CherryPi F1C200s board is a small development board, featuring the F1C200s with 64MB of co-packaged DRAM. It comes with two USB-C sockets, of which one is connected to a USB-UART chip, that provides easy access to UART1.
A similar board is trying to been upstreamed by Icenowy:
see : https://lore.kernel.org/lkml/20221012055602.1544944-11-uwu@icenowy.me/ [PATCH v2 10/10] ARM: dts: suniv: add device tree for PopStick v1.1
Maybe we should take into account the remarks that Krzysztof Kozlowski made to follow the same device-tree rules on U-boot.
Yeah, thanks for the heads up, I saw that. I just wanted to post this to demonstrate what needs to be done. I will be sending a Linux DT patch anyway, since DTs need to go via Linux anyway.
Thanks, Andre
Regards, Clement
Beside the usual micro-SD card slot, the board comes with a SPI NAND flash chip, which is not yet supported.
Signed-off-by: Andre Przywara andre.przywara@arm.com
.../dts/suniv-f1c100s-cherrypi-f1c200s.dts | 45 +++++++++++++++++++ configs/cherrypi_f1c200s_defconfig | 11 +++++ 2 files changed, 56 insertions(+) create mode 100644 arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts create mode 100644 configs/cherrypi_f1c200s_defconfig
diff --git a/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts new file mode 100644 index 00000000000..f0ebcb6d893 --- /dev/null +++ b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/*
- Copyright 2022 Arm Ltd.
- based on another DT, which is:
- Copyright 2018 Icenowy Zheng icenowy@aosc.io
Her email changed IDK if it is proper to change here.
- */
+/dts-v1/; +#include "suniv-f1c100s.dtsi"
+/ {
model = "Cherry Pi F1C200s";compatible = "lctech,cherrypi-f1c200s", "allwinner,suniv-f1c100s";aliases {mmc0 = &mmc0;serial0 = &uart1;spi0 = &spi0;no need for spi.
};chosen {stdout-path = "serial0:115200n8";};reg_vcc3v3: vcc3v3 {compatible = "regulator-fixed";regulator-name = "vcc3v3";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;};+};
+&mmc0 {
broken-cd;bus-width = <4>;disable-wp;status = "okay";vmmc-supply = <®_vcc3v3>;+};
+&uart1 {
pinctrl-names = "default";pinctrl-0 = <&uart1_pa_pins>;status = "okay";+}; diff --git a/configs/cherrypi_f1c200s_defconfig b/configs/cherrypi_f1c200s_defconfig new file mode 100644 index 00000000000..306d363f485 --- /dev/null +++ b/configs/cherrypi_f1c200s_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-cherrypi-f1c200s" +CONFIG_SPL=y +CONFIG_MACH_SUNIV=y +CONFIG_DRAM_CLK=156 +CONFIG_DRAM_ZQ=0
You need +CONFIG_SPL_STACK=0x8000
I posted "[PATCH 1/2] sunxi: Kconfig: use SoC-wide values for some symbols" (https://lore.kernel.org/u-boot/20220913234335.24902-2-andre.przywara@arm.com...) that solves that issue. That patch is applied before this series in the tree, so no change should be needed.
Thanks for the report!
Cheers, Andre
I will test this on both 100s and 200s. Thanks, Jesse Taube
+CONFIG_SUNXI_MINIMUM_DRAM_MB=64 +# CONFIG_VIDEO_SUNXI is not set
+CONFIG_CONS_INDEX=2
2.25.1
Hi Andre,
On 18/10/22 16:01, Andre Przywara wrote:
On Fri, 14 Oct 2022 01:04:18 -0400 Jesse Taube mr.bossman075@gmail.com wrote:
Hi Jesse, Giulio,
thanks for having a look and for the testing!
You're welcome: Tested-by: Giulio Benetti giulio.benetti@benettiengineering.com
Best regards
participants (6)
-
Andre Przywara -
Clément Péron -
Giulio Benetti -
Icenowy Zheng -
Jernej Škrabec -
Jesse Taube