This releases the DP configuration from reset early on during the boot process for K26 SOM. It will also avoid the boot hang situation should any attempt be made to configure the DP registers while it is still in reset.

Fixes the same issue as described by this commit: https://github.com/u-boot/u-boot/commit/8b81010a2fe385524b58bea9116f1b6954c3...

Signed-off-by: Neal Frager neal.frager@amd.com --- board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c index e5598807e8..f8d7c8466f 100644 --- a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c @@ -465,7 +465,7 @@ static unsigned long psu_peripherals_pre_init_data(void)

static unsigned long psu_peripherals_init_data(void) { - psu_mask_write(0xFD1A0100, 0x0000807CU, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U); psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);