pá 15. 10. 2021 v 15:17 odesílatel Michal Simek michal.simek@xilinx.com napsal:

When DT node has pwm-cells property it shouldn't be bind as timer driver but as PWM driver. That's why make sure that this property is checked.

Signed-off-by: Michal Simek michal.simek@xilinx.com Reviewed-by: Sean Anderson sean.anderson@seco.com Reviewed-by: Simon Glass sjg@chromium.org

---

Changes in v4:

• Add reviewed-by tags

Changes in v3:

• New patch in series

drivers/timer/cadence-ttc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c index 2f95d45ecd7a..2eff45060ad6 100644 --- a/drivers/timer/cadence-ttc.c +++ b/drivers/timer/cadence-ttc.c @@ -97,6 +97,17 @@ static int cadence_ttc_of_to_plat(struct udevice *dev) return 0; }

+static int cadence_ttc_bind(struct udevice *dev) +{

•   const char *cells;
  

•   cells = dev_read_prop(dev, "#pwm-cells", NULL);
  

•   if (cells)
  

•           return -ENODEV;
  

•   return 0;
  

+}

static const struct timer_ops cadence_ttc_ops = { .get_count = cadence_ttc_get_count, }; @@ -114,4 +125,5 @@ U_BOOT_DRIVER(cadence_ttc) = { .priv_auto = sizeof(struct cadence_ttc_priv), .probe = cadence_ttc_probe, .ops = &cadence_ttc_ops,

•   .bind = cadence_ttc_bind,
  

};

2.33.1

Applied. M

pá 15. 10. 2021 v 15:17 odesílatel Michal Simek michal.simek@xilinx.com napsal:

TTC has three modes of operations. Timer, PWM and input counters.

There is already driver for timer under CADENCE_TTC_TIMER which is used for ZynqMP R5 configuration. This driver is targeting PWM which is for example configuration which can be used for fan control. The driver has been tested on Xilinx Kria SOM platform where fan is connected to one PL pin. When TTC output is connected via EMIO to PL pin TTC pwm can be configured and tested for example like this: pwm config 0 0 10000 1200 pwm enable 0 0 pwm config 0 0 10000 1400 pwm config 0 0 10000 1600

Signed-off-by: Michal Simek michal.simek@xilinx.com Reviewed-by: Sean Anderson sean.anderson@seco.com

---

Changes in v4:

• • Add reviewed-by tag

Changes in v3:

• Add bind function to check pwm-cells to recognize PWM driver
• Use timer-width in prescaler calculation
• Record timer width in platdata instead of timer mask
• Also disable wave out in config function

Changes in v2:

• Detect pwm-cells property for PWM driver
• Fix all macro names
• Use BIT and GENMASK macros
• Introduce TTC_REG macro for reg offsets
• Use FIELD_PREP
• Move cadence_ttc_pwm_of_to_plat() below probe
• Introduce struct cadence_ttc_pwm_plat
• Read timer-width from DT
• Use NSEC_PER_SEC macro
• Use clock_ctrl variable instead of x - all reported by Sean

MAINTAINERS | 1 + drivers/pwm/Kconfig | 7 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-cadence-ttc.c | 261 ++++++++++++++++++++++++++++++++++ 4 files changed, 270 insertions(+) create mode 100644 drivers/pwm/pwm-cadence-ttc.c

diff --git a/MAINTAINERS b/MAINTAINERS index 71f468c00a8f..d8873e520c8f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -599,6 +599,7 @@ F: drivers/mmc/zynq_sdhci.c F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c +F: drivers/pwm/pwm-cadence-ttc.c F: drivers/serial/serial_zynq.c F: drivers/reset/reset-zynqmp.c F: drivers/rtc/zynqmp_rtc.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 669d3fa4fc59..ec205ae4fa8a 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -15,6 +15,13 @@ config PWM_AT91 help Support for PWM hardware on AT91 based SoC.

+config PWM_CADENCE_TTC

•   bool "Enable support for the Cadence TTC PWM"
  

•   depends on DM_PWM && !CADENCE_TTC_TIMER
  

•   help
  

•     Cadence TTC can be configured as timer which is done via
  

•     CONFIG_CADENCE_TTC_TIMER or as PWM. This is covering only PWM now.
  

config PWM_CROS_EC bool "Enable support for the Chrome OS EC PWM" depends on DM_PWM diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 55f2bc081d25..54413c689cac 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o

obj-$(CONFIG_PWM_AT91) += pwm-at91.o +obj-$(CONFIG_PWM_CADENCE_TTC) += pwm-cadence-ttc.o obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o diff --git a/drivers/pwm/pwm-cadence-ttc.c b/drivers/pwm/pwm-cadence-ttc.c new file mode 100644 index 000000000000..dc3b314b0cce --- /dev/null +++ b/drivers/pwm/pwm-cadence-ttc.c @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • (C) Copyright 2021 Xilinx, Inc. Michal Simek
• */

+#define LOG_CATEGORY UCLASS_PWM

+#include <clk.h> +#include <common.h> +#include <div64.h> +#include <dm.h> +#include <log.h> +#include <pwm.h> +#include <asm/io.h> +#include <log.h> +#include <div64.h> +#include <linux/bitfield.h> +#include <linux/math64.h> +#include <linux/log2.h> +#include <dm/device_compat.h>

+#define CLOCK_CONTROL 0 +#define COUNTER_CONTROL 0xc +#define INTERVAL_COUNTER 0x24 +#define MATCH_1_COUNTER 0x30

+#define CLK_FALLING_EDGE BIT(6) +#define CLK_SRC_EXTERNAL BIT(5) +#define CLK_PRESCALE_MASK GENMASK(4, 1) +#define CLK_PRESCALE_ENABLE BIT(0)

+#define COUNTER_WAVE_POL BIT(6) +#define COUNTER_WAVE_DISABLE BIT(5) +#define COUNTER_RESET BIT(4) +#define COUNTER_MATCH_ENABLE BIT(3) +#define COUNTER_DECREMENT_ENABLE BIT(2) +#define COUNTER_INTERVAL_ENABLE BIT(1) +#define COUNTER_COUNTING_DISABLE BIT(0)

+#define NSEC_PER_SEC 1000000000L

+#define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32)) +#define TTC_CLOCK_CONTROL(reg, channel) \

•   TTC_REG((reg) + CLOCK_CONTROL, (channel))
  

+#define TTC_COUNTER_CONTROL(reg, channel) \

•   TTC_REG((reg) + COUNTER_CONTROL, (channel))
  

+#define TTC_INTERVAL_COUNTER(reg, channel) \

•   TTC_REG((reg) + INTERVAL_COUNTER, (channel))
  

+#define TTC_MATCH_1_COUNTER(reg, channel) \

•   TTC_REG((reg) + MATCH_1_COUNTER, (channel))
  

+struct cadence_ttc_pwm_plat {

•   u8 *regs;
  

•   u32 timer_width;
  

+};

+struct cadence_ttc_pwm_priv {

•   u8 *regs;
  

•   u32 timer_width;
  

•   u32 timer_mask;
  

•   unsigned long frequency;
  

•   bool invert[2];
  

+};

+static int cadence_ttc_pwm_set_invert(struct udevice *dev, uint channel,

•                                 bool polarity)
  

+{

•   struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
  

•   if (channel > 2) {
  

•           dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
  

•           return -EINVAL;
  

•   }
  

•   priv->invert[channel] = polarity;
  

•   dev_dbg(dev, "polarity=%u. Please config PWM again\n", polarity);
  

•   return 0;
  

+}

+static int cadence_ttc_pwm_set_config(struct udevice *dev, uint channel,

•                                 uint period_ns, uint duty_ns)
  

+{

•   struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
  

•   u32 counter_ctrl, clock_ctrl;
  

•   int period_clocks, duty_clocks, prescaler;
  

•   dev_dbg(dev, "channel %d, duty %d/period %d ns\n", channel,
  

•           duty_ns, period_ns);
  

•   if (channel > 2) {
  

•           dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
  

•           return -EINVAL;
  

•   }
  

•   /* Make sure counter is stopped */
  

•   counter_ctrl = readl(TTC_COUNTER_CONTROL(priv->regs, channel));
  

•   setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
  

•                COUNTER_COUNTING_DISABLE | COUNTER_WAVE_DISABLE);
  

•   /* Calculate period, prescaler and set clock control register */
  

•   period_clocks = div64_u64(((int64_t)period_ns * priv->frequency),
  

•                             NSEC_PER_SEC);
  

•   prescaler = ilog2(period_clocks) + 1 - priv->timer_width;
  

•   if (prescaler < 0)
  

•           prescaler = 0;
  

•   clock_ctrl = readl(TTC_CLOCK_CONTROL(priv->regs, channel));
  

•   if (!prescaler) {
  

•           clock_ctrl &= ~(CLK_PRESCALE_ENABLE | CLK_PRESCALE_MASK);
  

•   } else {
  

•           clock_ctrl &= ~CLK_PRESCALE_MASK;
  

•           clock_ctrl |= CLK_PRESCALE_ENABLE;
  

•           clock_ctrl |= FIELD_PREP(CLK_PRESCALE_MASK, prescaler - 1);
  

•   };
  

•   /* External source is not handled by this driver now */
  

•   clock_ctrl &= ~CLK_SRC_EXTERNAL;
  

•   writel(clock_ctrl, TTC_CLOCK_CONTROL(priv->regs, channel));
  

•   /* Calculate interval and set counter control value */
  

•   duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency),
  

•                           NSEC_PER_SEC);
  

•   writel((period_clocks >> prescaler) & priv->timer_mask,
  

•          TTC_INTERVAL_COUNTER(priv->regs, channel));
  

•   writel((duty_clocks >> prescaler) & priv->timer_mask,
  

•          TTC_MATCH_1_COUNTER(priv->regs, channel));
  

•   /* Restore/reset counter */
  

•   counter_ctrl &= ~COUNTER_DECREMENT_ENABLE;
  

•   counter_ctrl |= COUNTER_INTERVAL_ENABLE |
  

•                   COUNTER_RESET |
  

•                   COUNTER_MATCH_ENABLE;
  

•   if (priv->invert[channel])
  

•           counter_ctrl |= COUNTER_WAVE_POL;
  

•   else
  

•           counter_ctrl &= ~COUNTER_WAVE_POL;
  

•   writel(counter_ctrl, TTC_COUNTER_CONTROL(priv->regs, channel));
  

•   dev_dbg(dev, "%d/%d clocks, prescaler 2^%d\n", duty_clocks,
  

•           period_clocks, prescaler);
  

•   return 0;
  

+};

+static int cadence_ttc_pwm_set_enable(struct udevice *dev, uint channel,

•                                 bool enable)
  

+{

•   struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
  

•   if (channel > 2) {
  

•           dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
  

•           return -EINVAL;
  

•   }
  

•   dev_dbg(dev, "Enable: %d, channel %d\n", enable, channel);
  

•   if (enable) {
  

•           clrbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
  

•                        COUNTER_COUNTING_DISABLE |
  

•                        COUNTER_WAVE_DISABLE);
  

•           setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
  

•                        COUNTER_RESET);
  

•   } else {
  

•           setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
  

•                        COUNTER_COUNTING_DISABLE |
  

•                        COUNTER_WAVE_DISABLE);
  

•   }
  

•   return 0;
  

+};

+static int cadence_ttc_pwm_probe(struct udevice *dev) +{

•   struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
  

•   struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
  

•   struct clk clk;
  

•   int ret;
  

•   priv->regs = plat->regs;
  

•   priv->timer_width = plat->timer_width;
  

•   priv->timer_mask = GENMASK(priv->timer_width - 1, 0);
  

•   ret = clk_get_by_index(dev, 0, &clk);
  

•   if (ret < 0) {
  

•           dev_err(dev, "failed to get clock\n");
  

•           return ret;
  

•   }
  

•   priv->frequency = clk_get_rate(&clk);
  

•   if (IS_ERR_VALUE(priv->frequency)) {
  

•           dev_err(dev, "failed to get rate\n");
  

•           return priv->frequency;
  

•   }
  

•   dev_dbg(dev, "Clk frequency: %ld\n", priv->frequency);
  

•   ret = clk_enable(&clk);
  

•   if (ret) {
  

•           dev_err(dev, "failed to enable clock\n");
  

•           return ret;
  

•   }
  

•   return 0;
  

+}

+static int cadence_ttc_pwm_of_to_plat(struct udevice *dev) +{

•   struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
  

•   const char *cells;
  

•   cells = dev_read_prop(dev, "#pwm-cells", NULL);
  

•   if (!cells)
  

•           return -EINVAL;
  

•   plat->regs = dev_read_addr_ptr(dev);
  

•   plat->timer_width = dev_read_u32_default(dev, "timer-width", 16);
  

•   return 0;
  

+}

+static int cadence_ttc_pwm_bind(struct udevice *dev) +{

•   const char *cells;
  

•   cells = dev_read_prop(dev, "#pwm-cells", NULL);
  

•   if (!cells)
  

•           return -ENODEV;
  

•   return 0;
  

+}

+static const struct pwm_ops cadence_ttc_pwm_ops = {

•   .set_invert = cadence_ttc_pwm_set_invert,
  

•   .set_config = cadence_ttc_pwm_set_config,
  

•   .set_enable = cadence_ttc_pwm_set_enable,
  

+};

+static const struct udevice_id cadence_ttc_pwm_ids[] = {

•   { .compatible = "cdns,ttc" },
  

•   { }
  

+};

+U_BOOT_DRIVER(cadence_ttc_pwm) = {

•   .name = "cadence_ttc_pwm",
  

•   .id = UCLASS_PWM,
  

•   .of_match = cadence_ttc_pwm_ids,
  

•   .ops = &cadence_ttc_pwm_ops,
  

•   .bind = cadence_ttc_pwm_bind,
  

•   .of_to_plat = cadence_ttc_pwm_of_to_plat,
  

•   .probe = cadence_ttc_pwm_probe,
  

•   .priv_auto = sizeof(struct cadence_ttc_pwm_priv),
  

•   .plat_auto = sizeof(struct cadence_ttc_pwm_plat),
  

+};

2.33.1

Applied. M

pá 15. 10. 2021 v 15:17 odesílatel Michal Simek michal.simek@xilinx.com napsal:

Enable PWM ttc driver and command in generic image.

Signed-off-by: Michal Simek michal.simek@xilinx.com

Changes in v4:

• New patch in the series

configs/xilinx_zynqmp_virt_defconfig | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 7401078c113e..94a45f293b9b 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -52,6 +52,7 @@ CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -160,6 +161,8 @@ CONFIG_XILINX_AXIEMAC=y CONFIG_ZYNQ_GEM=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_CADENCE_TTC=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_RTC_ZYNQMP=y -- 2.33.1

Applied. M

ne 24. 10. 2021 v 22:01 odesílatel Simon Glass sjg@chromium.org napsal:

Hi Michal,

On Fri, 15 Oct 2021 at 07:17, Michal Simek michal.simek@xilinx.com wrote:

...

When one IP can have multiple configurations (like timer and PWM) covered by multiple drivers. Because it is the same IP it should also have the same compatible string. Current code look for the first driver which matches compatible string and call bind function. If this is not the right driver which is express by returning -ENODEV ("Driver XYZ refuses to bind") there is no reason not to continue over compatible list to try to find out different driver with the same compatible string which match it.

When the first compatible string is found core looks for driver bind() function. If if assigned driver refuse to bind, core continue in a loop to check if there is another driver which match compatible string.

This driver is going to be used with cdnc,ttc driver which has driver as timer and also can be used as PWM. The difference is done via #pwm-cells property in DT.

Signed-off-by: Michal Simek michal.simek@xilinx.com

Changes in v4:

• Remove goto from code
• Also continue on prereloc case

Changes in v3:

• New patch in series

When this is acked I will spent my time on writing test for it.

---

drivers/core/lists.c | 84 +++++++++++++++++++++++++++----------------- 1 file changed, 52 insertions(+), 32 deletions(-)

diff --git a/drivers/core/lists.c b/drivers/core/lists.c index 5d4f2ea0e3ad..8b655db68edb 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -221,45 +221,65 @@ int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp, compat = compat_list + i; log_debug(" - attempt to match compatible string '%s'\n", compat);

•           for (entry = driver; entry != driver + n_ents; entry++) {
  

•                   ret = driver_check_compatible(entry->of_match, &id,
  

•                                                 compat);
  

•                   if ((drv) && (drv == entry))
  

•                           break;
  

•                   if (!ret)
  

•           entry = driver;
  

•           while (1) {
  

•                   for (; entry != driver + n_ents; entry++) {
  

•                           ret = driver_check_compatible(entry->of_match,
  

•                                                         &id, compat);
  

•                           if (drv && drv == entry)
  

•                                   break;
  

•                           if (!ret)
  

•                                   break;
  

•                   }
  

•                   /*
  

•                    * Reach the last entry - time to look at next
  

•                    * compatible string.
  

•                    */
  

•                   if (entry == driver + n_ents)
                            break;
  

•           }
  

•           if (entry == driver + n_ents)
  

•                   continue;
  

•           if (pre_reloc_only) {
  

•                   if (!ofnode_pre_reloc(node) &&
  

•                       !(entry->flags & DM_FLAG_PRE_RELOC)) {
  

•                           log_debug("Skipping device pre-relocation\n");
  

•                           return 0;
  

•                   if (pre_reloc_only) {
  

•                           if (!ofnode_pre_reloc(node) &&
  

•                               !(entry->flags & DM_FLAG_PRE_RELOC)) {
  

•                                   log_debug("Skipping device pre-relocation\n");
  

•                                   entry++;
  

•                                   continue;
  

•                           }
                    }
  

•           }
  
  

•           log_debug("   - found match at '%s': '%s' matches '%s'\n",
  

•                     entry->name, entry->of_match->compatible,
  

•                     id->compatible);
  

•           ret = device_bind_with_driver_data(parent, entry, name,
  

•                                              id->data, node, &dev);
  

•           if (ret == -ENODEV) {
  

•                   log_debug("Driver '%s' refuses to bind\n", entry->name);
  

•                   continue;
  

•           }
  

•           if (ret) {
  

•                   dm_warn("Error binding driver '%s': %d\n", entry->name,
  

•                           ret);
  

•                   return log_msg_ret("bind", ret);
  

•           } else {
  

•                   log_debug("   - found match at '%s': '%s' matches '%s'\n",
  

•                             entry->name, entry->of_match->compatible,
  

•                             id->compatible);
  

•                   ret = device_bind_with_driver_data(parent, entry, name,
  

•                                                      id->data, node,
  

•                                                      &dev);
  

•                   /*
  

•                    * Driver found but didn't bind properly try another one
  

•                    */
  

•                   if (ret == -ENODEV) {
  

•                           log_debug("Driver '%s' refuses to bind\n",
  

•                                     entry->name);
  

•                           entry++;
  

•                           continue;
  

•                   }
  

•                   /* Error in binding driver */
  

•                   if (ret) {
  

•                           dm_warn("Error binding driver '%s': %d\n",
  

•                                   entry->name, ret);
  

•                           return log_msg_ret("bind", ret);
  

•                   }
  

•                   /* Properly binded driver */
  

bound

...

                    found = true;
                    if (devp)
                            *devp = dev;

•                   break;
            }
  

•           break;
  

•           if (found)
  

•                   break;
    }
  
    if (!found && !result && ret != -ENODEV)
  

-- 2.33.1

The impl looks OK to me. I still feel a separate function would help readability...we don't need to worry about the parameters in general, since the compiler will inline the code and LTO is even more agressive.

But I'm OK with this as it is if you prefer it, as it isn't too horrendous.

Should we put this behind a Kconfig given the run-time penalty?

Also, please add a test.

I will take a look at adding a test. But in standard configuration PMW and TTC timers are not enabled both that's why the patch can come later.

Thanks, Michal