This patch adds support for our companies board CDU9G25 with Atmel AT91SAM9G25, 128MB DDR2, 256MB NAND.

Signed-off-by: Jiri Prchal jiri.prchal@aksignal.cz --- v2 Fixed static IP and MAC addr cofiguration by random MAC and DHCP. Added entry to MAINTAINERS. Fixed line lenght, trailing spaces and other cosmetics. v3 Removed static eth_gadget addresses. MAC address set from serial number of F-RAM. Kept CONFIG_SERVERIP as default configuration.

MAINTAINERS | 3 + board/cdu9g25/Makefile | 34 +++++++ board/cdu9g25/cdu9g25.c | 201 +++++++++++++++++++++++++++++++++++++++++ board/cdu9g25/config.mk | 1 + boards.cfg | 1 + include/configs/cdu9g25.h | 216 +++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 456 insertions(+) create mode 100644 board/cdu9g25/Makefile create mode 100644 board/cdu9g25/cdu9g25.c create mode 100644 board/cdu9g25/config.mk create mode 100644 include/configs/cdu9g25.h

diff --git a/MAINTAINERS b/MAINTAINERS index bd0f3a0..9d0008a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -851,6 +851,9 @@ Matt Porter mporter@ti.com

ti814x_evm ARM ARMV7 (TI814x Soc)

+Jiri Prchal jiri.prchal@aksignal.cz + cdu9g25 ARM926EJS (AT91SAM9G25 SoC) + Dave Purdy david.c.purdy@gmail.com

pogo_e02 ARM926EJS (Kirkwood SoC) diff --git a/board/cdu9g25/Makefile b/board/cdu9g25/Makefile new file mode 100644 index 0000000..b644a83 --- /dev/null +++ b/board/cdu9g25/Makefile @@ -0,0 +1,34 @@ +# +# U-boot - Makefile +# +# (C) Copyright 2013 +# Jiri Prchal jiri.prchal@aksignal.cz +# AK signal <www.aksignal.cz> +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += cdu9g25.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cdu9g25/cdu9g25.c b/board/cdu9g25/cdu9g25.c new file mode 100644 index 0000000..70c7647 --- /dev/null +++ b/board/cdu9g25/cdu9g25.c @@ -0,0 +1,201 @@ +/* + * (C) Copyright 2013 + * Jiri Prchal jiri.prchal@aksignal.cz + * AK signal <www.aksignal.cz> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/at91sam9x5_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_spi.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <atmel_hlcdc.h> +#include <atmel_mci.h> +#include <spi.h> +#include <net.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +static void cdu9g25_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + unsigned long csa; + + /* Enable CS3 */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[3].mode); + + writel(1 << ATMEL_ID_PIOCD, &pmc->pcer); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ + at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + debug("spi_cs_is_valid: bus=%u cs=%u\n", bus, cs); + if (bus < 2 && cs < 4) + return 1; + return 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + debug("spi_cs_activate: bus=%u cs=%u\n", slave->bus, slave->cs); + at91_set_pio_output(AT91_PIO_PORTA, 23, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + debug("spi_cs_deactivate: bus=%u cs=%u\n", slave->bus, slave->cs); + at91_set_pio_output(AT91_PIO_PORTA, 23, 1); +} + +void cdu9g25_spi0_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + + at91_set_pio_output(AT91_PIO_PORTA, 23, 1); +} + +void cdu9g25_init_enetaddr(void) +{ + struct spi_slave *slave; + uchar sernum[9]; + int ret, i; + + slave = spi_setup_slave(0, 3, 1000000, SPI_MODE_0); + if (!slave) { + debug("Failed to set up FRAM slave\n"); + goto err_spi_setup_slave; + } + + ret = spi_claim_bus(slave); + if (ret) { + debug("Failed to claim SPI bus: %d\n", ret); + goto err_spi_claim_bus; + } + + *sernum = 0xc3; /* opcode to read serial number */ + ret = spi_xfer(slave, sizeof(sernum) * 8, sernum, sernum, + SPI_XFER_BEGIN | SPI_XFER_END); + if (ret) { + debug("Failed to read serial#: %d\n", ret); + goto err_spi_xfer; + } + + memmove(sernum + 1, sernum + 3, 6); + *sernum = 0x02; + +err_spi_xfer: + spi_release_bus(slave); +err_spi_claim_bus: + spi_free_slave(slave); +err_spi_setup_slave: + if (!is_valid_ether_addr(sernum)) { + debug("Using random MAC address\n"); + eth_random_enetaddr(sernum); + } + eth_setenv_enetaddr("ethaddr", sernum); +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + cdu9g25_init_enetaddr(); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); + return rc; +} + +static void cdu9g25_led_init(void) +{ + at91_set_gpio_output(CONFIG_LED_B, 1); + at91_set_gpio_value(CONFIG_LED_B, 0); +} + +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + return 0; +} + +int board_init(void) +{ + /* arch number of AT91SAM9X5EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + cdu9g25_led_init(); + + cdu9g25_nand_hw_init(); + + cdu9g25_spi0_hw_init(); + + at91_macb_hw_init(); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +} +#endif + diff --git a/board/cdu9g25/config.mk b/board/cdu9g25/config.mk new file mode 100644 index 0000000..528ed4a --- /dev/null +++ b/board/cdu9g25/config.mk @@ -0,0 +1 @@ +CONFIG_SYS_TEXT_BASE = 0x27f00000 diff --git a/boards.cfg b/boards.cfg index be810c7..572d20d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -77,6 +77,7 @@ integratorcp_cm926ejs arm arm926ejs integrator armltd aspenite arm arm926ejs - Marvell armada100 gplugd arm arm926ejs - Marvell armada100 afeb9260 arm arm926ejs - - at91 +cdu9g25 arm arm926ejs - - at91 at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH diff --git a/include/configs/cdu9g25.h b/include/configs/cdu9g25.h new file mode 100644 index 0000000..d5eb992 --- /dev/null +++ b/include/configs/cdu9g25.h @@ -0,0 +1,216 @@ +/* + * (C) Copyright 2013 + * Jiri Prchal jiri.prchal@aksignal.cz + * AK signal <www.aksignal.cz> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +#define CONFIG_AT91SAM9X5 +#include <asm/hardware.h> + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ +#define CONFIG_SYS_HZ 1000 + +/* Define actual evaluation board type from used processor type */ +#define CONFIG_CDU9G25 +#define CONFIG_AT91FAMILY +#define CONFIG_IDENT_STRING "_cdu9g25" + +/* Misc CPU related */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +/* LEDs */ +#define CONFIG_LED_R AT91_PIN_PB18 +#define CONFIG_LED_G AT91_PIN_PB16 +#define CONFIG_LED_Y AT91_PIN_PB14 +#define CONFIG_LED_B AT91_PIN_PB12 + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_BOOT_RETRY_TIME 600 + +#define CONFIG_HW_WATCHDOG +#define CONFIG_AT91SAM9_WATCHDOG + +/* SPI */ +#define CONFIG_ATMEL_SPI +#define CONFIG_CMD_SPI + +/* RAMTRON FRAM */ +#define CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI0 /* SPI used for FRAM is SPI0 */ +#define CONFIG_SPI_FLASH /* RAMTRON FRAM on SPI bus */ +#define CONFIG_SPI_FRAM_RAMTRON + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT + +/* + * SDRAM: 1 bank, min 32, max 128 MB + * Initialized before u-boot gets started. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */ +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above + * that address while providing maximum stack area below. + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024\ + - GENERATED_GBL_DATA_SIZE) + +/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* NAND flash */ +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 + +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC 1 +#define CONFIG_ATMEL_NAND_HW_PMECC 1 +#define CONFIG_PMECC_CAP 8 +#define CONFIG_PMECC_SECTOR_SIZE 512 +#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000 + +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_NAND_TRIMFFS +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:256k(bootstrap),"\ + "768k(uboot),256k(ubootenv),"\ + "4864k(kernel),"\ + "-(root)" + +/* MMC */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#endif + +/* FAT */ +#ifdef CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY +#define CONFIG_RANDOM_MACADDR + +/* USB */ +#ifdef CONFIG_CMD_USB +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 +#else +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#endif +#define CONFIG_USB_ATMEL +#define CONFIG_USB_STORAGE +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_TEXT_BASE + +/* CONFIG_SYS_USE_NANDFLASH */ +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_SIZE 0x10000 /* 1 sector = 128kB */ +#define CONFIG_ENV_RANGE 0x20000 /* 2 sectors for bad sector handling */ +#define CONFIG_BOOTCOMMAND "nand read 21000000 kernel; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 ubi.mtd=root "\ + "root=ubi0:root rootfstype=ubifs rw" +#define CONFIG_SERVERIP 10.0.1.1 +#define CONFIG_BOOTFILE "kernel_cdu9g25" +#define CONFIG_PREBOOT "mtdparts default" /* for partitions */ + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)\ + + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + CONFIG_ENV_SIZE) + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- 1.7.9.5