From: Chuanhua Han chuanhua.han@nxp.com

Modify the Freescale ESPI driver to support the driver model. Also resolved the following problems:

===================== WARNING ====================== This board does not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ====================================================

Signed-off-by: Chuanhua Han chuanhua.han@nxp.com Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

drivers/spi/fsl_espi.c | 444 ++++++++++++++++++++-------- include/dm/platform_data/fsl_espi.h | 16 + 2 files changed, 337 insertions(+), 123 deletions(-) create mode 100644 include/dm/platform_data/fsl_espi.h

diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 50d194f614..5c76fd962e 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -3,7 +3,9 @@ * eSPI controller driver. * * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP * Author: Mingkai Hu (Mingkai.hu@freescale.com) + * Chuanhua Han (chuanhua.han@nxp.com) */

#include <common.h> @@ -14,10 +16,16 @@ #include <malloc.h> #include <spi.h> #include <asm/immap_85xx.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <dm/platform_data/fsl_espi.h>

struct fsl_spi_slave { struct spi_slave slave; ccsr_espi_t *espi; + u32 speed_hz; + unsigned int cs; unsigned int div16; unsigned int pm; int tx_timeout; @@ -31,6 +39,9 @@ struct fsl_spi_slave { #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) #define US_PER_SECOND 1000000UL

+/* default SCK frequency, unit: HZ */ +#define FSL_ESPI_DEFAULT_SCK_FREQ 10000000 + #define ESPI_MAX_CS_NUM 4 #define ESPI_FIFO_WIDTH_BIT 32

@@ -65,116 +76,27 @@ struct fsl_spi_slave {

#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0

-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct fsl_spi_slave *fsl; - sys_info_t sysinfo; - unsigned long spibrg = 0; - unsigned long spi_freq = 0; - unsigned char pm = 0; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); - if (!fsl) - return NULL; - - fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); - fsl->mode = mode; - fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; - - /* Set eSPI BRG clock source */ - get_sys_info(&sysinfo); - spibrg = sysinfo.freq_systembus / 2; - fsl->div16 = 0; - if ((spibrg / max_hz) > 32) { - fsl->div16 = ESPI_CSMODE_DIV16; - pm = spibrg / (max_hz * 16 * 2); - if (pm > 16) { - pm = 16; - debug("Requested speed is too low: %d Hz, %ld Hz " - "is used.\n", max_hz, spibrg / (32 * 16)); - } - } else - pm = spibrg / (max_hz * 2); - if (pm) - pm--; - fsl->pm = pm; - - if (fsl->div16) - spi_freq = spibrg / ((pm + 1) * 2 * 16); - else - spi_freq = spibrg / ((pm + 1) * 2); - - /* set tx_timeout to 10 times of one espi FIFO entry go out */ - fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT - * 10), spi_freq); - - return &fsl->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - free(fsl); -} - -int spi_claim_bus(struct spi_slave *slave) +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); ccsr_espi_t *espi = fsl->espi; - unsigned char pm = fsl->pm; - unsigned int cs = slave->cs; - unsigned int mode = fsl->mode; - unsigned int div16 = fsl->div16; - int i; - - debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs); - - /* Enable eSPI interface */ - out_be32(&espi->mode, ESPI_MODE_RXTHR(3) - | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); - - out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ - out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ - - /* Init CS mode interface */ - for (i = 0; i < ESPI_MAX_CS_NUM; i++) - out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); - - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & - ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 - | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK - | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); - - /* Set eSPI BRG clock source */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_PM(pm) | div16); - - /* Set eSPI mode */ - if (mode & SPI_CPHA) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CP_BEGIN_EDGCLK); - if (mode & SPI_CPOL) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CI_INACTIVEHIGH); - - /* Character bit order: msb first */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_REV_MSB_FIRST); - - /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_LEN(7)); + unsigned int com = 0; + size_t data_len = fsl->data_len;

- return 0; + com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); + com |= ESPI_COM_CS(cs); + com |= ESPI_COM_TRANLEN(data_len - 1); + out_be32(&espi->com, com); }

-void spi_release_bus(struct spi_slave *slave) +void fsl_spi_cs_deactivate(struct spi_slave *slave) { + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = fsl->espi;

+ /* clear the RXCNT and TXCNT */ + out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); + out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); }

static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) @@ -207,7 +129,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) debug("***spi_xfer:...Tx timeout! event = %08x\n", event); }

-static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, + unsigned int bytes) { ccsr_espi_t *espi = fsl->espi; unsigned int tmpdin, rx_times; @@ -239,10 +162,17 @@ static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) return bytes; }

-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, - void *data_in, unsigned long flags) +void espi_release_bus(struct fsl_spi_slave *fsl) { - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + /* Disable the SPI hardware */ + out_be32(&fsl->espi->mode, + in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN)); +} + +int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags) +{ + struct spi_slave *slave = &fsl->slave; ccsr_espi_t *espi = fsl->espi; unsigned int event, rx_bytes; const void *dout = NULL; @@ -261,13 +191,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, max_tran_len = fsl->max_transfer_length; switch (flags) { case SPI_XFER_BEGIN: - cmd_len = fsl->cmd_len = data_len; + cmd_len = data_len; + fsl->cmd_len = cmd_len; memcpy(cmd_buf, data_out, cmd_len); return 0; case 0: case SPI_XFER_END: if (bitlen == 0) { - spi_cs_deactivate(slave); + fsl_spi_cs_deactivate(slave); return 0; } buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len); @@ -307,7 +238,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); num_bytes = (tran_len + cmd_len) % 4; fsl->data_len = tran_len + cmd_len; - spi_cs_activate(slave); + fsl_spi_cs_activate(slave, cs);

/* Clear all eSPI events */ out_be32(&espi->event , 0xffffffff); @@ -350,37 +281,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, *(int *)buffer += tran_len; } } - spi_cs_deactivate(slave); + fsl_spi_cs_deactivate(slave); }

free(buffer); return 0; }

+void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs) +{ + ccsr_espi_t *espi = fsl->espi; + unsigned char pm = fsl->pm; + unsigned int mode = fsl->mode; + unsigned int div16 = fsl->div16; + int i; + + /* Enable eSPI interface */ + out_be32(&espi->mode, ESPI_MODE_RXTHR(3) + | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); + + out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ + out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ + + /* Init CS mode interface */ + for (i = 0; i < ESPI_MAX_CS_NUM; i++) + out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); + + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & + ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 + | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK + | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); + + /* Set eSPI BRG clock source */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_PM(pm) | div16); + + /* Set eSPI mode */ + if (mode & SPI_CPHA) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (mode & SPI_CPOL) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); + + /* Character bit order: msb first */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_REV_MSB_FIRST); + + /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_LEN(7)); +} + +void espi_setup_slave(struct fsl_spi_slave *fsl) +{ + unsigned int max_hz; + sys_info_t sysinfo; + unsigned long spibrg = 0; + unsigned long spi_freq = 0; + unsigned char pm = 0; + + max_hz = fsl->speed_hz; + + get_sys_info(&sysinfo); + spibrg = sysinfo.freq_systembus / 2; + fsl->div16 = 0; + if ((spibrg / max_hz) > 32) { + fsl->div16 = ESPI_CSMODE_DIV16; + pm = spibrg / (max_hz * 16 * 2); + if (pm > 16) { + pm = 16; + debug("max_hz is too low: %d Hz, %ld Hz is used.\n", + max_hz, spibrg / (32 * 16)); + } + } else { + pm = spibrg / (max_hz * 2); + } + if (pm) + pm--; + fsl->pm = pm; + + if (fsl->div16) + spi_freq = spibrg / ((pm + 1) * 2 * 16); + else + spi_freq = spibrg / ((pm + 1) * 2); + + /* set tx_timeout to 10 times of one espi FIFO entry go out */ + fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT + * 10), spi_freq);/* Set eSPI BRG clock source */ +} + +#if !CONFIG_IS_ENABLED(DM_SPI) int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus == 0 && cs < ESPI_MAX_CS_NUM; }

-void spi_cs_activate(struct spi_slave *slave) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct fsl_spi_slave *fsl; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); + if (!fsl) + return NULL; + + fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + fsl->mode = mode; + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + fsl->speed_hz = max_hz; + + espi_setup_slave(fsl); + + return &fsl->slave; +} + +void spi_free_slave(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - unsigned int com = 0; - size_t data_len = fsl->data_len;

- com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); - com |= ESPI_COM_CS(slave->cs); - com |= ESPI_COM_TRANLEN(data_len - 1); - out_be32(&espi->com, com); + free(fsl); }

-void spi_cs_deactivate(struct spi_slave *slave) +int spi_claim_bus(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi;

- /* clear the RXCNT and TXCNT */ - out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); - out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); + espi_claim_bus(fsl, slave->cs); + + return 0; } + +void spi_release_bus(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + + espi_release_bus(fsl); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave; + + return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags); +} +#else +static void __espi_set_speed(struct fsl_spi_slave *fsl) +{ + espi_setup_slave(fsl); + + /* Set eSPI BRG clock source */ + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_PM(fsl->pm) | fsl->div16); +} + +static void __espi_set_mode(struct fsl_spi_slave *fsl) +{ + /* Set eSPI mode */ + if (fsl->mode & SPI_CPHA) + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (fsl->mode & SPI_CPOL) + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); +} + +static int fsl_espi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + espi_claim_bus(fsl, fsl->cs); + + return 0; +} + +static int fsl_espi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + espi_release_bus(fsl); + + return 0; +} + +static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags); +} + +static int fsl_espi_set_speed(struct udevice *bus, uint speed) +{ + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s speed %u\n", __func__, speed); + fsl->speed_hz = speed; + + __espi_set_speed(fsl); + + return 0; +} + +static int fsl_espi_set_mode(struct udevice *bus, uint mode) +{ + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s mode %u\n", __func__, mode); + fsl->mode = mode; + + __espi_set_mode(fsl); + + return 0; +} + +static int fsl_espi_child_pre_probe(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s cs %u\n", __func__, slave_plat->cs); + fsl->cs = slave_plat->cs; + + return 0; +} + +static int fsl_espi_probe(struct udevice *bus) +{ + struct fsl_espi_platdata *plat = dev_get_platdata(bus); + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr); + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + fsl->speed_hz = plat->speed_hz; + + debug("%s probe done, bus-num %d.\n", bus->name, bus->seq); + + return 0; +} + +static const struct dm_spi_ops fsl_espi_ops = { + .claim_bus = fsl_espi_claim_bus, + .release_bus = fsl_espi_release_bus, + .xfer = fsl_espi_xfer, + .set_speed = fsl_espi_set_speed, + .set_mode = fsl_espi_set_mode, +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int fsl_espi_ofdata_to_platdata(struct udevice *bus) +{ + fdt_addr_t addr; + struct fsl_espi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = dev_of_offset(bus); + + addr = dev_read_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->regs_addr = lower_32_bits(addr); + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + FSL_ESPI_DEFAULT_SCK_FREQ); + + debug("ESPI: regs=%p, max-frequency=%d\n", + &plat->regs_addr, plat->speed_hz); + + return 0; +} + +static const struct udevice_id fsl_espi_ids[] = { + { .compatible = "fsl,mpc8536-espi" }, + { } +}; +#endif + +U_BOOT_DRIVER(fsl_espi) = { + .name = "fsl_espi", + .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .of_match = fsl_espi_ids, + .ofdata_to_platdata = fsl_espi_ofdata_to_platdata, +#endif + .ops = &fsl_espi_ops, + .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata), + .priv_auto_alloc_size = sizeof(struct fsl_spi_slave), + .probe = fsl_espi_probe, + .child_pre_probe = fsl_espi_child_pre_probe, +}; +#endif diff --git a/include/dm/platform_data/fsl_espi.h b/include/dm/platform_data/fsl_espi.h new file mode 100644 index 0000000000..812933f51c --- /dev/null +++ b/include/dm/platform_data/fsl_espi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __fsl_espi_h +#define __fsl_espi_h + +struct fsl_espi_platdata { + uint flags; + uint speed_hz; + uint num_chipselect; + fdt_addr_t regs_addr; +}; + +#endif /* __fsl_espi_h */

From: Chuanhua Han chuanhua.han@nxp.com

Add espi slave nodes to support t2080qds.

Signed-off-by: Chuanhua Han chuanhua.han@nxp.com Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

arch/powerpc/dts/t2080qds.dts | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)

diff --git a/arch/powerpc/dts/t2080qds.dts b/arch/powerpc/dts/t2080qds.dts index 1819a081dd..f9e786b239 100644 --- a/arch/powerpc/dts/t2080qds.dts +++ b/arch/powerpc/dts/t2080qds.dts @@ -14,4 +14,37 @@ #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; + + aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + + status = "okay"; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */ + reg = <0>; + spi-max-frequency = <10000000>; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25wf040", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <10000000>; + }; + + flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "eon,en25s64", "jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <10000000>; + }; + };

From: Xiaowei Bao xiaowei.bao@nxp.com

Add ESPI controller DT node for P1020.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

arch/powerpc/dts/p1020-post.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1dce8e86e9..65b844e5d0 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -44,6 +44,15 @@ clock-frequency = <0>; };

+ espi0: spi@7000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" };

From: Xiaowei Bao xiaowei.bao@nxp.com

Enable the DM ESPI driver in P1020RDB defconfig.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_defconfig | 2 ++ configs/P1020RDB-PC_NAND_defconfig | 2 ++ configs/P1020RDB-PC_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_defconfig | 2 ++ configs/P1020RDB-PD_NAND_defconfig | 2 ++ configs/P1020RDB-PD_SDCARD_defconfig | 2 ++ configs/P1020RDB-PD_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PD_defconfig | 2 ++ 12 files changed, 24 insertions(+)

diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 6ee52fe5e7..5ee48fd2ac 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -48,6 +48,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 489b91d8e7..e89e287f25 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -44,6 +44,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 4a8e4e3726..ba147e7d66 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -46,6 +46,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index f9a4b735ca..0b34b615ed 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -33,6 +33,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 5c8231cba2..e0f7ccdce2 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -47,6 +47,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index ad2bb90a49..412077866d 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -43,6 +43,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index b8055e49b0..3f27bcdfe5 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -45,6 +45,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index a71985374e..e865776f54 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -32,6 +32,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 0043fd5f66..d06709df65 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -50,6 +50,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index cb0a8aec65..98d1533248 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -46,6 +46,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 35e60ca856..25ef996407 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -48,6 +48,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index d7f19c3d96..c7208fc620 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -35,6 +35,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y

From: Xiaowei Bao xiaowei.bao@nxp.com

Add ESPI slave node for P2020RDB.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

arch/powerpc/dts/p2020rdb-pc.dts | 15 +++++++++++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 15 +++++++++++++++ 2 files changed, 30 insertions(+)

diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index 08befd4c59..5ae278cbfc 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -35,6 +35,21 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ }; + + aliases { + spi0 = &espi0; + }; };

/include/ "p2020-post.dtsi" + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index 04b2519e1a..542fffc33e 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -35,6 +35,21 @@ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ }; + + aliases { + spi0 = &espi0; + }; };

/include/ "p2020-post.dtsi" + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; +};

From: Xiaowei Bao xiaowei.bao@nxp.com

Add ESPI controller DT node for P2041.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

arch/powerpc/dts/p2041.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi index 95931e299d..8abc4a5ea9 100644 --- a/arch/powerpc/dts/p2041.dtsi +++ b/arch/powerpc/dts/p2041.dtsi @@ -40,6 +40,15 @@ reg = <3>; fsl,portid-mapping = <0x10000000>; }; + + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; };

soc: soc@ffe000000 {

From: Xiaowei Bao xiaowei.bao@nxp.com

Enable the DM ESPI driver in P2041RDB defconfig.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

configs/P2041RDB_NAND_defconfig | 2 ++ configs/P2041RDB_SDCARD_defconfig | 2 ++ configs/P2041RDB_SPIFLASH_defconfig | 2 ++ configs/P2041RDB_defconfig | 2 ++ 4 files changed, 8 insertions(+)

diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 13b20dd1c6..24c8012f6f 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -31,6 +31,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index d99c15342d..c62583360a 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -31,6 +31,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 78a2a97064..8d27dee5ca 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -32,6 +32,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 0b9625e91e..bc9f04536e 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -30,6 +30,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y

From: Xiaowei Bao xiaowei.bao@nxp.com

Add ESPI slave node for P3041DS.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

arch/powerpc/dts/p3041ds.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)

diff --git a/arch/powerpc/dts/p3041ds.dts b/arch/powerpc/dts/p3041ds.dts index c30bf7ac77..5d1bac2eed 100644 --- a/arch/powerpc/dts/p3041ds.dts +++ b/arch/powerpc/dts/p3041ds.dts @@ -15,4 +15,18 @@ #size-cells = <2>; interrupt-parent = <&mpic>;

+ aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; };

From: Xiaowei Bao xiaowei.bao@nxp.com

Add ESPI controller DT node for P4080.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

arch/powerpc/dts/p4080.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi index 4a80561e18..9d7d685229 100644 --- a/arch/powerpc/dts/p4080.dtsi +++ b/arch/powerpc/dts/p4080.dtsi @@ -60,6 +60,15 @@ reg = <7>; fsl,portid-mapping = <0x01000000>; }; + + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; };

soc: soc@ffe000000 {

From: Xiaowei Bao xiaowei.bao@nxp.com

Enable the DM ESPI driver in P4080DS defconfig.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

configs/P4080DS_SDCARD_defconfig | 2 ++ configs/P4080DS_SPIFLASH_defconfig | 2 ++ configs/P4080DS_defconfig | 2 ++ 3 files changed, 6 insertions(+)

diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 18ad56ac8d..db23cfa41e 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -31,6 +31,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index 81a513bec9..15510413eb 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -32,6 +32,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index 52db2e06c7..4ffeeb7660 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -30,6 +30,8 @@ CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y

From: Xiaowei Bao xiaowei.bao@nxp.com

Add ESPI slave node for P5040DS.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

arch/powerpc/dts/p5040ds.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)

diff --git a/arch/powerpc/dts/p5040ds.dts b/arch/powerpc/dts/p5040ds.dts index 723d31d5fb..0e1308a2ec 100644 --- a/arch/powerpc/dts/p5040ds.dts +++ b/arch/powerpc/dts/p5040ds.dts @@ -15,4 +15,18 @@ #size-cells = <2>; interrupt-parent = <&mpic>;

+ aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; };

From: Xiaowei Bao xiaowei.bao@nxp.com

Add ESPI controller DT node for T102x.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

arch/powerpc/dts/t102x.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi index 521825d85a..d5af5ca50a 100644 --- a/arch/powerpc/dts/t102x.dtsi +++ b/arch/powerpc/dts/t102x.dtsi @@ -29,6 +29,15 @@ reg = <1>; #cooling-cells = <2>; }; + + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; };

soc: soc@ffe000000 {

From: Xiaowei Bao xiaowei.bao@nxp.com

Enable the DM ESPI driver in T1024RDB defconfig.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

configs/T1024RDB_NAND_defconfig | 2 ++ configs/T1024RDB_SDCARD_defconfig | 2 ++ configs/T1024RDB_SPIFLASH_defconfig | 2 ++ configs/T1024RDB_defconfig | 2 ++ 4 files changed, 8 insertions(+)

diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 9b116548a7..8e247cb74d 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -52,6 +52,8 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DM_I2C=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 5e087fe2f3..a53fa3f03f 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -50,6 +50,8 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DM_I2C=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 39b4537e71..8b5188637d 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -53,6 +53,8 @@ CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0xFFFC9000 CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DM_I2C=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 8ff2fe3f0c..fcf9adc03f 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -38,6 +38,8 @@ CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DM_I2C=y

From: Xiaowei Bao xiaowei.bao@nxp.com

Add ESPI slave node for T1042D4RDB.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

arch/powerpc/dts/t1042d4rdb.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+)

diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts index 16a8ed4c79..3584c06aa8 100644 --- a/arch/powerpc/dts/t1042d4rdb.dts +++ b/arch/powerpc/dts/t1042d4rdb.dts @@ -14,4 +14,19 @@ #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; + + aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; };

From: Xiaowei Bao xiaowei.bao@nxp.com

Add ESPI slave node for T2080RDB.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

arch/powerpc/dts/t2080rdb.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+)

diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts index 49c1765b29..34ec6a74cb 100644 --- a/arch/powerpc/dts/t2080rdb.dts +++ b/arch/powerpc/dts/t2080rdb.dts @@ -14,4 +14,19 @@ #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; + + aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; /* 16MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; };

From: Xiaowei Bao xiaowei.bao@nxp.com

Add ESPI controller DT node for T4240.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

arch/powerpc/dts/t4240.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi index 9b5902fe9e..227e758988 100644 --- a/arch/powerpc/dts/t4240.dtsi +++ b/arch/powerpc/dts/t4240.dtsi @@ -79,6 +79,15 @@ reg = <22 23>; fsl,portid-mapping = <0x80000000>; }; + + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; };

soc: soc@ffe000000 {

From: Xiaowei Bao xiaowei.bao@nxp.com

Enable the DM ESPI driver in T4240RDB defconfig.

Signed-off-by: Xiaowei Bao xiaowei.bao@nxp.com Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Rebase the patch, no change intended.

configs/T4240RDB_SDCARD_defconfig | 2 ++ configs/T4240RDB_defconfig | 2 ++ 2 files changed, 4 insertions(+)

diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 14e366358b..a0238599f3 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -41,6 +41,8 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index dfe8953af7..95388a8cbf 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -29,6 +29,8 @@ CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y

From: Hou Zhiqiang Zhiqiang.Hou@nxp.com

Add DT nodes for eSPI slave device SPI flash.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - New patch to add support for P1010RDB.

arch/powerpc/dts/p1010rdb-pa.dts | 1 + arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 + arch/powerpc/dts/p1010rdb.dtsi | 17 +++++++++++++++++ 3 files changed, 19 insertions(+)

diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts index c66c4923ac..360d254d91 100644 --- a/arch/powerpc/dts/p1010rdb-pa.dts +++ b/arch/powerpc/dts/p1010rdb-pa.dts @@ -15,3 +15,4 @@ };

/include/ "p1010si-post.dtsi" +/include/ "p1010rdb.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts index b943de7cbb..062086a8c0 100644 --- a/arch/powerpc/dts/p1010rdb-pa_36b.dts +++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts @@ -15,3 +15,4 @@ };

/include/ "p1010si-post.dtsi" +/include/ "p1010rdb.dtsi" diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi index 4f58ee2446..20bd570299 100644 --- a/arch/powerpc/dts/p1010rdb.dtsi +++ b/arch/powerpc/dts/p1010rdb.dtsi @@ -4,6 +4,12 @@ * * Copyright 2020 NXP */ +/ { + aliases { + spi0 = &espi0; + }; +}; + &soc { i2c@3000 { rtc@68 { @@ -11,4 +17,15 @@ reg = <0x68>; }; }; + + spi@7000 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; + }; };