Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes it difficult to use (b/c then the memory is discontinuous and there is quite big memory hole between the DDR/SDRAM regions).

This patch reworks LBC SDRAM setup so that now we dynamically place the LBC SDRAM near the DDR (or at 0x0 if there isn't any DDR memory).

With this patch we're able to:

- Boot without external DDR memory; - Use most "DDR + SDRAM" setups without need to support for sparse/discontinuous memory model in the software.

Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8360emds/mpc8360emds.c | 39 ++++++++++++++++++++--------- include/configs/MPC8360EMDS.h | 25 ++++++++---------- 2 files changed, 38 insertions(+), 26 deletions(-)

diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 5c3b5db..afeb891 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -120,7 +120,7 @@ int board_early_init_r(void) extern void ddr_enable_ecc(unsigned int dram_size); #endif int fixed_sdram(void); -void sdram_init(void); +static int sdram_init(unsigned int base);

phys_size_t initdram(int board_type) { @@ -147,7 +147,7 @@ phys_size_t initdram(int board_type) /* * Initialize SDRAM if it is on local bus. */ - sdram_init(); + msize += sdram_init(msize * 1024 * 1024);

/* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); @@ -219,23 +219,32 @@ int checkboard(void) /* * if MPC8360EMDS is soldered with SDRAM */ -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) +#ifdef CFG_LB_SDRAM /* * Initialize SDRAM memory on the Local Bus. */

-void sdram_init(void) +static int sdram_init(unsigned int base) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile lbus83xx_t *lbc = &immap->lbus; - uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; + const int sdram_size = CFG_LBC_SDRAM_SIZE * 1024 * 1024; + int rem = base % sdram_size; + uint *sdram_addr;

+ /* window base address should be aligned to the window size */ + if (rem) + base = base - rem + sdram_size; + + sdram_addr = (uint *)base; /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c + * Setup SDRAM Base and Option Registers */ + immap->lbus.bank[2].br = base | CFG_BR2; + immap->lbus.bank[2].or = CFG_OR2; + immap->sysconf.lblaw[2].bar = base; + immap->sysconf.lblaw[2].ar = CFG_LBLAWAR2; + /*setup mtrpt, lsrt and lbcr for LB bus */ lbc->lbcr = CFG_LBC_LBCR; lbc->mrtpr = CFG_LBC_MRTPR; @@ -284,11 +293,17 @@ void sdram_init(void) asm("sync"); *sdram_addr = 0xff; udelay(100); + + /* + * In non-aligned case we don't [normally] use that memory because + * there is a hole. + */ + if (rem) + return 0; + return CFG_LBC_SDRAM_SIZE; } #else -void sdram_init(void) -{ -} +static int sdram_init(unsigned int base) { return 0; } #endif

#if defined(CONFIG_OF_BOARD_SETUP) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 43d4118..ae3d555 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -100,6 +100,7 @@ */ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ #define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_SDRAM_BASE2 (CFG_SDRAM_BASE + 0x10000000) /* + 256M */ #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) @@ -230,29 +231,25 @@ #define CFG_LB_SDRAM /* if board has SRDAM on local bus */

#ifdef CFG_LB_SDRAM -#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE -#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ +#define CFG_LBLAWBAR2 0 +#define CFG_LBLAWAR2 0x80000019 /* 64MB */

/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ /* * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. * * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * Base address = BR[0:16] = dynamic * port size = 32-bits = BR2[19:20] = 11 * no parity checking = BR2[21:22] = 00 * SDRAM for MSEL = BR2[24:26] = 011 * Valid = BR[31] = 1 * * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * the top 17 bits of BR2. + * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861 */

-#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ +#define CFG_BR2 0x00001861 /*Port size=32bit, MSEL=SDRAM */

/* * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. @@ -268,7 +265,7 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */

-#define CFG_OR2_PRELIM 0xfc006901 +#define CFG_OR2 0xfc006901

#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ @@ -517,7 +514,7 @@

#define CONFIG_HIGH_BATS 1 /* High BATs supported */

-/* DDR: cache cacheable */ +/* DDR/LBC SDRAM: cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_DBAT0L CFG_IBAT0L @@ -544,9 +541,9 @@ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT3U CFG_IBAT3U

-/* Local bus SDRAM: cacheable */ -#define CFG_IBAT4L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT4U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) +/* DDR/LBC SDRAM next 256M: cacheable */ +#define CFG_IBAT4L (CFG_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT4U (CFG_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_DBAT4L CFG_IBAT4L #define CFG_DBAT4U CFG_IBAT4U