[U-Boot] [PATCH 1/8] arm: am437x: PLL values for all input frequencies
From: James Doublesin doublesin@ti.com
Need to provide PLL values for all possible input frequencies (19.2, 24, 25, 26MHz). Values provide are also optimized for jitter (needed especially for PER PLL and DDR PLL).
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Felipe Balbi balbi@ti.com --- board/ti/am43xx/board.c | 59 +++++++++++++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 26 deletions(-)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index a1c3c17..8695fc1 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -81,12 +81,12 @@ static int read_eeprom(struct am43xx_board_id *header)
const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { { /* 19.2 MHz */ - {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */ + {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ - {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */ - {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */ - {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */ - {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */ + {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ + {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ + {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ + {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ }, { /* 24 MHz */ {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ @@ -115,24 +115,28 @@ const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { };
const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { - {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ };
const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { - {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */ - {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */ - {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */ + {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ + {32, 0, 8, -1, -1, -1, -1}, /* 25 MHz */ + {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ };
-const struct dpll_params epos_evm_dpll_ddr = { - 266, 24, 1, -1, 1, -1, -1}; +const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { + {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ + {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ + {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ + {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ +};
const struct dpll_params gp_evm_dpll_ddr = { - 400, 23, 1, -1, 1, -1, -1}; + 50, 2, 1, -1, 2, -1, -1};
const struct ctrl_ioregs ioregs_lpddr2 = { .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, @@ -157,7 +161,7 @@ const struct emif_regs emif_regs_lpddr2 = { .emif_rd_wr_lvl_rmp_win = 0x0, .emif_rd_wr_lvl_rmp_ctl = 0x0, .emif_rd_wr_lvl_ctl = 0x0, - .emif_ddr_phy_ctlr_1 = 0x0E084006, + .emif_ddr_phy_ctlr_1 = 0x0E284006, .emif_rd_wr_exec_thresh = 0x80000405, .emif_ddr_ext_phy_ctrl_1 = 0x04010040, .emif_ddr_ext_phy_ctrl_2 = 0x00500050, @@ -201,7 +205,7 @@ const struct ctrl_ioregs ioregs_ddr3 = { .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, - .emif_sdram_config_ext = 0x0143, + .emif_sdram_config_ext = 0xc163, };
const struct emif_regs ddr3_emif_regs_400Mhz = { @@ -434,17 +438,6 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) return; }
-const struct dpll_params *get_dpll_ddr_params(void) -{ - if (board_is_eposevm()) - return &epos_evm_dpll_ddr; - else if (board_is_gpevm() || board_is_sk()) - return &gp_evm_dpll_ddr; - - printf(" Board '%s' not supported\n", am43xx_board_name); - return NULL; -} - /* * get_sys_clk_index : returns the index of the sys_clk read from * ctrl status register. This value is either @@ -464,6 +457,20 @@ static u32 get_sys_clk_index(void) CTRL_SYSBOOT_15_14_SHIFT); }
+const struct dpll_params *get_dpll_ddr_params(void) +{ + int ind = get_sys_clk_index(); + + if (board_is_eposevm()) + return &epos_evm_dpll_ddr[ind]; + else if (board_is_gpevm() || board_is_sk()) + return &gp_evm_dpll_ddr; + + printf(" Board '%s' not supported\n", am43xx_board_name); + return NULL; +} + + /* * get_opp_offset: * Returns the index for safest OPP of the device to boot.
From: James Doublesin doublesin@ti.com
Switch to using hardware leveling for certain parameters on the EMIF rather than using precalculated values. Doing this also means we have a common place now between am437x and am335x for setting emif_sdram_ref_ctrl with a value for the correct delay length.
Tested-by: Felipe Balbi balbi@ti.com Tested-by: Tom Rini trini@ti.com Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Felipe Balbi balbi@ti.com --- arch/arm/cpu/armv7/am33xx/ddr.c | 134 ++++++++++++------ arch/arm/cpu/armv7/am33xx/emif4.c | 5 +- arch/arm/include/asm/arch-am33xx/cpu.h | 11 ++ arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 1 + arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 1 + arch/arm/include/asm/emif.h | 37 ++++- board/ti/am43xx/board.c | 156 --------------------- 7 files changed, 138 insertions(+), 207 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index fc66872..85cceae 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -76,13 +76,13 @@ static void configure_mr(int nr, u32 cs) }
/* - * Configure EMIF4D5 registers and MR registers + * Configure EMIF4D5 registers and MR registers For details about these magic + * values please see the EMIF registers section of the TRM. */ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) { writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); - writel(0x1, &emif_reg[nr]->emif_iodft_tlgc); writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config); @@ -106,10 +106,45 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config); }
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); - writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); + /* + * Sequence to ensure that the PHY is in a known state prior to + * startting hardware leveling. Also acts as to latch some state from + * the EMIF into the PHY. + */ + writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); + writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc); + writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); + + clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, + EMIF_REG_INITREF_DIS_MASK); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); + + /* Perform hardware leveling. */ + udelay(1000); + writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) | + 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); + writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) | + 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); + + writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); + + /* Enable read leveling */ + writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl); + + /* + * Enable full read and write leveling. Wait for read and write + * leveling bit to clear RDWRLVLFULL_START bit 31 + */ + while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0) + ; + + /* Check the timeout register to see if leveling is complete */ + if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0) + puts("DDR3 H/W leveling incomplete with errors\n");
if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) { configure_mr(nr, 0); @@ -123,21 +158,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) void config_sdram(const struct emif_regs *regs, int nr) { if (regs->zq_config) { - /* - * A value of 0x2800 for the REF CTRL will give us - * about 570us for a delay, which will be long enough - * to configure things. - */ - writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); } + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); }
/** @@ -153,46 +182,55 @@ void set_sdram_timings(const struct emif_regs *regs, int nr) writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw); }
-void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) -{ -} - /* - * Configure EXT PHY registers + * Configure EXT PHY registers for hardware leveling */ static void ext_phy_settings(const struct emif_regs *regs, int nr) { - u32 *ext_phy_ctrl_base = 0; - u32 *emif_ext_phy_ctrl_base = 0; - const u32 *ext_phy_ctrl_const_regs; - u32 i = 0; - u32 size; - - ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1); - emif_ext_phy_ctrl_base = - (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); - - /* Configure external phy control timing registers */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { - writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); - } - /* - * external phy 6-24 registers do not change with - * ddr frequency + * Enable hardware leveling on the EMIF. For details about these + * magic values please see the EMIF registers section of the TRM. */ - emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size); - - if (!size) - return; + writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw); + writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23); + writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw); + writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24); + writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw); + writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25); + writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30); + writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35); + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw); + writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); + writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
- for (i = 0; i < size; i++) { - writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); - } + /* + * Sequence to ensure that the PHY is again in a known state after + * hardware leveling. + */ + writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); + writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc); + writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); }
/** @@ -201,11 +239,17 @@ static void ext_phy_settings(const struct emif_regs *regs, int nr) void config_ddr_phy(const struct emif_regs *regs, int nr) { /* - * disable initialization and refreshes for now until we + * Disable initialization and refreshes for now until we * finish programming EMIF regs. + * Also set time between rising edge of DDR_RESET to rising + * edge of DDR_CKE to > 500us per memory spec. */ +#ifndef CONFIG_AM43XX setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); +#endif + if (regs->zq_config) + writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 8b7527c..9cf816c 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -112,17 +112,20 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
/* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); + #endif #ifdef CONFIG_AM43XX writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0) ; - writel(0x80000000, &ddrctrl->ddrioctrl);
config_io_ctrl(ioregs);
/* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); + + /* Allow EMIF to control DDR_RESET */ + writel(0x00000000, &ddrctrl->ddrioctrl); #endif
/* Program EMIF instance */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 8dd69b3..b94b56c 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -219,6 +219,12 @@ struct cm_dpll { unsigned int resv4[2]; unsigned int clklcdcpixelclk; /* offset 0x34 */ }; + +struct prm_device_inst { + unsigned int prm_rstctrl; + unsigned int prm_rsttime; + unsigned int prm_rstst; +}; #else /* Encapsulating core pll registers */ struct cm_wkuppll { @@ -386,6 +392,11 @@ struct cm_device_inst { unsigned int cm_dll_ctrl; };
+struct prm_device_inst { + unsigned int prm_rstctrl; + unsigned int prm_rstst; +}; + struct cm_dpll { unsigned int resv1; unsigned int clktimer2clk; /* offset 0x04 */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index c67a080..d1aed58 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -39,6 +39,7 @@ /* VTP Base address */ #define VTP0_CTRL_ADDR 0x44E10E0C #define VTP1_CTRL_ADDR 0x48140E10 +#define PRM_DEVICE_INST 0x44E00F00
/* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x44E12000 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index efdecf4..29e3816 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -71,6 +71,7 @@ #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) #define USBPHYOCPSCP_MODULE_EN (1 << 1) #define CM_DEVICE_INST 0x44df4100 +#define PRM_DEVICE_INST 0x44df4000
/* Control status register */ #define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 2fe5776..342f045 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -650,8 +650,8 @@ struct emif_reg_struct { u32 emif_rd_wr_exec_thresh; u32 emif_cos_config; u32 padding9[6]; - u32 emif_ddr_phy_status[21]; - u32 padding10[27]; + u32 emif_ddr_phy_status[28]; + u32 padding10[20]; u32 emif_ddr_ext_phy_ctrl_1; u32 emif_ddr_ext_phy_ctrl_1_shdw; u32 emif_ddr_ext_phy_ctrl_2; @@ -700,9 +700,36 @@ struct emif_reg_struct { u32 emif_ddr_ext_phy_ctrl_23_shdw; u32 emif_ddr_ext_phy_ctrl_24; u32 emif_ddr_ext_phy_ctrl_24_shdw; - u32 padding[22]; - u32 emif_ddr_fifo_misaligned_clear_1; - u32 emif_ddr_fifo_misaligned_clear_2; + u32 emif_ddr_ext_phy_ctrl_25; + u32 emif_ddr_ext_phy_ctrl_25_shdw; + u32 emif_ddr_ext_phy_ctrl_26; + u32 emif_ddr_ext_phy_ctrl_26_shdw; + u32 emif_ddr_ext_phy_ctrl_27; + u32 emif_ddr_ext_phy_ctrl_27_shdw; + u32 emif_ddr_ext_phy_ctrl_28; + u32 emif_ddr_ext_phy_ctrl_28_shdw; + u32 emif_ddr_ext_phy_ctrl_29; + u32 emif_ddr_ext_phy_ctrl_29_shdw; + u32 emif_ddr_ext_phy_ctrl_30; + u32 emif_ddr_ext_phy_ctrl_30_shdw; + u32 emif_ddr_ext_phy_ctrl_31; + u32 emif_ddr_ext_phy_ctrl_31_shdw; + u32 emif_ddr_ext_phy_ctrl_32; + u32 emif_ddr_ext_phy_ctrl_32_shdw; + u32 emif_ddr_ext_phy_ctrl_33; + u32 emif_ddr_ext_phy_ctrl_33_shdw; + u32 emif_ddr_ext_phy_ctrl_34; + u32 emif_ddr_ext_phy_ctrl_34_shdw; + u32 emif_ddr_ext_phy_ctrl_35; + u32 emif_ddr_ext_phy_ctrl_35_shdw; + union { + u32 emif_ddr_ext_phy_ctrl_36; + u32 emif_ddr_fifo_misaligned_clear_1; + }; + union { + u32 emif_ddr_ext_phy_ctrl_36_shdw; + u32 emif_ddr_fifo_misaligned_clear_2; + }; };
struct dmm_lisa_map_regs { diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 8695fc1..d851f83 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -174,29 +174,6 @@ const struct emif_regs emif_regs_lpddr2 = { .emif_cos_config = 0x000FFFFF };
-const u32 ext_phy_ctrl_const_base_lpddr2[] = { - 0x00500050, - 0x00350035, - 0x00350035, - 0x00350035, - 0x00350035, - 0x00350035, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x40001000, - 0x08102040 -}; - const struct ctrl_ioregs ioregs_ddr3 = { .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, @@ -305,139 +282,6 @@ static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { .emif_cos_config = 0x000FFFFF };
-const u32 ext_phy_ctrl_const_base_ddr3[] = { - 0x00400040, - 0x00350035, - 0x00350035, - 0x00350035, - 0x00350035, - 0x00350035, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00340034, - 0x00340034, - 0x00340034, - 0x00340034, - 0x00340034, - 0x0, - 0x0, - 0x40000000, - 0x08102040 -}; - -const u32 ext_phy_ctrl_const_base_ddr3_beta[] = { - 0x00000000, - 0x00000045, - 0x00000046, - 0x00000048, - 0x00000047, - 0x00000000, - 0x0000004C, - 0x00000070, - 0x00000085, - 0x000000A3, - 0x00000000, - 0x0000000C, - 0x00000030, - 0x00000045, - 0x00000063, - 0x00000000, - 0x0, - 0x0, - 0x40000000, - 0x08102040 -}; - -const u32 ext_phy_ctrl_const_base_ddr3_production[] = { - 0x00000000, - 0x00000044, - 0x00000044, - 0x00000046, - 0x00000046, - 0x00000000, - 0x00000059, - 0x00000077, - 0x00000093, - 0x000000A8, - 0x00000000, - 0x00000019, - 0x00000037, - 0x00000053, - 0x00000068, - 0x00000000, - 0x0, - 0x0, - 0x40000000, - 0x08102040 -}; - -static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = { - /* first 5 are taken care by emif_regs */ - 0x00700070, - - 0x00350035, - 0x00350035, - 0x00350035, - 0x00350035, - 0x00350035, - - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - - 0x00150015, - 0x00150015, - 0x00150015, - 0x00150015, - 0x00150015, - - 0x00800080, - 0x00800080, - - 0x40000000, - - 0x08102040, - - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) -{ - if (board_is_eposevm()) { - *regs = ext_phy_ctrl_const_base_lpddr2; - *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); - } else if (board_is_evm_14_or_later()) { - *regs = ext_phy_ctrl_const_base_ddr3_production; - *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production); - } else if (board_is_evm_12_or_later()) { - *regs = ext_phy_ctrl_const_base_ddr3_beta; - *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta); - } else if (board_is_gpevm()) { - *regs = ext_phy_ctrl_const_base_ddr3; - *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); - } else if (board_is_sk()) { - *regs = ext_phy_ctrl_const_base_ddr3_sk; - *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk); - } - - return; -} - /* * get_sys_clk_index : returns the index of the sys_clk read from * ctrl status register. This value is either
On Mon, Dec 22, 2014 at 04:26:11PM -0600, Felipe Balbi wrote:
From: James Doublesin doublesin@ti.com
Switch to using hardware leveling for certain parameters on the EMIF rather than using precalculated values. Doing this also means we have a common place now between am437x and am335x for setting emif_sdram_ref_ctrl with a value for the correct delay length.
Tested-by: Felipe Balbi balbi@ti.com Tested-by: Tom Rini trini@ti.com Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Felipe Balbi balbi@ti.com
Applied to u-boot-ti/master, thanks!
From: James Doublesin doublesin@ti.com
The frequencies for 25MHz in dpll_per were out of spec for 25MHz, correct.
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Felipe Balbi balbi@ti.com --- board/ti/am43xx/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index d851f83..9874773 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -124,7 +124,7 @@ const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ - {32, 0, 8, -1, -1, -1, -1}, /* 25 MHz */ + {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ };
On Mon, Dec 22, 2014 at 04:26:12PM -0600, Felipe Balbi wrote:
From: James Doublesin doublesin@ti.com
The frequencies for 25MHz in dpll_per were out of spec for 25MHz, correct.
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Felipe Balbi balbi@ti.com
Applied to u-boot-ti/master, thanks!
A switch statement fits better in this case, specially considering we have a few extra frequencies to use.
Signed-off-by: Felipe Balbi balbi@ti.com --- board/ti/am43xx/board.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 9874773..c418e68 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -381,11 +381,14 @@ void scale_vcores(void) if (i2c_probe(TPS65218_CHIP_PM)) return;
- if (mpu_params->m == 1000) { + switch (mpu_params->m) { + case 1000: mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; - } else if (mpu_params->m == 600) { + break; + case 600: mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; - } else { + break; + default: puts("Unknown MPU clock, not scaling\n"); return; }
On Mon, Dec 22, 2014 at 04:26:13PM -0600, Felipe Balbi wrote:
A switch statement fits better in this case, specially considering we have a few extra frequencies to use.
Signed-off-by: Felipe Balbi balbi@ti.com
Applied to u-boot-ti/master, thanks!
DCDC1 is used as VDD_MPU in all known boards, let's define all other valid voltages for that rail so it can be used by our boards.
Signed-off-by: Felipe Balbi balbi@ti.com --- include/power/tps65218.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/power/tps65218.h b/include/power/tps65218.h index f8f33b8..63fc7b3 100644 --- a/include/power/tps65218.h +++ b/include/power/tps65218.h @@ -54,7 +54,10 @@ enum {
#define TPS65218_MASK_ALL_BITS 0xFF
+#define TPS65218_DCDC_VOLT_SEL_0950MV 0x0a #define TPS65218_DCDC_VOLT_SEL_1100MV 0x19 +#define TPS65218_DCDC_VOLT_SEL_1200MV 0x23 +#define TPS65218_DCDC_VOLT_SEL_1260MV 0x29 #define TPS65218_DCDC_VOLT_SEL_1330MV 0x30
int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
On Mon, Dec 22, 2014 at 04:26:14PM -0600, Felipe Balbi wrote:
DCDC1 is used as VDD_MPU in all known boards, let's define all other valid voltages for that rail so it can be used by our boards.
Signed-off-by: Felipe Balbi balbi@ti.com
Applied to u-boot-ti/master, thanks!
Make sure that all OPPs are checked on scale_vcores(). While at that also fix 600MHz VDD_MPU voltage according to AM437x Data Manual available at [1].
Table 5-3 on that document, lists all valid voltages per frequency.
[1] http://www.ti.com/lit/ds/symlink/am4379.pdf
Signed-off-by: Felipe Balbi balbi@ti.com --- board/ti/am43xx/board.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index c418e68..7f1f980 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -385,9 +385,18 @@ void scale_vcores(void) case 1000: mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; break; + case 800: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; + break; + case 720: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; + break; case 600: mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; break; + case 300: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; + break; default: puts("Unknown MPU clock, not scaling\n"); return;
On Mon, Dec 22, 2014 at 04:26:15PM -0600, Felipe Balbi wrote:
Make sure that all OPPs are checked on scale_vcores(). While at that also fix 600MHz VDD_MPU voltage according to AM437x Data Manual available at [1].
Table 5-3 on that document, lists all valid voltages per frequency.
[1] http://www.ti.com/lit/ds/symlink/am4379.pdf
Signed-off-by: Felipe Balbi balbi@ti.com
Applied to u-boot-ti/master, thanks!
This regulator is used with AM437x IDK to feed VDD_MPU, without means to scale VDD_MPU we can't support higher frequencies.
Signed-off-by: Felipe Balbi balbi@ti.com --- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps62362.c | 47 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps62362.c
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index e7b07eb..985cfdb 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -14,5 +14,6 @@ obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o +obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps62362.c b/drivers/power/pmic/pmic_tps62362.c new file mode 100644 index 0000000..2123685 --- /dev/null +++ b/drivers/power/pmic/pmic_tps62362.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com + * Author: Felipe Balbi balbi@ti.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/errno.h> +#include <power/pmic.h> +#include <power/tps62362.h> + +/** + * tps62362_voltage_update() - Function to change a voltage level, as this + * is a multi-step process. + * @reg: Register address to write to + * @volt_sel: Voltage register value to write + * @return: 0 on success, 1 on failure + */ +int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel) +{ + if (reg > TPS62362_NUM_REGS) + return 1; + + return i2c_write(TPS62362_I2C_ADDR, reg, 1, &volt_sel, 1); +} + +int power_tps62362_init(unsigned char bus) +{ + static const char name[] = "TPS62362"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = TPS62362_NUM_REGS; + p->hw.i2c.addr = TPS62362_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +}
On Tuesday 23 December 2014 03:56 AM, Felipe Balbi wrote:
This regulator is used with AM437x IDK to feed VDD_MPU, without means to scale VDD_MPU we can't support higher frequencies.
Signed-off-by: Felipe Balbi balbi@ti.com
drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps62362.c | 47 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps62362.c
There is a build error with this patch because tps62362.h is missing in the commit.
Regards Mugunthan V N
On Tue, Jan 06, 2015 at 02:28:23PM +0530, Mugunthan V N wrote:
On Tuesday 23 December 2014 03:56 AM, Felipe Balbi wrote:
This regulator is used with AM437x IDK to feed VDD_MPU, without means to scale VDD_MPU we can't support higher frequencies.
Signed-off-by: Felipe Balbi balbi@ti.com
drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps62362.c | 47 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps62362.c
There is a build error with this patch because tps62362.h is missing in the commit.
looks like I forgot to git add :-s
yeah, I did. I'll resend it.
This regulator is used with AM437x IDK to feed VDD_MPU, without means to scale VDD_MPU we can't support higher frequencies.
Signed-off-by: Felipe Balbi balbi@ti.com ---
Changes since v1: - git add the header which I had missed originally
drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps62362.c | 47 ++++++++++++++++++++++++++++++++++++++ include/power/tps62362.h | 29 +++++++++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps62362.c create mode 100644 include/power/tps62362.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index e7b07eb..985cfdb 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -14,5 +14,6 @@ obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o +obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps62362.c b/drivers/power/pmic/pmic_tps62362.c new file mode 100644 index 0000000..2123685 --- /dev/null +++ b/drivers/power/pmic/pmic_tps62362.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com + * Author: Felipe Balbi balbi@ti.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/errno.h> +#include <power/pmic.h> +#include <power/tps62362.h> + +/** + * tps62362_voltage_update() - Function to change a voltage level, as this + * is a multi-step process. + * @reg: Register address to write to + * @volt_sel: Voltage register value to write + * @return: 0 on success, 1 on failure + */ +int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel) +{ + if (reg > TPS62362_NUM_REGS) + return 1; + + return i2c_write(TPS62362_I2C_ADDR, reg, 1, &volt_sel, 1); +} + +int power_tps62362_init(unsigned char bus) +{ + static const char name[] = "TPS62362"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = TPS62362_NUM_REGS; + p->hw.i2c.addr = TPS62362_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/include/power/tps62362.h b/include/power/tps62362.h new file mode 100644 index 0000000..720c338 --- /dev/null +++ b/include/power/tps62362.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com + * Author: Felipe Balbi balbi@ti.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __POWER_TPS62362_H__ +#define __POWER_TPS62362_H__ + +/* I2C chip address */ +#define TPS62362_I2C_ADDR 0x60 + +/* Registers */ +#define TPS62362_SET0 0x00 +#define TPS62362_SET1 0x01 +#define TPS62362_SET2 0x02 +#define TPS62362_SET3 0x03 +#define TPS62362_NUM_REGS 4 + +#define TPS62362_DCDC_VOLT_SEL_0950MV 0x12 +#define TPS62362_DCDC_VOLT_SEL_1100MV 0x21 +#define TPS62362_DCDC_VOLT_SEL_1200MV 0x2b +#define TPS62362_DCDC_VOLT_SEL_1260MV 0x31 +#define TPS62362_DCDC_VOLT_SEL_1330MV 0x38 + +int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel); +int power_tps62362_init(unsigned char bus); +#endif /* __POWER_TPS62362_H__ */
On Tue, Jan 06, 2015 at 09:14:36AM -0600, Felipe Balbi wrote:
This regulator is used with AM437x IDK to feed VDD_MPU, without means to scale VDD_MPU we can't support higher frequencies.
Signed-off-by: Felipe Balbi balbi@ti.com
Applied to u-boot-ti/master, thanks!
AM43xx Industrial Development Kit is a new board based on AM437x line of SoCs. Targetted at Industrial Automation applications, it comes with EtherCAT, motor control and other goodies.
Thanks to James Doublesin for all the help.
Cc: James Doublesin doublesin@ti.com Signed-off-by: Felipe Balbi balbi@ti.com --- board/ti/am43xx/board.c | 127 +++++++++++++++++++++++++++++++++++++------ board/ti/am43xx/board.h | 5 ++ board/ti/am43xx/mux.c | 2 +- include/configs/am43xx_evm.h | 3 + 4 files changed, 118 insertions(+), 19 deletions(-)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 7f1f980..6703670 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -21,6 +21,7 @@ #include "board.h" #include <power/pmic.h> #include <power/tps65218.h> +#include <power/tps62362.h> #include <miiphy.h> #include <cpsw.h>
@@ -138,6 +139,10 @@ const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { const struct dpll_params gp_evm_dpll_ddr = { 50, 2, 1, -1, 2, -1, -1};
+static const struct dpll_params idk_dpll_ddr = { + 400, 23, 1, -1, 2, -1, -1 +}; + const struct ctrl_ioregs ioregs_lpddr2 = { .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, @@ -282,6 +287,32 @@ static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { .emif_cos_config = 0x000FFFFF };
+static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { + .sdram_config = 0x61a11b32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00000c30, + .sdram_tim1 = 0xeaaad4db, + .sdram_tim2 = 0x266b7fda, + .sdram_tim3 = 0x107f8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074be4, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1 = 0x00008009, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000040, + .emif_ddr_ext_phy_ctrl_3 = 0x0000003e, + .emif_ddr_ext_phy_ctrl_4 = 0x00000051, + .emif_ddr_ext_phy_ctrl_5 = 0x00000051, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000405, + .emif_prio_class_serv_map = 0x00000000, + .emif_connect_id_serv_1_map = 0x00000000, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x00ffffff +}; + /* * get_sys_clk_index : returns the index of the sys_clk read from * ctrl status register. This value is either @@ -309,6 +340,8 @@ const struct dpll_params *get_dpll_ddr_params(void) return &epos_evm_dpll_ddr[ind]; else if (board_is_gpevm() || board_is_sk()) return &gp_evm_dpll_ddr; + else if (board_is_idk()) + return &idk_dpll_ddr;
printf(" Board '%s' not supported\n", am43xx_board_name); return NULL; @@ -364,24 +397,14 @@ const struct dpll_params *get_dpll_per_params(void) return &dpll_per[ind]; }
-void scale_vcores(void) +void scale_vcores_generic(u32 m) { - const struct dpll_params *mpu_params; int mpu_vdd; - struct am43xx_board_id header; - - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - if (read_eeprom(&header) < 0) - puts("Could not get board ID.\n"); - - /* Get the frequency */ - mpu_params = get_dpll_mpu_params();
if (i2c_probe(TPS65218_CHIP_PM)) return;
- switch (mpu_params->m) { + switch (m) { case 1000: mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; break; @@ -405,17 +428,71 @@ void scale_vcores(void) /* Set DCDC1 (CORE) voltage to 1.1V */ if (tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV)) { - puts("tps65218_voltage_update failure\n"); + printf("%s failure\n", __func__); return; }
/* Set DCDC2 (MPU) voltage */ if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { - puts("tps65218_voltage_update failure\n"); + printf("%s failure\n", __func__); return; } }
+void scale_vcores_idk(u32 m) +{ + int mpu_vdd; + + if (i2c_probe(TPS62362_I2C_ADDR)) + return; + + switch (m) { + case 1000: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; + break; + case 800: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV; + break; + case 720: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV; + break; + case 600: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV; + break; + case 300: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; + break; + default: + puts("Unknown MPU clock, not scaling\n"); + return; + } + + /* Set VDD_MPU voltage */ + if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { + printf("%s failure\n", __func__); + return; + } +} + +void scale_vcores(void) +{ + const struct dpll_params *mpu_params; + struct am43xx_board_id header; + + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + /* Get the frequency */ + mpu_params = get_dpll_mpu_params(); + + if (board_is_idk()) + scale_vcores_idk(mpu_params->m); + else + scale_vcores_generic(mpu_params->m); +} + void set_uart_mux_conf(void) { enable_uart0_pin_mux(); @@ -465,6 +542,9 @@ void sdram_init(void) } else if (board_is_sk()) { config_ddr(400, &ioregs_ddr3, NULL, NULL, &ddr3_sk_emif_regs_400Mhz, 0); + } else if (board_is_idk()) { + config_ddr(400, &ioregs_ddr3, NULL, NULL, + &ddr3_idk_emif_regs_400Mhz, 0); } } #endif @@ -474,10 +554,17 @@ int power_init_board(void) { struct pmic *p;
- power_tps65218_init(I2C_PMIC); - p = pmic_get("TPS65218_PMIC"); - if (p && !pmic_probe(p)) - puts("PMIC: TPS65218\n"); + if (board_is_idk()) { + power_tps62362_init(I2C_PMIC); + p = pmic_get("TPS62362"); + if (p && !pmic_probe(p)) + puts("PMIC: TPS62362\n"); + } else { + power_tps65218_init(I2C_PMIC); + p = pmic_get("TPS65218_PMIC"); + if (p && !pmic_probe(p)) + puts("PMIC: TPS65218\n"); + }
return 0; } @@ -634,6 +721,10 @@ int board_eth_init(bd_t *bis) cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; cpsw_slaves[0].phy_addr = 4; cpsw_slaves[1].phy_addr = 5; + } else if (board_is_idk()) { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 0; } else { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 8e12191..eb9493e 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -53,6 +53,11 @@ static inline int board_is_sk(void) return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN); }
+static inline int board_is_idk(void) +{ + return !strncmp(am43xx_board_name, "AM43_IDK", HDR_NAME_LEN); +} + static inline int board_is_evm_14_or_later(void) { return (board_is_gpevm() && strncmp("1.4", am43xx_board_rev, 3) <= 0); diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index a670b0b..510477d 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -131,7 +131,7 @@ void enable_board_pin_mux(void) #if defined(CONFIG_NAND) configure_module_pin_mux(nand_pin_mux); #endif - } else if (board_is_sk()) { + } else if (board_is_sk() || board_is_idk()) { configure_module_pin_mux(rgmii1_pin_mux); #if defined(CONFIG_NAND) printf("Error: NAND flash not present on this board\n"); diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 4472c3e..96e7e23 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -39,6 +39,7 @@ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_TPS65218 +#define CONFIG_POWER_TPS62362
/* SPL defines. */ #define CONFIG_SPL_TEXT_BASE 0x40300350 @@ -237,6 +238,8 @@ "setenv fdtfile am437x-gp-evm.dtb; fi; " \ "if test $board_name = AM43__SK; then " \ "setenv fdtfile am437x-sk-evm.dtb; fi; " \ + "if test $board_name = AM43_IDK; then " \ + "setenv fdtfile am437x-idk-evm.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree; fi; \0"
On Mon, Dec 22, 2014 at 04:26:17PM -0600, Felipe Balbi wrote:
AM43xx Industrial Development Kit is a new board based on AM437x line of SoCs. Targetted at Industrial Automation applications, it comes with EtherCAT, motor control and other goodies.
Thanks to James Doublesin for all the help.
Cc: James Doublesin doublesin@ti.com Signed-off-by: Felipe Balbi balbi@ti.com
Applied to u-boot-ti/master, thanks!
On Tuesday 23 December 2014 03:56 AM, Felipe Balbi wrote:
From: James Doublesin doublesin@ti.com
Need to provide PLL values for all possible input frequencies (19.2, 24, 25, 26MHz). Values provide are also optimized for jitter (needed especially for PER PLL and DDR PLL).
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Felipe Balbi balbi@ti.com
Tested the full series.
Tested-by: Mugunthan V N mugunthanvnm@ti.com
Regards Mugunthan V N
On Mon, Dec 22, 2014 at 04:26:10PM -0600, Felipe Balbi wrote:
From: James Doublesin doublesin@ti.com
Need to provide PLL values for all possible input frequencies (19.2, 24, 25, 26MHz). Values provide are also optimized for jitter (needed especially for PER PLL and DDR PLL).
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Felipe Balbi balbi@ti.com Tested-by: Mugunthan V N mugunthanvnm@ti.com
Applied to u-boot-ti/master, thanks!
On Mon, Dec 22, 2014 at 04:26:10PM -0600, Felipe Balbi wrote:
From: James Doublesin doublesin@ti.com
Need to provide PLL values for all possible input frequencies (19.2, 24, 25, 26MHz). Values provide are also optimized for jitter (needed especially for PER PLL and DDR PLL).
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Felipe Balbi balbi@ti.com Tested-by: Mugunthan V N mugunthanvnm@ti.com
Applied to u-boot-ti/master, thanks!
participants (3)
-
Felipe Balbi -
Mugunthan V N -
Tom Rini