[U-Boot] [PATCH V2 1/2] ARM: tegra: Add e2220-1170 board
From: Stephen Warren swarren@nvidia.com
Signed-off-by: Stephen Warren swarren@nvidia.com --- v2: Use named constants for PMIC I2C and register addresses. --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra210-e2220-1170.dts | 58 +++++ arch/arm/mach-tegra/tegra210/Kconfig | 6 + board/nvidia/e2220-1170/Kconfig | 12 + board/nvidia/e2220-1170/MAINTAINERS | 6 + board/nvidia/e2220-1170/Makefile | 8 + board/nvidia/e2220-1170/e2220-1170.c | 51 ++++ board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 269 +++++++++++++++++++++ configs/e2220-1170_defconfig | 16 ++ include/configs/e2220-1170.h | 72 ++++++ 10 files changed, 499 insertions(+) create mode 100644 arch/arm/dts/tegra210-e2220-1170.dts create mode 100644 board/nvidia/e2220-1170/Kconfig create mode 100644 board/nvidia/e2220-1170/MAINTAINERS create mode 100644 board/nvidia/e2220-1170/Makefile create mode 100644 board/nvidia/e2220-1170/e2220-1170.c create mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h create mode 100644 configs/e2220-1170_defconfig create mode 100644 include/configs/e2220-1170.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ba6355379cba..d8e1841eb4d8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ tegra124-venice2.dtb \ + tegra210-e2220-1170.dtb \ tegra210-p2571.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-sld3-ref.dtb \ diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210-e2220-1170.dts new file mode 100644 index 000000000000..75efbba1061e --- /dev/null +++ b/arch/arm/dts/tegra210-e2220-1170.dts @@ -0,0 +1,58 @@ +/dts-v1/; + +#include "tegra210.dtsi" + +/ { + model = "NVIDIA E2220-1170"; + compatible = "nvidia,e2220-1170", "nvidia,tegra210"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@0,7000d000"; + sdhci0 = "/sdhci@0,700b0600"; + sdhci1 = "/sdhci@0,700b0000"; + usb0 = "/usb@0,7d000000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + sdhci@0,700b0000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@0,700b0600 { + status = "okay"; + bus-width = <8>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + usb@0,7d000000 { + status = "okay"; + dr_mode = "peripheral"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig index 147e6a83d722..9633ba8c629e 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -3,6 +3,11 @@ if TEGRA210 choice prompt "Tegra210 board select"
+config TARGET_E2220_1170 + bool "NVIDIA Tegra210 E2220-1170 base board" + help + E2220-1170 ERS + config TARGET_P2571 bool "NVIDIA Tegra210 P2571 base board" help @@ -13,6 +18,7 @@ endchoice config SYS_SOC default "tegra210"
+source "board/nvidia/e2220-1170/Kconfig" source "board/nvidia/p2571/Kconfig"
endif diff --git a/board/nvidia/e2220-1170/Kconfig b/board/nvidia/e2220-1170/Kconfig new file mode 100644 index 000000000000..0a30f4936223 --- /dev/null +++ b/board/nvidia/e2220-1170/Kconfig @@ -0,0 +1,12 @@ +if TARGET_E2220_1170 + +config SYS_BOARD + default "e2220-1170" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "e2220-1170" + +endif diff --git a/board/nvidia/e2220-1170/MAINTAINERS b/board/nvidia/e2220-1170/MAINTAINERS new file mode 100644 index 000000000000..0abb37884018 --- /dev/null +++ b/board/nvidia/e2220-1170/MAINTAINERS @@ -0,0 +1,6 @@ +E2220-1170 BOARD +M: Tom Warren twarren@nvidia.com +S: Maintained +F: board/nvidia/e2220-1170/ +F: include/configs/e2220-1170.h +F: configs/e2220-1170_defconfig diff --git a/board/nvidia/e2220-1170/Makefile b/board/nvidia/e2220-1170/Makefile new file mode 100644 index 000000000000..c956b1972deb --- /dev/null +++ b/board/nvidia/e2220-1170/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2013-2015 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += e2220-1170.o diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c new file mode 100644 index 000000000000..d66a72e5204c --- /dev/null +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include "../p2571/max77620_init.h" +#include "pinmux-config-e2220-1170.h" + +void pin_mux_mmc(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); +} + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_clear_tristate_input_clamping(); + + gpio_config_table(e2220_1170_gpio_inits, + ARRAY_SIZE(e2220_1170_gpio_inits)); + + pinmux_config_pingrp_table(e2220_1170_pingrps, + ARRAY_SIZE(e2220_1170_pingrps)); + + pinmux_config_drvgrp_table(e2220_1170_drvgrps, + ARRAY_SIZE(e2220_1170_drvgrps)); +} diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h new file mode 100644 index 000000000000..397dc7f44b11 --- /dev/null +++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_E2220_1170_H_ +#define _PINMUX_CONFIG_E2220_1170_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config e2220_1170_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A5, IN), + GPIO_INIT(A6, IN), + GPIO_INIT(B4, IN), + GPIO_INIT(E6, IN), + GPIO_INIT(G2, OUT0), + GPIO_INIT(G3, OUT0), + GPIO_INIT(H0, OUT0), + GPIO_INIT(H1, OUT0), + GPIO_INIT(H2, IN), + GPIO_INIT(H3, OUT0), + GPIO_INIT(H4, OUT0), + GPIO_INIT(H5, IN), + GPIO_INIT(H6, OUT0), + GPIO_INIT(H7, OUT0), + GPIO_INIT(I0, OUT0), + GPIO_INIT(I1, IN), + GPIO_INIT(I2, OUT0), + GPIO_INIT(I3, OUT0), + GPIO_INIT(K0, IN), + GPIO_INIT(K1, OUT0), + GPIO_INIT(K2, OUT0), + GPIO_INIT(K3, OUT0), + GPIO_INIT(K4, IN), + GPIO_INIT(K5, OUT0), + GPIO_INIT(K6, IN), + GPIO_INIT(K7, OUT0), + GPIO_INIT(L0, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S5, OUT0), + GPIO_INIT(S6, OUT0), + GPIO_INIT(S7, OUT0), + GPIO_INIT(T0, OUT0), + GPIO_INIT(T1, OUT0), + GPIO_INIT(V1, OUT0), + GPIO_INIT(V2, OUT0), + GPIO_INIT(V3, IN), + GPIO_INIT(V5, OUT0), + GPIO_INIT(V6, OUT0), + GPIO_INIT(X0, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X2, IN), + GPIO_INIT(X3, IN), + GPIO_INIT(X4, IN), + GPIO_INIT(X5, IN), + GPIO_INIT(X6, IN), + GPIO_INIT(X7, IN), + GPIO_INIT(Y0, IN), + GPIO_INIT(Y1, IN), + GPIO_INIT(Z0, IN), + GPIO_INIT(Z4, OUT0), + GPIO_INIT(BB2, OUT0), + GPIO_INIT(BB3, OUT0), + GPIO_INIT(BB4, IN), + GPIO_INIT(CC1, IN), + GPIO_INIT(CC5, OUT0), + GPIO_INIT(CC6, IN), + GPIO_INIT(CC7, OUT0), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + } + +static const struct pmux_pingrp_config e2220_1170_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ + PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MOSI_PB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MOSI_PC0, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MISO_PC1, SPI1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_SCK_PC2, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS0_PC3, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS1_PC4, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_CTS_PD4, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_DAT_PE1, DMIC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_DAT_PE3, DMIC2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_DAT_PE5, DMIC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(UART2_TX_PG0, UART, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_RX_PG1, UART, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART2_RTS_PG2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO1_PV3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X3_AUD_PBB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SPDIF_OUT_PCC2, SPDIF, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPDIF_IN_PCC3, SPDIF, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(USB_VBUS_EN1_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_E2220_1170_H */ diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig new file mode 100644 index 000000000000..a31f5fa78a05 --- /dev/null +++ b/configs/e2220-1170_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA210=y +CONFIG_TARGET_E2220_1170=y +CONFIG_DEFAULT_DEVICE_TREE="tegra210-e2220-1170" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPL_DM=y +CONFIG_SPI_FLASH=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h new file mode 100644 index 000000000000..49eb55ae4b29 --- /dev/null +++ b/include/configs/e2220-1170.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _E2220_1170_H +#define _E2220_1170_H + +#include <linux/sizes.h> + +/* enable PMIC */ +#define CONFIG_MAX77620_POWER + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra210 (E2220-1170) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA E2220-1170" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB2.0 Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#define COUNTER_FREQUENCY 38400000 + +#endif /* _E2220_1170_H */
From: Stephen Warren swarren@nvidia.com
Signed-off-by: Stephen Warren swarren@nvidia.com --- v2: Use named constants for PMIC I2C and register addresses. --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra210-p2371-0000.dts | 59 +++++ arch/arm/mach-tegra/tegra210/Kconfig | 6 + board/nvidia/p2371-0000/Kconfig | 12 + board/nvidia/p2371-0000/MAINTAINERS | 6 + board/nvidia/p2371-0000/Makefile | 8 + board/nvidia/p2371-0000/p2371-0000.c | 51 ++++ board/nvidia/p2371-0000/pinmux-config-p2371-0000.h | 260 +++++++++++++++++++++ configs/p2371-0000_defconfig | 16 ++ include/configs/p2371-0000.h | 72 ++++++ 10 files changed, 491 insertions(+) create mode 100644 arch/arm/dts/tegra210-p2371-0000.dts create mode 100644 board/nvidia/p2371-0000/Kconfig create mode 100644 board/nvidia/p2371-0000/MAINTAINERS create mode 100644 board/nvidia/p2371-0000/Makefile create mode 100644 board/nvidia/p2371-0000/p2371-0000.c create mode 100644 board/nvidia/p2371-0000/pinmux-config-p2371-0000.h create mode 100644 configs/p2371-0000_defconfig create mode 100644 include/configs/p2371-0000.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d8e1841eb4d8..f61060fc92e5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-nyan-big.dtb \ tegra124-venice2.dtb \ tegra210-e2220-1170.dtb \ + tegra210-p2371-0000.dtb \ tegra210-p2571.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-sld3-ref.dtb \ diff --git a/arch/arm/dts/tegra210-p2371-0000.dts b/arch/arm/dts/tegra210-p2371-0000.dts new file mode 100644 index 000000000000..10172a23ad70 --- /dev/null +++ b/arch/arm/dts/tegra210-p2371-0000.dts @@ -0,0 +1,59 @@ +/dts-v1/; + +#include "tegra210.dtsi" + +/ { + model = "NVIDIA P2371-0000"; + compatible = "nvidia,p2371-0000", "nvidia,tegra210"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@0,7000d000"; + sdhci0 = "/sdhci@0,700b0600"; + sdhci1 = "/sdhci@0,700b0000"; + usb0 = "/usb@0,7d000000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + sdhci@0,700b0000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@0,700b0600 { + status = "okay"; + bus-width = <8>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + usb@0,7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig index 9633ba8c629e..895002c5942b 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -8,6 +8,11 @@ config TARGET_E2220_1170 help E2220-1170 ERS
+config TARGET_P2371_0000 + bool "NVIDIA Tegra210 P2371-0000 base board" + help + P2371-0000 + config TARGET_P2571 bool "NVIDIA Tegra210 P2571 base board" help @@ -19,6 +24,7 @@ config SYS_SOC default "tegra210"
source "board/nvidia/e2220-1170/Kconfig" +source "board/nvidia/p2371-0000/Kconfig" source "board/nvidia/p2571/Kconfig"
endif diff --git a/board/nvidia/p2371-0000/Kconfig b/board/nvidia/p2371-0000/Kconfig new file mode 100644 index 000000000000..f94be12be1a0 --- /dev/null +++ b/board/nvidia/p2371-0000/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P2371_0000 + +config SYS_BOARD + default "p2371-0000" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "p2371-0000" + +endif diff --git a/board/nvidia/p2371-0000/MAINTAINERS b/board/nvidia/p2371-0000/MAINTAINERS new file mode 100644 index 000000000000..e6d04bf7c5e1 --- /dev/null +++ b/board/nvidia/p2371-0000/MAINTAINERS @@ -0,0 +1,6 @@ +P2371-0000 BOARD +M: Tom Warren twarren@nvidia.com +S: Maintained +F: board/nvidia/p2371-0000/ +F: include/configs/p2371-0000.h +F: configs/p2371-0000_defconfig diff --git a/board/nvidia/p2371-0000/Makefile b/board/nvidia/p2371-0000/Makefile new file mode 100644 index 000000000000..9f580ae5b296 --- /dev/null +++ b/board/nvidia/p2371-0000/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2013-2015 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += p2371-0000.o diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c new file mode 100644 index 000000000000..9df543a4c9e8 --- /dev/null +++ b/board/nvidia/p2371-0000/p2371-0000.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include "../p2571/max77620_init.h" +#include "pinmux-config-p2371-0000.h" + +void pin_mux_mmc(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); +} + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_clear_tristate_input_clamping(); + + gpio_config_table(p2371_0000_gpio_inits, + ARRAY_SIZE(p2371_0000_gpio_inits)); + + pinmux_config_pingrp_table(p2371_0000_pingrps, + ARRAY_SIZE(p2371_0000_pingrps)); + + pinmux_config_drvgrp_table(p2371_0000_drvgrps, + ARRAY_SIZE(p2371_0000_drvgrps)); +} diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h new file mode 100644 index 000000000000..5b2fbb7bd7cb --- /dev/null +++ b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_P2371_0000_H_ +#define _PINMUX_CONFIG_P2371_0000_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config p2371_0000_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A5, IN), + GPIO_INIT(E4, OUT0), + GPIO_INIT(E6, IN), + GPIO_INIT(G0, IN), + GPIO_INIT(G3, OUT0), + GPIO_INIT(H0, OUT0), + GPIO_INIT(H2, IN), + GPIO_INIT(H3, OUT0), + GPIO_INIT(H4, OUT0), + GPIO_INIT(H5, IN), + GPIO_INIT(H6, OUT0), + GPIO_INIT(H7, OUT0), + GPIO_INIT(I0, OUT0), + GPIO_INIT(I1, IN), + GPIO_INIT(I2, OUT0), + GPIO_INIT(I3, OUT0), + GPIO_INIT(K4, IN), + GPIO_INIT(K5, OUT0), + GPIO_INIT(K6, IN), + GPIO_INIT(K7, OUT0), + GPIO_INIT(L0, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S5, OUT0), + GPIO_INIT(S6, OUT0), + GPIO_INIT(S7, OUT0), + GPIO_INIT(T0, OUT0), + GPIO_INIT(T1, OUT0), + GPIO_INIT(V1, OUT0), + GPIO_INIT(V2, OUT0), + GPIO_INIT(V5, OUT0), + GPIO_INIT(V6, OUT0), + GPIO_INIT(V7, OUT1), + GPIO_INIT(X0, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X2, IN), + GPIO_INIT(X3, IN), + GPIO_INIT(X4, IN), + GPIO_INIT(X5, IN), + GPIO_INIT(X6, IN), + GPIO_INIT(X7, IN), + GPIO_INIT(Y1, IN), + GPIO_INIT(Z0, IN), + GPIO_INIT(Z4, OUT0), + GPIO_INIT(BB2, OUT0), + GPIO_INIT(BB3, OUT0), + GPIO_INIT(CC1, IN), + GPIO_INIT(CC6, IN), + GPIO_INIT(CC7, OUT0), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + } + +static const struct pmux_pingrp_config p2371_0000_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ + PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), + PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), + PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MOSI_PC0, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MISO_PC1, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_SCK_PC2, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS0_PC3, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS1_PC4, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_DAT_PE1, DMIC1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_DAT_PE3, DMIC2, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK0, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK1, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK2, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK3, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_CLK_PV7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config p2371_0000_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_P2371_0000_H */ diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig new file mode 100644 index 000000000000..b2d0e83e3d96 --- /dev/null +++ b/configs/p2371-0000_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA210=y +CONFIG_TARGET_P2371_0000=y +CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPL_DM=y +CONFIG_SPI_FLASH=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h new file mode 100644 index 000000000000..e70c3c24e301 --- /dev/null +++ b/include/configs/p2371-0000.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _P2371_0000_H +#define _P2371_0000_H + +#include <linux/sizes.h> + +/* enable PMIC */ +#define CONFIG_MAX77620_POWER + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra210 (P2371-0000) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB2.0 Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#define COUNTER_FREQUENCY 38400000 + +#endif /* _P2371_0000_H */
On Wed, Jul 29, 2015 at 02:16:33PM -0600, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
Signed-off-by: Stephen Warren swarren@nvidia.com
v2: Use named constants for PMIC I2C and register addresses.
arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra210-p2371-0000.dts | 59 +++++ arch/arm/mach-tegra/tegra210/Kconfig | 6 + board/nvidia/p2371-0000/Kconfig | 12 + board/nvidia/p2371-0000/MAINTAINERS | 6 + board/nvidia/p2371-0000/Makefile | 8 + board/nvidia/p2371-0000/p2371-0000.c | 51 ++++ board/nvidia/p2371-0000/pinmux-config-p2371-0000.h | 260 +++++++++++++++++++++ configs/p2371-0000_defconfig | 16 ++ include/configs/p2371-0000.h | 72 ++++++ 10 files changed, 491 insertions(+) create mode 100644 arch/arm/dts/tegra210-p2371-0000.dts create mode 100644 board/nvidia/p2371-0000/Kconfig create mode 100644 board/nvidia/p2371-0000/MAINTAINERS create mode 100644 board/nvidia/p2371-0000/Makefile create mode 100644 board/nvidia/p2371-0000/p2371-0000.c create mode 100644 board/nvidia/p2371-0000/pinmux-config-p2371-0000.h create mode 100644 configs/p2371-0000_defconfig create mode 100644 include/configs/p2371-0000.h
Sorry for being late on this. I just rebased my tree on origin/master and got rid of my preliminary P2371 patches in favour of this only to notice that it doesn't work the way it used to. For example I used to use:
# ums 0 mmc 1
to upload kernel, DTB and such to the external SD card. Unfortunately that no longer works with this version of the patches. I tried to see what the differences are but couldn't spot anything. I see that dmesg shows a bunch of USB device reset messages, and failures to read the superblock on /dev/sdc, which is what the mass storage shows up as. I also tried porting a couple of changes from my earlier tree over to master, but to no avail.
Any ideas what could be the reason here? Does the external SD card work for anybody else?
I also noticed two other things:
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
[...]
+CONFIG_USE_PRIVATE_LIBGCC=y
Why do we need this?
diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h
[...]
+#define COUNTER_FREQUENCY 38400000
As far as I know the system counter is actually clocked by clk_m, which on most (all?) Tegra210 platforms will be configured to run at half the oscillator frequency (19.2 MHz). This is corroborated by the fact that running:
# sleep 5
actually takes 10 seconds rather than the expected 5. Changing the above to 19200000 fixes that.
Thierry
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On 08/19/2015 07:56 AM, Thierry Reding wrote:
On Wed, Jul 29, 2015 at 02:16:33PM -0600, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
Signed-off-by: Stephen Warren swarren@nvidia.com
v2: Use named constants for PMIC I2C and register addresses.
arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra210-p2371-0000.dts | 59 +++++ arch/arm/mach-tegra/tegra210/Kconfig | 6 + board/nvidia/p2371-0000/Kconfig | 12 + board/nvidia/p2371-0000/MAINTAINERS | 6 + board/nvidia/p2371-0000/Makefile | 8 + board/nvidia/p2371-0000/p2371-0000.c | 51 ++++ board/nvidia/p2371-0000/pinmux-config-p2371-0000.h | 260 +++++++++++++++++++++ configs/p2371-0000_defconfig | 16 ++
...
Sorry for being late on this. I just rebased my tree on origin/master and got rid of my preliminary P2371 patches in favour of this only to notice that it doesn't work the way it used to. For example I used to use:
# ums 0 mmc 1
to upload kernel, DTB and such to the external SD card. Unfortunately that no longer works with this version of the patches. I tried to see what the differences are but couldn't spot anything. I see that dmesg shows a bunch of USB device reset messages, and failures to read the superblock on /dev/sdc, which is what the mass storage shows up as. I also tried porting a couple of changes from my earlier tree over to master, but to no avail.
Any ideas what could be the reason here? Does the external SD card work for anybody else?
It certainly did when I tested it. I haven't tested it on this particular board since the patch was actually applied though.
A few questions:
- Do regular filesystem commands such as part list, ls, load work on the SD card?
- Does ums work on the eMMC but not SD, or fail on both?
Perhaps related: I have just noticed that one of my SD cards works just fine in p2371-2180 but the other card doesn't. I swear they both used to work. Unfortunately I can't test those cards on p2371-0000 since it has a uSD slot instead of full-size. I've also noticed some stability issues with "ums" even on the eMMC; basic stuff like the device enumeration and various sized dd operations work fine, but mounting filesystems doesn't always work. I'll see if I can work out what's up. I wonder if the recent T210 clock driver patches had anything to do with this; IIRC they didn't exist when I first did all these board ports.
I also noticed two other things:
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
[...]
+CONFIG_USE_PRIVATE_LIBGCC=y
Why do we need this?
I copied the configuration from the p2571 patches that Tom sent, to keep all the T210 boards consistent. Perhaps Tom can shed some light? FWIW, I tested removing that line for p2371-2180 and the build and boot to U-Boot prompt still seemed to work. This option might be a hold-over from previous chips where SPL existed and needed to be built with different CPU options. Perhaps we can remove this.
diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h
[...]
+#define COUNTER_FREQUENCY 38400000
As far as I know the system counter is actually clocked by clk_m, which on most (all?) Tegra210 platforms will be configured to run at half the oscillator frequency (19.2 MHz). This is corroborated by the fact that running:
# sleep 5
actually takes 10 seconds rather than the expected 5. Changing the above to 19200000 fixes that.
That's odd. I just tested this on p2371-2180 which should have the same basic clock/crystal setup, and "sleep 10" takes 10 seconds. What SW are you using as the primary bootloader? I'm using nvtboot from our internal L4T main branch. Once that's released, I would expect people to use that same thing (and NVIDIAns can use it already:-)
On 08/19/2015 11:41 AM, Stephen Warren wrote:
On 08/19/2015 07:56 AM, Thierry Reding wrote:
On Wed, Jul 29, 2015 at 02:16:33PM -0600, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
Signed-off-by: Stephen Warren swarren@nvidia.com
v2: Use named constants for PMIC I2C and register addresses.
arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra210-p2371-0000.dts | 59 +++++ arch/arm/mach-tegra/tegra210/Kconfig | 6 + board/nvidia/p2371-0000/Kconfig | 12 + board/nvidia/p2371-0000/MAINTAINERS | 6 + board/nvidia/p2371-0000/Makefile | 8 + board/nvidia/p2371-0000/p2371-0000.c | 51 ++++ board/nvidia/p2371-0000/pinmux-config-p2371-0000.h | 260 +++++++++++++++++++++ configs/p2371-0000_defconfig | 16 ++
...
Sorry for being late on this. I just rebased my tree on origin/master and got rid of my preliminary P2371 patches in favour of this only to notice that it doesn't work the way it used to.
...
diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h
[...]
+#define COUNTER_FREQUENCY 38400000
As far as I know the system counter is actually clocked by clk_m, which on most (all?) Tegra210 platforms will be configured to run at half the oscillator frequency (19.2 MHz). This is corroborated by the fact that running:
# sleep 5actually takes 10 seconds rather than the expected 5. Changing the above to 19200000 fixes that.
That's odd. I just tested this on p2371-2180 which should have the same basic clock/crystal setup, and "sleep 10" takes 10 seconds. What SW are you using as the primary bootloader? I'm using nvtboot from our internal L4T main branch. Once that's released, I would expect people to use that same thing (and NVIDIAns can use it already:-)
So, COUNTER_FREQUENCY is only used if U-Boot is started in EL3, to program the cntfrq_el0 register. Since I'm booting a secure monitor first, U-Boot is starting in EL2 for me, and COUNTER_FREQUENCY isn't actually used. I've confirmed in the TRM that clk_m does run at half the crystal rate, and that the secure monitor is indeed setting cntfrq_el0 is 19.2MHz rather than 38.4MHz. I'll send a patch to correct this.
On 08/19/2015 11:41 AM, Stephen Warren wrote:
On 08/19/2015 07:56 AM, Thierry Reding wrote:
On Wed, Jul 29, 2015 at 02:16:33PM -0600, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
Signed-off-by: Stephen Warren swarren@nvidia.com
v2: Use named constants for PMIC I2C and register addresses.
arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra210-p2371-0000.dts | 59 +++++ arch/arm/mach-tegra/tegra210/Kconfig | 6 + board/nvidia/p2371-0000/Kconfig | 12 + board/nvidia/p2371-0000/MAINTAINERS | 6 + board/nvidia/p2371-0000/Makefile | 8 + board/nvidia/p2371-0000/p2371-0000.c | 51 ++++ board/nvidia/p2371-0000/pinmux-config-p2371-0000.h | 260 +++++++++++++++++++++ configs/p2371-0000_defconfig | 16 ++
...
Sorry for being late on this. I just rebased my tree on origin/master and got rid of my preliminary P2371 patches in favour of this only to notice that it doesn't work the way it used to. For example I used to use:
# ums 0 mmc 1to upload kernel, DTB and such to the external SD card. Unfortunately that no longer works with this version of the patches. I tried to see what the differences are but couldn't spot anything. I see that dmesg shows a bunch of USB device reset messages, and failures to read the superblock on /dev/sdc, which is what the mass storage shows up as. I also tried porting a couple of changes from my earlier tree over to master, but to no avail.
Any ideas what could be the reason here? Does the external SD card work for anybody else?
It certainly did when I tested it. I haven't tested it on this particular board since the patch was actually applied though.
A few questions:
- Do regular filesystem commands such as part list, ls, load work on the
SD card?
- Does ums work on the eMMC but not SD, or fail on both?
Perhaps related: I have just noticed that one of my SD cards works just fine in p2371-2180 but the other card doesn't. I swear they both used to work. Unfortunately I can't test those cards on p2371-0000 since it has a uSD slot instead of full-size. I've also noticed some stability issues with "ums" even on the eMMC; basic stuff like the device enumeration and various sized dd operations work fine, but mounting filesystems doesn't always work. I'll see if I can work out what's up. I wonder if the recent T210 clock driver patches had anything to do with this; IIRC they didn't exist when I first did all these board ports.
Well, I found what was preventing one of my SD cards from working; the fix is:
http://lists.denx.de/pipermail/u-boot/2015-August/224545.html [PATCH] ARM: tegra: fix PLLP frequency calc on T210
ums is still solid for me with dd but unreliable with mount. Still investigating that one.
On Wed, Aug 19, 2015 at 11:41:09AM -0600, Stephen Warren wrote:
On 08/19/2015 07:56 AM, Thierry Reding wrote:
On Wed, Jul 29, 2015 at 02:16:33PM -0600, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
Signed-off-by: Stephen Warren swarren@nvidia.com
v2: Use named constants for PMIC I2C and register addresses.
arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra210-p2371-0000.dts | 59 +++++ arch/arm/mach-tegra/tegra210/Kconfig | 6 + board/nvidia/p2371-0000/Kconfig | 12 + board/nvidia/p2371-0000/MAINTAINERS | 6 + board/nvidia/p2371-0000/Makefile | 8 + board/nvidia/p2371-0000/p2371-0000.c | 51 ++++ board/nvidia/p2371-0000/pinmux-config-p2371-0000.h | 260 +++++++++++++++++++++ configs/p2371-0000_defconfig | 16 ++
...
Sorry for being late on this. I just rebased my tree on origin/master and got rid of my preliminary P2371 patches in favour of this only to notice that it doesn't work the way it used to. For example I used to use:
# ums 0 mmc 1
to upload kernel, DTB and such to the external SD card. Unfortunately that no longer works with this version of the patches. I tried to see what the differences are but couldn't spot anything. I see that dmesg shows a bunch of USB device reset messages, and failures to read the superblock on /dev/sdc, which is what the mass storage shows up as. I also tried porting a couple of changes from my earlier tree over to master, but to no avail.
Any ideas what could be the reason here? Does the external SD card work for anybody else?
It certainly did when I tested it. I haven't tested it on this particular board since the patch was actually applied though.
A few questions:
- Do regular filesystem commands such as part list, ls, load work on the SD
card?
- Does ums work on the eMMC but not SD, or fail on both?
eMMC seems to work better. I see various partitions detected on the /dev/sdc device and I don't see device reset messages. But I do see other issues that are similar as for the SD card.
I didn't mention that before, but when I run
# ums 0 mmc 1
I have trouble interrupting it using Ctrl+C. This used to work fine but for some reason this isn't working reliably anymore. I have to keep pressing Ctrl+C for half a minute or so before it reacts.
Perhaps related: I have just noticed that one of my SD cards works just fine in p2371-2180 but the other card doesn't. I swear they both used to work. Unfortunately I can't test those cards on p2371-0000 since it has a uSD slot instead of full-size. I've also noticed some stability issues with "ums" even on the eMMC; basic stuff like the device enumeration and various sized dd operations work fine, but mounting filesystems doesn't always work. I'll see if I can work out what's up. I wonder if the recent T210 clock driver patches had anything to do with this; IIRC they didn't exist when I first did all these board ports.
I also noticed two other things:
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
[...]
+CONFIG_USE_PRIVATE_LIBGCC=y
Why do we need this?
I copied the configuration from the p2571 patches that Tom sent, to keep all the T210 boards consistent. Perhaps Tom can shed some light? FWIW, I tested removing that line for p2371-2180 and the build and boot to U-Boot prompt still seemed to work. This option might be a hold-over from previous chips where SPL existed and needed to be built with different CPU options. Perhaps we can remove this.
My recollection is that we needed this in order for SPL to be linked against a custom version of libgcc, because the default libgcc provided by the cross-compiler would typically be optimized for ARMv7 and crash on the AVP (ARMv4). I think the string functions were the problematic parts. Given that we don't have the split architecture issue with U-Boot on Tegra210, there's no longer a need to build the private version. I've successfully been booting U-Boot for a long time without it.
diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h
[...]
+#define COUNTER_FREQUENCY 38400000
As far as I know the system counter is actually clocked by clk_m, which on most (all?) Tegra210 platforms will be configured to run at half the oscillator frequency (19.2 MHz). This is corroborated by the fact that running:
# sleep 5
actually takes 10 seconds rather than the expected 5. Changing the above to 19200000 fixes that.
That's odd. I just tested this on p2371-2180 which should have the same basic clock/crystal setup, and "sleep 10" takes 10 seconds. What SW are you using as the primary bootloader? I'm using nvtboot from our internal L4T main branch. Once that's released, I would expect people to use that same thing (and NVIDIAns can use it already:-)
That's odd. The miniloader that I use was "inspired" by nvtboot, so it uses mostly the same initialization. It then goes and implements the old RCM/nv3p protocol so that it can be used in conjunction with tegrarcm rather than the newer flashing tools that L4T provides.
That said, it seems to me like there might be a difference between how nvtboot and the miniloader that I use set up clocks, resulting in this discrepancy. So hard-coding the frequency may not be a good option because it would be assuming primary bootloader behaviour. I do have a couple of patches in my local tree that I wrote as a result of some review feedback. The goal was to make the hard-coded COUNTER_FREQUENCY optional and instead allow our architected timer setup code to query the clk_m frequency and program that value instead. I'll send those out shortly, perhaps you could try those on your setup to see if it works correctly.
Thierry
-----Original Message----- From: Stephen Warren [mailto:swarren@wwwdotorg.org] Sent: Wednesday, July 29, 2015 1:17 PM To: u-boot@lists.denx.de; Simon Glass; Tom Warren; Stephen Warren Cc: Thierry Reding Subject: [PATCH V2 1/2] ARM: tegra: Add e2220-1170 board
From: Stephen Warren swarren@nvidia.com
Signed-off-by: Stephen Warren swarren@nvidia.com
v2: Use named constants for PMIC I2C and register addresses.
arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra210-e2220-1170.dts | 58 +++++ arch/arm/mach-tegra/tegra210/Kconfig | 6 + board/nvidia/e2220-1170/Kconfig | 12 + board/nvidia/e2220-1170/MAINTAINERS | 6 + board/nvidia/e2220-1170/Makefile | 8 + board/nvidia/e2220-1170/e2220-1170.c | 51 ++++ board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 269 +++++++++++++++++++++ configs/e2220-1170_defconfig | 16 ++ include/configs/e2220-1170.h | 72 ++++++ 10 files changed, 499 insertions(+) create mode 100644 arch/arm/dts/tegra210-e2220-1170.dts create mode 100644 board/nvidia/e2220-1170/Kconfig create mode 100644 board/nvidia/e2220-1170/MAINTAINERS create mode 100644 board/nvidia/e2220-1170/Makefile create mode 100644 board/nvidia/e2220-1170/e2220-1170.c create mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h create mode 100644 configs/e2220-1170_defconfig create mode 100644 include/configs/e2220-1170.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ba6355379cba..d8e1841eb4d8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ tegra124-venice2.dtb \
- tegra210-e2220-1170.dtb \ tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-sld3-ref.dtb \ diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210- e2220-1170.dts new file mode 100644 index 000000000000..75efbba1061e --- /dev/null +++ b/arch/arm/dts/tegra210-e2220-1170.dts @@ -0,0 +1,58 @@ +/dts-v1/;
+#include "tegra210.dtsi"
+/ {
- model = "NVIDIA E2220-1170";
- compatible = "nvidia,e2220-1170", "nvidia,tegra210";
- chosen {
stdout-path = &uarta;- };
- aliases {
i2c0 = "/i2c@0,7000d000";sdhci0 = "/sdhci@0,700b0600";sdhci1 = "/sdhci@0,700b0000";usb0 = "/usb@0,7d000000";- };
- memory {
reg = <0x0 0x80000000 0x0 0xc0000000>;- };
- sdhci@0,700b0000 {
status = "okay";cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;power-gpios = <&gpio TEGRA_GPIO(Z, 4)GPIO_ACTIVE_HIGH>;
bus-width = <4>;- };
- sdhci@0,700b0600 {
status = "okay";bus-width = <8>;- };
- i2c@0,7000d000 {
status = "okay";clock-frequency = <400000>;- };
- usb@0,7d000000 {
status = "okay";dr_mode = "peripheral";- };
- clocks {
compatible = "simple-bus";#address-cells = <1>;#size-cells = <0>;clk32k_in: clock@0 {compatible = "fixed-clock";reg = <0>;#clock-cells = <0>;clock-frequency = <32768>;};- };
+}; diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach- tegra/tegra210/Kconfig index 147e6a83d722..9633ba8c629e 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -3,6 +3,11 @@ if TEGRA210 choice prompt "Tegra210 board select"
+config TARGET_E2220_1170
- bool "NVIDIA Tegra210 E2220-1170 base board"
- help
E2220-1170 ERSconfig TARGET_P2571 bool "NVIDIA Tegra210 P2571 base board" help @@ -13,6 +18,7 @@ endchoice config SYS_SOC default "tegra210"
+source "board/nvidia/e2220-1170/Kconfig" source "board/nvidia/p2571/Kconfig"
endif diff --git a/board/nvidia/e2220-1170/Kconfig b/board/nvidia/e2220- 1170/Kconfig new file mode 100644 index 000000000000..0a30f4936223 --- /dev/null +++ b/board/nvidia/e2220-1170/Kconfig @@ -0,0 +1,12 @@ +if TARGET_E2220_1170
+config SYS_BOARD
- default "e2220-1170"
+config SYS_VENDOR
- default "nvidia"
+config SYS_CONFIG_NAME
- default "e2220-1170"
+endif diff --git a/board/nvidia/e2220-1170/MAINTAINERS b/board/nvidia/e2220- 1170/MAINTAINERS new file mode 100644 index 000000000000..0abb37884018 --- /dev/null +++ b/board/nvidia/e2220-1170/MAINTAINERS @@ -0,0 +1,6 @@ +E2220-1170 BOARD +M: Tom Warren twarren@nvidia.com +S: Maintained +F: board/nvidia/e2220-1170/ +F: include/configs/e2220-1170.h +F: configs/e2220-1170_defconfig diff --git a/board/nvidia/e2220-1170/Makefile b/board/nvidia/e2220- 1170/Makefile new file mode 100644 index 000000000000..c956b1972deb --- /dev/null +++ b/board/nvidia/e2220-1170/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2013-2015 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += e2220-1170.o diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220- 1170/e2220-1170.c new file mode 100644 index 000000000000..d66a72e5204c --- /dev/null +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -0,0 +1,51 @@ +/*
- (C) Copyright 2013-2015
- NVIDIA Corporation <www.nvidia.com>
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <i2c.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include "../p2571/max77620_init.h" +#include "pinmux-config-e2220-1170.h"
+void pin_mux_mmc(void) +{
- struct udevice *dev;
- uchar val;
- int ret;
- /* Turn on MAX77620 LDO2 to 3.3V for SD card power */
- debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n",
__func__);
- ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1,
&dev);
- if (ret) {
printf("%s: Cannot find MAX77620 I2C chip\n", __func__);return;- }
- /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- val = 0xF2;
- ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
- if (ret)
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); }+/*
- Routine: pinmux_init
- Description: Do individual peripheral pinmux configs */ void
+pinmux_init(void) {
- pinmux_clear_tristate_input_clamping();
- gpio_config_table(e2220_1170_gpio_inits,
ARRAY_SIZE(e2220_1170_gpio_inits));- pinmux_config_pingrp_table(e2220_1170_pingrps,
ARRAY_SIZE(e2220_1170_pingrps));- pinmux_config_drvgrp_table(e2220_1170_drvgrps,
ARRAY_SIZE(e2220_1170_drvgrps)); }diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h new file mode 100644 index 000000000000..397dc7f44b11 --- /dev/null +++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h @@ -0,0 +1,269 @@ +/*
- Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _PINMUX_CONFIG_E2220_1170_H_ +#define _PINMUX_CONFIG_E2220_1170_H_
+#define GPIO_INIT(_gpio, _init) \
- { \
.gpio = GPIO_P##_gpio, \.init = TEGRA_GPIO_INIT_##_init, \- }
+static const struct tegra_gpio_config e2220_1170_gpio_inits[] = {
- /* gpio, init_val */
- GPIO_INIT(A5, IN),
- GPIO_INIT(A6, IN),
- GPIO_INIT(B4, IN),
- GPIO_INIT(E6, IN),
- GPIO_INIT(G2, OUT0),
- GPIO_INIT(G3, OUT0),
- GPIO_INIT(H0, OUT0),
- GPIO_INIT(H1, OUT0),
- GPIO_INIT(H2, IN),
- GPIO_INIT(H3, OUT0),
- GPIO_INIT(H4, OUT0),
- GPIO_INIT(H5, IN),
- GPIO_INIT(H6, OUT0),
- GPIO_INIT(H7, OUT0),
- GPIO_INIT(I0, OUT0),
- GPIO_INIT(I1, IN),
- GPIO_INIT(I2, OUT0),
- GPIO_INIT(I3, OUT0),
- GPIO_INIT(K0, IN),
- GPIO_INIT(K1, OUT0),
- GPIO_INIT(K2, OUT0),
- GPIO_INIT(K3, OUT0),
- GPIO_INIT(K4, IN),
- GPIO_INIT(K5, OUT0),
- GPIO_INIT(K6, IN),
- GPIO_INIT(K7, OUT0),
- GPIO_INIT(L0, OUT0),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S5, OUT0),
- GPIO_INIT(S6, OUT0),
- GPIO_INIT(S7, OUT0),
- GPIO_INIT(T0, OUT0),
- GPIO_INIT(T1, OUT0),
- GPIO_INIT(V1, OUT0),
- GPIO_INIT(V2, OUT0),
- GPIO_INIT(V3, IN),
- GPIO_INIT(V5, OUT0),
- GPIO_INIT(V6, OUT0),
- GPIO_INIT(X0, IN),
- GPIO_INIT(X1, IN),
- GPIO_INIT(X2, IN),
- GPIO_INIT(X3, IN),
- GPIO_INIT(X4, IN),
- GPIO_INIT(X5, IN),
- GPIO_INIT(X6, IN),
- GPIO_INIT(X7, IN),
- GPIO_INIT(Y0, IN),
- GPIO_INIT(Y1, IN),
- GPIO_INIT(Z0, IN),
- GPIO_INIT(Z4, OUT0),
- GPIO_INIT(BB2, OUT0),
- GPIO_INIT(BB3, OUT0),
- GPIO_INIT(BB4, IN),
- GPIO_INIT(CC1, IN),
- GPIO_INIT(CC5, OUT0),
- GPIO_INIT(CC6, IN),
- GPIO_INIT(CC7, OUT0),
+};
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
- { \
.pingrp = PMUX_PINGRP_##_pingrp, \.func = PMUX_FUNC_##_mux, \.pull = PMUX_PULL_##_pull, \.tristate = PMUX_TRI_##_tri, \.io = PMUX_PIN_##_io, \.od = PMUX_PIN_OD_##_od, \.e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \.lock = PMUX_PIN_LOCK_DEFAULT, \- }
+static const struct pmux_pingrp_config e2220_1170_pingrps[] = {
- /* pingrp, mux, pull, tri, e_input, od, e_io_hv */
- PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT,
DISABLE, NORMAL),
- PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT,
DISABLE, NORMAL),
- PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT,
DISABLE, NORMAL),
- PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT,
DISABLE, NORMAL),
- PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT,
DISABLE, NORMAL),
- PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE,
DEFAULT),
- PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(SPI2_MOSI_PB4, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(SPI1_MOSI_PC0, SPI1, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(SPI1_MISO_PC1, SPI1, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(SPI1_SCK_PC2, SPI1, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(SPI1_CS0_PC3, SPI1, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(SPI1_CS1_PC4, SPI1, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(UART3_CTS_PD4, UARTC, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(DMIC1_DAT_PE1, DMIC1, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(DMIC2_DAT_PE3, DMIC2, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(DMIC3_DAT_PE5, DMIC3, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE,
DEFAULT),
- PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT,
DISABLE, NORMAL),
- PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT,
DISABLE, NORMAL),
- PINCFG(UART2_TX_PG0, UART, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(UART2_RX_PG1, UART, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(UART2_RTS_PG2, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT,
DISABLE, NORMAL),
- PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT,
DISABLE, NORMAL),
- PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT,
DISABLE, NORMAL),
- PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT,
DISABLE, NORMAL),
- PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(PK2, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(PK3, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE,
DEFAULT),
- PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL,
INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL,
INPUT, DISABLE, DEFAULT),
- PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT,
DISABLE, NORMAL),
- PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT,
DISABLE, NORMAL),
- PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(LCD_GPIO1_PV3, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL,
INPUT, DISABLE, DEFAULT),
- PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL,
INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL,
INPUT, DISABLE, DEFAULT),
- PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT,
DISABLE, NORMAL),
- PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL,
INPUT, DISABLE, NORMAL),
- PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE,
DEFAULT),
- PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE,
DEFAULT),
- PINCFG(PZ2, SDMMC3, UP, NORMAL, INPUT, DISABLE,
DEFAULT),
- PINCFG(PZ3, SDMMC3, UP, NORMAL, INPUT, DISABLE,
DEFAULT),
- PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE,
DEFAULT),
- PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT),
- PINCFG(GPIO_X3_AUD_PBB4, DEFAULT, UP, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT,
DISABLE, HIGH),
- PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL,
INPUT, DISABLE, NORMAL),
- PINCFG(SPDIF_OUT_PCC2, SPDIF, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(SPDIF_IN_PCC3, SPDIF, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT,
DISABLE, HIGH),
- PINCFG(USB_VBUS_EN1_PCC5, DEFAULT, NORMAL, NORMAL,
OUTPUT, DISABLE, NORMAL),
- PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT,
DISABLE, NORMAL),
- PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE,
DEFAULT),
- PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT,
DISABLE, DEFAULT),
- PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT,
DISABLE, DEFAULT),
- PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL,
OUTPUT, DISABLE, DEFAULT), +};
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
- { \
.drvgrp = PMUX_DRVGRP_##_drvgrp, \.slwf = _slwf, \.slwr = _slwr, \.drvup = _drvup, \.drvdn = _drvdn, \.lpmd = PMUX_LPMD_##_lpmd, \.schmt = PMUX_SCHMT_##_schmt, \.hsm = PMUX_HSM_##_hsm, \- }
+static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = { };
+#endif /* PINMUX_CONFIG_E2220_1170_H */ diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig new file mode 100644 index 000000000000..a31f5fa78a05 --- /dev/null +++ b/configs/e2220-1170_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA210=y +CONFIG_TARGET_E2220_1170=y +CONFIG_DEFAULT_DEVICE_TREE="tegra210-e2220-1170" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPL_DM=y +CONFIG_SPI_FLASH=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h new file mode 100644 index 000000000000..49eb55ae4b29 --- /dev/null +++ b/include/configs/e2220-1170.h @@ -0,0 +1,72 @@ +/*
- (C) Copyright 2013-2015
- NVIDIA Corporation <www.nvidia.com>
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _E2220_1170_H +#define _E2220_1170_H
+#include <linux/sizes.h>
+/* enable PMIC */ +#define CONFIG_MAX77620_POWER
+#include "tegra210-common.h"
+/* High-level configuration options */ +#define V_PROMPT "Tegra210 (E2220-1170) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA E2220-1170"
+/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C
+/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC
+/* Environment in eMMC, at the end of 2nd "boot sector" */ #define +CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+/* USB2.0 Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB
+/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX
+/* General networking support */ +#define CONFIG_CMD_DHCP
+#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h"
+#define COUNTER_FREQUENCY 38400000
+#endif /* _E2220_1170_H */
1.9.1
The series, Acked-by: Tom Warren twarren@nvidia.com
-- nvpublic
participants (3)
-
Stephen Warren -
Thierry Reding -
Tom Warren