also preparation for using hwconfig and device tree support

Signed-off-by: Klaus Heydeck heydeck@kieback-peter.de

diff -purN u-boot.git/board/kup/common/kup.c u-boot/board/kup/common/kup.c --- u-boot.git/board/kup/common/kup.c 2010-02-16 09:02:08.000000000 +0100 +++ u-boot/board/kup/common/kup.c 2010-02-17 13:03:51.000000000 +0100 @@ -24,6 +24,24 @@ #include <common.h> #include <mpc8xx.h> #include "kup.h" +#ifdef CONFIG_KUP4_LOGO + #include "s1d13706.h" +#endif + +#undef DEBUG +#ifdef DEBUG +# define debugk(fmt,args...) printf(fmt ,##args) +#else +# define debugk(fmt,args...) +#endif + +#define PRINTF(fmt,args...) printf(fmt ,##args) + +typedef struct { + volatile unsigned char *VmemAddr; + volatile unsigned char *RegAddr; +} FB_INFO_S1D13xxx; +

int misc_init_f (void) { @@ -31,7 +49,7 @@ int misc_init_f (void) volatile sysconf8xx_t *siu = &immap->im_siu_conf;

while (siu->sc_sipend & 0x20000000) { - /* printf("waiting for 5V VCC\n"); */ + debugk("waiting for 5V VCC\n"); ; }

@@ -40,6 +58,14 @@ int misc_init_f (void) immap->im_ioport.iop_papar &= ~(PA_RS485); immap->im_ioport.iop_paodr &= ~(PA_RS485); immap->im_ioport.iop_padir |= (PA_RS485); + + /* IO Reset min 1 msec */ + immap->im_ioport.iop_padat |= (PA_RESET_IO_01 | PA_RESET_IO_02); + immap->im_ioport.iop_papar &= ~(PA_RESET_IO_01 | PA_RESET_IO_02); + immap->im_ioport.iop_paodr &= ~(PA_RESET_IO_01 | PA_RESET_IO_02); + immap->im_ioport.iop_padir |= (PA_RESET_IO_01 | PA_RESET_IO_02); + udelay(1000); + immap->im_ioport.iop_padat &= ~(PA_RESET_IO_01 | PA_RESET_IO_02); return (0); }

@@ -70,3 +96,159 @@ void poweron_key (void) else setenv ("key1", "on"); } + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed (void) +{ + return (0); +} +#endif + +unsigned char swapbyte(unsigned char c) +{ + unsigned char result=0; + int i=0; + for(i=0;i<8;++i){ + result=result<<1; + result|=(c&1); + c=c>>1; + } + return result; +} + +#ifdef CONFIG_KUP4_LOGO + +void lcd_logo (bd_t * bd) +{ + FB_INFO_S1D13xxx fb_info; + S1D_INDEX s1dReg; + S1D_VALUE s1dValue; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl; + ushort i; + uchar *fb; + int rs, gs, bs; + int r = 8, g = 8, b = 4; + int r1, g1, b1; + + immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM); + immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM); + immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */ + immr->im_cpm.cp_pbdir |= (PB_LCD_PWM); + +/*----------------------------------------------------------------------------- */ +/* Initialize the chip and the frame buffer driver. */ +/*----------------------------------------------------------------------------- */ + memctl = &immr->im_memctl; + + /* + * Init ChipSelect #5 (S1D13768) + */ + memctl->memc_or5 = CONFIG_SYS_OR5; + memctl->memc_br5 = CONFIG_SYS_BR5; + __asm__ ("eieio"); + + fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR); + fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR); + + if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28) + || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) { + printf ("Warning:LCD Controller S1D13706 not found\n"); + setenv ("lcd", "none"); + return; + } + ((S1D_VALUE*)fb_info.RegAddr)[0xA8] = 0x00; + ((S1D_VALUE*)fb_info.RegAddr)[0xA9] = 0x80; + unsigned char s1d1gpio = ((S1D_VALUE*)fb_info.RegAddr)[0xAC]; + /* printf("s1d1gpio:0x%02X\n",s1d1gpio); */ + s1d1gpio &= 0x1E; + s1d1gpio >>= 1; + + /* init controller */ + switch (s1d1gpio){ + + case 0x02: /* STN */ + for (i = 0; i < sizeof (aS1DRegs_stn) / sizeof (aS1DRegs_stn[0]); i++) + { + s1dReg = aS1DRegs_stn[i].Index; + s1dValue = aS1DRegs_stn[i].Value; + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = s1dValue; + } + switch (bd->bi_busfreq){ + case 40000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41; + break; + case 48000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; + break; + default: + printf ("KUP4 S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); + case 64000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66; + break; + } + break; + + case 0x00: /* TFT */ + for (i = 0; i < sizeof (aS1DRegs_tft) / sizeof (aS1DRegs_tft[0]); i++) + { + s1dReg = aS1DRegs_tft[i].Index; + s1dValue = aS1DRegs_tft[i].Value; + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = s1dValue; + } + switch (bd->bi_busfreq){ + default: + printf ("KUP4 S1D1: unknown busfrequency: %ld assuming 40 MHz\n", bd->bi_busfreq); + case 40000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30; + break; + } + break; + + case 0x01: /* mono */ + for (i = 0; i < sizeof (aS1DRegs_mono) / sizeof (aS1DRegs_mono[0]); i++) + { + s1dReg = aS1DRegs_mono[i].Index; + s1dValue = aS1DRegs_mono[i].Value; + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = s1dValue; + } + switch (bd->bi_busfreq){ + default: + printf ("KUP4 S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); + case 40000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; + break; + } + break; + default: + printf("Unknown LCD config!!!\n"); + break; + } + + /* create and set colormap */ + rs = 256 / (r - 1); + gs = 256 / (g - 1); + bs = 256 / (b - 1); + for (i = 0; i < 256; i++) { + r1 = (rs * ((i / (g * b)) % r)) * 255; + g1 = (gs * ((i / b) % g)) * 255; + b1 = (bs * ((i) % b)) * 255; + debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4); + S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4), + (b1 >> 4)); + } + + /* copy bitmap */ + fb = (uchar *) (fb_info.VmemAddr); + memcpy (fb, (uchar *) CONFIG_KUP4_LOGO, 320 * 240); +} +#endif /* CONFIG_KUP4_LOGO */ diff -purN u-boot.git/board/kup/common/kup.h u-boot/board/kup/common/kup.h --- u-boot.git/board/kup/common/kup.h 2010-02-16 09:02:08.000000000 +0100 +++ u-boot/board/kup/common/kup.h 2010-02-17 13:03:51.000000000 +0100 @@ -25,22 +25,35 @@ #define __KUP_H

#define PA_8 0x0080 +#define PA_9 0x0040 +#define PA_10 0x0020 #define PA_11 0x0010 #define PA_12 0x0008

#define PB_14 0x00020000 +#define PB_15 0x00010000 +#define PB_16 0x00008000 #define PB_17 0x00004000

#define PC_9 0x0040

#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ -#define PA_LED_YELLOW PA_8 +#define PA_LED_YELLOW PA_8 /* */ +#define PA_RESET_IO_01 PA_9 /* Reset left IO */ +#define PA_RESET_IO_02 PA_10 /* Reset right IO */ +#define PB_PROG_IO_01 PB_15 /* Program left IO */ +#define PB_PROG_IO_02 PB_16 /* Program right IO */ #define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off*/ #define PB_LCD_PWM PB_17 /* PB 17 */ #define PC_SWITCH1 PC_9 /* Reboot switch */

-extern void poweron_key (void); +#define CONFIG_KUP4_LOGO 0x40050000 /* Address of logo bitmap */

-extern void load_sernum_ethaddr(void); +extern void poweron_key (void); +extern unsigned char swapbyte(unsigned char c); +void lcd_logo (bd_t * bd); +extern int read_diag (void); +extern void load_sernum_ethaddr (void);

#endif /* __KUP_H */ + diff -purN u-boot.git/board/kup/common/s1d13706.h u-boot/board/kup/common/s1d13706.h --- u-boot.git/board/kup/common/s1d13706.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/kup/common/s1d13706.h 2010-02-17 13:03:51.000000000 +0100 @@ -0,0 +1,237 @@ +/*---------------------------------------------------------------------------- */ +/* */ +/* File generated by S1D13706CFG.EXE */ +/* */ +/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ +/* All rights reserved. */ +/* */ +/*---------------------------------------------------------------------------- */ + +/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ + +#define S1D_DISPLAY_WIDTH 320 +#define S1D_DISPLAY_HEIGHT 240 +#define S1D_DISPLAY_BPP 8 +#define S1D_DISPLAY_SCANLINE_BYTES 320 +#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L +#define S1D_PHYSICAL_VMEM_SIZE 0x14000L +#define S1D_PHYSICAL_REG_ADDR 0x80080000L +#define S1D_PHYSICAL_REG_SIZE 0x100 +#define S1D_DISPLAY_PCLK 6250 +#define S1D_PALETTE_SIZE 256 +#define S1D_REGDELAYOFF 0xFFFE +#define S1D_REGDELAYON 0xFFFF + +#define S1D_WRITE_PALETTE(p,i,r,g,b) \ +{ \ + ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ + ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ + ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ + ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ +} + +#define S1D_READ_PALETTE(p,i,r,g,b) \ +{ \ + ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ + r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ + g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ + b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ +} + +typedef unsigned short S1D_INDEX; +typedef unsigned char S1D_VALUE; + + +typedef struct +{ + S1D_INDEX Index; + S1D_VALUE Value; +} S1D_REGS; + + +static S1D_REGS aS1DRegs_stn[] = +{ + {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ + {0x10,0xD0}, /* PANEL Type Register */ + {0x11,0x00}, /* MOD Rate Register */ + {0x14,0x27}, /* Horizontal Display Period Register */ + {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ + {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ + {0x18,0xF0}, /* Vertical Total Register 0 */ + {0x19,0x00}, /* Vertical Total Register 1 */ + {0x1C,0xEF}, /* Vertical Display Period Register 0 */ + {0x1D,0x00}, /* Vertical Display Period Register 1 */ + {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ + {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ + {0x20,0x87}, /* Horizontal Sync Pulse Width Register */ + {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ + {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ + {0x24,0x80}, /* Vertical Sync Pulse Width Register */ + {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ + {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ + {0x70,0x83}, /* Display Mode Register */ + {0x71,0x00}, /* Special Effects Register */ + {0x74,0x00}, /* Main Window Display Start Address Register 0 */ + {0x75,0x00}, /* Main Window Display Start Address Register 1 */ + {0x76,0x00}, /* Main Window Display Start Address Register 2 */ + {0x78,0x50}, /* Main Window Address Offset Register 0 */ + {0x79,0x00}, /* Main Window Address Offset Register 1 */ + {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ + {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ + {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ + {0x80,0x50}, /* Sub Window Address Offset Register 0 */ + {0x81,0x00}, /* Sub Window Address Offset Register 1 */ + {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ + {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ + {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ + {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ + {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ + {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ + {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ + {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ + {0xA0,0x00}, /* Power Save Config Register */ + {0xA1,0x00}, /* CPU Access Control Register */ + {0xA2,0x00}, /* Software Reset Register */ + {0xA3,0x00}, /* BIG Endian Support Register */ + {0xA4,0x00}, /* Scratch Pad Register 0 */ + {0xA5,0x00}, /* Scratch Pad Register 1 */ + {0xB0,0x10}, /* PWM CV Clock Control Register */ + {0xB1,0x80}, /* PWM CV Clock Config Register */ + {0xB2,0x00}, /* CV Clock Burst Length Register */ + {0xAD,0x80}, /* reset seq */ + {0x70,0x03}, +}; + +static S1D_REGS aS1DRegs_tft[] = +{ + {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ + {0x05,0x42}, /* PCLK Config Register */ + {0x10,0x61}, /* PANEL Type Register */ + {0x11,0x00}, /* MOD Rate Register */ + {0x12,0x30}, /* Horizontal Total Register */ + {0x14,0x27}, /* Horizontal Display Period Register */ + {0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */ + {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ + {0x18,0xFA}, /* Vertical Total Register 0 */ + {0x19,0x00}, /* Vertical Total Register 1 */ + {0x1C,0xEF}, /* Vertical Display Period Register 0 */ + {0x1D,0x00}, /* Vertical Display Period Register 1 */ + {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ + {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ + {0x20,0x07}, /* Horizontal Sync Pulse Width Register */ + {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ + {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ + {0x24,0x00}, /* Vertical Sync Pulse Width Register */ + {0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */ + {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ + {0x70,0x03}, /* Display Mode Register */ + {0x71,0x00}, /* Special Effects Register */ + {0x74,0x00}, /* Main Window Display Start Address Register 0 */ + {0x75,0x00}, /* Main Window Display Start Address Register 1 */ + {0x76,0x00}, /* Main Window Display Start Address Register 2 */ + {0x78,0x50}, /* Main Window Address Offset Register 0 */ + {0x79,0x00}, /* Main Window Address Offset Register 1 */ + {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ + {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ + {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ + {0x80,0x50}, /* Sub Window Address Offset Register 0 */ + {0x81,0x00}, /* Sub Window Address Offset Register 1 */ + {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ + {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ + {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ + {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ + {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ + {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ + {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ + {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ + {0xA0,0x00}, /* Power Save Config Register */ + {0xA1,0x00}, /* CPU Access Control Register */ + {0xA2,0x00}, /* Software Reset Register */ + {0xA3,0x00}, /* BIG Endian Support Register */ + {0xA4,0x00}, /* Scratch Pad Register 0 */ + {0xA5,0x00}, /* Scratch Pad Register 1 */ + {0xB0,0x10}, /* PWM CV Clock Control Register */ + {0xB1,0x80}, /* PWM CV Clock Config Register */ + {0xB2,0x00}, /* CV Clock Burst Length Register */ + {0xAD,0x80}, /* reset seq */ + {0x70,0x03}, +}; + + + + +/* + MOD Rate = 200Hz (bei 60Hz Framerate) 60 * 3.33 = 240/3.33 = 72 (/2 weil togglen gemeint ist) = 36 = 0x24 + MOD Rate = 400Hz (bei 60Hz Framerate) 60 * 3.33 = 36 (/2 weil togglen gemeint ist) = 18 = 0x12 + MOD Rate 300Hz = 60Hz*5 = 240/5 = 48 (/2 weil togglen gemeint ist) = 24 = 0x18 + + Framerate Powertip-PS320240 : 55..75Hz + + Für MPC859 mit 64/128MHz + +*/ + +static S1D_REGS aS1DRegs_mono[] = +{ + {0x70,0x80}, + {0x04,0x10}, + {0x05,0x30}, + {0x10,0x00}, + {0x11,0x00}, + {0x12,0x30}, + {0x14,0x27}, + {0x16,0x00}, + {0x17,0x00}, + {0x18,0xf0}, + {0x19,0x00}, + {0x1c,0xef}, + {0x1d,0x00}, + {0x1e,0x00}, + {0x1f,0x00}, + {0x20,0x87}, + {0x22,0x00}, + {0x23,0x00}, + {0x24,0x80}, + {0x26,0x01}, + {0x27,0x00}, + {0x70,0x82}, + {0x71,0x00}, + {0x74,0x00}, + {0x75,0x00}, + {0x76,0x00}, + {0x78,0x50}, + {0x79,0x00}, + {0x7c,0x00}, + {0x7d,0x00}, + {0x7e,0x00}, + {0x80,0x50}, + {0x81,0x00}, + {0x84,0x00}, + {0x85,0x00}, + {0x88,0x00}, + {0x89,0x00}, + {0x8c,0x4f}, + {0x8d,0x00}, + {0x90,0xef}, + {0x91,0x00}, + {0xa0,0x00}, + {0xa1,0x00}, + {0xa2,0x00}, + {0xa3,0x00}, + {0xa4,0x00}, + {0xa5,0x00}, + {0xb0,0x11}, + {0xb1,0x08}, + {0xb2,0x01}, + {0xb3,0x00}, + {0xa8,0x01}, + {0xa9,0x80}, + {0xac,0x01}, + {0xad,0x00}, + {0xad,0x80}, + {0x70,0x53}, + {0xb0,0x13}, + {0xb1,0x4e}, + {0xb2,0x01}, + {0xb3,0x00}, +}; diff -purN u-boot.git/board/kup/kup4k/kup4k.c u-boot/board/kup/kup4k/kup4k.c --- u-boot.git/board/kup/kup4k/kup4k.c 2010-02-16 09:02:08.000000000 +0100 +++ u-boot/board/kup/kup4k/kup4k.c 2010-02-17 13:03:51.000000000 +0100 @@ -23,32 +23,20 @@ */

#include <common.h> +#include <command.h> #include <mpc8xx.h> +#include <hwconfig.h> +#include <i2c.h> #include "../common/kup.h" -#ifdef CONFIG_KUP4K_LOGO - #include "s1d13706.h" -#endif - -DECLARE_GLOBAL_DATA_PTR;

-#undef DEBUG -#ifdef DEBUG -# define debugk(fmt,args...) printf(fmt ,##args) -#else -# define debugk(fmt,args...) +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> #endif

-typedef struct { - volatile unsigned char *VmemAddr; - volatile unsigned char *RegAddr; -} FB_INFO_S1D13xxx; - - -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR;

-#ifdef CONFIG_KUP4K_LOGO -void lcd_logo(bd_t *bd); -#endif +int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);

/* ------------------------------------------------------------------------- */ @@ -60,7 +48,7 @@ const uint sdram_table[] = { * Single Read. (Offset 0 in UPMA RAM) */ 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ + 0x1FF77C47, /* last */

/* * SDRAM Initialization (offset 5 in UPMA RAM) @@ -70,28 +58,28 @@ const uint sdram_table[] = { * sequence, which is executed by a RUN command. * */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */

/* * Burst Read. (Offset 8 in UPMA RAM) */ 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

/* * Single Write. (Offset 18 in UPMA RAM) */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

/* * Burst Write. (Offset 20 in UPMA RAM) */ 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

@@ -99,55 +87,87 @@ const uint sdram_table[] = { * Refresh (Offset 30 in UPMA RAM) */ 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

/* * Exception. (Offset 3c in UPMA RAM) */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, };

/* ------------------------------------------------------------------------- */

- /* * Check Board Identity: */

int checkboard (void) { + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - uchar *latch,rev,mod; - - /* - * Init ChipSelect #4 (CAN + HW-Latch) - */ - immap->im_memctl.memc_or4 = 0xFFFF8926; - immap->im_memctl.memc_br4 = 0x90000401; - __asm__ ("eieio"); - latch=(uchar *)0x90000200; - rev = (*latch & 0xF8) >> 3; - mod=(*latch & 0x03); - printf ("Board: KUP4K Rev %d.%d\n",rev,mod); - return (0); + uchar *latch,rev,mod,tmp,pcf,ak_rev,ak_mod; + + /* + * Init ChipSelect #4 (CAN + HW-Latch) + */ + immap->im_memctl.memc_or4 = CONFIG_SYS_OR4; + immap->im_memctl.memc_br4 = CONFIG_SYS_BR4; + __asm__ ("eieio"); + latch = (uchar *)0x90000200; + tmp = swapbyte (*latch); + rev = (tmp & 0xF8) >> 3; + mod = (tmp & 0x07); + + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + if (read_diag()) + gd->flags &= ~GD_FLG_SILENT; + + printf ("Board: KUP4K Rev %d.%d AK:",rev,mod); + + /* TI Application report: Before using the IO as an input, + * a high must be written to the IO first + */ + pcf = 0xFF; + i2c_write (0x21, 0, 0 , &pcf, 1); + if (i2c_read (0x21, 0, 0, &pcf, 1)) { + puts ("n/a\n"); + } + else { + ak_rev = (pcf & 0xF8) >> 3; + ak_mod = (pcf & 0x07); + printf ("%d.%d\n",ak_rev,ak_mod); + } + return (0); }

/* ------------------------------------------------------------------------- */

+ phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0 = 0; - long int size_b1 = 0; - long int size_b2 = 0; + long int size = 0; + uchar *latch,rev,mod,tmp;

- upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); + /* + * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision + * Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB + */ + immap->im_memctl.memc_or4 = CONFIG_SYS_OR4; + immap->im_memctl.memc_br4 = CONFIG_SYS_BR4; + __asm__ ("eieio"); + latch = (uchar *)0x90000200; + tmp = swapbyte (*latch); + rev = (tmp & 0xF8) >> 3; + mod = (tmp & 0x07);

+ upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); /* * Preliminary prescaler for refresh (depends on number of * banks): This value is selected for four cycles every 62.4 us @@ -158,20 +178,12 @@ phys_size_t initdram (int board_type)

memctl->memc_mar = 0x00000088;

- /* - * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ -/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; */ -/* memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */ - -/* memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; */ -/* memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; */ - - - memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ - + if(rev >= 7){ + memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ + } + else{ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + } udelay (200);

/* perform SDRAM initializsation sequence */ @@ -200,49 +212,53 @@ phys_size_t initdram (int board_type) memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ udelay (1000);

-#if 0 /* 3 x 8MB */ - size_b0 = 0x00800000; - size_b1 = 0x00800000; - size_b2 = 0x00800000; memctl->memc_mptpr = CONFIG_SYS_MPTPR; udelay (1000); - memctl->memc_or1 = 0xFF800A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFF000A00; - memctl->memc_br2 = 0x00800081; - memctl->memc_or3 = 0xFE000A00; - memctl->memc_br3 = 0x01000081; -#else /* 3 x 16 MB */ - size_b0 = 0x01000000; - size_b1 = 0x01000000; - size_b2 = 0x01000000; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - udelay (1000); - memctl->memc_or1 = 0xFF000A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFE000A00; - memctl->memc_br2 = 0x01000081; - memctl->memc_or3 = 0xFC000A00; - memctl->memc_br3 = 0x02000081; -#endif - - udelay (10000); - - return (size_b0 + size_b1 + size_b2); + if(rev >= 7){ + char* arguments[3]={"memtest","0x00000000","0x05FFFFFF"}; + char *s; + size = 32 * 3 * 1024 * 1024; + memctl->memc_or1 = CONFIG_SYS_OR1_9COL; + memctl->memc_br1 = CONFIG_SYS_BR1_9COL; + memctl->memc_or2 = CONFIG_SYS_OR2_9COL; + memctl->memc_br2 = CONFIG_SYS_BR2_9COL; + memctl->memc_or3 = CONFIG_SYS_OR3_9COL; + memctl->memc_br3 = CONFIG_SYS_BR3_9COL; + s = getenv ("memtest"); + if(s) + do_mem_mtest(0,0,3,arguments); + } + else{ + char* arguments[3]={"memtest","0x00000000","0x02FFFFFF"}; + char *s; + size = 16 * 3 * 1024 * 1024; + memctl->memc_or1 = CONFIG_SYS_OR1_8COL; + memctl->memc_br1 = CONFIG_SYS_BR1_8COL; + memctl->memc_or2 = CONFIG_SYS_OR2_8COL; + memctl->memc_br2 = CONFIG_SYS_BR2_8COL; + memctl->memc_or3 = CONFIG_SYS_OR3_8COL; + memctl->memc_br3 = CONFIG_SYS_BR3_8COL; + s = getenv ("memtest"); + if(s) + do_mem_mtest(0,0,3,arguments); + } + return (size); }

/* ------------------------------------------------------------------------- */

+ int misc_init_r (void) { -#ifdef CONFIG_STATUS_LED + DECLARE_GLOBAL_DATA_PTR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -#endif -#ifdef CONFIG_KUP4K_LOGO + +#ifdef CONFIG_KUP4_LOGO bd_t *bd = gd->bd;

lcd_logo (bd); -#endif /* CONFIG_KUP4K_LOGO */ +#endif #ifdef CONFIG_IDE_LED /* Configure PA8 as output port */ immap->im_ioport.iop_padir |= 0x80; @@ -253,152 +269,156 @@ int misc_init_r (void) load_sernum_ethaddr(); setenv("hw","4k"); poweron_key(); +#if 0 + if ((char *p = getenv ("contrast")) != NULL) { + char buffer[64]; + unsigned long contrast = simple_strtoul (p, NULL, 10) * 127 / 100; + sprintf(buffer,"%x",contrast); + char* arguments[4]={"imw","2E","0.0",buffer}; + do_i2c_mw(0,0,4,arguments); + } +#endif return (0); }

-#ifdef CONFIG_KUP4K_LOGO -

-void lcd_logo (bd_t * bd) +int read_diag (void) { - FB_INFO_S1D13xxx fb_info; - S1D_INDEX s1dReg; - S1D_VALUE s1dValue; - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl; - ushort i; - uchar *fb; - int rs, gs, bs; - int r = 8, g = 8, b = 4; - int r1, g1, b1; - int n; - char tmp[64]; /* long enough for environment variables */ - int tft = 0; - - immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM); - immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM); - immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */ - immr->im_cpm.cp_pbdir |= (PB_LCD_PWM); - -/*----------------------------------------------------------------------------- */ -/* Initialize the chip and the frame buffer driver. */ -/*----------------------------------------------------------------------------- */ - memctl = &immr->im_memctl; - - - /* - * Init ChipSelect #5 (S1D13768) - */ - memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */ - memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */ - __asm__ ("eieio"); - - fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR); - fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR); - - if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28) - || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) { - printf ("Warning:LCD Controller S1D13706 not found\n"); - setenv ("lcd", "none"); - return; - } - - - for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) { - s1dReg = aS1DRegs_prelimn[i].Index; - s1dValue = aS1DRegs_prelimn[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = - s1dValue; - } - - - n = getenv_r ("lcd", tmp, sizeof (tmp)); - if (n > 0) { - if (!strcmp ("tft", tmp)) - tft = 1; - else - tft = 0; - } -#if 0 - if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04) - tft = 0; - else - tft = 1; -#endif - - debugk ("Port=0x%02x -> TFT=%d\n", tft, - ((S1D_VALUE *) fb_info.RegAddr)[0xAC]); - - /* init controller */ - if (!tft) { - for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) { - s1dReg = aS1DRegs_stn[i].Index; - s1dValue = aS1DRegs_stn[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_stn[i].Index, - aS1DRegs_stn[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] = - s1dValue; + #define PC4 0x0800 + #define PC5 0x0400 + int diag; + + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + immr->im_ioport.iop_pcdir &= ~PC4; /* input */ + immr->im_ioport.iop_pcpar &= ~PC4; /* gpio */ + immr->im_ioport.iop_pcdir |= PC5; /* output */ + immr->im_ioport.iop_pcpar &= ~PC4; /* gpio */ + immr->im_ioport.iop_pcdat |= PC5; /* 1 */ + udelay(500); + if(immr->im_ioport.iop_pcdat & PC4){ + immr->im_ioport.iop_pcdat &= ~PC5; /* 0 */ + udelay(500); + if(immr->im_ioport.iop_pcdat & PC4){ + diag=0; } - n = getenv_r ("contrast", tmp, sizeof (tmp)); - ((S1D_VALUE *) fb_info.RegAddr)[0xB3] = - (n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0; - switch (bd->bi_busfreq) { - case 40000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41; - break; - case 48000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; - break; - default: - printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); - case 64000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66; - break; + else{ + diag=1; } - /* setenv("lcd","stn"); */ - } else { - for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) { - s1dReg = aS1DRegs_tft[i].Index; - s1dValue = aS1DRegs_tft[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_tft[i].Index, - aS1DRegs_tft[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = - s1dValue; - } - - switch (bd->bi_busfreq) { - default: - printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); - case 40000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30; - break; - } - /* setenv("lcd","tft"); */ } - - /* create and set colormap */ - rs = 256 / (r - 1); - gs = 256 / (g - 1); - bs = 256 / (b - 1); - for (i = 0; i < 256; i++) { - r1 = (rs * ((i / (g * b)) % r)) * 255; - g1 = (gs * ((i / b) % g)) * 255; - b1 = (bs * ((i) % b)) * 255; - debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4); - S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4), - (b1 >> 4)); + else{ + diag=0; } - - /* copy bitmap */ - fb = (uchar *) (fb_info.VmemAddr); - memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240); + immr->im_ioport.iop_pcdir &= ~PC5; /* input */ + return (diag); } -#endif /* CONFIG_KUP4K_LOGO */ + + +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +int fdt_set_node_and_value (void *blob, + char *nodename, + char *regname, + void *var, + int size) +{ + int ret = 0; + int nodeoffset = 0; + + nodeoffset = fdt_path_offset (blob, nodename); + if (nodeoffset >= 0) { + ret = fdt_setprop (blob, nodeoffset, regname, var, + size); + if (ret < 0) { + printf("ft_blob_update(): " + "cannot set %s/%s property; err: %s\n", + nodename, regname, fdt_strerror (ret)); + } + } else { + printf("ft_blob_update(): " + "cannot find %s node err:%s\n", + nodename, fdt_strerror (nodeoffset)); + } + return ret; +} + +int fdt_del_node_name (void *blob, char *nodename) { + int ret = 0; + int nodeoffset = 0; + + nodeoffset = fdt_path_offset (blob, nodename); + if (nodeoffset >= 0) { + ret = fdt_del_node (blob, nodeoffset); + if (ret < 0) { + printf("%s: cannot delete %s; err: %s\n", + __func__, nodename, fdt_strerror (ret)); + } + } else { + printf("%s: cannot find %s node err:%s\n", + __func__, nodename, fdt_strerror (nodeoffset)); + } + return ret; +} + +int fdt_del_prop_name (void *blob, char *nodename, char *propname) { + int ret = 0; + int nodeoffset = 0; + + nodeoffset = fdt_path_offset (blob, nodename); + if (nodeoffset >= 0) { + ret = fdt_delprop (blob, nodeoffset, propname); + if (ret < 0) { + printf("%s: cannot delete %s %s; err: %s\n", + __func__, nodename, propname, + fdt_strerror (ret)); + } + } else { + printf("%s: cannot find %s node err:%s\n", + __func__, nodename, fdt_strerror (nodeoffset)); + } + return ret; +} + +/* + * update "brg" property in the blob + */ +void ft_blob_update (void *blob, bd_t *bd) { + uchar enetaddr[6]; + ulong brg_data = 0; + + /* BRG */ + brg_data = cpu_to_be32(bd->bi_busfreq); + fdt_set_node_and_value(blob, + "/soc/cpm", "brg-frequency", + &brg_data, sizeof(brg_data)); + + /* MAC addr */ + if (eth_getenv_enetaddr("ethaddr", enetaddr)) { + fdt_set_node_and_value(blob, + "ethernet0", "local-mac-address", + enetaddr, sizeof(u8) * 6); + } + + if (hwconfig_arg_cmp("fec", "off")) { + /* no FEC on this plattform, delete DTS nodes */ + fdt_del_node_name (blob, "ethernet1"); + fdt_del_node_name (blob, "mdio1"); + /* also the aliases entries */ + fdt_del_prop_name (blob, "/aliases", "ethernet1"); + fdt_del_prop_name (blob, "/aliases", "mdio1"); + } else { + /* adjust local-mac-address for FEC ethernet */ + if (eth_getenv_enetaddr("eth1addr", enetaddr)) { + fdt_set_node_and_value(blob, + "ethernet1", "local-mac-address", + enetaddr, sizeof(u8) * 6); + } + } +} + +void ft_board_setup(void *blob, bd_t *bd) { + ft_cpu_setup(blob, bd); + ft_blob_update(blob, bd); +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff -purN u-boot.git/board/kup/kup4k/s1d13706.h u-boot/board/kup/kup4k/s1d13706.h --- u-boot.git/board/kup/kup4k/s1d13706.h 2010-02-16 09:02:08.000000000 +0100 +++ u-boot/board/kup/kup4k/s1d13706.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,174 +0,0 @@ -/*---------------------------------------------------------------------------- */ -/* */ -/* File generated by S1D13706CFG.EXE */ -/* */ -/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ -/* All rights reserved. */ -/* */ -/*---------------------------------------------------------------------------- */ - -/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ - -#define S1D_DISPLAY_WIDTH 320 -#define S1D_DISPLAY_HEIGHT 240 -#define S1D_DISPLAY_BPP 8 -#define S1D_DISPLAY_SCANLINE_BYTES 320 -#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L -#define S1D_PHYSICAL_VMEM_SIZE 0x14000L -#define S1D_PHYSICAL_REG_ADDR 0x80080000L -#define S1D_PHYSICAL_REG_SIZE 0x100 -#define S1D_DISPLAY_PCLK 6250 -#define S1D_PALETTE_SIZE 256 -#define S1D_REGDELAYOFF 0xFFFE -#define S1D_REGDELAYON 0xFFFF - -#define S1D_WRITE_PALETTE(p,i,r,g,b) \ -{ \ - ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ - ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ - ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ - ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ -} - -#define S1D_READ_PALETTE(p,i,r,g,b) \ -{ \ - ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ - r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ - g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ - b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ -} - -typedef unsigned short S1D_INDEX; -typedef unsigned char S1D_VALUE; - - -typedef struct -{ - S1D_INDEX Index; - S1D_VALUE Value; -} S1D_REGS; - - -static S1D_REGS aS1DRegs_prelimn[] = -{ - {0x10,0x00}, /* PANEL Type Register */ - {0xA8,0x00}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - -}; - -static S1D_REGS aS1DRegs_stn[] = -{ - {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ - {0x10,0xD0}, /* PANEL Type Register */ - {0x11,0x00}, /* MOD Rate Register */ - {0x14,0x27}, /* Horizontal Display Period Register */ - {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ - {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ - {0x18,0xF0}, /* Vertical Total Register 0 */ - {0x19,0x00}, /* Vertical Total Register 1 */ - {0x1C,0xEF}, /* Vertical Display Period Register 0 */ - {0x1D,0x00}, /* Vertical Display Period Register 1 */ - {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ - {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ - {0x20,0x87}, /* Horizontal Sync Pulse Width Register */ - {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ - {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ - {0x24,0x80}, /* Vertical Sync Pulse Width Register */ - {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ - {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ - {0x70,0x83}, /* Display Mode Register */ - {0x71,0x00}, /* Special Effects Register */ - {0x74,0x00}, /* Main Window Display Start Address Register 0 */ - {0x75,0x00}, /* Main Window Display Start Address Register 1 */ - {0x76,0x00}, /* Main Window Display Start Address Register 2 */ - {0x78,0x50}, /* Main Window Address Offset Register 0 */ - {0x79,0x00}, /* Main Window Address Offset Register 1 */ - {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ - {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ - {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ - {0x80,0x50}, /* Sub Window Address Offset Register 0 */ - {0x81,0x00}, /* Sub Window Address Offset Register 1 */ - {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ - {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ - {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ - {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ - {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ - {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ - {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ - {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ - {0xA0,0x00}, /* Power Save Config Register */ - {0xA1,0x00}, /* CPU Access Control Register */ - {0xA2,0x00}, /* Software Reset Register */ - {0xA3,0x00}, /* BIG Endian Support Register */ - {0xA4,0x00}, /* Scratch Pad Register 0 */ - {0xA5,0x00}, /* Scratch Pad Register 1 */ - {0xA8,0x01}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - {0xAC,0x01}, /* GPIO Status Control Register 0 */ - {0xAD,0x00}, /* GPIO Status Control Register 1 */ - {0xB0,0x10}, /* PWM CV Clock Control Register */ - {0xB1,0x80}, /* PWM CV Clock Config Register */ - {0xB2,0x00}, /* CV Clock Burst Length Register */ - {0xAD,0x80}, /* reset seq */ - {0x70,0x03}, -}; - -static S1D_REGS aS1DRegs_tft[] = -{ - {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ - {0x05,0x42}, /* PCLK Config Register */ - {0x10,0x61}, /* PANEL Type Register */ - {0x11,0x00}, /* MOD Rate Register */ - {0x12,0x30}, /* Horizontal Total Register */ - {0x14,0x27}, /* Horizontal Display Period Register */ - {0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */ - {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ - {0x18,0xFA}, /* Vertical Total Register 0 */ - {0x19,0x00}, /* Vertical Total Register 1 */ - {0x1C,0xEF}, /* Vertical Display Period Register 0 */ - {0x1D,0x00}, /* Vertical Display Period Register 1 */ - {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ - {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ - {0x20,0x07}, /* Horizontal Sync Pulse Width Register */ - {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ - {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ - {0x24,0x00}, /* Vertical Sync Pulse Width Register */ - {0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */ - {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ - {0x70,0x03}, /* Display Mode Register */ - {0x71,0x00}, /* Special Effects Register */ - {0x74,0x00}, /* Main Window Display Start Address Register 0 */ - {0x75,0x00}, /* Main Window Display Start Address Register 1 */ - {0x76,0x00}, /* Main Window Display Start Address Register 2 */ - {0x78,0x50}, /* Main Window Address Offset Register 0 */ - {0x79,0x00}, /* Main Window Address Offset Register 1 */ - {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ - {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ - {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ - {0x80,0x50}, /* Sub Window Address Offset Register 0 */ - {0x81,0x00}, /* Sub Window Address Offset Register 1 */ - {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ - {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ - {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ - {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ - {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ - {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ - {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ - {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ - {0xA0,0x00}, /* Power Save Config Register */ - {0xA1,0x00}, /* CPU Access Control Register */ - {0xA2,0x00}, /* Software Reset Register */ - {0xA3,0x00}, /* BIG Endian Support Register */ - {0xA4,0x00}, /* Scratch Pad Register 0 */ - {0xA5,0x00}, /* Scratch Pad Register 1 */ - {0xA8,0x01}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - {0xAC,0x01}, /* GPIO Status Control Register 0 */ - {0xAD,0x00}, /* GPIO Status Control Register 1 */ - {0xB0,0x10}, /* PWM CV Clock Control Register */ - {0xB1,0x80}, /* PWM CV Clock Config Register */ - {0xB2,0x00}, /* CV Clock Burst Length Register */ - {0xAD,0x80}, /* reset seq */ - {0x70,0x03}, -}; diff -purN u-boot.git/include/configs/KUP4K.h u-boot/include/configs/KUP4K.h --- u-boot.git/include/configs/KUP4K.h 2010-02-16 09:02:08.000000000 +0100 +++ u-boot/include/configs/KUP4K.h 2010-02-17 13:03:51.000000000 +0100 @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de * @@ -42,11 +42,7 @@ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 115200 /* console baudrate */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ -#endif

#define CONFIG_BOARD_TYPES 1 /* support board types */

@@ -56,26 +52,32 @@

#define CONFIG_EXTRA_ENV_SETTINGS \ "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw; diskboot 200000 0:1; bootm 200000\0" \ + "run addhw; mw.b 200000 00 80; diskboot 200000 0:1; bootm 200000\0" \ "slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw; diskboot 200000 2:1; bootm 200000\0" \ -"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \ + "run addhw; mw.b 200000 00 80; diskboot 200000 2:1; bootm 200000\0" \ +"nfs_boot=mw.b 200000 00 80; dhcp; run nfsargs addip addhw; bootm 200000\0" \ +"fat_boot=mw.b 200000 00 80; fatload ide 2:1 200000 st.bin; run addhw;\ + bootm 200000 \0" \ "panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ +"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}${nfs-options}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ +"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \ ":${netmask}:${hostname}:${netdev}:off\0" \ -"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ +"addhw=setenv bootargs ${bootargs} console=${console} ${debug} hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \ +"nfs-options=,timeo=20,retrans=5\0" \ +"console=ttyS0\0" \ "netdev=eth0\0" \ -"contrast=55\0" \ +"contrast=20\0" \ "silent=1\0" \ +"initrd_high=c00000\0" \ "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \ -"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \ +"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \ "cp.b 200000 40050000 14000\0"

#define CONFIG_BOOTCOMMAND \ - "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot" + "run fat_boot; run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot"

+#define CONFIG_PREBOOT "setenv preboot; saveenv"

#define CONFIG_MISC_INIT_R 1 #define CONFIG_MISC_INIT_F 1 @@ -151,20 +153,8 @@ #define CONFIG_SYS_DISCOVER_PHY #define CONFIG_MII

-#if 0 -#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */ -#endif -#define CONFIG_KUP4K_LOGO 0x40050000 /* Address of logo bitmap */ - /* Define to allow the user to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#if 1 -/* POST support */ - -#define CONFIG_POST (CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_I2C) -#endif

/* @@ -176,13 +166,18 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE +#define CONFIG_CMD_MII #define CONFIG_CMD_NFS +#define CONFIG_CMD_FAT #define CONFIG_CMD_SNTP

#ifdef CONFIG_POST #define CONFIG_CMD_DIAG #endif

+ + + /* * Miscellaneous configurable options */ @@ -197,8 +192,10 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */

-#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */ +#define CONFIG_SYS_ALT_MEMTEST 1 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */

#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */

@@ -416,8 +413,8 @@ /* * FLASH timing: */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) +#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_CSNT_SAM | \ + OR_SCY_5_CLK | OR_EHTR | OR_BI)

#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) @@ -475,7 +472,39 @@ /* * MAMR settings for SDRAM */ -#define CONFIG_SYS_MAMR 0x80802114 + +/* 8 column SDRAM */ +#define CONFIG_SYS_MAMR_8COL 0x68802114 +/* 9 column SDRAM */ +#define CONFIG_SYS_MAMR_9COL 0x68904114 + +/* + * Chip Selects +*/ +#define CONFIG_SYS_OR0 +#define CONFIG_SYS_BR0 + +#define CONFIG_SYS_OR1_8COL 0xFF000A00 +#define CONFIG_SYS_BR1_8COL 0x00000081 +#define CONFIG_SYS_OR2_8COL 0xFE000A00 +#define CONFIG_SYS_BR2_8COL 0x01000081 +#define CONFIG_SYS_OR3_8COL 0xFC000A00 +#define CONFIG_SYS_BR3_8COL 0x02000081 + +#define CONFIG_SYS_OR1_9COL 0xFE000A00 +#define CONFIG_SYS_BR1_9COL 0x00000081 +#define CONFIG_SYS_OR2_9COL 0xFE000A00 +#define CONFIG_SYS_BR2_9COL 0x02000081 +#define CONFIG_SYS_OR3_9COL 0xFE000A00 +#define CONFIG_SYS_BR3_9COL 0x04000081 + +#define CONFIG_SYS_OR4 0xFFFF8926 +#define CONFIG_SYS_BR4 0x90000401 + +#define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */ +#define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */ + +

/* * Internal Definitions @@ -487,11 +516,15 @@

#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#if 0 -#define CONFIG_AUTOBOOT_PROMPT \ - "Boote in %d Sekunden - stop mit "2"\n", bootdelay -#endif -#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ -#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_AUTOBOOT_STOP_STR "." +#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */ +#define CONFIG_VERSION_VARIABLE 1 + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_HWCONFIG 1 +

#endif /* __CONFIG_H */

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