[U-Boot] [PATCH v1 1/4] udoo: Move and optimize platform register setting.
Previous uDoo configuration adopts register settings for DDR3, clock, muxing, etc. taken from Nitrogen6x. uDoo schematics is rather different from that board, and it needs customized setting for most of the registers. All this changes can be considered atomical since it is part of initial support of the board.
Patch changes uDoo configuration files path to a specific one, and adopt optimized value for every configured register.
Signed-off-by: Giuseppe Pagano giuseppe.pagano@seco.com CC: Stefano Babic sbabic@denx.de CC: Fabio Estevam fabio.estevam@freescale.com --- board/udoo/1066mhz_4x256mx16.cfg | 56 ++++++++++++++++++++++++ board/udoo/clocks.cfg | 32 ++++++++++++++ board/udoo/ddr-setup.cfg | 87 ++++++++++++++++++++++++++++++++++++++ board/udoo/udoo.cfg | 29 +++++++++++++ boards.cfg | 2 +- 5 files changed, 205 insertions(+), 1 deletion(-) create mode 100644 board/udoo/1066mhz_4x256mx16.cfg create mode 100644 board/udoo/clocks.cfg create mode 100644 board/udoo/ddr-setup.cfg create mode 100644 board/udoo/udoo.cfg
diff --git a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg new file mode 100644 index 0000000..539e3f6 --- /dev/null +++ b/board/udoo/1066mhz_4x256mx16.cfg @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 + +DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB + +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 + +DATA 4, MX6_MMDC_P0_MDOR, 0x00591023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001 + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + diff --git a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg new file mode 100644 index 0000000..9cd1af1 --- /dev/null +++ b/board/udoo/clocks.cfg @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + diff --git a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg new file mode 100644 index 0000000..78cbe17 --- /dev/null +++ b/board/udoo/ddr-setup.cfg @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + diff --git a/board/udoo/udoo.cfg b/board/udoo/udoo.cfg new file mode 100644 index 0000000..8d7ff25 --- /dev/null +++ b/board/udoo/udoo.cfg @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/boards.cfg b/boards.cfg index cec154b..1863f2a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -288,7 +288,7 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic sbabic@denx.de -Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Fabio Estevam fabio.estevam@freescale.com +Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam fabio.este...@freescale.com Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam fabio.estevam@freescale.com Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam fabio.estevam@freescale.com Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam fabio.estevam@freescale.com
Add Ethernet and networking support on uDoo board (FEC + phy Micrel KSZ9031).
Signed-off-by: Giuseppe Pagano giuseppe.pagano@seco.com CC: Stefano Babic sbabic@denx.de CC: Fabio Estevam fabio.estevam@freescale.com --- board/udoo/udoo.c | 140 ++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/udoo.h | 16 ++++++ include/micrel.h | 5 ++ 3 files changed, 161 insertions(+)
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index e9d6375..ca49ebb 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -9,6 +9,7 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> +#include <malloc.h> #include <asm/arch/mx6-pins.h> #include <asm/errno.h> #include <asm/gpio.h> @@ -18,6 +19,9 @@ #include <asm/arch/crm_regs.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> +#include <micrel.h> +#include <miiphy.h> +#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +29,9 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -58,6 +65,99 @@ static iomux_v3_cfg_t const wdog_pads[] = { MX6_PAD_EIM_D19__GPIO_3_19, };
+int mx6_rgmii_rework(struct phy_device *phydev) +{ + /* + * Bug: Apparently uDoo does not works with Gigabit switches... + * Limiting speed to 10/100Mbps, and setting master mode, seems to + * be the only way to have a successfull PHY auto negotiation. + * How to fix: Understand why Linux kernel do not have this issue. + */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); + + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); + return 0; +} + +static iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* RGMII reset */ + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* alimentazione ethernet*/ + MX6_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + udelay(20); + gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power on enet */ + + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */ + + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + udelay(1000); + + gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */ + + /* Need delay 100ms to exit from reset. */ + udelay(1000 * 100); + + gpio_free(IMX_GPIO_NR(6, 24)); + gpio_free(IMX_GPIO_NR(6, 25)); + gpio_free(IMX_GPIO_NR(6, 27)); + gpio_free(IMX_GPIO_NR(6, 28)); + gpio_free(IMX_GPIO_NR(6, 29)); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); @@ -77,6 +177,37 @@ int board_mmc_getcd(struct mmc *mmc) return 1; /* Always present */ }
+int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy 4,5,6,7 */ + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + + if (!phydev) { + free(bus); + return 0; + } + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + int board_mmc_init(bd_t *bis) { imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); @@ -94,6 +225,15 @@ int board_early_init_f(void) return 0; }
+int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + int board_init(void) { /* address of boot parameters */ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 78df071..b9a493c 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -34,6 +34,22 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE
+/* Network support */ + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 diff --git a/include/micrel.h b/include/micrel.h index e1c62d8..1d72b50 100644 --- a/include/micrel.h +++ b/include/micrel.h @@ -15,6 +15,11 @@ #define MII_KSZ9031_MOD_DATA_POST_INC_RW 0x8000 #define MII_KSZ9031_MOD_DATA_POST_INC_W 0xC000
+#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW 0x4 +#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW 0x5 +#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6 +#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8 + struct phy_device; int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val); int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
On Mon, Nov 11, 2013 at 3:11 PM, Giuseppe Pagano giuseppe.pagano@seco.com wrote:
Add Ethernet and networking support on uDoo board (FEC + phy Micrel KSZ9031).
Signed-off-by: Giuseppe Pagano giuseppe.pagano@seco.com CC: Stefano Babic sbabic@denx.de CC: Fabio Estevam fabio.estevam@freescale.com
TFTP transfer worked fine here, so:
Tested-by: Fabio Estevam fabio.estevam@freescale.com
Thanks
Hi Giuseppe,
On Mon, Nov 11, 2013 at 3:11 PM, Giuseppe Pagano giuseppe.pagano@seco.com wrote:
+static iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),/* RGMII reset */MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),/* alimentazione ethernet*/
Actually this is pin is Ethernet PHY reset, so the comment in Italian is not correct :-)
On Tue, Nov 12, 2013 at 12:51 PM, Fabio Estevam festevam@gmail.com wrote:
Hi Giuseppe,
On Mon, Nov 11, 2013 at 3:11 PM, Giuseppe Pagano giuseppe.pagano@seco.com wrote:
+static iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),/* RGMII reset */MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),/* alimentazione ethernet*/Actually this is pin is Ethernet PHY reset, so the comment in Italian is not correct :-)
Sorry, I looked at the wrong line. Anyway, please change the comment to "Ethernet power supply".
Thanks,
Fabio Estevam
Hi Fabio,
On Tue, 2013-11-12 at 13:00 -0200, Fabio Estevam wrote:
/* alimentazione ethernet*/Actually this is pin is Ethernet PHY reset, so the comment in Italian is not correct :-)
Sorry, I looked at the wrong line. Anyway, please change the comment to "Ethernet power supply".
Sure, I'll do in the next v2 version.
Thanks, Fabio Estevam
Bye Giuseppe
Hi Giuseppe,
On 11/11/2013 18:11, Giuseppe Pagano wrote:
Add Ethernet and networking support on uDoo board (FEC + phy Micrel KSZ9031).
Signed-off-by: Giuseppe Pagano giuseppe.pagano@seco.com CC: Stefano Babic sbabic@denx.de CC: Fabio Estevam fabio.estevam@freescale.com
ok - remember to increment the version number of the patchset for next time (this is really V2 instead of V1).
board/udoo/udoo.c | 140 ++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/udoo.h | 16 ++++++ include/micrel.h | 5 ++ 3 files changed, 161 insertions(+)
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index e9d6375..ca49ebb 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -9,6 +9,7 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> +#include <malloc.h> #include <asm/arch/mx6-pins.h> #include <asm/errno.h> #include <asm/gpio.h> @@ -18,6 +19,9 @@ #include <asm/arch/crm_regs.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> +#include <micrel.h> +#include <miiphy.h> +#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +29,9 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -58,6 +65,99 @@ static iomux_v3_cfg_t const wdog_pads[] = { MX6_PAD_EIM_D19__GPIO_3_19, };
+int mx6_rgmii_rework(struct phy_device *phydev) +{
- /*
* Bug: Apparently uDoo does not works with Gigabit switches...* Limiting speed to 10/100Mbps, and setting master mode, seems to* be the only way to have a successfull PHY auto negotiation.* How to fix: Understand why Linux kernel do not have this issue.*/
Fine. This is ok, but could you also add to the commit message that Ethernet is currently limited to 10/100Mbps ?
Best regards, Stefano Babic
Hi Stefano,
On Wed, 2013-11-13 at 10:04 +0100, Stefano Babic wrote:
Hi Giuseppe,
On 11/11/2013 18:11, Giuseppe Pagano wrote:
Add Ethernet and networking support on uDoo board (FEC + phy Micrel KSZ9031).
Signed-off-by: Giuseppe Pagano giuseppe.pagano@seco.com CC: Stefano Babic sbabic@denx.de CC: Fabio Estevam fabio.estevam@freescale.com
ok - remember to increment the version number of the patchset for next time (this is really V2 instead of V1).
Ok, I'm going to prepare next patch. Sorry for the error, for this time I think it would be better to use V2 in next submit to reduce confusion.
+int mx6_rgmii_rework(struct phy_device *phydev) +{
- /*
* Bug: Apparently uDoo does not works with Gigabit switches...* Limiting speed to 10/100Mbps, and setting master mode, seems to* be the only way to have a successfull PHY auto negotiation.* How to fix: Understand why Linux kernel do not have this issue.*/Fine. This is ok, but could you also add to the commit message that Ethernet is currently limited to 10/100Mbps ?
Ok, I will do.
Best regards, Stefano Babic
Best Regards Giuseppe Pagano
Adds SATA support on uDoo Board. Moves sata_setup function definition from nitrogen6x.c and udoo.c to arch/arm/imx-common/sata.c to avoid code duplication.
Signed-off-by: Giuseppe Pagano giuseppe.pagano@seco.com CC: Stefano Babic sbabic@denx.de CC: Fabio Estevam fabio.estevam@freescale.com CC: Eric Nelson eric.nelson@boundarydevices.com --- arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/sata.c | 33 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/imx-common/sata.h | 17 ++++++++++++++++ board/boundary/nitrogen6x/nitrogen6x.c | 27 +------------------------- board/udoo/udoo.c | 4 ++++ include/configs/udoo.h | 12 ++++++++++++ 6 files changed, 68 insertions(+), 26 deletions(-) create mode 100644 arch/arm/imx-common/sata.c create mode 100644 arch/arm/include/asm/imx-common/sata.h
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 727a052..6f85c42 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -17,6 +17,7 @@ endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) COBJS-y += timer.o cpu.o speed.o COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o +COBJS-$(CONFIG_CMD_SATA) += sata.o endif ifeq ($(SOC),$(filter $(SOC),mx6 mxs)) COBJS-y += misc.o diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c new file mode 100644 index 0000000..00b3d92 --- /dev/null +++ b/arch/arm/imx-common/sata.c @@ -0,0 +1,33 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/imx-common/iomux-v3.h> +#include <asm/arch/iomux.h> +#include <asm/io.h> + +int sata_setup(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + + int ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) + |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED + |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 + |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB + |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V + |IOMUXC_GPR13_SATA_PHY_1_SLOW); + + return 0; +} diff --git a/arch/arm/include/asm/imx-common/sata.h b/arch/arm/include/asm/imx-common/sata.h new file mode 100644 index 0000000..40fbf77 --- /dev/null +++ b/arch/arm/include/asm/imx-common/sata.h @@ -0,0 +1,17 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX_SATA_H_ +#define __IMX_SATA_H_ + +/* + * SATA setup for i.mx6 quad based platform + */ + +int sata_setup(void); + +#endif + diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 1712908..0c26bcb 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -17,6 +17,7 @@ #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> #include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/sata.h> #include <asm/imx-common/boot_mode.h> #include <mmc.h> #include <fsl_esdhc.h> @@ -378,32 +379,6 @@ static void setup_buttons(void) ARRAY_SIZE(button_pads)); }
-#ifdef CONFIG_CMD_SATA - -int setup_sata(void) -{ - struct iomuxc_base_regs *const iomuxc_regs - = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; - int ret = enable_sata_clock(); - if (ret) - return ret; - - clrsetbits_le32(&iomuxc_regs->gpr[13], - IOMUXC_GPR13_SATA_MASK, - IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB - |IOMUXC_GPR13_SATA_PHY_7_SATA2M - |IOMUXC_GPR13_SATA_SPEED_3G - |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) - |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED - |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 - |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB - |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V - |IOMUXC_GPR13_SATA_PHY_1_SLOW); - - return 0; -} -#endif - #if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = { diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index ca49ebb..b53f70c 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -14,6 +14,7 @@ #include <asm/errno.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/sata.h> #include <mmc.h> #include <fsl_esdhc.h> #include <asm/arch/crm_regs.h> @@ -239,6 +240,9 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_CMD_SATA + sata_setup(); +#endif return 0; }
diff --git a/include/configs/udoo.h b/include/configs/udoo.h index b9a493c..a1a1750 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -34,6 +34,18 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE
+/* SATA Configs */ + +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + /* Network support */
#define CONFIG_CMD_PING
Hello Giuseppe,
On Mon, Nov 11, 2013 at 3:11 PM, Giuseppe Pagano giuseppe.pagano@seco.com wrote:
Adds SATA support on uDoo Board. Moves sata_setup function definition from nitrogen6x.c and udoo.c to arch/arm/imx-common/sata.c to avoid code duplication.
Signed-off-by: Giuseppe Pagano giuseppe.pagano@seco.com
Your patches should have the long description split in 80 cols; please do the nitrogen code move in a separated patch so it is clear what you did to include support for uDoo board.
Hi Ottavio,
On Mon, 2013-11-11 at 16:00 -0200, Otavio Salvador wrote:
Hello Giuseppe,
On Mon, Nov 11, 2013 at 3:11 PM, Giuseppe Pagano giuseppe.pagano@seco.com wrote:
Adds SATA support on uDoo Board. Moves sata_setup function definition from nitrogen6x.c and udoo.c to arch/arm/imx-common/sata.c to avoid code duplication.
Signed-off-by: Giuseppe Pagano giuseppe.pagano@seco.com
Your patches should have the long description split in 80 cols; please do the nitrogen code move in a separated patch so it is clear what you did to include support for uDoo board.
Ok I will split. Thanks
Giuseppe
uDoo uses APX823-31W5 watchdog chip. Timeout is about 1.2 seconds. To disabled watchdog during kernel boot, WDI pin of that chip needs to be in "high impedance" state. I.mx6 gpio configuration does not contemplate tristate, so pin is set as input in high impedance.
Signed-off-by: Giuseppe Pagano giuseppe.pagano@seco.com CC: Stefano Babic sbabic@denx.de CC: Fabio Estevam fabio.estevam@freescale.com --- board/udoo/udoo.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index b53f70c..af8004e 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -169,6 +169,7 @@ static void setup_iomux_wdog(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); gpio_direction_output(WDT_TRG, 0); gpio_direction_output(WDT_EN, 1); + gpio_direction_input(WDT_TRG); }
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
On Mon, Nov 11, 2013 at 3:11 PM, Giuseppe Pagano giuseppe.pagano@seco.com wrote:
uDoo uses APX823-31W5 watchdog chip. Timeout is about 1.2 seconds. To disabled watchdog during kernel boot, WDI pin of that chip needs to be in "high impedance" state. I.mx6 gpio configuration does not contemplate tristate, so pin is set as input in high impedance.
Signed-off-by: Giuseppe Pagano giuseppe.pagano@seco.com CC: Stefano Babic sbabic@denx.de CC: Fabio Estevam fabio.estevam@freescale.com
board/udoo/udoo.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index b53f70c..af8004e 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -169,6 +169,7 @@ static void setup_iomux_wdog(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); gpio_direction_output(WDT_TRG, 0); gpio_direction_output(WDT_EN, 1);
gpio_direction_input(WDT_TRG);
Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
Hi Giuseppe,
On Mon, Nov 11, 2013 at 3:11 PM, Giuseppe Pagano giuseppe.pagano@seco.com wrote:
Previous uDoo configuration adopts register settings for DDR3, clock, muxing, etc. taken from Nitrogen6x. uDoo schematics is rather different from that board, and it needs customized setting for most of the registers. All this changes can be considered atomical since it is part of initial support of the board.
Patch changes uDoo configuration files path to a specific one, and adopt optimized value for every configured register.
Signed-off-by: Giuseppe Pagano giuseppe.pagano@seco.com CC: Stefano Babic sbabic@denx.de CC: Fabio Estevam fabio.estevam@freescale.com
Tested-by: Fabio Estevam fabio.estevam@freescale.com
Thanks.
Only one minor nit below:
board/udoo/1066mhz_4x256mx16.cfg | 56 ++++++++++++++++++++++++ board/udoo/clocks.cfg | 32 ++++++++++++++ board/udoo/ddr-setup.cfg | 87 ++++++++++++++++++++++++++++++++++++++ board/udoo/udoo.cfg | 29 +++++++++++++ boards.cfg | 2 +- 5 files changed, 205 insertions(+), 1 deletion(-) create mode 100644 board/udoo/1066mhz_4x256mx16.cfg create mode 100644 board/udoo/clocks.cfg create mode 100644 board/udoo/ddr-setup.cfg create mode 100644 board/udoo/udoo.cfg
diff --git a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg new file mode 100644 index 0000000..539e3f6 --- /dev/null +++ b/board/udoo/1066mhz_4x256mx16.cfg @@ -0,0 +1,56 @@ +/*
- Copyright (C) 2013 Boundary Devices
- SPDX-License-Identifier: GPL-2.0+
- */
No need to add two lines here. One line is enough.
Hi Giuseppe,
On 11/11/2013 18:11, Giuseppe Pagano wrote:
Previous uDoo configuration adopts register settings for DDR3, clock, muxing, etc. taken from Nitrogen6x. uDoo schematics is rather different from that board, and it needs customized setting for most of the registers. All this changes can be considered atomical since it is part of initial support of the board.
Patch changes uDoo configuration files path to a specific one, and adopt optimized value for every configured register.
Signed-off-by: Giuseppe Pagano giuseppe.pagano@seco.com CC: Stefano Babic sbabic@denx.de CC: Fabio Estevam fabio.estevam@freescale.com
diff --git a/boards.cfg b/boards.cfg index cec154b..1863f2a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -288,7 +288,7 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic sbabic@denx.de -Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Fabio Estevam fabio.estevam@freescale.com +Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam fabio.este...@freescale.com
Fabio's mail address is corrupted by some tool.
Best regards, Stefano Babic
participants (4)
-
Fabio Estevam -
Giuseppe Pagano -
Otavio Salvador -
Stefano Babic