[PATCH 0/8] ARM: ti: AM64x: Add Ethernet boot support on AM64x SK
This series enables ethernet boot support on AM64x SK.
AM64x SoC has CPSW3g IP that supports 2 ext Eth port. ROM supports booting from 2nd port. But currently am65-cpsw-nuss only supports single port (1st port). So the first two patches modify driver to support more than 1 ext port. This is done by breaking up am65-cpsw-nuss into UCLASS_MISC for toplevel NUSS driver and UCLASS_ETH for each of individual ports.
Next 4 patches add mach-k3 and board level changes to enable Ethernet and TFTP to work at SPL.
Last two patches add dts and config changes need to for Ethernet boot.
Tested on AM64x SK with RGMII 1G bootmode at 1G. https://controlc.com/90d555ee
Sanity tested TFTP at U-Boot prompt on AM65x and J721e.
Vignesh Raghavendra (8): mach-k3: common: Instantiate AM65 CPSW NUSS wrapper net: ti: am65-cpsw: Add support for multi port independent MAC mode board: ti: am64x: Init DRAM size in R5/A53 SPL mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL mach-k3: am64_spl: Alias Ethernet RGMII boot to CPGMAC configs: am64x_evm: set eth1 as boot interface ARM: dts: K3-am642-r5-sk: Enable Second CPSW port in R5/A53 SPL configs: am64x_evm_r5/a53_defconfig: Enable configs required for Ethboot
arch/arm/dts/k3-am642-r5-sk.dts | 74 +++++++++++++++++++++++ arch/arm/dts/k3-am642-sk-u-boot.dtsi | 40 +++++++++++- arch/arm/mach-k3/am642_init.c | 7 +++ arch/arm/mach-k3/common.c | 16 +++++ arch/arm/mach-k3/include/mach/am64_spl.h | 1 + board/ti/am64x/evm.c | 3 + configs/am64x_evm_a53_defconfig | 4 ++ configs/am64x_evm_r5_defconfig | 12 ++++ drivers/net/ti/Kconfig | 2 + drivers/net/ti/am65-cpsw-nuss.c | 77 +++++++++++++++--------- include/configs/am64x_evm.h | 5 +- 11 files changed, 212 insertions(+), 29 deletions(-)
Probe toplevel AM65 CPSW NUSS driver from misc_init_r() when driver is enabled. Since driver is modeled as UCLASS_MISC, we need to explicitly probe the driver. Use common misc_init_r() that entire K3 family of SoCs.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- arch/arm/mach-k3/common.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 2666cd2d7b..39d00270b7 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -549,3 +549,19 @@ void spl_board_prepare_for_linux(void) dcache_disable(); } #endif + +int misc_init_r(void) +{ + if (IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(am65_cpsw_nuss), + &dev); + if (ret) + printf("Failed to probe am65_cpsw_nuss driver\n"); + } + + return 0; +}
On Fri, Dec 24, 2021 at 12:55:29PM +0530, Vignesh Raghavendra wrote:
Probe toplevel AM65 CPSW NUSS driver from misc_init_r() when driver is enabled. Since driver is modeled as UCLASS_MISC, we need to explicitly probe the driver. Use common misc_init_r() that entire K3 family of SoCs.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
Applied to u-boot/master, thanks!
On certain TI SoC, like AM64x there is a CPSW3G which supports 2 external independent MAC ports for single CPSW instance. It is not possible for Ethernet driver to register more than one port for given instance.
This patch modifies top level CPSW NUSS as UCLASS_MISC and binds UCLASS_ETH to individual ports so as to support bring up more than one Ethernet interface in U-Boot.
Note that there is no isolation in the since, CPSW NUSS is in promisc mode and forwards all packets to host.
Since top level driver is now UCLASS_MISC, board files would need to instantiate this driver explicitly.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/net/ti/Kconfig | 2 + drivers/net/ti/am65-cpsw-nuss.c | 77 +++++++++++++++++++++------------ 2 files changed, 52 insertions(+), 27 deletions(-)
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index f2dbbd0128..59c96d862d 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -28,6 +28,8 @@ config DRIVER_TI_KEYSTONE_NET config TI_AM65_CPSW_NUSS bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver" depends on ARCH_K3 + imply MISC_INIT_R + imply MISC select PHYLIB help This driver supports TI K3 MCU CPSW Nuss Ethernet controller diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 3ab6a30828..6ae69b51c7 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -597,7 +597,7 @@ static int am65_cpsw_phy_init(struct udevice *dev) return ret; }
-static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np) +static int am65_cpsw_ofdata_parse_phy(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct am65_cpsw_priv *priv = dev_get_priv(dev); @@ -605,7 +605,9 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np) const char *phy_mode; int ret = 0;
- phy_mode = ofnode_read_string(port_np, "phy-mode"); + dev_read_u32(dev, "reg", &priv->port_id); + + phy_mode = dev_read_string(dev, "phy-mode"); if (phy_mode) { pdata->phy_interface = phy_get_interface_by_name(phy_mode); @@ -617,13 +619,13 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np) } }
- ofnode_read_u32(port_np, "max-speed", (u32 *)&pdata->max_speed); + dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed); if (pdata->max_speed) dev_err(dev, "Port %u speed froced to %uMbit\n", priv->port_id, pdata->max_speed);
priv->has_phy = true; - ret = ofnode_parse_phandle_with_args(port_np, "phy-handle", + ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle", NULL, 0, 0, &out_args); if (ret) { dev_err(dev, "can't parse phy-handle port %u (%d)\n", @@ -646,21 +648,46 @@ out: return ret; }
-static int am65_cpsw_probe_cpsw(struct udevice *dev) +static int am65_cpsw_port_probe(struct udevice *dev) { struct am65_cpsw_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); struct am65_cpsw_common *cpsw_common; - ofnode ports_np, node; - int ret, i; + char portname[15]; + int ret;
priv->dev = dev;
- cpsw_common = calloc(1, sizeof(*priv->cpsw_common)); - if (!cpsw_common) - return -ENOMEM; + cpsw_common = dev_get_priv(dev->parent); priv->cpsw_common = cpsw_common;
+ sprintf(portname, "%s%s", dev->parent->name, dev->name); + device_set_name(dev, portname); + + ret = am65_cpsw_ofdata_parse_phy(dev); + if (ret) + goto out; + + am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id); + + ret = am65_cpsw_mdio_init(dev); + if (ret) + goto out; + + ret = am65_cpsw_phy_init(dev); + if (ret) + goto out; +out: + return ret; +} + +static int am65_cpsw_probe_nuss(struct udevice *dev) +{ + struct am65_cpsw_common *cpsw_common = dev_get_priv(dev); + ofnode ports_np, node; + int ret, i; + struct udevice *port_dev; + cpsw_common->dev = dev; cpsw_common->ss_base = dev_read_addr(dev); if (cpsw_common->ss_base == FDT_ADDR_T_NONE) @@ -723,10 +750,9 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev) if (disabled) continue;
- priv->port_id = port_id; - ret = am65_cpsw_ofdata_parse_phy(dev, node); + ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", ofnode_get_name(node), node, &port_dev); if (ret) - goto out; + printf("SCREEEM\n"); }
for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) { @@ -756,16 +782,6 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev) dev_read_u32_default(dev, "bus_freq", AM65_CPSW_MDIO_BUS_FREQ_DEF);
- am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id); - - ret = am65_cpsw_mdio_init(dev); - if (ret) - goto out; - - ret = am65_cpsw_phy_init(dev); - if (ret) - goto out; - dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u mdio_freq:%u\n", readl(cpsw_common->ss_base), readl(cpsw_common->cpsw_base), @@ -786,11 +802,18 @@ static const struct udevice_id am65_cpsw_nuss_ids[] = { { } };
-U_BOOT_DRIVER(am65_cpsw_nuss_slave) = { - .name = "am65_cpsw_nuss_slave", - .id = UCLASS_ETH, +U_BOOT_DRIVER(am65_cpsw_nuss) = { + .name = "am65_cpsw_nuss", + .id = UCLASS_MISC, .of_match = am65_cpsw_nuss_ids, - .probe = am65_cpsw_probe_cpsw, + .probe = am65_cpsw_probe_nuss, + .priv_auto = sizeof(struct am65_cpsw_common), +}; + +U_BOOT_DRIVER(am65_cpsw_nuss_port) = { + .name = "am65_cpsw_nuss_port", + .id = UCLASS_ETH, + .probe = am65_cpsw_port_probe, .ops = &am65_cpsw_ops, .priv_auto = sizeof(struct am65_cpsw_priv), .plat_auto = sizeof(struct eth_pdata),
On Fri, Dec 24, 2021 at 9:25 AM Vignesh Raghavendra vigneshr@ti.com wrote:
On certain TI SoC, like AM64x there is a CPSW3G which supports 2 external independent MAC ports for single CPSW instance. It is not possible for Ethernet driver to register more than one port for given instance.
This patch modifies top level CPSW NUSS as UCLASS_MISC and binds UCLASS_ETH to individual ports so as to support bring up more than one Ethernet interface in U-Boot.
Note that there is no isolation in the since, CPSW NUSS is in promisc mode and forwards all packets to host.
So both ports are working in parallel, how do I choose from which port to exit ?
Since top level driver is now UCLASS_MISC, board files would need to instantiate this driver explicitly.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
drivers/net/ti/Kconfig | 2 + drivers/net/ti/am65-cpsw-nuss.c | 77 +++++++++++++++++++++------------ 2 files changed, 52 insertions(+), 27 deletions(-)
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index f2dbbd0128..59c96d862d 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -28,6 +28,8 @@ config DRIVER_TI_KEYSTONE_NET config TI_AM65_CPSW_NUSS bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver" depends on ARCH_K3
imply MISC_INIT_Rimply MISC select PHYLIB help This driver supports TI K3 MCU CPSW Nuss Ethernet controllerdiff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 3ab6a30828..6ae69b51c7 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -597,7 +597,7 @@ static int am65_cpsw_phy_init(struct udevice *dev) return ret; }
-static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np) +static int am65_cpsw_ofdata_parse_phy(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct am65_cpsw_priv *priv = dev_get_priv(dev); @@ -605,7 +605,9 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np) const char *phy_mode; int ret = 0;
phy_mode = ofnode_read_string(port_np, "phy-mode");
dev_read_u32(dev, "reg", &priv->port_id);phy_mode = dev_read_string(dev, "phy-mode"); if (phy_mode) { pdata->phy_interface = phy_get_interface_by_name(phy_mode);@@ -617,13 +619,13 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np) } }
ofnode_read_u32(port_np, "max-speed", (u32 *)&pdata->max_speed);
dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed); if (pdata->max_speed) dev_err(dev, "Port %u speed froced to %uMbit\n", priv->port_id, pdata->max_speed); priv->has_phy = true;
ret = ofnode_parse_phandle_with_args(port_np, "phy-handle",
ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle", NULL, 0, 0, &out_args); if (ret) { dev_err(dev, "can't parse phy-handle port %u (%d)\n",@@ -646,21 +648,46 @@ out: return ret; }
-static int am65_cpsw_probe_cpsw(struct udevice *dev) +static int am65_cpsw_port_probe(struct udevice *dev) { struct am65_cpsw_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); struct am65_cpsw_common *cpsw_common;
ofnode ports_np, node;int ret, i;
char portname[15];int ret; priv->dev = dev;
cpsw_common = calloc(1, sizeof(*priv->cpsw_common));if (!cpsw_common)return -ENOMEM;
cpsw_common = dev_get_priv(dev->parent); priv->cpsw_common = cpsw_common;sprintf(portname, "%s%s", dev->parent->name, dev->name);device_set_name(dev, portname);ret = am65_cpsw_ofdata_parse_phy(dev);if (ret)goto out;am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id);ret = am65_cpsw_mdio_init(dev);if (ret)goto out;ret = am65_cpsw_phy_init(dev);if (ret)goto out;+out:
return ret;+}
+static int am65_cpsw_probe_nuss(struct udevice *dev) +{
struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);ofnode ports_np, node;int ret, i;struct udevice *port_dev;cpsw_common->dev = dev; cpsw_common->ss_base = dev_read_addr(dev); if (cpsw_common->ss_base == FDT_ADDR_T_NONE)@@ -723,10 +750,9 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev) if (disabled) continue;
priv->port_id = port_id;ret = am65_cpsw_ofdata_parse_phy(dev, node);
ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", ofnode_get_name(node), node, &port_dev); if (ret)
goto out;
printf("SCREEEM\n");
Please handle reasonably.
} for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {@@ -756,16 +782,6 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev) dev_read_u32_default(dev, "bus_freq", AM65_CPSW_MDIO_BUS_FREQ_DEF);
am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id);ret = am65_cpsw_mdio_init(dev);if (ret)goto out;ret = am65_cpsw_phy_init(dev);if (ret)goto out;dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u mdio_freq:%u\n", readl(cpsw_common->ss_base), readl(cpsw_common->cpsw_base),@@ -786,11 +802,18 @@ static const struct udevice_id am65_cpsw_nuss_ids[] = { { } };
-U_BOOT_DRIVER(am65_cpsw_nuss_slave) = {
.name = "am65_cpsw_nuss_slave",.id = UCLASS_ETH,+U_BOOT_DRIVER(am65_cpsw_nuss) = {
.name = "am65_cpsw_nuss",.id = UCLASS_MISC, .of_match = am65_cpsw_nuss_ids,
.probe = am65_cpsw_probe_cpsw,
.probe = am65_cpsw_probe_nuss,.priv_auto = sizeof(struct am65_cpsw_common),+};
+U_BOOT_DRIVER(am65_cpsw_nuss_port) = {
.name = "am65_cpsw_nuss_port",.id = UCLASS_ETH,.probe = am65_cpsw_port_probe, .ops = &am65_cpsw_ops, .priv_auto = sizeof(struct am65_cpsw_priv), .plat_auto = sizeof(struct eth_pdata),-- 2.34.1
On 30/12/21 1:01 am, Ramon Fried wrote:
On Fri, Dec 24, 2021 at 9:25 AM Vignesh Raghavendra vigneshr@ti.com wrote:
On certain TI SoC, like AM64x there is a CPSW3G which supports 2 external independent MAC ports for single CPSW instance. It is not possible for Ethernet driver to register more than one port for given instance.
This patch modifies top level CPSW NUSS as UCLASS_MISC and binds UCLASS_ETH to individual ports so as to support bring up more than one Ethernet interface in U-Boot.
Note that there is no isolation in the since, CPSW NUSS is in promisc mode and forwards all packets to host.
So both ports are working in parallel, how do I choose from which port to exit ?
One would have to chose active port with ethact. Packet from non active port is dropped by the driver.
Since top level driver is now UCLASS_MISC, board files would need to instantiate this driver explicitly.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
[...]
-static int am65_cpsw_probe_cpsw(struct udevice *dev) +static int am65_cpsw_port_probe(struct udevice *dev) { struct am65_cpsw_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); struct am65_cpsw_common *cpsw_common;
ofnode ports_np, node;int ret, i;
char portname[15];int ret; priv->dev = dev;
cpsw_common = calloc(1, sizeof(*priv->cpsw_common));if (!cpsw_common)return -ENOMEM;
cpsw_common = dev_get_priv(dev->parent); priv->cpsw_common = cpsw_common;sprintf(portname, "%s%s", dev->parent->name, dev->name);device_set_name(dev, portname);ret = am65_cpsw_ofdata_parse_phy(dev);if (ret)goto out;am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id);ret = am65_cpsw_mdio_init(dev);if (ret)goto out;ret = am65_cpsw_phy_init(dev);if (ret)goto out;+out:
return ret;+}
+static int am65_cpsw_probe_nuss(struct udevice *dev) +{
struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);ofnode ports_np, node;int ret, i;struct udevice *port_dev;cpsw_common->dev = dev; cpsw_common->ss_base = dev_read_addr(dev); if (cpsw_common->ss_base == FDT_ADDR_T_NONE)@@ -723,10 +750,9 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev) if (disabled) continue;
priv->port_id = port_id;ret = am65_cpsw_ofdata_parse_phy(dev, node);
ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", ofnode_get_name(node), node, &port_dev); if (ret)
goto out;
printf("SCREEEM\n");Please handle reasonably.
Oops, sorry, I missed to clean this up before posting... Since the patch is merged, will send a followup patch addressing the same.
[...]
Regards Vignesh
On Fri, Dec 24, 2021 at 12:55:30PM +0530, Vignesh Raghavendra wrote:
On certain TI SoC, like AM64x there is a CPSW3G which supports 2 external independent MAC ports for single CPSW instance. It is not possible for Ethernet driver to register more than one port for given instance.
This patch modifies top level CPSW NUSS as UCLASS_MISC and binds UCLASS_ETH to individual ports so as to support bring up more than one Ethernet interface in U-Boot.
Note that there is no isolation in the since, CPSW NUSS is in promisc mode and forwards all packets to host.
Since top level driver is now UCLASS_MISC, board files would need to instantiate this driver explicitly.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
Applied to u-boot/master, thanks!
On Mon, Jan 17, 2022 at 8:37 PM Tom Rini trini@konsulko.com wrote:
On Fri, Dec 24, 2021 at 12:55:30PM +0530, Vignesh Raghavendra wrote:
On certain TI SoC, like AM64x there is a CPSW3G which supports 2 external independent MAC ports for single CPSW instance. It is not possible for Ethernet driver to register more than one port for given instance.
This patch modifies top level CPSW NUSS as UCLASS_MISC and binds UCLASS_ETH to individual ports so as to support bring up more than one Ethernet interface in U-Boot.
Note that there is no isolation in the since, CPSW NUSS is in promisc mode and forwards all packets to host.
Since top level driver is now UCLASS_MISC, board files would need to instantiate this driver explicitly.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
Applied to u-boot/master, thanks!
why ? comments were not addressed.
-- Tom
On Fri, Jan 21, 2022 at 01:13:54AM +0200, Ramon Fried wrote:
On Mon, Jan 17, 2022 at 8:37 PM Tom Rini trini@konsulko.com wrote:
On Fri, Dec 24, 2021 at 12:55:30PM +0530, Vignesh Raghavendra wrote:
On certain TI SoC, like AM64x there is a CPSW3G which supports 2 external independent MAC ports for single CPSW instance. It is not possible for Ethernet driver to register more than one port for given instance.
This patch modifies top level CPSW NUSS as UCLASS_MISC and binds UCLASS_ETH to individual ports so as to support bring up more than one Ethernet interface in U-Boot.
Note that there is no isolation in the since, CPSW NUSS is in promisc mode and forwards all packets to host.
Since top level driver is now UCLASS_MISC, board files would need to instantiate this driver explicitly.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
Applied to u-boot/master, thanks!
why ? comments were not addressed.
I missed that you had comments, sorry. Shall I revert this one for now?
On 21/01/22 4:49 am, Tom Rini wrote:
On Fri, Jan 21, 2022 at 01:13:54AM +0200, Ramon Fried wrote:
On Mon, Jan 17, 2022 at 8:37 PM Tom Rini trini@konsulko.com wrote:
On Fri, Dec 24, 2021 at 12:55:30PM +0530, Vignesh Raghavendra wrote:
On certain TI SoC, like AM64x there is a CPSW3G which supports 2 external independent MAC ports for single CPSW instance. It is not possible for Ethernet driver to register more than one port for given instance.
This patch modifies top level CPSW NUSS as UCLASS_MISC and binds UCLASS_ETH to individual ports so as to support bring up more than one Ethernet interface in U-Boot.
Note that there is no isolation in the since, CPSW NUSS is in promisc mode and forwards all packets to host.
Since top level driver is now UCLASS_MISC, board files would need to instantiate this driver explicitly.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
Applied to u-boot/master, thanks!
why ? comments were not addressed.
I missed that you had comments, sorry. Shall I revert this one for now?
Could you please hold off revert? Will send follow up patch fixing stray printf() pointed out by Ramon
Apologies for not noticing comment beforehand!
Regards Vignesh
Call dram_init_banksize() from spl_board_init() otherwise TFTP download fails due to lmb_get_free_size() not able to find unreserved region due to lack of DRAM size info. Required to support Ethernet boot on AM64x.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- board/ti/am64x/evm.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index 1a9f69c6cf..8373c768f1 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -196,5 +196,8 @@ void spl_board_init(void) val = readl(CTRLMMR_USB0_PHY_CTRL); val &= ~(CORE_VOLTAGE); writel(val, CTRLMMR_USB0_PHY_CTRL); + + /* Init DRAM size for R5/A53 SPL */ + dram_init_banksize(); } #endif
On Fri, Dec 24, 2021 at 12:55:31PM +0530, Vignesh Raghavendra wrote:
Call dram_init_banksize() from spl_board_init() otherwise TFTP download fails due to lmb_get_free_size() not able to find unreserved region due to lack of DRAM size info. Required to support Ethernet boot on AM64x.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
Applied to u-boot/master, thanks!
In order to support Ethernet boot on AM64x, probe AM65 CPSW NUSS.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- arch/arm/mach-k3/am642_init.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 533905daeb..184f1a2761 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -196,6 +196,13 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif + if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && + spl_boot_device() == BOOT_DEVICE_ETHERNET) { + struct udevice *cpswdev; + + if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev)) + printf("Failed to probe am65_cpsw_nuss driver\n"); + } }
u32 spl_mmc_boot_mode(const u32 boot_device)
On Fri, Dec 24, 2021 at 12:55:32PM +0530, Vignesh Raghavendra wrote:
In order to support Ethernet boot on AM64x, probe AM65 CPSW NUSS.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
Applied to u-boot/master, thanks!
This is required to enables spl_net boot on AM64x
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- arch/arm/mach-k3/include/mach/am64_spl.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-k3/include/mach/am64_spl.h b/arch/arm/mach-k3/include/mach/am64_spl.h index 607b09c2e5..b4f396b2c0 100644 --- a/arch/arm/mach-k3/include/mach/am64_spl.h +++ b/arch/arm/mach-k3/include/mach/am64_spl.h @@ -12,6 +12,7 @@ #define BOOT_DEVICE_QSPI 0x02 #define BOOT_DEVICE_SPI 0x03 #define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_CPGMAC 0x04 #define BOOT_DEVICE_ETHERNET_RGMII 0x04 #define BOOT_DEVICE_ETHERNET_RMII 0x05 #define BOOT_DEVICE_I2C 0x06
On Fri, Dec 24, 2021 at 12:55:33PM +0530, Vignesh Raghavendra wrote:
This is required to enables spl_net boot on AM64x
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
Applied to u-boot/master, thanks!
ROM supports boot from CPSW second port, therefore set eth1 boot interface
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- include/configs/am64x_evm.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 99624081c3..cd4b658e5f 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -33,7 +33,7 @@ * our memory footprint. The less we use for BSS the more we have available * for everything else. */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 +#define CONFIG_SPL_BSS_MAX_SIZE 0xa000 /* * Link BSS to be within SPL in a dedicated region located near the top of * the MCU SRAM, this way making it available also before relocation. Note @@ -64,6 +64,7 @@ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "name_kern=Image\0" \ + "ethact=eth0\0" \ "console=ttyS2,115200n8\0" \ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \ "${mtdparts}\0" \ @@ -140,4 +141,6 @@
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_ETH_DEVICE "eth1" + #endif /* __CONFIG_AM642_EVM_H */
On Fri, Dec 24, 2021 at 12:55:34PM +0530, Vignesh Raghavendra wrote:
ROM supports boot from CPSW second port, therefore set eth1 boot interface
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
include/configs/am64x_evm.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 99624081c3..cd4b658e5f 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -33,7 +33,7 @@
- our memory footprint. The less we use for BSS the more we have available
- for everything else.
*/ -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 +#define CONFIG_SPL_BSS_MAX_SIZE 0xa000 /*
- Link BSS to be within SPL in a dedicated region located near the top of
- the MCU SRAM, this way making it available also before relocation. Note
@@ -64,6 +64,7 @@ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "name_kern=Image\0" \
- "ethact=eth0\0" \ "console=ttyS2,115200n8\0" \ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \ "${mtdparts}\0" \
@@ -140,4 +141,6 @@
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_ETH_DEVICE "eth1"
#endif /* __CONFIG_AM642_EVM_H */
What's going on exactly here? First, CONFIG_SPL_ETH_DEVICE needs to be migrated to Kconfig now, if we're going to use it. But, it's used to set "ethact", which wouldd normally be eth0, but you're setting it to eth1 here and eth0 for U-Boot itself? Can you please explain the setup here? Thanks!
On 17/01/22 8:16 pm, Tom Rini wrote:
On Fri, Dec 24, 2021 at 12:55:34PM +0530, Vignesh Raghavendra wrote:
ROM supports boot from CPSW second port, therefore set eth1 boot interface
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
include/configs/am64x_evm.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 99624081c3..cd4b658e5f 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -33,7 +33,7 @@
- our memory footprint. The less we use for BSS the more we have available
- for everything else.
*/ -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 +#define CONFIG_SPL_BSS_MAX_SIZE 0xa000 /*
- Link BSS to be within SPL in a dedicated region located near the top of
- the MCU SRAM, this way making it available also before relocation. Note
@@ -64,6 +64,7 @@ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "name_kern=Image\0" \
- "ethact=eth0\0" \
This is redundant, will drop.
"console=ttyS2,115200n8\0" \ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \ "${mtdparts}\0" \ @@ -140,4 +141,6 @@
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_ETH_DEVICE "eth1"
#endif /* __CONFIG_AM642_EVM_H */
What's going on exactly here? First, CONFIG_SPL_ETH_DEVICE needs to be migrated to Kconfig now, if we're going to use it. But, it's used to set "ethact", which wouldd normally be eth0, but you're setting it to eth1 here and eth0 for U-Boot itself? Can you please explain the setup here? Thanks!
ROM supports boot from cpsw_port2 (eth1) and not cpsw_port1 (eth0), hence I had to set CONFIG_SPL_ETH_DEVICE to eth1. Thinking a bit more, it does not make sense to enable both ports in SPL as only eth1 is used during ethboot. So CONFIG_SPL_ETH_DEVICE need not be touched if eth0 is disabled for SPL.
Will update DT files accordingly.
Regards Vignesh
Enable Second Ethernet port on which ROM support Ethboot.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- arch/arm/dts/k3-am642-r5-sk.dts | 74 ++++++++++++++++++++++++++++ arch/arm/dts/k3-am642-sk-u-boot.dtsi | 40 ++++++++++++++- 2 files changed, 113 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 79eff8259f..b4a0438449 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/phy/phy.h> +#include <dt-bindings/net/ti-dp83867.h> #include "k3-am642.dtsi" #include "k3-am64-sk-lp4-1333MTs.dtsi" #include "k3-am64-ddr.dtsi" @@ -107,6 +109,47 @@ AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ >; }; + + mdio1_pins_default: mdio1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ + AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ + AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */ + AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */ + AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */ + AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */ + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ + AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ + >; + }; + + rgmii2_pins_default: rgmii2-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; };
&dmsc { @@ -142,4 +185,35 @@ pinctrl-0 = <&main_mmc1_pins_default>; };
+&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default + &rgmii1_pins_default + &rgmii2_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; +}; + #include "k3-am642-sk-u-boot.dtsi" diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi index efbcfb36e9..ade040e601 100644 --- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi @@ -100,13 +100,51 @@ <0x0 0x43000200 0x0 0x8>; reg-names = "cpsw_nuss", "mac_efuse"; /delete-property/ ranges; + u-boot,dm-spl;
cpsw-phy-sel@04044 { compatible = "ti,am64-phy-gmii-sel"; reg = <0x0 0x43004044 0x0 0x8>; + u-boot,dm-spl; + }; + + ethernet-ports { + u-boot,dm-spl; }; };
&cpsw_port2 { - status = "disabled"; + u-boot,dm-spl; +}; + +&cpsw_port1 { + u-boot,dm-spl; +}; + +&main_bcdma { + u-boot,dm-spl; +}; + +&main_pktdma { + u-boot,dm-spl; +}; + +&rgmii1_pins_default { + u-boot,dm-spl; +}; + +&rgmii2_pins_default { + u-boot,dm-spl; +}; + +&mdio1_pins_default { + u-boot,dm-spl; +}; + +&cpsw3g_phy0 { + u-boot,dm-spl; +}; + +&cpsw3g_phy1 { + u-boot,dm-spl; };
On Fri, Dec 24, 2021 at 12:55:35PM +0530, Vignesh Raghavendra wrote:
Enable Second Ethernet port on which ROM support Ethboot.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
Applied to u-boot/master, thanks!
Enable config options needed to support Ethernet boot on AM64x SK.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- configs/am64x_evm_a53_defconfig | 4 ++++ configs/am64x_evm_r5_defconfig | 12 ++++++++++++ 2 files changed, 16 insertions(+)
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index aafbb410b6..b8add31a30 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y @@ -36,8 +37,11 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y +CONFIG_SPL_ETH=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot A53 SPL" CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index f564fa064e..01c1bc02ae 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -36,10 +36,14 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y +CONFIG_SPL_ETH=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot R5 SPL" CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y @@ -61,6 +65,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y @@ -84,12 +89,15 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_SPL_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -97,6 +105,9 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_TI_DP83867=y +CONFIG_DM_ETH=y +CONFIG_TI_AM65_CPSW_NUSS=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y @@ -114,6 +125,7 @@ CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y +CONFIG_SOC_TI=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y
On Fri, Dec 24, 2021 at 12:55:36PM +0530, Vignesh Raghavendra wrote:
Enable config options needed to support Ethernet boot on AM64x SK.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
This leads to size overflow on r5.
On 17/01/22 8:47 am, Tom Rini wrote:
On Fri, Dec 24, 2021 at 12:55:36PM +0530, Vignesh Raghavendra wrote:
Enable config options needed to support Ethernet boot on AM64x SK.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
This leads to size overflow on r5.
Hmm, I don't see size limitations locally.
$ size spl/u-boot-spl text data bss dec hex filename 230470 10401 12992 253863 3dfa7 spl/u-boot-spl
vs limit declared in configs/am64x_evm_r5_defconfig:
CONFIG_SPL_SIZE_LIMIT=0x190000
I don't expect size overflow?
Regards Vignesh
On Fri, Jan 21, 2022 at 09:59:21AM +0530, Vignesh Raghavendra wrote:
On 17/01/22 8:47 am, Tom Rini wrote:
On Fri, Dec 24, 2021 at 12:55:36PM +0530, Vignesh Raghavendra wrote:
Enable config options needed to support Ethernet boot on AM64x SK.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
This leads to size overflow on r5.
Hmm, I don't see size limitations locally.
$ size spl/u-boot-spl text data bss dec hex filename 230470 10401 12992 253863 3dfa7 spl/u-boot-spl
vs limit declared in configs/am64x_evm_r5_defconfig:
CONFIG_SPL_SIZE_LIMIT=0x190000
I don't expect size overflow?
What toolchain are you using? I'm seeing this with gcc-11.1.
On 21/01/22 8:27 pm, Tom Rini wrote:
On Fri, Jan 21, 2022 at 09:59:21AM +0530, Vignesh Raghavendra wrote:
On 17/01/22 8:47 am, Tom Rini wrote:
On Fri, Dec 24, 2021 at 12:55:36PM +0530, Vignesh Raghavendra wrote:
Enable config options needed to support Ethernet boot on AM64x SK.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
This leads to size overflow on r5.
Hmm, I don't see size limitations locally.
$ size spl/u-boot-spl text data bss dec hex filename 230470 10401 12992 253863 3dfa7 spl/u-boot-spl
vs limit declared in configs/am64x_evm_r5_defconfig:
CONFIG_SPL_SIZE_LIMIT=0x190000
I don't expect size overflow?
What toolchain are you using? I'm seeing this with gcc-11.1.
I am using 10.3.1. Will try 11.1. But what's is overflow error being reported?
Also, could you try if [1] compiles fine on top of latest master?
[1] https://lore.kernel.org/u-boot/20220121071754.197577-1-vigneshr@ti.com/T/#t
Regards Vignesh
On Fri, Jan 21, 2022 at 08:48:05PM +0530, Vignesh Raghavendra wrote:
On 21/01/22 8:27 pm, Tom Rini wrote:
On Fri, Jan 21, 2022 at 09:59:21AM +0530, Vignesh Raghavendra wrote:
On 17/01/22 8:47 am, Tom Rini wrote:
On Fri, Dec 24, 2021 at 12:55:36PM +0530, Vignesh Raghavendra wrote:
Enable config options needed to support Ethernet boot on AM64x SK.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
This leads to size overflow on r5.
Hmm, I don't see size limitations locally.
$ size spl/u-boot-spl text data bss dec hex filename 230470 10401 12992 253863 3dfa7 spl/u-boot-spl
vs limit declared in configs/am64x_evm_r5_defconfig:
CONFIG_SPL_SIZE_LIMIT=0x190000
I don't expect size overflow?
What toolchain are you using? I'm seeing this with gcc-11.1.
I am using 10.3.1. Will try 11.1. But what's is overflow error being reported?
Also, could you try if [1] compiles fine on top of latest master?
[1] https://lore.kernel.org/u-boot/20220121071754.197577-1-vigneshr@ti.com/T/#t
Yes, this builds, so I guess you can set aside the report. Thanks!
participants (3)
-
Ramon Fried -
Tom Rini -
Vignesh Raghavendra