[U-Boot] [PATCH 0/1] rk3328: clk: Configure CPU clock during initialization
This patch changes the RK3328 CRU driver so it explicitly configures the CPU clock during initialization, through a call to rk3328_configure_cpu().
Previously rk3328_configure_cpu() was implemented but not called from anywhere, which I'm assuming was unintentional.
This change matches the RK3399's CRU driver (drivers/clk/rockchip/clk_rk3399.c) by
- Invoking the function at the start of rkclk_init() and - Setting the CPU clock to the lowest defined frequency, 600 MHz.
It yields no real functional change (the CPU clock is already set to 600 MHz at power-on) but it does make it straightforward to set a higher clock rate at compile time for systems like the ROCK64 that run reliably at higher frequencies.
Tested on my ROCK64.
Simon South (1): clk: rockchip: rk3328: Configure CPU clock
arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 3 +++ drivers/clk/rockchip/clk_rk3328.c | 2 ++ 2 files changed, 5 insertions(+)
Add a call to rk3328_configure_cpu() during initialization to set the CPU-clock frequency.
Signed-off-by: Simon South simon@simonsouth.net --- arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 3 +++ drivers/clk/rockchip/clk_rk3328.c | 2 ++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h index 15b9788d9c..4bf69dbe08 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h @@ -66,4 +66,7 @@ enum apll_frequencies { APLL_600_MHZ, };
+void rk3328_configure_cpu(struct rk3328_cru *cru, + enum apll_frequencies apll_freq); + #endif /* __ASM_ARCH_CRU_RK3328_H_ */ diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index a89e2ecc4a..4331048a87 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -282,6 +282,8 @@ static void rkclk_init(struct rk3328_cru *cru) u32 hclk_div; u32 pclk_div;
+ rk3328_configure_cpu(cru, APLL_600_MHZ); + /* configure gpll cpll */ rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
On 2019/10/11 上午3:28, Simon South wrote:
Add a call to rk3328_configure_cpu() during initialization to set the CPU-clock frequency.
Signed-off-by: Simon South simon@simonsouth.net
Reviewed-by: Kever Yangkever.yang@rock-chips.com
Thanks, - Kever
arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 3 +++ drivers/clk/rockchip/clk_rk3328.c | 2 ++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h index 15b9788d9c..4bf69dbe08 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h @@ -66,4 +66,7 @@ enum apll_frequencies { APLL_600_MHZ, };
+void rk3328_configure_cpu(struct rk3328_cru *cru,
enum apll_frequencies apll_freq);- #endif /* __ASM_ARCH_CRU_RK3328_H_ */
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index a89e2ecc4a..4331048a87 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -282,6 +282,8 @@ static void rkclk_init(struct rk3328_cru *cru) u32 hclk_div; u32 pclk_div;
- rk3328_configure_cpu(cru, APLL_600_MHZ);
- /* configure gpll cpll */ rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
On 2019/10/14 下午5:06, Kever Yang wrote:
On 2019/10/11 上午3:28, Simon South wrote:
Add a call to rk3328_configure_cpu() during initialization to set the CPU-clock frequency.
Signed-off-by: Simon South simon@simonsouth.net
Reviewed-by: Kever Yangkever.yang@rock-chips.com
Applied to u-boot-rockchip master.
Thanks,
- Kever
arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 3 +++ drivers/clk/rockchip/clk_rk3328.c | 2 ++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h index 15b9788d9c..4bf69dbe08 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h @@ -66,4 +66,7 @@ enum apll_frequencies { APLL_600_MHZ, }; +void rk3328_configure_cpu(struct rk3328_cru *cru, + enum apll_frequencies apll_freq);
#endif /* __ASM_ARCH_CRU_RK3328_H_ */ diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index a89e2ecc4a..4331048a87 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -282,6 +282,8 @@ static void rkclk_init(struct rk3328_cru *cru) u32 hclk_div; u32 pclk_div; + rk3328_configure_cpu(cru, APLL_600_MHZ);
/* configure gpll cpll */ rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
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