[U-Boot] [PATCH] pepper: Add support for DDR3 variants
Some variants of the Gumstix Pepper board use DDR3 memory instead of DDR2. This adds a machine variant to support these DDR3-based boards which can be built as 'pepper_ddr3_defconfig' rather than the normal 'pepper_defconfig'.
Signed-off-by: Ash Charles ashcharles@gmail.com --- board/gumstix/pepper/MAINTAINERS | 1 + board/gumstix/pepper/board.c | 95 ++++++++++++++++++++++++++++++---------- configs/pepper_ddr3_defconfig | 4 ++ 3 files changed, 77 insertions(+), 23 deletions(-) create mode 100644 configs/pepper_ddr3_defconfig
diff --git a/board/gumstix/pepper/MAINTAINERS b/board/gumstix/pepper/MAINTAINERS index ae860ec..7132095 100644 --- a/board/gumstix/pepper/MAINTAINERS +++ b/board/gumstix/pepper/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/gumstix/pepper/ F: include/configs/pepper.h F: configs/pepper_defconfig +F: configs/pepper_ddr3_defconfig diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c index f644f81..fbbca3b 100644 --- a/board/gumstix/pepper/board.c +++ b/board/gumstix/pepper/board.c @@ -33,13 +33,55 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD -static const struct ddr_data ddr2_data = { +#define OSC (V_OSCK/1000000) + +#ifdef CONFIG_USE_DDR3 +static const struct ddr_data ddr_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +const struct dpll_params dpll_ddr = {400, OSC-1, 1, -1, -1, -1, -1}; + +const struct ctrl_ioregs ioregs_ddr = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +#else +static const struct ddr_data ddr_data = { .datardsratio0 = MT47H128M16RT25E_RD_DQS, .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, };
-static const struct cmd_control ddr2_cmd_ctrl_data = { +static const struct cmd_control ddr_cmd_ctrl_data = { .cmd0csratio = MT47H128M16RT25E_RATIO,
.cmd1csratio = MT47H128M16RT25E_RATIO, @@ -47,7 +89,7 @@ static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd2csratio = MT47H128M16RT25E_RATIO, };
-static const struct emif_regs ddr2_emif_reg_data = { +static const struct emif_regs ddr_emif_reg_data = { .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, @@ -56,6 +98,33 @@ static const struct emif_regs ddr2_emif_reg_data = { .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, };
+const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1}; + +const struct ctrl_ioregs ioregs_ddr = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; +#endif /* CONFIG_USE_DDR3 */ + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +void sdram_init(void) +{ +#ifdef CONFIG_USE_DDR3 + config_ddr(400, &ioregs_ddr, &ddr_data, + &ddr_cmd_ctrl_data, &ddr_emif_reg_data, 0); +#else + config_ddr(266, &ioregs_ddr, &ddr_data, + &ddr_cmd_ctrl_data, &ddr_emif_reg_data, 0); +#endif +} + #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { @@ -64,14 +133,6 @@ int spl_start_uboot(void) } #endif
-#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1}; - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - void set_uart_mux_conf(void) { enable_uart0_pin_mux(); @@ -82,19 +143,7 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); }
-const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, -};
-void sdram_init(void) -{ - config_ddr(266, &ioregs, &ddr2_data, - &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); -} #endif
int board_init(void) diff --git a/configs/pepper_ddr3_defconfig b/configs/pepper_ddr3_defconfig new file mode 100644 index 0000000..8077399 --- /dev/null +++ b/configs/pepper_ddr3_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USE_DDR3" +CONFIG_ARM=y +CONFIG_TARGET_PEPPER=y
On Tue, Apr 28, 2015 at 04:25:44PM -0700, Ash Charles wrote:
Some variants of the Gumstix Pepper board use DDR3 memory instead of DDR2. This adds a machine variant to support these DDR3-based boards which can be built as 'pepper_ddr3_defconfig' rather than the normal 'pepper_defconfig'.
Signed-off-by: Ash Charles ashcharles@gmail.com
There's no way to tell at run time which board we're on?
Hi Tom,
There is actually an EEPROM on new boards that we'd like to use in the future in order to detect that we should use DDR3 (and frankly, everything will be DDR3 going forward). We still don't have everything sorted in hardware and at the factories for programming the eeprom though. This patch was a shot at capturing and makes generally available the interim measure that has been carried for a bit on our Gumstix tree. If this is not appropriate for mainline, we can certainly carry it until hardware gets settled.
--Ash
On Tue, Apr 28, 2015 at 5:24 PM, Tom Rini trini@konsulko.com wrote:
On Tue, Apr 28, 2015 at 04:25:44PM -0700, Ash Charles wrote:
Some variants of the Gumstix Pepper board use DDR3 memory instead of DDR2. This adds a machine variant to support these DDR3-based boards which can be built as 'pepper_ddr3_defconfig' rather than the normal 'pepper_defconfig'.
Signed-off-by: Ash Charles ashcharles@gmail.com
There's no way to tell at run time which board we're on?
-- Tom
On Tue, Apr 28, 2015 at 05:50:53PM -0700, Ash Charles wrote:
Hi Tom,
There is actually an EEPROM on new boards that we'd like to use in the future in order to detect that we should use DDR3 (and frankly, everything will be DDR3 going forward). We still don't have everything sorted in hardware and at the factories for programming the eeprom though. This patch was a shot at capturing and makes generally available the interim measure that has been carried for a bit on our Gumstix tree. If this is not appropriate for mainline, we can certainly carry it until hardware gets settled.
Well, lets look at it this way. You got it posted before the merge window. Lets revisit this early July and see if this is still the direction you want to go in mainline for the hardware.
On Wed, Apr 29, 2015 at 2:36 PM, Tom Rini trini@konsulko.com wrote:
Well, lets look at it this way. You got it posted before the merge window. Lets revisit this early July and see if this is still the direction you want to go in mainline for the hardware.
Okay---that seems fair. Hopefully we can get hardware sorted on our end to use an EEPROM for DDR3 by then.
--Ash
From: Adam YH Lee adam.yh.lee@gmail.com
AM335x-based 'Gumstix Pepper' SBCs and variants use different types of RAM (DDR2 vs DDR3 with DDR3 being the default). Detect the board type by reading the factory-programmed EEPROM [1] and use this to select any runtime boot options such as RAM type.
[1] http://elinux.org/BeagleBoardPinMux#List_of_Vendor_and_Device_IDs
Signed-off-by: Adam YH Lee adam.yh.lee@gmail.com Signed-off-by: Ash Charles ashcharles@gmail.com --- board/gumstix/pepper/board.c | 124 ++++++++++++++++++++++++++++++++++++------- board/gumstix/pepper/board.h | 13 +++++ board/gumstix/pepper/mux.c | 5 ++ include/configs/pepper.h | 2 + 4 files changed, 124 insertions(+), 20 deletions(-)
diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c index f644f81..acf1c64 100644 --- a/board/gumstix/pepper/board.c +++ b/board/gumstix/pepper/board.c @@ -33,6 +33,46 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD +#define OSC (V_OSCK/1000000) + +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1}; + +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + static const struct ddr_data ddr2_data = { .datardsratio0 = MT47H128M16RT25E_RD_DQS, .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, @@ -56,6 +96,70 @@ static const struct emif_regs ddr2_emif_reg_data = { .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, };
+const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1}; + +const struct ctrl_ioregs ioregs_ddr2 = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; + +static int read_eeprom(struct pepper_board_id *header) +{ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + return -ENODEV; + } + + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct pepper_board_id))) { + return -EIO; + } + + return 0; +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + struct pepper_board_id header; + + enable_i2c0_pin_mux(); + i2c_set_bus_num(0); + + if (read_eeprom(&header) < 0) + return &dpll_ddr3; + + switch (header.device_vendor) { + case GUMSTIX_PEPPER: + return &dpll_ddr2; + case GUMSTIX_PEPPER_DVI: + return &dpll_ddr3; + default: + return &dpll_ddr3; + } +} + +void sdram_init(void) +{ + const struct dpll_params *dpll = get_dpll_ddr_params(); + + /* + * Here we are assuming PLL clock reveals the type of RAM. + * DDR2 = 266 + * DDR3 = 400 + * Note that DDR3 is the default. + */ + if (dpll->m == 266) { + config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data, + &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); + } + else if (dpll->m == 400) { + config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); + } +} + #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { @@ -64,14 +168,6 @@ int spl_start_uboot(void) } #endif
-#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1}; - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - void set_uart_mux_conf(void) { enable_uart0_pin_mux(); @@ -82,19 +178,7 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); }
-const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, -};
-void sdram_init(void) -{ - config_ddr(266, &ioregs, &ddr2_data, - &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); -} #endif
int board_init(void) diff --git a/board/gumstix/pepper/board.h b/board/gumstix/pepper/board.h index 0512735..a6df319 100644 --- a/board/gumstix/pepper/board.h +++ b/board/gumstix/pepper/board.h @@ -9,6 +9,18 @@ #ifndef _BOARD_H_ #define _BOARD_H_
+#define GUMSTIX_PEPPER 0x30000200 +#define GUMSTIX_PEPPER_DVI 0x31000200 + +struct pepper_board_id { + unsigned int device_vendor; + unsigned char revision; + unsigned char content; + char fab_revision[8]; + char env_var[16]; + char en_setting[64]; +}; + /* * We must be able to enable uart0, for initial output. We then have a * main pinmux function that can be overridden to enable all other pinmux that @@ -16,4 +28,5 @@ */ void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); #endif diff --git a/board/gumstix/pepper/mux.c b/board/gumstix/pepper/mux.c index 50b1266..92c73f8 100644 --- a/board/gumstix/pepper/mux.c +++ b/board/gumstix/pepper/mux.c @@ -64,6 +64,11 @@ void enable_uart0_pin_mux(void) configure_module_pin_mux(uart0_pin_mux); }
+void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + /* * Do board-specific muxes. */ diff --git a/include/configs/pepper.h b/include/configs/pepper.h index cc153ab..16149f6 100644 --- a/include/configs/pepper.h +++ b/include/configs/pepper.h @@ -20,6 +20,8 @@ #undef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT "pepper# "
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + /* Mach type */ #define MACH_TYPE_PEPPER 4207 /* Until the next sync */ #define CONFIG_MACH_TYPE MACH_TYPE_PEPPER
On Mon, Jun 01, 2015 at 02:29:09PM -0700, Ash Charles wrote:
From: Adam YH Lee adam.yh.lee@gmail.com
AM335x-based 'Gumstix Pepper' SBCs and variants use different types of RAM (DDR2 vs DDR3 with DDR3 being the default). Detect the board type by reading the factory-programmed EEPROM [1] and use this to select any runtime boot options such as RAM type.
[1] http://elinux.org/BeagleBoardPinMux#List_of_Vendor_and_Device_IDs
Signed-off-by: Adam YH Lee adam.yh.lee@gmail.com Signed-off-by: Ash Charles ashcharles@gmail.com
Applied to u-boot/master, thanks!
participants (2)
-
Ash Charles -
Tom Rini