On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

Before adding one more function, create a separate header to help reduce the size of common.h. Add the missing function comments and tidy up.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2:

• Use capitals for the header guard
• Change 'print' to 'Print' in comment

include/common.h | 16 +--------------- include/display_options.h | 48 +++++++++++++++++++++++++++++++++++++++++++++++ lib/display_options.c | 13 ------------- 3 files changed, 49 insertions(+), 28 deletions(-) create mode 100644 include/display_options.h

diff --git a/include/common.h b/include/common.h index cde3474..d4d704a 100644 --- a/include/common.h +++ b/include/common.h @@ -192,22 +192,8 @@ int cpu_init(void);

/* */ phys_size_t initdram (int); -int display_options (void);

-/**

• • print_size() - Print a size with a suffic
• • print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB",
• • xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string
• • (like "\n")
• • @size: Size to print
• • @suffix String to print after the size
• */

-void print_size(uint64_t size, const char *suffix);

-int print_buffer(ulong addr, const void *data, uint width, uint count,

•            uint linelen);
  

+#include <display_options.h>

/* common/main.c */ void main_loop (void); diff --git a/include/display_options.h b/include/display_options.h new file mode 100644 index 0000000..54bd41d --- /dev/null +++ b/include/display_options.h @@ -0,0 +1,48 @@ +/*

• • Copyright (c) 2015 Google, Inc
• • (C) Copyright 2000-2002
• • Wolfgang Denk, DENX Software Engineering, wd@denx.de.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __DISPLAY_OPTIONS_H +#define __DISPLAY_OPTIONS_H

+/**

• • print_size() - Print a size with a suffix
• • Print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB",
• • xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string
• • (like "\n")
• • @size: Size to print
• • @suffix String to print after the size
• */

+void print_size(uint64_t size, const char *suffix);

+/**

• • print_buffer() - Print data buffer in hex and ascii form
• • Data reads are buffered so that each memory address is only read once.
• • This is useful when displaying the contents of volatile registers.
• • @addr: Starting address to display at start of line
• • @data: pointer to data buffer
• • @width: data value width. May be 1, 2, or 4.
• • @count: number of values to display
• • @linelen: Number of values to print per line; specify 0 for default length
• */

+int print_buffer(ulong addr, const void *data, uint width, uint count,

•            uint linelen);
  

+/**

• • display_options() - display the version string / build tag
• • This displays the U-Boot version string. If a build tag is available this
• • is displayed also.
• */

+int display_options(void);

+#endif diff --git a/lib/display_options.c b/lib/display_options.c index d5d17b2..3f32bcd 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -63,19 +63,6 @@ void print_size(uint64_t size, const char *s) printf (" %ciB%s", c, s); }

-/*

• • Print data buffer in hex and ascii form to the terminal.
• • data reads are buffered so that each memory address is only read once.
• • Useful when displaying the contents of volatile registers.
• • parameters:
• • addr: Starting address to display at start of line
• • data: pointer to data buffer
• • width: data value width. May be 1, 2, or 4.
• • count: number of values to display
• • linelen: Number of values to print per line; specify 0 for default length
• */

#define MAX_LINE_LENGTH_BYTES (64) #define DEFAULT_LINE_LENGTH_BYTES (16) int print_buffer(ulong addr, const void *data, uint width, uint count, --

Reviewed-by: Bin Meng bmeng.cn@gmail.com

Hi Bin,

On 28 April 2015 at 22:56, Bin Meng bmeng.cn@gmail.com wrote:

Hi Simon,

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

...

Add a function similar to print_size() that works for frequencies. It can handle from Hz to GHz.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2:

• Correct bugs in number output

include/display_options.h | 11 +++++++++++ lib/display_options.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+)

diff --git a/include/display_options.h b/include/display_options.h index 54bd41d..ac44c45 100644 --- a/include/display_options.h +++ b/include/display_options.h @@ -23,6 +23,17 @@ void print_size(uint64_t size, const char *suffix);

/**

• • print_freq() - Print a frequency with a suffix
• • Print frequencies as "x.xx GHz", "xxx KHz", etc as needed; allow for
• • optional trailing string (like "\n")
• • @freq: Frequency to print in Hz
• • @suffix String to print after the frequency
• */

+void print_freq(uint64_t freq, const char *suffix);

+/**

• print_buffer() - Print data buffer in hex and ascii form
• Data reads are buffered so that each memory address is only read once.

diff --git a/lib/display_options.c b/lib/display_options.c index 3f32bcd..3a70e14 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -7,6 +7,7 @@

#include <config.h> #include <common.h> +#include <div64.h> #include <inttypes.h> #include <version.h> #include <linux/ctype.h> @@ -22,6 +23,43 @@ int display_options (void) return 0; }

+void print_freq(uint64_t freq, const char *s) +{

•   unsigned long m = 0, n;
  

•   uint64_t f;
  

•   static const char names[] = {'G', 'M', 'K'};
  

•   unsigned long d = 1e9;
  

•   char c = 0;
  

•   unsigned int i;
  

•   for (i = 0; i < ARRAY_SIZE(names); i++, d /= 1000) {
  

•           if (freq >= d) {
  

•                   c = names[i];
  

•                   break;
  

•           }
  

•   }
  

•   if (!c) {
  

•           printf("%" PRIu64 " Hz%s", freq, s);
  

•           return;
  

•   }
  

•   f = do_div(freq, d);
  

•   n = freq;
  

•   /* If there's a remainder, show the first few digits */
  

•   if (f) {
  

•           m = f % d;
  

•           while (!(m % 10))
  

•                   m /= 10;
  

•   }
  

This 'first few digits' issue is not fixed. Do you intend to print all numbers after the radix point? If yes, then we need fix the comment to say all numbers will be printed.

I think it is better not to. I'll change my tests a bit and send a new version of just this patch.

Regards, Simon

Hi Simon,

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

It is useful to be able to keep track of the available CPUs in a multi-CPU system. This uclass is mostly intended for use with SMP systems.

The uclass provides methods for getting basic information about each CPU.

Signed-off-by: Simon Glass sjg@chromium.org

Reviewed-by: Bin Meng bmeng.cn@gmail.com

But one comment raised previously not addressed below.

Changes in v2:

• Change header guard to capital letters
• Change get_info() in function comment to cpu_get_info()

drivers/Kconfig | 2 ++ drivers/Makefile | 1 + drivers/cpu/Kconfig | 8 +++++ drivers/cpu/Makefile | 7 ++++ drivers/cpu/cpu-uclass.c | 61 +++++++++++++++++++++++++++++++++++ include/cpu.h | 84 ++++++++++++++++++++++++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + 7 files changed, 164 insertions(+) create mode 100644 drivers/cpu/Kconfig create mode 100644 drivers/cpu/Makefile create mode 100644 drivers/cpu/cpu-uclass.c create mode 100644 include/cpu.h

diff --git a/drivers/Kconfig b/drivers/Kconfig index 941aa0c..1f40887 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -2,6 +2,8 @@ menu "Device Drivers"

source "drivers/core/Kconfig"

+source "drivers/cpu/Kconfig"

source "drivers/demo/Kconfig"

source "drivers/pci/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 5ef58c0..405b64b 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_DM_DEMO) += demo/ obj-$(CONFIG_BIOSEMU) += bios_emulator/ obj-y += block/ obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/ +obj-$(CONFIG_CPU) += cpu/ obj-y += crypto/ obj-$(CONFIG_FPGA) += fpga/ obj-y += hwmon/ diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig new file mode 100644 index 0000000..0d1424d --- /dev/null +++ b/drivers/cpu/Kconfig @@ -0,0 +1,8 @@ +config CPU

Should it be DM_CPU? Like other DM drivers (DM_SERIAL, DM_I2C, etc).

•   bool "Enable CPU drivers using Driver Model"
  

•   help
  

•     This allows drivers to be provided for CPUs and their type to be
  

•     specified in the board's device tree. For boards which support
  

•     multiple CPUs, then normally have to be set up in U-Boot so that
  

•     they can work correctly in the OS. This provides a framework for
  

•     finding out information about available CPUs and making changes.
  

[snip]

Regards, Bin

Hi Simon,

On Wed, Apr 29, 2015 at 9:32 PM, Simon Glass sjg@chromium.org wrote:

Hi Bin,

On 28 April 2015 at 23:01, Bin Meng bmeng.cn@gmail.com wrote:

...

Hi Simon,

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

...

It is useful to be able to keep track of the available CPUs in a multi-CPU system. This uclass is mostly intended for use with SMP systems.

The uclass provides methods for getting basic information about each CPU.

Signed-off-by: Simon Glass sjg@chromium.org

Reviewed-by: Bin Meng bmeng.cn@gmail.com

But one comment raised previously not addressed below.

...

Changes in v2:

• Change header guard to capital letters
• Change get_info() in function comment to cpu_get_info()

drivers/Kconfig | 2 ++ drivers/Makefile | 1 + drivers/cpu/Kconfig | 8 +++++ drivers/cpu/Makefile | 7 ++++ drivers/cpu/cpu-uclass.c | 61 +++++++++++++++++++++++++++++++++++ include/cpu.h | 84 ++++++++++++++++++++++++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + 7 files changed, 164 insertions(+) create mode 100644 drivers/cpu/Kconfig create mode 100644 drivers/cpu/Makefile create mode 100644 drivers/cpu/cpu-uclass.c create mode 100644 include/cpu.h

diff --git a/drivers/Kconfig b/drivers/Kconfig index 941aa0c..1f40887 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -2,6 +2,8 @@ menu "Device Drivers"

source "drivers/core/Kconfig"

+source "drivers/cpu/Kconfig"

source "drivers/demo/Kconfig"

source "drivers/pci/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 5ef58c0..405b64b 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_DM_DEMO) += demo/ obj-$(CONFIG_BIOSEMU) += bios_emulator/ obj-y += block/ obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/ +obj-$(CONFIG_CPU) += cpu/ obj-y += crypto/ obj-$(CONFIG_FPGA) += fpga/ obj-y += hwmon/ diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig new file mode 100644 index 0000000..0d1424d --- /dev/null +++ b/drivers/cpu/Kconfig @@ -0,0 +1,8 @@ +config CPU

Should it be DM_CPU? Like other DM drivers (DM_SERIAL, DM_I2C, etc).

...

•   bool "Enable CPU drivers using Driver Model"
  

•   help
  

•     This allows drivers to be provided for CPUs and their type to be
  

•     specified in the board's device tree. For boards which support
  

•     multiple CPUs, then normally have to be set up in U-Boot so that
  

•     they can work correctly in the OS. This provides a framework for
  

•     finding out information about available CPUs and making changes.
  

I prefer only using the DM prefix when there is a non-DM option. In fact the way it is supposed to work is that eventually the CONFIG_DM... option goes away. When every board uses DM for a subsystem we should be able to drop it.

Good to know that those CONFIG_DM_xxx will eventually go away.

CPU support (or whatever we call it) will only be available with driver model, so I don't think we need separate CONFIG_CPU and CONFIG_DM_CPU options.

OK.

Regards, Bin

On 28 April 2015 at 23:16, Bin Meng bmeng.cn@gmail.com wrote:

Hi Simon,

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

...

This provides a way of passing information to Linux without requiring the full ACPI horror. Provide a rudimentary implementation sufficient to be recognised and parsed by Linux.

Signed-off-by: Simon Glass sjg@chromium.org

Looks good, thanks!

Reviewed-by: Bin Meng bmeng.cn@gmail.com

Applied to u-boot-x86.

(fixed nits)

But some nits below :)

...

Changes in v2:

• Rename CONFIG_SFI to CONFIG_GENERATE_SFI_TABLE and move within Kconfig
• Correct Kconfig help indentation and text
• Drop SFI_BASE config option
• Always build sfi.o
• Use SFI_TABLE_MAX_ENTRIES instead of 16 and ARRAY_SIZE()
• Make get_entry_start() static
• Use table_compute_checksum() to computer checksum
• Add a few blank lines
• Move patch to after the CPU uclass patch
• Drop the RTC table as it is not needed
• Move SFI calling code to write_tables()
• Remove IDLE table
• Remove SFI_SYST_SEARCH_BEGIN and SFI_SYST_SEARCH_END
• Move '__packed' to immediately after 'struct'
• Add SFI_DEV_TYPE_SD and convert to enum
• Remove #ifdef CONFIG_SFI from hedaer file
• Move sfi.h header file to arch/x86/include/asm

arch/x86/Kconfig | 14 +++++ arch/x86/include/asm/sfi.h | 137 ++++++++++++++++++++++++++++++++++++++++ arch/x86/lib/Makefile | 1 + arch/x86/lib/sfi.c | 154 +++++++++++++++++++++++++++++++++++++++++++++ arch/x86/lib/tables.c | 5 ++ 5 files changed, 311 insertions(+) create mode 100644 arch/x86/include/asm/sfi.h create mode 100644 arch/x86/lib/sfi.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f3a600e..f38e9ba 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -393,6 +393,20 @@ config GENERATE_PIRQ_TABLE It specifies the interrupt router information as well how all the PCI devices' interrupt pins are wired to PIRQs.

+config GENERATE_SFI_TABLE

•   bool "SFI (Simple Firmware Interface) Support"
  

Should we say: Generate an SFI (Simple Firmware Interface) table? This is to match 'Generate a PIRQ table'.

...

•   help
  

•     The Simple Firmware Interface (SFI) provides a lightweight method
  

•     for platform firmware to pass information to the operating system
  

•     via static tables in memory.  Kernel SFI support is required to
  

•     boot on SFI-only platforms.  If you have ACPI tables then these are
  

•     used instead.
  

•     U-Boot writes this table in sfi_write_tables() just before booting
  

Should be: write_sfi_table

...

•     the OS.
  

•     For more information, see http://simplefirmware.org
  

endmenu

[snip]

Regards, Bin

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

Provide access to this x86 instruction from C code.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2:

• Remove unnecessary \t\n after mfence assembler instruction

arch/x86/include/asm/cpu.h | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index c839291..08284ee 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -151,6 +151,11 @@ static inline int flag_is_changeable_p(uint32_t flag) return ((f1^f2) & flag) != 0; }

+static inline void mfence(void) +{

•   __asm__ __volatile__("mfence" : : : "memory");
  

+}

/**

• cpu_enable_paging_pae() - Enable PAE-paging

--

Reviewed-by: Bin Meng bmeng.cn@gmail.com

On 28 April 2015 at 23:23, Bin Meng bmeng.cn@gmail.com wrote:

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

...

Add a function to return the address of the Interrupt Descriptor Table.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2: None

arch/x86/cpu/interrupts.c | 5 +++++ arch/x86/include/asm/interrupt.h | 2 ++ 2 files changed, 7 insertions(+)

diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index a21d2a6..c777d36 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -147,6 +147,11 @@ int cpu_init_interrupts(void) return 0; }

+void *x86_get_idt(void) +{

•   return &idt_ptr;
  

+}

void __do_irq(int irq) { printf("Unhandled IRQ : %d\n", irq); diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index 25abde7..0a75f89 100644 --- a/arch/x86/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -38,4 +38,6 @@ extern char exception_stack[]; */ void configure_irq_trigger(int int_num, bool is_level_triggered);

+void *x86_get_idt(void);

#endif

Reviewed-by: Bin Meng bmeng.cn@gmail.com

Applied to u-boot-x86.

Hi Simon,

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

Most modern x86 CPUs include more than one CPU core. The OS normally requires that these 'Application Processors' (APs) be brought up by the boot loader. Add the required support to U-Boot to init additional APs.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2: None

arch/x86/Kconfig | 25 ++ arch/x86/cpu/Makefile | 2 + arch/x86/cpu/ivybridge/model_206ax.c | 4 +- arch/x86/cpu/mp_init.c | 507 +++++++++++++++++++++++++++++++++++ arch/x86/cpu/sipi.S | 215 +++++++++++++++ arch/x86/include/asm/mp.h | 94 +++++++ arch/x86/include/asm/sipi.h | 79 ++++++ arch/x86/include/asm/smm.h | 14 + 8 files changed, 938 insertions(+), 2 deletions(-) create mode 100644 arch/x86/cpu/mp_init.c create mode 100644 arch/x86/cpu/sipi.S create mode 100644 arch/x86/include/asm/mp.h create mode 100644 arch/x86/include/asm/sipi.h create mode 100644 arch/x86/include/asm/smm.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f38e9ba..f89ee5c 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -361,6 +361,31 @@ config FSP_TEMP_RAM_ADDR Stack top address which is used in FspInit after DRAM is ready and CAR is disabled.

+config MAX_CPUS

•    int "Maximum number of CPUs permitted"
  

•    default 4
  

•    help
  

•      When using multi-CPU chips it is possible for U-Boot to start up
  

•      more than one CPU. The stack memory used by all of these CPUs is
  

•      pre-allocated so at present U-Boot wants to know the maximum
  

•      number of CPUs that may be present. Set this to at least as high
  

•      as the number of CPUs in your system (it uses about 4KB of RAM for
  

•      each CPU).
  

+config SMP

•   bool "Enable Symmetric Multiprocessing"
  

•   default n
  

•   help
  

•     Enable use of more than one CPU in U-Boot and the Operating System
  

•     when loaded. Each CPU will be started up and information can be
  

•     obtained using the 'cpu' command. If this option is disabled, then
  

•     only one CPU will be enabled regardless of the number of CPUs
  

•     available.
  

+config STACK_SIZE

•   hex
  

•   default 0x1000
  

The name looks too generic. Maybe AP_STACK_SIZE? Please also include a help text.

config TSC_CALIBRATION_BYPASS bool "Bypass Time-Stamp Counter (TSC) calibration" default n diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 6ded0a7..9a08ab4 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -19,6 +19,8 @@ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-y += lapic.o +obj-$(CONFIG_SMP) += mp_init.o obj-y += mtrr.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_SMP) += sipi.o obj-y += turbo.o diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 11dc625..8b08c40 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -435,8 +435,8 @@ static int intel_cores_init(struct x86_cpu_priv *cpu)

            debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id);

-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1

•           /* Start the new cpu */
  

+#if 0 && CONFIG_SMP && CONFIG_MAX_CPUS > 1

•           /* TODO(sjg@chromium.org): Start the new cpu */
            if (!start_cpu(new_cpu)) {
                    /* Record the error in cpu? */
                    printk(BIOS_ERR, "CPU %u would not start!\n",
  

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c new file mode 100644 index 0000000..c1fd4e0 --- /dev/null +++ b/arch/x86/cpu/mp_init.c @@ -0,0 +1,507 @@ +/*

• • Copyright (C) 2015 Google, Inc
• • SPDX-License-Identifier: GPL-2.0+
• • Based on code from the coreboot file of the same name
• */

+#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <errno.h> +#include <malloc.h> +#include <asm/atomic.h> +#include <asm/cpu.h> +#include <asm/interrupt.h> +#include <asm/lapic.h> +#include <asm/mp.h> +#include <asm/mtrr.h> +#include <asm/sipi.h> +#include <asm/smm.h> +#include <dm/device-internal.h> +#include <dm/uclass-internal.h> +#include <linux/linkage.h>

+/* This also needs to match the sipi.S assembly code for saved MSR encoding */ +struct saved_msr {

•   uint32_t index;
  

•   uint32_t lo;
  

•   uint32_t hi;
  

+} __packed;

+/*

• • The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the
• • memory range is already reserved so the OS cannot use it. That region is
• • free to use for AP bringup before SMM is initialised.
• */

+static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE; +static const int sipi_vector_location_size = SMM_DEFAULT_SIZE;

Since they are static and const, we can just use the macro directly without declare a variable.

+struct mp_flight_plan {

•   int num_records;
  

•   struct mp_flight_record *records;
  

+};

+static struct mp_flight_plan mp_info;

+struct cpu_map {

•   struct udevice *dev;
  

•   int apic_id;
  

•   int err_code;
  

+};

+static inline void barrier_wait(atomic_t *b) +{

•   while (atomic_read(b) == 0)
  

•           asm("pause");
  

•   mfence();
  

+}

+static inline void release_barrier(atomic_t *b) +{

•   mfence();
  

•   atomic_set(b, 1);
  

+}

+/* Returns 1 if timeout waiting for APs. 0 if target APs found */ +static int wait_for_aps(atomic_t *val, int target, int total_delay,

•                   int delay_step)
  

+{

•   int timeout = 0;
  

•   int delayed = 0;
  

•   while (atomic_read(val) != target) {
  

•           udelay(delay_step);
  

•           delayed += delay_step;
  

•           if (delayed >= total_delay) {
  

•                   timeout = 1;
  

•                   break;
  

•           }
  

•   }
  

•   return timeout;
  

+}

+static void ap_do_flight_plan(struct udevice *cpu) +{

•   int i;
  

•   for (i = 0; i < mp_info.num_records; i++) {
  

•           struct mp_flight_record *rec = &mp_info.records[i];
  

•           atomic_inc(&rec->cpus_entered);
  

•           barrier_wait(&rec->barrier);
  

•           if (rec->ap_call != NULL)
  

•                   rec->ap_call(cpu, rec->ap_arg);
  

•   }
  

+}

+static int find_cpu_by_apid_id(int apic_id, struct udevice **devp) +{

•   struct udevice *dev;
  

•   *devp = NULL;
  

•   for (uclass_find_first_device(UCLASS_CPU, &dev);
  

•        dev;
  

•        uclass_find_next_device(&dev)) {
  

•           struct cpu_platdata *plat = dev_get_parent_platdata(dev);
  

•           if (plat->cpu_id == apic_id) {
  

•                   *devp = dev;
  

•                   return 0;
  

•           }
  

•   }
  

•   return -ENOENT;
  

+}

+/*

• • By the time APs call ap_init() caching has been setup, and microcode has
• • been loaded
• */

+static void asmlinkage ap_init(unsigned int cpu_index)

Is asmlinkage a must? I think we can pass cpu_index via eax.

+{

•   struct udevice *dev;
  

•   int apic_id;
  

•   int ret;
  

•   /* Ensure the local apic is enabled */
  

•   enable_lapic();
  

•   apic_id = lapicid();
  

•   ret = find_cpu_by_apid_id(apic_id, &dev);
  

•   if (ret) {
  

•           debug("Unknown CPU apic_id %x\n", apic_id);
  

•           goto done;
  

•   }
  

•   debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id,
  

•         dev ? dev->name : "(apic_id not found)");
  

•   /* Walk the flight plan */
  

•   ap_do_flight_plan(dev);
  

•   /* Park the AP */
  

•   debug("parking\n");
  

+done:

•   stop_this_cpu();
  

+}

+#define NUM_FIXED_MTRRS 11

Can we move this to the MTRR patch (#11 of this series)? So that NUM_FIXED_RANGES in patch#11 can be defined as

#define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR)

+static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {

•   MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR,
  

•   MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR,
  

•   MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR,
  

•   MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR,
  

+};

+static inline struct saved_msr *save_msr(int index, struct saved_msr *entry) +{

•   msr_t msr;
  

•   msr = msr_read(index);
  

•   entry->index = index;
  

•   entry->lo = msr.lo;
  

•   entry->hi = msr.hi;
  

•   /* Return the next entry */
  

•   entry++;
  

•   return entry;
  

+}

+static int save_bsp_msrs(char *start, int size) +{

•   int msr_count;
  

•   int num_var_mtrrs;
  

•   struct saved_msr *msr_entry;
  

•   int i;
  

•   msr_t msr;
  

•   /* Determine number of MTRRs need to be saved */
  

•   msr = msr_read(MTRR_CAP_MSR);
  

•   num_var_mtrrs = msr.lo & 0xff;
  

•   /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */
  

•   msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
  

•   if ((msr_count * sizeof(struct saved_msr)) > size) {
  

•           printf("Cannot mirror all %d msrs.\n", msr_count);
  

•           return -ENOSPC;
  

•   }
  

•   msr_entry = (void *)start;
  

•   for (i = 0; i < NUM_FIXED_MTRRS; i++)
  

•           msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
  

•   for (i = 0; i < num_var_mtrrs; i++) {
  

•           msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry);
  

•           msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry);
  

•   }
  

•   msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
  

•   return msr_count;
  

+}

+static int load_sipi_vector(atomic_t **ap_countp) +{

•   struct sipi_params_16bit *params16;
  

•   struct sipi_params *params;
  

•   static char msr_save[512];
  

•   char *stack;
  

•   ulong addr;
  

•   int code_len;
  

•   int size;
  

•   int ret;
  

•   /* Copy in the code */
  

•   code_len = ap_start16_code_end - ap_start16;
  

•   debug("Copying SIPI code to %x: %d bytes\n", SMM_DEFAULT_BASE,
  

•         code_len);
  

•   memcpy((void *)SMM_DEFAULT_BASE, ap_start16, code_len);
  

•   addr = SMM_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16;
  

•   params16 = (struct sipi_params_16bit *)addr;
  

•   params16->ap_start = (uint32_t)ap_start;
  

My read of this is that AP will jump to the flash address of ap_start (pre-relocation)? Is this intentional?

•   params16->gdt = (uint32_t)gd->arch.gdt;
  

•   params16->gdt_limit = X86_GDT_SIZE - 1;
  

•   debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit);
  

•   params = (struct sipi_params *)sipi_params;
  

•   debug("SIPI 32-bit params at %p\n", params);
  

•   params->idt_ptr = (uint32_t)x86_get_idt();
  

•   params->stack_size = 4096;
  

•   size = params->stack_size * CONFIG_MAX_CPUS;
  

•   stack = memalign(size, 4096);
  

•   if (!stack)
  

•           return -ENOMEM;
  

•   params->stack_top = (u32)(stack + size);
  

•   params->microcode_ptr = 0;
  

•   params->msr_table_ptr = (u32)msr_save;
  

•   ret = save_bsp_msrs(msr_save, sizeof(msr_save));
  

•   if (ret < 0)
  

•           return ret;
  

•   params->msr_count = ret;
  

•   params->c_handler = (uint32_t)&ap_init;
  

Also here flash address of ap_init()?

•   *ap_countp = &params->ap_count;
  

•   atomic_set(*ap_countp, 0);
  

•   debug("SIPI vector is ready\n");
  

•   return 0;
  

+}

+static int check_cpu_devices(int expected_cpus) +{

•   int i;
  

•   for (i = 0; i < expected_cpus; i++) {
  

•           struct udevice *dev;
  

•           int ret;
  

•           ret = uclass_find_device(UCLASS_CPU, i, &dev);
  

•           if (ret) {
  

•                   debug("Cannot find CPU %d in device tree\n", i);
  

•                   return ret;
  

•           }
  

•   }
  

•   return 0;
  

+}

+/* Returns 1 for timeout. 0 on success */ +static int apic_wait_timeout(int total_delay, int delay_step) +{

•   int total = 0;
  

•   int timeout = 0;
  

•   while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
  

•           udelay(delay_step);
  

•           total += delay_step;
  

•           if (total >= total_delay) {
  

•                   timeout = 1;
  

•                   break;
  

•           }
  

•   }
  

•   return timeout;
  

+}

+static int start_aps(int ap_count, atomic_t *num_aps) +{

•   int sipi_vector;
  

•   /* Max location is 4KiB below 1MiB */
  

•   const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
  

•   if (ap_count == 0)
  

•           return 0;
  

•   /* The vector is sent as a 4k aligned address in one byte */
  

•   sipi_vector = sipi_vector_location >> 12;
  

•   if (sipi_vector > max_vector_loc) {
  

•           printf("SIPI vector too large! 0x%08x\n",
  

•                  sipi_vector);
  

•           return -1;
  

•   }
  

Guess this sanity check is not necessary given we hardcode the sipi_vector to 0x30.

•   debug("Attempting to start %d APs\n", ap_count);
  

•   if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
  

•           debug("Waiting for ICR not to be busy...");
  

•           if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
  

Can we move the /* 1ms */ comment out of the codes? If we fix, please fix this globally in this file.

•                   debug("timed out. Aborting.\n");
  

•                   return -1;
  

•           } else {
  

•                   debug("done.\n");
  

•           }
  

•   }
  

•   /* Send INIT IPI to all but self */
  

•   lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
  

•   lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
  

•                      LAPIC_DM_INIT);
  

•   debug("Waiting for 10ms after sending INIT.\n");
  

•   mdelay(10);
  

•   /* Send 1st SIPI */
  

•   if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
  

•           debug("Waiting for ICR not to be busy...");
  

•           if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
  

•                   debug("timed out. Aborting.\n");
  

•                   return -1;
  

•           } else {
  

•                   debug("done.\n");
  

•           }
  

•   }
  

•   lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
  

•   lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
  

•                      LAPIC_DM_STARTUP | sipi_vector);
  

•   debug("Waiting for 1st SIPI to complete...");
  

•   if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) {
  

•           debug("timed out.\n");
  

•           return -1;
  

•   } else {
  

•           debug("done.\n");
  

•   }
  

•   /* Wait for CPUs to check in up to 200 us */
  

•   wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */);
  

•   /* Send 2nd SIPI */
  

•   if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
  

•           debug("Waiting for ICR not to be busy...");
  

•           if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
  

•                   debug("timed out. Aborting.\n");
  

•                   return -1;
  

•           } else {
  

•                   debug("done.\n");
  

•           }
  

•   }
  

•   lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
  

•   lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
  

•                      LAPIC_DM_STARTUP | sipi_vector);
  

•   debug("Waiting for 2nd SIPI to complete...");
  

•   if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) {
  

•           debug("timed out.\n");
  

•           return -1;
  

•   } else {
  

•           debug("done.\n");
  

•   }
  

•   /* Wait for CPUs to check in */
  

•   if (wait_for_aps(num_aps, ap_count, 10000 /* 10 ms */, 50 /* us */)) {
  

•           debug("Not all APs checked in: %d/%d.\n",
  

•                 atomic_read(num_aps), ap_count);
  

•           return -1;
  

•   }
  

•   return 0;
  

+}

+static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params) +{

•   int i;
  

•   int ret = 0;
  

•   const int timeout_us = 100000;
  

•   const int step_us = 100;
  

•   int num_aps = mp_params->num_cpus - 1;
  

•   for (i = 0; i < mp_params->num_records; i++) {
  

•           struct mp_flight_record *rec = &mp_params->flight_plan[i];
  

•           /* Wait for APs if the record is not released */
  

•           if (atomic_read(&rec->barrier) == 0) {
  

•                   /* Wait for the APs to check in */
  

•                   if (wait_for_aps(&rec->cpus_entered, num_aps,
  

•                                    timeout_us, step_us)) {
  

•                           debug("MP record %d timeout.\n", i);
  

•                           ret = -1;
  

•                   }
  

•           }
  

•           if (rec->bsp_call != NULL)
  

•                   rec->bsp_call(cpu, rec->bsp_arg);
  

•           release_barrier(&rec->barrier);
  

•   }
  

•   return ret;
  

+}

+static int init_bsp(struct udevice **devp) +{

•   char processor_name[CPU_MAX_NAME_LEN];
  

•   int apic_id;
  

•   int ret;
  

•   cpu_get_name(processor_name);
  

•   debug("CPU: %s.\n", processor_name);
  

•   enable_lapic();
  

•   apic_id = lapicid();
  

•   ret = find_cpu_by_apid_id(apic_id, devp);
  

•   if (ret) {
  

•           printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
  

•           return ret;
  

•   }
  

•   return 0;
  

+}

+int mp_init(struct mp_params *p) +{

•   int num_aps;
  

•   atomic_t *ap_count;
  

•   struct udevice *cpu;
  

•   int ret;
  

•   /* This will cause the CPUs devices to be bound */
  

•   struct uclass *uc;
  

•   ret = uclass_get(UCLASS_CPU, &uc);
  

•   if (ret)
  

•           return ret;
  

•   ret = init_bsp(&cpu);
  

•   if (ret) {
  

•           debug("Cannot init boot CPU: err=%d\n", ret);
  

•           return ret;
  

•   }
  

•   if (p == NULL || p->flight_plan == NULL || p->num_records < 1) {
  

•           printf("Invalid MP parameters\n");
  

•           return -1;
  

•   }
  

•   ret = check_cpu_devices(p->num_cpus);
  

•   if (ret)
  

•           debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
  

•   /* Copy needed parameters so that APs have a reference to the plan */
  

•   mp_info.num_records = p->num_records;
  

•   mp_info.records = p->flight_plan;
  

•   /* Load the SIPI vector */
  

•   ret = load_sipi_vector(&ap_count);
  

•   if (ap_count == NULL)
  

•           return -1;
  

•   /*
  

•    * Make sure SIPI data hits RAM so the APs that come up will see
  

•    * the startup code even if the caches are disabled
  

•    */
  

•   wbinvd();
  

•   /* Start the APs providing number of APs and the cpus_entered field */
  

•   num_aps = p->num_cpus - 1;
  

•   ret = start_aps(num_aps, ap_count);
  

•   if (ret) {
  

•           mdelay(1000);
  

•           debug("%d/%d eventually checked in?\n", atomic_read(ap_count),
  

•                 num_aps);
  

•           return ret;
  

•   }
  

•   /* Walk the flight plan for the BSP */
  

•   ret = bsp_do_flight_plan(cpu, p);
  

•   if (ret) {
  

•           debug("CPU init failed: err=%d\n", ret);
  

•           return ret;
  

•   }
  

•   return 0;
  

+}

+int mp_init_cpu(struct udevice *cpu, void *unused) +{

•   return device_probe(cpu);
  

+} diff --git a/arch/x86/cpu/sipi.S b/arch/x86/cpu/sipi.S new file mode 100644 index 0000000..09fde21 --- /dev/null +++ b/arch/x86/cpu/sipi.S @@ -0,0 +1,215 @@ +/*

• • Copyright (c) 2015 Google, Inc
• • SPDX-License-Identifier: GPL-2.0
• • Taken from coreboot file of the same name

Looks that this is from coreboot is sipi_vector.S. Should we keep the same file name as coreboot?

• */

+/*

• • The SIPI vector is responsible for initializing the APs in the sytem. It
• • loads microcode, sets up MSRs, and enables caching before calling into
• • C code
• */

+#include <asm/global_data.h> +#include <asm/msr-index.h> +#include <asm/processor.h> +#include <asm/processor-flags.h> +#include <asm/smm.h>

+#define CODE_SEG (X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE) +#define DATA_SEG (X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE)

+#define o32 .byte 0x66;

data32 directly?

+/*

• • First we have the 16-bit section. Every AP process starts here.
• • The simple task is to load U-Boot's Global Descriptor Table (GDT) to allow
• • U-Boot's 32-bit code to become visible, then jump to ap_start32.

ap_start

• • Note that this code is copied to RAM below 1MB in mp_init.c, and runs from
• • there, but the 32-bit code (ap_start32 and onwards) is part of U-Boot and

ap_start

• • is therefore relocated to the top of RAM with other U-Boot code. This
• • means that for the 16-bit code we must write relocatable code, but for the
• • rest, we can do what we like.
• */

+.text +.code16 +.globl ap_start16 +ap_start16:

•   cli
  

•   xorl    %eax, %eax
  

•   movl    %eax, %cr3              /* Invalidate TLB */
  

•   /* setup the data segment */
  

•   movw    %cs, %ax
  

•   movw    %ax, %ds
  

•   /* Use an address relative to the data segment for the GDT */
  

•   movl    $gdtaddr, %ebx
  

•   subl    $ap_start16, %ebx
  

•   data32 lgdt (%ebx)
  

•   movl    %cr0, %eax
  

•   andl    $0x7ffaffd1, %eax       /* PG, AM, WP, NE, TS, EM, MP = 0 */
  

•   orl     $0x60000001, %eax       /* CD, NW, PE = 1 */
  

•   movl    %eax, %cr0
  

Can we use macros for the cr0 bit fileds? Like we used in arch/x86/cpu/start16.S

•   movl    $ap_start_jmp, %eax
  

•   subl    $ap_start16, %eax
  

•   movw    %ax, %bp
  

•   /* Jump to ap_start32 within U-Boot */
  

ap_start

+o32 cs ljmp *(%bp)

•   .align  4
  

+.globl sipi_params_16bit +sipi_params_16bit:

•   /* 48-bit far pointer */
  

+ap_start_jmp:

•   .long   0               /* offset set to ap_start by U-Boot */
  

•   .word   CODE_SEG        /* segment */
  

•   .word   0               /* padding */
  

+gdtaddr:

•   .word   0 /* limit */
  

•   .long   0 /* table */
  

•   .word   0 /* unused */
  

+.globl ap_start16_code_end +ap_start16_code_end:

+/*

• • Set up the special 'fs' segment for global_data. Then jump to ap_continue
• • to set up the AP.
• */

+.globl ap_start +ap_start:

•   .code32
  

•   movw    $DATA_SEG, %ax
  

•   movw    %ax, %ds
  

•   movw    %ax, %es
  

•   movw    %ax, %ss
  

•   movw    %ax, %gs
  

•   movw    $(X86_GDT_ENTRY_32BIT_FS * X86_GDT_ENTRY_SIZE), %ax
  

•   movw    %ax, %fs
  

•   /* Load the Interrupt descriptor table */
  

•   mov     idt_ptr, %ebx
  

•   lidt    (%ebx)
  

•   /* Obtain cpu number */
  

•   movl    ap_count, %eax
  

+1:

•   movl    %eax, %ecx
  

•   inc     %ecx
  

•   lock cmpxchg %ecx, ap_count
  

•   jnz     1b
  

•   /* Setup stacks for each CPU */
  

•   movl    stack_size, %eax
  

•   mul     %ecx
  

•   movl    stack_top, %edx
  

•   subl    %eax, %edx
  

•   mov     %edx, %esp
  

•   /* Save cpu number */
  

•   mov     %ecx, %esi
  

•   /* Determine if one should check microcode versions */
  

•   mov     microcode_ptr, %edi
  

•   test    %edi, %edi
  

•   jz      microcode_done /* Bypass if no microde exists */
  

•   /* Get the Microcode version */
  

•   mov     $1, %eax
  

•   cpuid
  

•   mov     $MSR_IA32_UCODE_REV, %ecx
  

•   rdmsr
  

•   /* If something already loaded skip loading again */
  

•   test    %edx, %edx
  

•   jnz     microcode_done
  

•   /* Determine if parallel microcode loading is allowed */
  

•   cmp     $0xffffffff, microcode_lock
  

•   je      load_microcode
  

•   /* Protect microcode loading */
  

+lock_microcode:

•   lock bts $0, microcode_lock
  

•   jc      lock_microcode
  

+load_microcode:

•   /* Load new microcode */
  

•   mov     $MSR_IA32_UCODE_WRITE, %ecx
  

•   xor     %edx, %edx
  

•   mov     %edi, %eax
  

•   /* The microcode pointer is passed in pointing to the header. Adjust
  

•    * pointer to reflect the payload (header size is 48 bytes) */
  

Please fix the multi-line comment style.

•   add     $48, %eax
  

48->UCODE_HEADER_LEN

•   pusha
  

•   wrmsr
  

•   popa
  

•   /* Unconditionally unlock microcode loading */
  

•   cmp     $0xffffffff, microcode_lock
  

•   je      microcode_done
  

•   xor     %eax, %eax
  

•   mov     %eax, microcode_lock
  

+microcode_done:

•   /*
  

•    * Load MSRs. Each entry in the table consists of:
  

•    * 0: index,
  

•    * 4: value[31:0]
  

•    * 8: value[63:32]
  

•    * See struct saved_msr in mp_init.c.
  

•    */
  

•   mov     msr_table_ptr, %edi
  

•   mov     msr_count, %ebx
  

•   test    %ebx, %ebx
  

•   jz      1f
  

+load_msr:

•   mov     (%edi), %ecx
  

•   mov     4(%edi), %eax
  

•   mov     8(%edi), %edx
  

•   wrmsr
  

•   add     $12, %edi
  

•   dec     %ebx
  

•   jnz     load_msr
  

+1:

•   /* Enable caching */
  

•   mov     %cr0, %eax
  

•   and     $0x9fffffff, %eax /* CD, NW = 0 */
  

Please use existing macros.

•   mov     %eax, %cr0
  

•   /* c_handler(cpu_num) */
  

•   push    %esi    /* cpu_num */
  

•   mov     c_handler, %eax
  

•   call    *%eax
  

•   .align  4
  

+.globl sipi_params +sipi_params: +idt_ptr:

•   .long 0
  

+stack_top:

•   .long 0
  

+stack_size:

•   .long 0
  

+microcode_lock:

•   .long 0
  

+microcode_ptr:

•   .long 0
  

+msr_table_ptr:

•   .long 0
  

+msr_count:

•   .long 0
  

+c_handler:

•   .long 0
  

+ap_count:

•   .long 0
  

diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h new file mode 100644 index 0000000..5dc0e33 --- /dev/null +++ b/arch/x86/include/asm/mp.h @@ -0,0 +1,94 @@ +/*

• • Copyright (c) 2015 Google, Inc
• • SPDX-License-Identifier: GPL-2.0
• • Taken from coreboot file of the same name
• */

+#ifndef _X86_MP_H_ +#define _X86_MP_H_

+#include <asm/atomic.h>

+typedef int (*mp_callback_t)(struct udevice *cpu, void *arg);

+/*

• • A mp_flight_record details a sequence of calls for the APs to perform
• • along with the BSP to coordinate sequencing. Each flight record either
• • provides a barrier for each AP before calling the callback or the APs
• • are allowed to perform the callback without waiting. Regardless, each
• • record has the cpus_entered field incremented for each record. When
• • the BSP observes that the cpus_entered matches the number of APs
• • the bsp_call is called with bsp_arg and upon returning releases the
• • barrier allowing the APs to make further progress.
• • Note that ap_call() and bsp_call() can be NULL. In the NULL case the
• • callback will just not be called.
• */

+struct mp_flight_record {

•   atomic_t barrier;
  

•   atomic_t cpus_entered;
  

•   mp_callback_t ap_call;
  

•   void *ap_arg;
  

•   mp_callback_t bsp_call;
  

•   void *bsp_arg;
  

+} __attribute__((aligned(ARCH_DMA_MINALIGN)));

+#define _MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \

Can we remove the underscore in those variables?

•   {                                                       \
  

•           .barrier = ATOMIC_INIT(barrier_),               \
  

•           .cpus_entered = ATOMIC_INIT(0),                 \
  

•           .ap_call = ap_func_,                            \
  

•           .ap_arg = ap_arg_,                              \
  

•           .bsp_call = bsp_func_,                          \
  

•           .bsp_arg = bsp_arg_,                            \
  

•   }
  

+#define MP_FR_BLOCK_APS(ap_func_, ap_arg_, bsp_func_, bsp_arg_) \

•   _MP_FLIGHT_RECORD(0, ap_func_, ap_arg_, bsp_func_, bsp_arg_)
  

underscore

+#define MP_FR_NOBLOCK_APS(ap_func_, ap_arg_, bsp_func_, bsp_arg_) \

•   _MP_FLIGHT_RECORD(1, ap_func_, ap_arg_, bsp_func_, bsp_arg_)
  

underscore

+/*

• • The mp_params structure provides the arguments to the mp subsystem
• • for bringing up APs.
• • At present this is overkill for U-Boot, but it may make it easier to add
• • SMM support.
• */

+struct mp_params {

•   int num_cpus; /* Total cpus include BSP */
  

•   int parallel_microcode_load;
  

•   const void *microcode_pointer;
  

•   /* Flight plan  for APs and BSP */
  

•   struct mp_flight_record *flight_plan;
  

•   int num_records;
  

+};

+/*

• • mp_init() will set up the SIPI vector and bring up the APs according to
• • mp_params. Each flight record will be executed according to the plan. Note
• • that the MP infrastructure uses SMM default area without saving it. It's
• • up to the chipset or mainboard to either e820 reserve this area or save this
• • region prior to calling mp_init() and restoring it after mp_init returns.
• • At the time mp_init() is called the MTRR MSRs are mirrored into APs then
• • caching is enabled before running the flight plan.
• • The MP init has the following properties:
• • 1. APs are brought up in parallel.
• • 2. The ordering of coreboot cpu number and APIC ids is not deterministic.

coreboot->U-Boot

• • Therefore, one cannot rely on this property or the order of devices in
• • the device tree unless the chipset or mainboard know the APIC ids
• • a priori.
• • mp_init() returns < 0 on error, 0 on success.
• */

+int mp_init(struct mp_params *params);

+/* Probes the CPU device */ +int mp_init_cpu(struct udevice *cpu, void *unused);

+#endif /* _X86_MP_H_ */ diff --git a/arch/x86/include/asm/sipi.h b/arch/x86/include/asm/sipi.h new file mode 100644 index 0000000..bb2f0de --- /dev/null +++ b/arch/x86/include/asm/sipi.h @@ -0,0 +1,79 @@ +/*

• • Copyright (c) 2015 Gooogle, Inc
• • Written by Simon Glass sjg@chromium.org
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef _ASM_SIPI_H +#define _ASM_SIPI_H

+/**

• • struct sipi_params_16bit - 16-bit SIPI entry-point parameters
• • These are set up in the same space as the SIPI 16-bit code so that each AP
• • can access the parameters when it boots.
• • Each of these must be set up for the AP to boot, except @segment which is
• • set in the assembly code.
• • @ap_start: 32-bit SIPI entry point for U-Boot
• • @segment: Code segment for U-Boot
• • @pad: Padding (not used)
• • @gdt_limit: U-Boot GDT limit (X86_GDT_SIZE - 1)
• • @gdt: U-Boot GDT (gd->arch.gdt)
• • @unused: Not used
• */

+struct __packed sipi_params_16bit {

•   u32 ap_start;
  

•   u16 segment;
  

•   u16 pad;
  

Please remove this blank line.

•   u16 gdt_limit;
  

•   u32 gdt;
  

•   u16 unused;
  

+};

+/**

• • struct sipi_params - 32-bit SIP entry-point parameters
• • These are used by the AP init code and must be set up before the APs start.
• • The stack area extends down from @stack_top, with @stack_size allocated
• • for each AP.
• • @idt_ptr: Interrupt descriptor table pointer
• • @stack_top: Top of the AP stack area
• • @stack_size: Size of each AP's stack
• • @microcode_lock: Used to ensure only one AP loads microcode at once

We should document: 0xffffffff means parallel loading

• • @microcode_ptr: Pointer to microcode, or 0 if none
• • @msr_table_ptr: Pointer to saved MSRs, a list of struct saved_msr
• • @msr_count: Number of saved MSRs
• • @c_handler: C function to call once early init is complete
• • @ap_count: Shared atomic value to allocate CPU indexes
• */

+struct sipi_params {

•   u32 idt_ptr;
  

•   u32 stack_top;
  

•   u32 stack_size;
  

•   u32 microcode_lock;
  

•   u32 microcode_ptr;
  

•   u32 msr_table_ptr;
  

•   u32 msr_count;
  

•   u32 c_handler;
  

•   atomic_t ap_count;
  

+};

+/* 16-bit AP entry point */ +void ap_start16(void);

+/* end of 16-bit code/data, marks the region to be copied to SIP vector */ +void ap_start16_code_end(void);

+/* 32-bit AP entry point */ +void ap_start(void);

+extern char sipi_params_16bit[]; +extern char sipi_params[];

+#endif diff --git a/arch/x86/include/asm/smm.h b/arch/x86/include/asm/smm.h new file mode 100644 index 0000000..79b4a8e --- /dev/null +++ b/arch/x86/include/asm/smm.h @@ -0,0 +1,14 @@ +/*

• • Copyright (c) 2015 Google, Inc
• • Copyright (C) 2008-2009 coresystems GmbH
• • SPDX-License-Identifier: GPL-2.0
• */

+#ifndef CPU_X86_SMM_H +#define CPU_X86_SMM_H

+#define SMM_DEFAULT_BASE 0x30000 +#define SMM_DEFAULT_SIZE 0x10000

Actually they are not related to SMM, but just for AP start-up codes entry. Should we rename them to AP_xxx and move them to sipi.h?

+#endif

Regards, Bin

Hi Simon,

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

Since we do these sorts of operations a lot, it is useful to have a simpler API, similar to clrsetbits_le32().

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2: None

arch/x86/include/asm/msr.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)

diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 1955a75..5349519 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -128,6 +128,25 @@ static inline void wrmsr(unsigned msr, unsigned low, unsigned high) #define wrmsrl(msr, val) \ native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))

+static inline void msr_clrsetbits_64(unsigned msr, u64 clear, u64 set) +{

•   u64 val;
  

•   val = native_read_msr(msr);
  

•   val &= ~clear;
  

•   val |= set;
  

•   wrmsrl(msr, val);
  

+}

+static inline void msr_setbits_64(unsigned msr, u64 set) +{

•   u64 val;
  

•   val = native_read_msr(msr);
  

•   val |= set;
  

•   wrmsrl(msr, val);
  

+}

/* rdmsr with exception handling */ #define rdmsr_safe(msr, p1, p2) \ ({ \ --

For completeness, should we add msr_clrbits_64() as well?

Regards, Bin

Hi Simon,

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

This permits init of additional CPU cores after relocation and when driver model is ready.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2: None

arch/x86/cpu/cpu.c | 37 +++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/cpu.h | 14 ++++++++++++++ arch/x86/include/asm/u-boot-x86.h | 2 ++ common/board_r.c | 2 +- 4 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 78eb3fe..6263511 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -21,6 +21,8 @@

#include <common.h> #include <command.h> +#include <cpu.h> +#include <dm.h> #include <errno.h> #include <malloc.h> #include <asm/control_regs.h> @@ -518,6 +520,15 @@ char *cpu_get_name(char *name) return ptr; }

+int x86_cpu_get_desc(struct udevice *dev, char *buf, int size) +{

•   if (size < CPU_MAX_NAME_LEN)
  

•           return -ENOSPC;
  

Please add a blank line here.

•   cpu_get_name(buf);
  

•   return 0;
  

+}

int default_print_cpuinfo(void) { printf("CPU: %s, vendor %s, device %xh\n", @@ -600,3 +611,29 @@ int last_stage_init(void) return 0; } #endif

+__weak int x86_init_cpus(void) +{

•   return 0;
  

+}

+int cpu_init_r(void) +{

•   return x86_init_cpus();
  

+}

+static const struct cpu_ops cpu_x86_ops = {

•   .get_desc       = x86_cpu_get_desc,
  

+};

+static const struct udevice_id cpu_x86_ids[] = {

•   { .compatible = "cpu-x86" },
  

•   { }
  

+};

+U_BOOT_DRIVER(cpu_x86_drv) = {

•   .name           = "cpu_x86",
  

•   .id             = UCLASS_CPU,
  

•   .of_match       = cpu_x86_ids,
  

•   .ops            = &cpu_x86_ops,
  

+}; diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 08284ee..01bee52 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -197,6 +197,20 @@ const char *cpu_vendor_name(int vendor); char *cpu_get_name(char *name);

/**

+* x86_cpu_get_desc() - Get a description string for an x86 CPU +* +* This uses cpu_get_name() and is suitable to use as the get_desc() method for +* the I2C uclass.

I2C uclass?

+* +* @dev: Device to check (UCLASS_CPU) +* @buf: Buffer to place string +* @size: Size of string space +* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error +*/ +int x86_cpu_get_desc(struct udevice *dev, char *buf, int size);

+/**

• cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
• The kernel is uncompressed and the 64-bit entry point is expected to be

diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 122e054..be103c0 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -69,6 +69,8 @@ uint64_t timer_get_tsc(void);

void quick_ram_check(void);

+int x86_init_cpus(void);

#define PCI_VGA_RAM_IMAGE_START 0xc0000

#endif /* _U_BOOT_I386_H_ */ diff --git a/common/board_r.c b/common/board_r.c index 307124e..1a46f62 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -779,7 +779,7 @@ init_fnc_t init_sequence_r[] = { initr_flash, #endif INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86) /* initialize higher level parts of CPU like time base and timers */ cpu_init_r,

I see there is a cpu_secondary_init_r() in board_r.c. Looks that it is intended for multicore initialization. Should we use that instead?

#endif

Regards, Bin

Hi Simon,

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

This driver supports multi-core init and sets up the CPU frequencies correctly.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2: None

arch/x86/cpu/baytrail/Makefile | 1 + arch/x86/cpu/baytrail/cpu.c | 206 +++++++++++++++++++++++++++++++ arch/x86/include/asm/arch-baytrail/msr.h | 30 +++++ 3 files changed, 237 insertions(+) create mode 100644 arch/x86/cpu/baytrail/cpu.c create mode 100644 arch/x86/include/asm/arch-baytrail/msr.h

diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile index 8914e8b..c78b644 100644 --- a/arch/x86/cpu/baytrail/Makefile +++ b/arch/x86/cpu/baytrail/Makefile @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ #

+obj-y += cpu.o obj-y += early_uart.o obj-y += fsp_configs.o obj-y += pci.o diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c new file mode 100644 index 0000000..5a2a8ee --- /dev/null +++ b/arch/x86/cpu/baytrail/cpu.c @@ -0,0 +1,206 @@ +/*

• • Copyright (C) 2015 Google, Inc
• • SPDX-License-Identifier: GPL-2.0+
• • Based on code from coreboot
• */

+#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <asm/cpu.h> +#include <asm/lapic.h> +#include <asm/mp.h> +#include <asm/msr.h> +#include <asm/turbo.h> +#include <asm/arch/msr.h>

+#ifdef CONFIG_SMP +static int enable_smis(struct udevice *cpu, void *unused) +{

•   return 0;
  

+}

What is this function for? Is this a must-have?

+static struct mp_flight_record mp_steps[] = {

•   MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
  

•   /* Wait for APs to finish initialization before proceeding. */
  

•   MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
  

+};

+static int detect_num_cpus(void) +{

•   int ecx = 0;
  

•   /*
  

•    * Use the algorithm described in Intel 64 and IA-32 Architectures
  

•    * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
  

•    * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
  

•    * of CPUID Extended Topology Leaf.
  

•    */
  

•   while (1) {
  

•           struct cpuid_result leaf_b;
  

•           leaf_b = cpuid_ext(0xb, ecx);
  

•           /*
  

•            * Bay Trail doesn't have hyperthreading so just determine the
  

•            * number of cores by from level type (ecx[15:8] == * 2)
  

•            */
  

•           if ((leaf_b.ecx & 0xff00) == 0x0200)
  

•                   return leaf_b.ebx & 0xffff;
  

•           ecx++;
  

•   }
  

+}

Since we already describe all cpus in the device tree, is this dynamic probe really needed?

+static int baytrail_init_cpus(void) +{

•   struct mp_params mp_params;
  

•   lapic_setup();
  

•   mp_params.num_cpus = detect_num_cpus();
  

•   mp_params.parallel_microcode_load = 0,
  

•   mp_params.flight_plan = &mp_steps[0];
  

•   mp_params.num_records = ARRAY_SIZE(mp_steps);
  

•   mp_params.microcode_pointer = 0;
  

•   if (mp_init(&mp_params)) {
  

•           printf("Warning: MP init failure\n");
  

•           return -EIO;
  

•   }
  

•   return 0;
  

+} +#endif

+int x86_init_cpus(void) +{ +#ifdef CONFIG_SMP

•   debug("Init additional CPUs\n");
  

•   baytrail_init_cpus();
  

+#endif

•   return 0;
  

+}

+void set_max_freq(void)

Should this be static?

+{

•   msr_t perf_ctl;
  

•   msr_t msr;
  

•   /* Enable speed step */
  

•   msr = msr_read(MSR_IA32_MISC_ENABLES);
  

•   msr.lo |= (1 << 16);
  

•   msr_write(MSR_IA32_MISC_ENABLES, msr);
  

•   /*
  

•    * Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
  

•    * the PERF_CTL
  

•    */
  

•   msr = msr_read(MSR_IACORE_RATIOS);
  

•   perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
  

•   /*
  

•    * Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
  

•    * the PERF_CTL
  

•    */
  

•   msr = msr_read(MSR_IACORE_VIDS);
  

•   perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
  

•   perf_ctl.hi = 0;
  

•   msr_write(MSR_IA32_PERF_CTL, perf_ctl);
  

+}

+static int cpu_x86_baytrail_probe(struct udevice *dev) +{

•   debug("Init baytrail core\n");
  

BayTrail?

•   /*
  

•    * On bay trail the turbo disable bit is actually scoped at the
  

BayTrail?

•    * building-block level, not package. For non-BSP cores that are
  

•    * within a building block, enable turbo. The cores within the BSP's
  

•    * building block will just see it already enabled and move on.
  

•    */
  

•   if (lapicid())
  

•           turbo_enable();
  

•   /* Dynamic L2 shrink enable and threshold */
  

•   msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f000f, 0xe0008),
  

•   /* Disable C1E */
  

•   msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
  

•   msr_setbits_64(MSR_POWER_MISC, 0x44);
  

•   /* Set this core to max frequency ratio */
  

•   set_max_freq();
  

•   return 0;
  

+}

+static unsigned bus_freq(void) +{

•   msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
  

•   switch (clk_info.lo & 0x3) {
  

•   case 0:
  

•           return 83333333;
  

•   case 1:
  

•           return 100000000;
  

•   case 2:
  

•           return 133333333;
  

•   case 3:
  

•           return 116666666;
  

•   default:
  

•           return 0;
  

•   }
  

+}

+static unsigned long tsc_freq(void) +{

•   msr_t platform_info;
  

•   ulong bclk = bus_freq();
  

•   if (!bclk)
  

•           return 0;
  

•   platform_info = msr_read(MSR_PLATFORM_INFO);
  

•   return bclk * ((platform_info.lo >> 8) & 0xff);
  

+}

+static int baytrail_get_info(struct udevice *dev, struct cpu_info *info) +{

•   info->cpu_freq = tsc_freq();
  

•   info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
  

•   return 0;
  

+}

+static int cpu_x86_baytrail_bind(struct udevice *dev) +{

•   struct cpu_platdata *plat = dev_get_parent_platdata(dev);
  

•   plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
  

•                                 "intel,apic-id", -1);
  

•   return 0;
  

+}

+static const struct cpu_ops cpu_x86_baytrail_ops = {

•   .get_desc       = x86_cpu_get_desc,
  

•   .get_info       = baytrail_get_info,
  

+};

+static const struct udevice_id cpu_x86_baytrail_ids[] = {

•   { .compatible = "intel,baytrail-cpu" },
  

•   { }
  

+};

+U_BOOT_DRIVER(cpu_x86_baytrail_drv) = {

•   .name           = "cpu_x86_baytrail",
  

•   .id             = UCLASS_CPU,
  

•   .of_match       = cpu_x86_baytrail_ids,
  

•   .bind           = cpu_x86_baytrail_bind,
  

•   .probe          = cpu_x86_baytrail_probe,
  

•   .ops            = &cpu_x86_baytrail_ops,
  

+}; diff --git a/arch/x86/include/asm/arch-baytrail/msr.h b/arch/x86/include/asm/arch-baytrail/msr.h new file mode 100644 index 0000000..1975aec --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/msr.h @@ -0,0 +1,30 @@ +/*

• • Copyright (C) 2015 Google, Inc
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __asm_arch_msr_h +#define __asm_arch_msr_h

Should be capital letters, or (see below)

+#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define SINGLE_PCTL (1 << 11) +#define MSR_POWER_MISC 0x120 +#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) +#define ENABLE_INDP_AUTOCM_MASK (1 << 3) +#define MSR_IA32_MISC_ENABLES 0x1a0 +#define MSR_POWER_CTL 0x1fc +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_IACORE_RATIOS 0x66a +#define MSR_IACORE_TURBO_RATIOS 0x66c +#define MSR_IACORE_VIDS 0x66b +#define MSR_IACORE_TURBO_VIDS 0x66d +#define MSR_PKG_TURBO_CFG1 0x670 +#define MSR_CPU_TURBO_WKLD_CFG1 0x671 +#define MSR_CPU_TURBO_WKLD_CFG2 0x672 +#define MSR_CPU_THERM_CFG1 0x673 +#define MSR_CPU_THERM_CFG2 0x674 +#define MSR_CPU_THERM_SENS_CFG 0x675

Should these be all put into arch/x86/include/asm/msr-index.h, a single place for all x86 processors' MSR?

+#endif

Regards, Bin

Hi Simon,

On Wed, Apr 29, 2015 at 10:00 PM, Simon Glass sjg@chromium.org wrote:

Hi Bin,

On 29 April 2015 at 07:57, Bin Meng bmeng.cn@gmail.com wrote:

...

Hi Simon,

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

...

This driver supports multi-core init and sets up the CPU frequencies correctly.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2: None

arch/x86/cpu/baytrail/Makefile | 1 + arch/x86/cpu/baytrail/cpu.c | 206 +++++++++++++++++++++++++++++++ arch/x86/include/asm/arch-baytrail/msr.h | 30 +++++ 3 files changed, 237 insertions(+) create mode 100644 arch/x86/cpu/baytrail/cpu.c create mode 100644 arch/x86/include/asm/arch-baytrail/msr.h

diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile index 8914e8b..c78b644 100644 --- a/arch/x86/cpu/baytrail/Makefile +++ b/arch/x86/cpu/baytrail/Makefile @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ #

+obj-y += cpu.o obj-y += early_uart.o obj-y += fsp_configs.o obj-y += pci.o diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c new file mode 100644 index 0000000..5a2a8ee --- /dev/null +++ b/arch/x86/cpu/baytrail/cpu.c @@ -0,0 +1,206 @@ +/*

• • Copyright (C) 2015 Google, Inc
• • SPDX-License-Identifier: GPL-2.0+
• • Based on code from coreboot
• */

+#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <asm/cpu.h> +#include <asm/lapic.h> +#include <asm/mp.h> +#include <asm/msr.h> +#include <asm/turbo.h> +#include <asm/arch/msr.h>

+#ifdef CONFIG_SMP +static int enable_smis(struct udevice *cpu, void *unused) +{

•   return 0;
  

+}

What is this function for? Is this a must-have?

It's partly a placeholder, and also is intended to ensure that the APs are all started before the main CPU continues execution.

...

...

+static struct mp_flight_record mp_steps[] = {

•   MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
  

•   /* Wait for APs to finish initialization before proceeding. */
  

•   MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
  

+};

+static int detect_num_cpus(void) +{

•   int ecx = 0;
  

•   /*
  

•    * Use the algorithm described in Intel 64 and IA-32 Architectures
  

•    * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
  

•    * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
  

•    * of CPUID Extended Topology Leaf.
  

•    */
  

•   while (1) {
  

•           struct cpuid_result leaf_b;
  

•           leaf_b = cpuid_ext(0xb, ecx);
  

•           /*
  

•            * Bay Trail doesn't have hyperthreading so just determine the
  

•            * number of cores by from level type (ecx[15:8] == * 2)
  

•            */
  

•           if ((leaf_b.ecx & 0xff00) == 0x0200)
  

•                   return leaf_b.ebx & 0xffff;
  

•           ecx++;
  

•   }
  

+}

Since we already describe all cpus in the device tree, is this dynamic probe really needed?

With MinnowMax I'd like to support the single-core version of the board also. It could have its own device tree, but I don't want to break in this case. However, this case is not tested.

Do you mean that there is a specific version of MinnowMax board which contains an single core version of Atom E3800 (?, maybe another brand name)? But as you said, we can create another device tree for the single core version. No? Or maybe we fix up the DTB node here dynamically, that we still only have one device tree to describe the dual-core version, but after this dynamic probe, we fix up the DTB to remove one cpu node if we get a single core version?

...

...

+static int baytrail_init_cpus(void) +{

•   struct mp_params mp_params;
  

•   lapic_setup();
  

•   mp_params.num_cpus = detect_num_cpus();
  

•   mp_params.parallel_microcode_load = 0,
  

•   mp_params.flight_plan = &mp_steps[0];
  

•   mp_params.num_records = ARRAY_SIZE(mp_steps);
  

•   mp_params.microcode_pointer = 0;
  

•   if (mp_init(&mp_params)) {
  

•           printf("Warning: MP init failure\n");
  

•           return -EIO;
  

•   }
  

•   return 0;
  

+} +#endif

+int x86_init_cpus(void) +{ +#ifdef CONFIG_SMP

•   debug("Init additional CPUs\n");
  

•   baytrail_init_cpus();
  

+#endif

•   return 0;
  

+}

+void set_max_freq(void)

Should this be static?

Yes

...

...

+{

•   msr_t perf_ctl;
  

•   msr_t msr;
  

•   /* Enable speed step */
  

•   msr = msr_read(MSR_IA32_MISC_ENABLES);
  

•   msr.lo |= (1 << 16);
  

•   msr_write(MSR_IA32_MISC_ENABLES, msr);
  

•   /*
  

•    * Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
  

•    * the PERF_CTL
  

•    */
  

•   msr = msr_read(MSR_IACORE_RATIOS);
  

•   perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
  

•   /*
  

•    * Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
  

•    * the PERF_CTL
  

•    */
  

•   msr = msr_read(MSR_IACORE_VIDS);
  

•   perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
  

•   perf_ctl.hi = 0;
  

•   msr_write(MSR_IA32_PERF_CTL, perf_ctl);
  

+}

+static int cpu_x86_baytrail_probe(struct udevice *dev) +{

•   debug("Init baytrail core\n");
  

BayTrail?

OK

...

...

•   /*
  

•    * On bay trail the turbo disable bit is actually scoped at the
  

BayTrail?

...

•    * building-block level, not package. For non-BSP cores that are
  

•    * within a building block, enable turbo. The cores within the BSP's
  

•    * building block will just see it already enabled and move on.
  

•    */
  

•   if (lapicid())
  

•           turbo_enable();
  

•   /* Dynamic L2 shrink enable and threshold */
  

•   msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f000f, 0xe0008),
  

•   /* Disable C1E */
  

•   msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
  

•   msr_setbits_64(MSR_POWER_MISC, 0x44);
  

•   /* Set this core to max frequency ratio */
  

•   set_max_freq();
  

•   return 0;
  

+}

+static unsigned bus_freq(void) +{

•   msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
  

•   switch (clk_info.lo & 0x3) {
  

•   case 0:
  

•           return 83333333;
  

•   case 1:
  

•           return 100000000;
  

•   case 2:
  

•           return 133333333;
  

•   case 3:
  

•           return 116666666;
  

•   default:
  

•           return 0;
  

•   }
  

+}

+static unsigned long tsc_freq(void) +{

•   msr_t platform_info;
  

•   ulong bclk = bus_freq();
  

•   if (!bclk)
  

•           return 0;
  

•   platform_info = msr_read(MSR_PLATFORM_INFO);
  

•   return bclk * ((platform_info.lo >> 8) & 0xff);
  

+}

+static int baytrail_get_info(struct udevice *dev, struct cpu_info *info) +{

•   info->cpu_freq = tsc_freq();
  

•   info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
  

•   return 0;
  

+}

+static int cpu_x86_baytrail_bind(struct udevice *dev) +{

•   struct cpu_platdata *plat = dev_get_parent_platdata(dev);
  

•   plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
  

•                                 "intel,apic-id", -1);
  

•   return 0;
  

+}

+static const struct cpu_ops cpu_x86_baytrail_ops = {

•   .get_desc       = x86_cpu_get_desc,
  

•   .get_info       = baytrail_get_info,
  

+};

+static const struct udevice_id cpu_x86_baytrail_ids[] = {

•   { .compatible = "intel,baytrail-cpu" },
  

•   { }
  

+};

+U_BOOT_DRIVER(cpu_x86_baytrail_drv) = {

•   .name           = "cpu_x86_baytrail",
  

•   .id             = UCLASS_CPU,
  

•   .of_match       = cpu_x86_baytrail_ids,
  

•   .bind           = cpu_x86_baytrail_bind,
  

•   .probe          = cpu_x86_baytrail_probe,
  

•   .ops            = &cpu_x86_baytrail_ops,
  

+}; diff --git a/arch/x86/include/asm/arch-baytrail/msr.h b/arch/x86/include/asm/arch-baytrail/msr.h new file mode 100644 index 0000000..1975aec --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/msr.h @@ -0,0 +1,30 @@ +/*

• • Copyright (C) 2015 Google, Inc
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __asm_arch_msr_h +#define __asm_arch_msr_h

Should be capital letters, or (see below)

...

+#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define SINGLE_PCTL (1 << 11) +#define MSR_POWER_MISC 0x120 +#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) +#define ENABLE_INDP_AUTOCM_MASK (1 << 3) +#define MSR_IA32_MISC_ENABLES 0x1a0 +#define MSR_POWER_CTL 0x1fc +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_IACORE_RATIOS 0x66a +#define MSR_IACORE_TURBO_RATIOS 0x66c +#define MSR_IACORE_VIDS 0x66b +#define MSR_IACORE_TURBO_VIDS 0x66d +#define MSR_PKG_TURBO_CFG1 0x670 +#define MSR_CPU_TURBO_WKLD_CFG1 0x671 +#define MSR_CPU_TURBO_WKLD_CFG2 0x672 +#define MSR_CPU_THERM_CFG1 0x673 +#define MSR_CPU_THERM_CFG2 0x674 +#define MSR_CPU_THERM_SENS_CFG 0x675

Should these be all put into arch/x86/include/asm/msr-index.h, a single place for all x86 processors' MSR?

I was worried that they might be specific to this CPU. But if they are common then yes they should go in the common file.

Maybe some of them are BayTrail-specific. But there MSRs are documented in the Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3, right? If yes, I think it's fine to put them at just one place.

Regards, Bin

Hi Simon,

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

This driver supports multi-core init and sets up the CPU frequencies correctly.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2: None

arch/x86/cpu/baytrail/Makefile | 1 + arch/x86/cpu/baytrail/cpu.c | 206 +++++++++++++++++++++++++++++++ arch/x86/include/asm/arch-baytrail/msr.h | 30 +++++ 3 files changed, 237 insertions(+) create mode 100644 arch/x86/cpu/baytrail/cpu.c create mode 100644 arch/x86/include/asm/arch-baytrail/msr.h

diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile index 8914e8b..c78b644 100644 --- a/arch/x86/cpu/baytrail/Makefile +++ b/arch/x86/cpu/baytrail/Makefile @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ #

+obj-y += cpu.o obj-y += early_uart.o obj-y += fsp_configs.o obj-y += pci.o diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c new file mode 100644 index 0000000..5a2a8ee --- /dev/null +++ b/arch/x86/cpu/baytrail/cpu.c @@ -0,0 +1,206 @@ +/*

• • Copyright (C) 2015 Google, Inc
• • SPDX-License-Identifier: GPL-2.0+
• • Based on code from coreboot
• */

+#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <asm/cpu.h> +#include <asm/lapic.h> +#include <asm/mp.h> +#include <asm/msr.h> +#include <asm/turbo.h> +#include <asm/arch/msr.h>

+#ifdef CONFIG_SMP +static int enable_smis(struct udevice *cpu, void *unused) +{

•   return 0;
  

+}

+static struct mp_flight_record mp_steps[] = {

•   MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
  

•   /* Wait for APs to finish initialization before proceeding. */
  

•   MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
  

+};

+static int detect_num_cpus(void) +{

•   int ecx = 0;
  

•   /*
  

•    * Use the algorithm described in Intel 64 and IA-32 Architectures
  

•    * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
  

•    * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
  

•    * of CPUID Extended Topology Leaf.
  

•    */
  

•   while (1) {
  

•           struct cpuid_result leaf_b;
  

•           leaf_b = cpuid_ext(0xb, ecx);
  

•           /*
  

•            * Bay Trail doesn't have hyperthreading so just determine the
  

•            * number of cores by from level type (ecx[15:8] == * 2)
  

•            */
  

•           if ((leaf_b.ecx & 0xff00) == 0x0200)
  

•                   return leaf_b.ebx & 0xffff;
  

•           ecx++;
  

•   }
  

+}

+static int baytrail_init_cpus(void) +{

•   struct mp_params mp_params;
  

•   lapic_setup();
  

One more comment, I believe this lapic_setup() call can be moved into mp_init(), thoughts?

•   mp_params.num_cpus = detect_num_cpus();
  

•   mp_params.parallel_microcode_load = 0,
  

•   mp_params.flight_plan = &mp_steps[0];
  

•   mp_params.num_records = ARRAY_SIZE(mp_steps);
  

•   mp_params.microcode_pointer = 0;
  

•   if (mp_init(&mp_params)) {
  

•           printf("Warning: MP init failure\n");
  

•           return -EIO;
  

•   }
  

•   return 0;
  

+} +#endif

[snip]

Regards, Bin

Hi Simon,

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

We don't need to support really old x86 CPUs, so drop this code.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2: None

arch/x86/cpu/lapic.c | 20 ++++++++++++-------- arch/x86/include/asm/lapic.h | 7 ------- 2 files changed, 12 insertions(+), 15 deletions(-)

diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c index 4690603..0c9c324 100644 --- a/arch/x86/cpu/lapic.c +++ b/arch/x86/cpu/lapic.c @@ -15,7 +15,6 @@

void lapic_setup(void) { -#if NEED_LAPIC == 1 /* Only Pentium Pro and later have those MSR stuff */ debug("Setting up local apic: ");

@@ -46,12 +45,17 @@ void lapic_setup(void) (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | LAPIC_DELIVERY_MODE_NMI));

•   debug("apic_id: 0x%02lx, ", lapicid());
  

-#else /* !NEED_LLAPIC */

•   /* Only Pentium Pro and later have those MSR stuff */
  

•   debug("Disabling local apic: ");
  

•   disable_lapic();
  

-#endif /* !NEED_LAPIC */

•   debug("done.\n");
  

•   debug("apic_id: 0x%02lx\n", lapicid());
    post_code(POST_LAPIC);
  

}

+void lapic_enable(void) +{

•   msr_t msr;
  

•   msr = msr_read(LAPIC_BASE_MSR);
  

•   msr.hi &= 0xffffff00;
  

•   msr.lo &= 0x000007ff;
  

•   msr.lo |= LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE;
  

•   msr_write(LAPIC_BASE_MSR, msr);
  

+}

This is duplicated. There is already a enable_lapic() in lapic.h which has the same codes.

diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h index 0a7f443..dff75c5 100644 --- a/arch/x86/include/asm/lapic.h +++ b/arch/x86/include/asm/lapic.h @@ -14,13 +14,6 @@ #include <asm/msr.h> #include <asm/processor.h>

-/* See if I need to initialize the local apic */ -#if CONFIG_SMP || CONFIG_IOAPIC -# define NEED_LAPIC 1 -#else -# define NEED_LAPIC 0 -#endif

static inline __attribute__((always_inline)) unsigned long lapic_read(unsigned long reg) { --

Regards, Bin

On Wed, Apr 29, 2015 at 10:25 AM, Simon Glass sjg@chromium.org wrote:

Enable the CPU uclass and Simple Firmware interface for Minnowbaord MAX. This enables multi-core support in Linux.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2: None

arch/x86/dts/minnowmax.dts | 20 ++++++++++++++++++++ configs/minnowmax_defconfig | 4 ++++ 2 files changed, 24 insertions(+)

diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 0233f61..7103bc5 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -68,6 +68,26 @@ stdout-path = "/serial"; };

•   cpus {
  

•           #address-cells = <1>;
  

•           #size-cells = <0>;
  

•           cpu@0 {
  

•                   device_type = "cpu";
  

•                   compatible = "intel,baytrail-cpu";
  

•                   reg = <0>;
  

•                   intel,apic-id = <0>;
  

•           };
  

•           cpu@1 {
  

•                   device_type = "cpu";
  

•                   compatible = "intel,baytrail-cpu";
  

•                   reg = <1>;
  

•                   intel,apic-id = <4>;
  

•           };
  

•   };
  

•   spi {
            #address-cells = <1>;
            #size-cells = <0>;
  

diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index c59f4ac..426fb52 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -8,3 +8,7 @@ CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 CONFIG_HAVE_INTEL_ME=y +CONFIG_GENERATE_SFI_TABLE=y +CONFIG_CPU=y +CONFIG_CMD_CPU=y

+CONFIG_SMP=y

Reviewed-by: Bin Meng bmeng.cn@gmail.com