[U-Boot] [PATCH] powerpc/t1040qds: Add DDR Raw Timing support
T1040QDS-D3 has dual-rank DDR: Micron, MT18KSF51272AZ-1G6 (4GB, x72, CL=10). Add Raw Timing structure for this DDR.
Typically SPD method is used for getting DDR parameter and calculating values for various DDR controller registers.
But somentimes it may happen that SPD present on DDR may get accidently erased or is not working properly during initial bring-up. In that circumnstance, DDR raw timing structure can be use as fallback option for getting DDR parameters.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com --- Based on u-boot-mpc85xx/next branch. board/freescale/t1040qds/ddr.c | 15 +++++++++++++++ board/freescale/t1040qds/ddr.h | 29 +++++++++++++++++++++++++++++ include/configs/T1040QDS.h | 1 + 3 files changed, 45 insertions(+), 0 deletions(-)
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 4fd17da..16ab829 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -15,6 +15,21 @@
DECLARE_GLOBAL_DATA_PTR;
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "RAW timing DDR"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index 8ee206e..4a4f76a 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -6,6 +6,35 @@
#ifndef __DDR_H__ #define __DDR_H__ +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 2147483648u, + .capacity = 4294967296u, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 2, /* ECC */ + .burst_lengths_bitmask = 0x0c, + .tckmin_x_ps = 1071, + .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 6000, + .trp_ps = 13125, + .tras_ps = 34000, + .trc_ps = 48125, + .trfc_ps = 260000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 35000, +}; + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 2738242..a8b32fe 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -168,6 +168,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD +#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE
On 10/25/2013 02:49 AM, Priyanka Jain wrote:
T1040QDS-D3 has dual-rank DDR: Micron, MT18KSF51272AZ-1G6 (4GB, x72, CL=10). Add Raw Timing structure for this DDR.
Typically SPD method is used for getting DDR parameter and calculating values for various DDR controller registers.
But somentimes it may happen that SPD present on DDR may get accidently erased or is not working properly during initial bring-up. In that circumnstance, DDR raw timing structure can be use as fallback option for getting DDR parameters.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com
I don't think it is appropriate to use raw timing for this application. This board use DIMMs, not soldered DDR chips. In normal cases, this piece of code is not used. It is only useful if you have a DIMM without a valid SPD. You could get another DIMM. I am not saying this patch is wrong, it is just useless for general public.
York
-----Original Message----- From: sun york-R58495 Sent: Wednesday, October 30, 2013 10:14 PM To: Jain Priyanka-B32167; u-boot@lists.denx.de Cc: Aggrwal Poonam-B10812 Subject: Re: [PATCH] powerpc/t1040qds: Add DDR Raw Timing support
On 10/25/2013 02:49 AM, Priyanka Jain wrote:
T1040QDS-D3 has dual-rank DDR: Micron, MT18KSF51272AZ-1G6 (4GB, x72, CL=10). Add Raw Timing structure for this DDR.
Typically SPD method is used for getting DDR parameter and calculating values for various DDR controller registers.
But somentimes it may happen that SPD present on DDR may get accidently erased or is not working properly during initial bring-up. In that circumnstance, DDR raw timing structure can be use as fallback option for getting DDR parameters.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com
I don't think it is appropriate to use raw timing for this application. This board use DIMMs, not soldered DDR chips. In normal cases, this piece of code is not used. It is only useful if you have a DIMM without a valid SPD. You could get another DIMM. I am not saying this patch is wrong, it is just useless for general public.
York
[Jain Priyanka-B32167] You are right that in case of DIMM type of memories, raw timing may not be required. But there are certain scenarios in which keeping raw timing is useful like 1)During initial bring-up, there is a possibility that I2C bus may be broken, In that case boot-loader has to rely on the fallback option of raw timing. 2)Also raw timings are used in emulator to test t1040. So, we prefer to keep raw timing as fallback option.
Regards Priyanka
On Oct 30, 2013, at 9:55 PM, Jain Priyanka-B32167 wrote:
-----Original Message----- From: sun york-R58495 Sent: Wednesday, October 30, 2013 10:14 PM To: Jain Priyanka-B32167; u-boot@lists.denx.de Cc: Aggrwal Poonam-B10812 Subject: Re: [PATCH] powerpc/t1040qds: Add DDR Raw Timing support
On 10/25/2013 02:49 AM, Priyanka Jain wrote:
T1040QDS-D3 has dual-rank DDR: Micron, MT18KSF51272AZ-1G6 (4GB, x72, CL=10). Add Raw Timing structure for this DDR.
Typically SPD method is used for getting DDR parameter and calculating values for various DDR controller registers.
But somentimes it may happen that SPD present on DDR may get accidently erased or is not working properly during initial bring-up. In that circumnstance, DDR raw timing structure can be use as fallback option for getting DDR parameters.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com
I don't think it is appropriate to use raw timing for this application. This board use DIMMs, not soldered DDR chips. In normal cases, this piece of code is not used. It is only useful if you have a DIMM without a valid SPD. You could get another DIMM. I am not saying this patch is wrong, it is just useless for general public.
York
[Jain Priyanka-B32167] You are right that in case of DIMM type of memories, raw timing may not be required. But there are certain scenarios in which keeping raw timing is useful like 1)During initial bring-up, there is a possibility that I2C bus may be broken, In that case boot-loader has to rely on the fallback option of raw timing. 2)Also raw timings are used in emulator to test t1040. So, we prefer to keep raw timing as fallback option.
It is a debug technique, not an implementation. You can use fixed register setting as well for debugging. But it doesn't mean you have to keep it in the final code. After you cleaning up the code, all "fixed" code should be removed, including the raw timing parameters you are using. Emulator target also has I2C EEPROM modeled. You should use SPD as well.
York
Ok, I will drop this patch and maintain it locally.
Regards Priyanka
-----Original Message----- From: sun york-R58495 Sent: Thursday, October 31, 2013 10:50 AM To: Jain Priyanka-B32167 Cc: sun york-R58495; u-boot@lists.denx.de; Aggrwal Poonam-B10812 Subject: Re: [PATCH] powerpc/t1040qds: Add DDR Raw Timing support
On Oct 30, 2013, at 9:55 PM, Jain Priyanka-B32167 wrote:
-----Original Message----- From: sun york-R58495 Sent: Wednesday, October 30, 2013 10:14 PM To: Jain Priyanka-B32167; u-boot@lists.denx.de Cc: Aggrwal Poonam-B10812 Subject: Re: [PATCH] powerpc/t1040qds: Add DDR Raw Timing support
On 10/25/2013 02:49 AM, Priyanka Jain wrote:
T1040QDS-D3 has dual-rank DDR: Micron, MT18KSF51272AZ-1G6 (4GB, x72, CL=10). Add Raw Timing structure for this DDR.
Typically SPD method is used for getting DDR parameter and calculating values for various DDR controller registers.
But somentimes it may happen that SPD present on DDR may get accidently erased or is not working properly during initial bring-up. In that circumnstance, DDR raw timing structure can be use as fallback option for getting DDR parameters.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com
I don't think it is appropriate to use raw timing for this
application.
This board use DIMMs, not soldered DDR chips. In normal cases, this piece of code is not used. It is only useful if you have a DIMM without a valid SPD. You could get another DIMM. I am not saying this patch is wrong, it is just useless for general public.
York
[Jain Priyanka-B32167] You are right that in case of DIMM type of
memories, raw timing may not be required.
But there are certain scenarios in which keeping raw timing is useful like 1)During initial bring-up, there is a possibility that I2C bus may be broken, In that case boot-loader has to rely on the fallback
option of raw timing.
2)Also raw timings are used in emulator to test t1040. So, we prefer to keep raw timing as fallback option.
It is a debug technique, not an implementation. You can use fixed register setting as well for debugging. But it doesn't mean you have to keep it in the final code. After you cleaning up the code, all "fixed" code should be removed, including the raw timing parameters you are using. Emulator target also has I2C EEPROM modeled. You should use SPD as well.
York
participants (4)
-
Jain Priyanka-B32167 -
Priyanka Jain -
sun york-R58495 -
York Sun