[U-Boot] u-boot-x86 sf probe fail
Hi,
I use Coreboot with u-boot-x86 as payload to bring-up my Intel Atom C2000 platform, but I cannot make my SPI flash(w25q128fv) to work. Actually the SPI was detected under coreboot with correct ID, but in u-boot “sf probe” command, it just always failed. After tracing and code dump, I found it was failed due to SPIS_FCERR in spi/ich.c spi_xfer function. I totally have no idea why this happened and how to proceed my bring-up. My u-boot-x86 is up-to-date version and the SPI use intel,ich9-spi compatible in my dts file.
Following is my dm tree and there is spi-flash device
=> dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver serial [ + ] |-- serial keyboard [ + ] |-- keyboard rtc [ ] |-- rtc timer [ + ] |-- tsc-timer pci [ + ] `-- pci pch [ + ] |-- pch@1f,0 irq [ + ] | |-- irq-router spi [ ] | `-- spi spi_flash [ ] | `-- spi-flash@0 pci_generic [ ] |-- pci_0:0.0 pci [ + ] |-- pci_0:1.0 pci_generic [ ] | `-- pci_1:0.0 pci [ + ] |-- pci_0:3.0 pci_generic [ ] |-- pci_0:e.0 pci_generic [ ] |-- pci_0:f.0 pci_generic [ ] |-- pci_0:13.0 usb [ ] |-- ehci_pci pci_generic [ ] |-- pci_0:17.0 pci_generic [ ] |-- pci_0:18.0 pci_generic [ ] `-- pci_0:1f.3 => Could you please give me some hint or tell me where I can reference? Thanks.
Regards, Hilbert This e-mail and its attachment may contain PEGATRON Corp information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited.
Hi,
On Tue, May 31, 2016 at 6:14 PM, Hilbert Tu(杜睿哲_Pegatron) Hilbert_Tu@pegatroncorp.com wrote:
Hi,
I use Coreboot with u-boot-x86 as payload to bring-up my Intel Atom C2000 platform, but I cannot make my SPI flash(w25q128fv) to work. Actually the SPI was detected under coreboot with correct ID, but in u-boot “sf probe” command, it just always failed. After tracing and code dump, I found it was failed due to SPIS_FCERR in spi/ich.c spi_xfer function. I totally have no idea why this happened and how to proceed my bring-up. My u-boot-x86 is up-to-date version and the SPI use intel,ich9-spi compatible in my dts file.
Can you double check Atom C2000 SPI controller that it is ICH9 compatible? Or maybe ICH7 compatible? Did you check its register can be accessed correctly?
Following is my dm tree and there is spi-flash device
=> dm tree Class Probed Name
root [ + ] root_driver serial [ + ] |-- serial keyboard [ + ] |-- keyboard rtc [ ] |-- rtc timer [ + ] |-- tsc-timer pci [ + ] `-- pci pch [ + ] |-- pch@1f,0 irq [ + ] | |-- irq-router spi [ ] | `-- spi spi_flash [ ] | `-- spi-flash@0 pci_generic [ ] |-- pci_0:0.0 pci [ + ] |-- pci_0:1.0 pci_generic [ ] | `-- pci_1:0.0 pci [ + ] |-- pci_0:3.0 pci_generic [ ] |-- pci_0:e.0 pci_generic [ ] |-- pci_0:f.0 pci_generic [ ] |-- pci_0:13.0 usb [ ] |-- ehci_pci pci_generic [ ] |-- pci_0:17.0 pci_generic [ ] |-- pci_0:18.0 pci_generic [ ] `-- pci_0:1f.3 => Could you please give me some hint or tell me where I can reference? Thanks.
Regards, Bin
Hi Bin,
Sorry for the late.
I have checked with Intel's support and following is their response:
On the other hand, for the question about ICH7 or ICH9. Unfortunately, the Bios Writers Guides (BWGs) or the EDS is unstated any information about ICH9. But, reviewing in section 22.4.1 on page 498 of the EDS specifies that the non-descriptor mode is the same as ICH7 mode. However, the non-descriptor mode is not supported and a valid Flash Descriptor is required for this SoC.
So I think the current u-boot cannot support SPI access under Atom C2000 with Intel FSP. I am still working on how to read the related registers in u-boot since I am not sure the default SPI base address (0x00001fff) is correct or not. If you know that, please advise. Thanks.
Regards, Hilbert
-----Original Message----- From: Bin Meng [mailto:bmeng.cn@gmail.com] Sent: Wednesday, June 01, 2016 11:36 AM To: Hilbert Tu(杜睿哲_Pegatron) Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] u-boot-x86 sf probe fail
Hi,
On Tue, May 31, 2016 at 6:14 PM, Hilbert Tu(杜睿哲_Pegatron) Hilbert_Tu@pegatroncorp.com wrote:
Hi,
I use Coreboot with u-boot-x86 as payload to bring-up my Intel Atom C2000 platform, but I cannot make my SPI flash(w25q128fv) to work. Actually the SPI was detected under coreboot with correct ID, but in u-boot “sf probe” command, it just always failed. After tracing and code dump, I found it was failed due to SPIS_FCERR in spi/ich.c spi_xfer function. I totally have no idea why this happened and how to proceed my bring-up. My u-boot-x86 is up-to-date version and the SPI use intel,ich9-spi compatible in my dts file.
Can you double check Atom C2000 SPI controller that it is ICH9 compatible? Or maybe ICH7 compatible? Did you check its register can be accessed correctly?
Following is my dm tree and there is spi-flash device
=> dm tree Class Probed Name
root [ + ] root_driver serial [ + ] |-- serial keyboard [ + ] |-- keyboard rtc [ ] |-- rtc timer [ + ] |-- tsc-timer pci [ + ] `-- pci pch [ + ] |-- pch@1f,0 irq [ + ] | |-- irq-router spi [ ] | `-- spi spi_flash [ ] | `-- spi-flash@0 pci_generic [ ] |-- pci_0:0.0 pci [ + ] |-- pci_0:1.0 pci_generic [ ] | `-- pci_1:0.0 pci [ + ] |-- pci_0:3.0 pci_generic [ ] |-- pci_0:e.0 pci_generic [ ] |-- pci_0:f.0 pci_generic [ ] |-- pci_0:13.0 usb [ ] |-- ehci_pci pci_generic [ ] |-- pci_0:17.0 pci_generic [ ] |-- pci_0:18.0 pci_generic [ ] `-- pci_0:1f.3 => Could you please give me some hint or tell me where I can reference? Thanks.
Regards, Bin This e-mail and its attachment may contain PEGATRON Corp information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited.
Hi Hilbert,
On Thu, Jun 2, 2016 at 11:46 AM, Hilbert Tu(杜睿哲_Pegatron) Hilbert_Tu@pegatroncorp.com wrote:
Hi Bin,
Sorry for the late.
I have checked with Intel's support and following is their response:
On the other hand, for the question about ICH7 or ICH9. Unfortunately, the Bios Writers Guides (BWGs) or the EDS is unstated any information about ICH9. But, reviewing in section 22.4.1 on page 498 of the EDS specifies that the non-descriptor mode is the same as ICH7 mode. However, the non-descriptor mode is not supported and a valid Flash Descriptor is required for this SoC.
So I think the current u-boot cannot support SPI access under Atom C2000 with Intel FSP. I am still working on how to read the related registers in u-boot since I am not sure the default SPI base address (0x00001fff) is correct or not. If you know that, please advise. Thanks.
I am confused, You said you were booting U-Boot from coreboot, so U-Boot itself does not use Intel FSP. But here you mentioned Intel FSP?
The SPI base address 0x1ffff does not look correct. That's probably the failure of SPI flash probe.
Regards, Bin
Hi Hilbert,
On 2 June 2016 at 19:40, Bin Meng bmeng.cn@gmail.com wrote:
Hi Hilbert,
On Thu, Jun 2, 2016 at 11:46 AM, Hilbert Tu(杜睿哲_Pegatron) Hilbert_Tu@pegatroncorp.com wrote:
Hi Bin,
Sorry for the late.
I have checked with Intel's support and following is their response:
On the other hand, for the question about ICH7 or ICH9. Unfortunately, the Bios Writers Guides (BWGs) or the EDS is unstated any information about ICH9. But, reviewing in section 22.4.1 on page 498 of the EDS specifies that the non-descriptor mode is the same as ICH7 mode. However, the non-descriptor mode is not supported and a valid Flash Descriptor is required for this SoC.
So I think the current u-boot cannot support SPI access under Atom C2000 with Intel FSP. I am still working on how to read the related registers in u-boot since I am not sure the default SPI base address (0x00001fff) is correct or not. If you know that, please advise. Thanks.
I am confused, You said you were booting U-Boot from coreboot, so U-Boot itself does not use Intel FSP. But here you mentioned Intel FSP?
The SPI base address 0x1ffff does not look correct. That's probably the failure of SPI flash probe.
You started another thread, but can we continue the discussion here?
It sounds like you are using coreboot with an FSP. So U-Boot should be able to access SPI flash. I suggest you dig into the SPI driver in coreboot, and see if the SPI base address is the same. I agree with Bin that 1ffff sounds wrong. See the call to pch_get_spi_base() in the U-Boot SPI driver.
Regards, Simon
participants (3)
-
Bin Meng -
Hilbert Tu(杜睿哲_Pegatron) -
Simon Glass