[U-Boot] [PATCH] T210: P2571: Enable SD-card power via PMIC LDO2
This was done in the 32-bit AVP loader (SPL) but is board-specific so should be moved to the CPU portion.
Signed-off-by: Tom Warren twarren@nvidia.com --- board/nvidia/p2571/Makefile | 1 - board/nvidia/p2571/max77620_init.c | 85 -------------------------------------- board/nvidia/p2571/max77620_init.h | 3 +- board/nvidia/p2571/p2571.c | 22 ++++++++++ 4 files changed, 24 insertions(+), 87 deletions(-) delete mode 100644 board/nvidia/p2571/max77620_init.c
diff --git a/board/nvidia/p2571/Makefile b/board/nvidia/p2571/Makefile index 223062e..627b7ef 100644 --- a/board/nvidia/p2571/Makefile +++ b/board/nvidia/p2571/Makefile @@ -5,5 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-y += max77620_init.o obj-y += p2571.o diff --git a/board/nvidia/p2571/max77620_init.c b/board/nvidia/p2571/max77620_init.c deleted file mode 100644 index ed8d4dc..0000000 --- a/board/nvidia/p2571/max77620_init.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch-tegra/tegra_i2c.h> -#include "max77620_init.h" - -/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */ - -void tegra_i2c_ll_write_addr(uint addr, uint config) -{ - struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; - - writel(addr, ®->cmd_addr0); - writel(config, ®->cnfg); -} - -void tegra_i2c_ll_write_data(uint data, uint config) -{ - struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; - - writel(data, ®->cmd_data1); - writel(config, ®->cnfg); -} - -void pmic_enable_cpu_vdd(void) -{ - uint reg; - debug("%s entry\n", __func__); - - /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */ - debug("%s: Setting GPIO5 to enable CPU regulator\n", __func__); - /* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */ - reg = 0x0900 | MAX77620_GPIO5_REG; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); - - /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN */ - debug("%s: Setting GPIO1 to enable HDMI\n", __func__); - reg = 0x0900 | MAX77620_GPIO1_REG; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); - - /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */ - reg = 0x1C00 | MAX77620_AME_GPIO; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); - - /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v */ - debug("%s: Set SD1 for LPDDR4, disable SD1RS, voltage to 1.125v\n", - __func__); - /* bit1=0, SD1 remote sense disabled */ - reg = 0x0400 | MAX77620_CNFG2SD_REG; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); - - /* SD1 output = 1.125V */ - reg = 0x2A00 | MAX77620_SD1_REG; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); - - debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); - /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ - reg = 0xF200 | MAX77620_CNFG1_L2_REG; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); - - debug("%s: Set LDO1 for USB3 phy power to 1.05V??\n", __func__); - /* 0xCA for 105v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ - reg = 0xCA00 | MAX77620_CNFG1_L1_REG; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); -} diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h index 9d5cce7..92c3719 100644 --- a/board/nvidia/p2571/max77620_init.h +++ b/board/nvidia/p2571/max77620_init.h @@ -10,7 +10,8 @@
/* MAX77620-PMIC-specific early init regs */
-#define MAX77620_I2C_ADDR 0x78 /* or 0x3C 7-bit */ +#define MAX77620_I2C_ADDR 0x78 +#define MAX77620_I2C_ADDR_7BIT 0x3C
#define MAX77620_SD0_REG 0x16 #define MAX77620_SD1_REG 0x17 diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index fc710c1..842242c 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -6,10 +6,32 @@ */
#include <common.h> +#include <i2c.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include "max77620_init.h" #include "pinmux-config-p2571.h"
+void pin_mux_mmc(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); +} + /* * Routine: pinmux_init * Description: Do individual peripheral pinmux configs
The tegra-common-usb-gadget.h include was causing some build problems in ci_udc.c with a 64-bit gcc in an earlier version of the T210 patches, but it is working fine now, so restore it.
Signed-off-by: Tom Warren twarren@nvidia.com --- include/configs/p2571.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 77faf5f..d39fa2a 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -68,6 +68,7 @@ * TODO(twarren@nvidia.com) - add tegra-common-usb-gadget.h back * breaks 64-bit build in ci_udc.c */ +#include "tegra-common-usb-gadget.h" #include "tegra-common-post.h"
#define COUNTER_FREQUENCY 38400000
CPU board (E2530) has a fan - turn it on via GPIO to keep the SoC cool.
Signed-off-by: Tom Warren twarren@nvidia.com --- arch/arm/mach-tegra/board2.c | 3 +++ board/nvidia/p2571/p2571.c | 12 ++++++++++++ 2 files changed, 15 insertions(+)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 36bcfb0..2927b4e 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -60,6 +60,7 @@ __weak void pin_mux_usb(void) {} __weak void pin_mux_spi(void) {} __weak void gpio_early_init_uart(void) {} __weak void pin_mux_display(void) {} +__weak void start_cpu_fan(void) {}
#if defined(CONFIG_TEGRA_NAND) __weak void pin_mux_nand(void) @@ -230,6 +231,8 @@ int board_late_init(void) setenv("cpu_ns_mode", ""); } #endif + start_cpu_fan(); + return 0; }
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index 842242c..4b0f973 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -9,6 +9,7 @@ #include <i2c.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include <asm/gpio.h> #include "max77620_init.h" #include "pinmux-config-p2571.h"
@@ -49,3 +50,14 @@ void pinmux_init(void) pinmux_config_drvgrp_table(p2571_drvgrps, ARRAY_SIZE(p2571_drvgrps)); } + +/* + * Routine: start_cpu_fan + * Description: Enable/start PWM CPU fan on Foster-FFD + */ +void start_cpu_fan(void) +{ + /* GPIO_PE4 is PS_VDD_FAN_ENABLE */ + gpio_request(GPIO_PE4, "FAN_VDD"); + gpio_direction_output(GPIO_PE4, 1); +}
VPR (Video Protect Region) may be reconfigured from secure code in the kernel/OS. Set the ALLOW_TZ_WRITE_ACCESS bit in REG_CTRL to allow this. Also used common CONFIG option (CONFIG_LOCK_VPR) in T124/T210 builds to enable VPR setup.
Signed-off-by: Tom Warren twarren@nvidia.com --- arch/arm/include/asm/arch-tegra124/mc.h | 2 ++ arch/arm/include/asm/arch-tegra210/mc.h | 2 ++ arch/arm/mach-tegra/Makefile | 4 +--- arch/arm/mach-tegra/vpr.c | 9 +++++++-- include/configs/tegra124-common.h | 3 +++ include/configs/tegra210-common.h | 3 +++ 6 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h index 37998a4..851e3df 100644 --- a/arch/arm/include/asm/arch-tegra124/mc.h +++ b/arch/arm/include/asm/arch-tegra124/mc.h @@ -78,5 +78,7 @@ struct mc_ctlr {
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) +#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_DISABLED (0 << 1) +#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_ENABLED (1 << 1)
#endif /* _TEGRA124_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/mc.h b/arch/arm/include/asm/arch-tegra210/mc.h index 77e9aa5..2a20b47 100644 --- a/arch/arm/include/asm/arch-tegra210/mc.h +++ b/arch/arm/include/asm/arch-tegra210/mc.h @@ -68,5 +68,7 @@ struct mc_ctlr {
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) +#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_DISABLED (0 << 1) +#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_ENABLED (1 << 1)
#endif /* _TEGRA210_MC_H_ */ diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 0db8ee0..8a42216 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -24,9 +24,7 @@ obj-y += pinmux-common.o obj-y += powergate.o obj-y += xusb-padctl.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o -#TCW Fix this to use a common config switch (CONFIG_LOCK_VPR?) -obj-$(CONFIG_TEGRA124) += vpr.o -obj-$(CONFIG_TEGRA210) += vpr.o +obj-$(CONFIG_LOCK_VPR) += vpr.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-tegra/vpr.c b/arch/arm/mach-tegra/vpr.c index f695811..091163e 100644 --- a/arch/arm/mach-tegra/vpr.c +++ b/arch/arm/mach-tegra/vpr.c @@ -21,14 +21,19 @@ #include <asm/arch/tegra.h> #include <asm/arch/mc.h>
-/* Configures VPR. Right now, all we do is turn it off. */ +/* + * Configures VPR. Right now, all we do is turn it off. + * But we set ALLOW_TZ_WRITE_ACCESS so secure code + * in the kernel/OS can reconfig it later if needed. + */ void config_vpr(void) { struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
/* Turn VPR off */ writel(0, &mc->mc_video_protect_size_mb); - writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED, + writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED | + TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_ENABLED, &mc->mc_video_protect_reg_ctrl); /* read back to ensure the write went through */ readl(&mc->mc_video_protect_reg_ctrl); diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index af7698d..e850a75 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -70,4 +70,7 @@ #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+/* Set up VPR (Video Protect Region) */ +#define CONFIG_LOCK_VPR + #endif /* _TEGRA124_COMMON_H_ */ diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 0348d47..267beab 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -73,4 +73,7 @@ #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+/* Set up VPR (Video Protect Region) */ +#define CONFIG_LOCK_VPR + #endif /* _TEGRA210_COMMON_H_ */
On 07/29/2015 10:24 AM, Tom Warren wrote:
VPR (Video Protect Region) may be reconfigured from secure code in the kernel/OS. Set the ALLOW_TZ_WRITE_ACCESS bit in REG_CTRL to allow this. Also used common CONFIG option (CONFIG_LOCK_VPR) in T124/T210 builds to enable VPR setup.
Acked-by: Stephen Warren swarren@nvidia.com
I haven't investigated this much, but it seems fine.
Stephen,
-----Original Message----- From: Stephen Warren [mailto:swarren@wwwdotorg.org] Sent: Wednesday, August 05, 2015 12:52 PM To: Tom Warren Cc: u-boot@lists.denx.de; Thierry Reding; Stephen Warren; tomcwarren3959@gmail.com Subject: Re: [U-Boot] [PATCH] Tegra: Allow TZ writes to VPR aperature regs
On 07/29/2015 10:24 AM, Tom Warren wrote:
VPR (Video Protect Region) may be reconfigured from secure code in the kernel/OS. Set the ALLOW_TZ_WRITE_ACCESS bit in REG_CTRL to allow this. Also used common CONFIG option (CONFIG_LOCK_VPR) in T124/T210 builds to enable VPR setup.
Acked-by: Stephen Warren swarren@nvidia.com
I haven't investigated this much, but it seems fine.
Thanks, but I'm dropping this patch. I've added Alex's 2 GPU/VPR patches, so this isn't needed (and enabling TZ writes is only done for dynamic VPR, which I've learned isn't needed/used).
Tom -- nvpublic
On 07/29/2015 10:24 AM, Tom Warren wrote:
This was done in the 32-bit AVP loader (SPL) but is board-specific so should be moved to the CPU portion.
For: T210: P2571: Enable SD-card power via PMIC LDO2 T210: P2571: Restore USB gadget mode (ums) T210: P2571: Turn CPU fan on
Acked-by: Stephen Warren swarren@nvidia.com
(the line lengths in the commit messages are very short...)
For: Tegra: Allow TZ writes to VPR aperature regs
I need to learn/think some more to review that.
participants (3)
-
Stephen Warren -
Tom Warren -
Tom Warren