From: Feng Kan fkan@amcc.com

Add AMCC Redwood reference board that uses the latest PPC 464 CPU processor combined with a rich mix of peripheral controllers. The board will support PCIe, mutiple Gig ethernet ports, advanced hardware RAID assistance and IEEE 1588.

Signed-off-by: Feng Kan fkan@amcc.com --- MAINTAINERS | 3 + MAKEALL | 1 + Makefile | 3 + board/amcc/redwood/Makefile | 50 ++++ board/amcc/redwood/config.mk | 42 ++++ board/amcc/redwood/init.S | 77 +++++++ board/amcc/redwood/redwood.c | 496 +++++++++++++++++++++++++++++++++++++++++ board/amcc/redwood/redwood.h | 50 ++++ board/amcc/redwood/u-boot.lds | 147 ++++++++++++ 9 files changed, 869 insertions(+), 0 deletions(-) create mode 100644 board/amcc/redwood/Makefile create mode 100644 board/amcc/redwood/config.mk create mode 100644 board/amcc/redwood/init.S create mode 100644 board/amcc/redwood/redwood.c create mode 100644 board/amcc/redwood/redwood.h create mode 100644 board/amcc/redwood/u-boot.lds

diff --git a/MAINTAINERS b/MAINTAINERS index a3d70b1..a4637fd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -420,6 +420,9 @@ Guennadi Liakhovetski g.liakhovetski@gmx.de

linkstation MPC8241

+Feng Kan fkan@amcc.com + + redwood PPC4xx -------------------------------------------------------------------------

Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index 32caab7..566e63a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -221,6 +221,7 @@ LIST_4xx=" \ PPChameleonEVB \ quad100hd \ rainier \ + redwood \ sbc405 \ sc3 \ sequoia \ diff --git a/Makefile b/Makefile index 8bfc891..ff38e0c 100644 --- a/Makefile +++ b/Makefile @@ -1417,6 +1417,9 @@ rainier_nand_config: unconfig @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk

+redwood_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx redwood amcc + sc3_config:unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx sc3

diff --git a/board/amcc/redwood/Makefile b/board/amcc/redwood/Makefile new file mode 100644 index 0000000..a8bdb05 --- /dev/null +++ b/board/amcc/redwood/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2008 +# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/redwood/config.mk b/board/amcc/redwood/config.mk new file mode 100644 index 0000000..531d9d3 --- /dev/null +++ b/board/amcc/redwood/config.mk @@ -0,0 +1,42 @@ +# +# (C) Copyright 2008 +# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# AMCC 460SX Reference Platform (redwood) board +# + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xfffb0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/redwood/init.S b/board/amcc/redwood/init.S new file mode 100644 index 0000000..876f96a --- /dev/null +++ b/board/amcc/redwood/init.S @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2008 + * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm-ppc/mmu.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G) + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + + /* Although 512 KB, map 256k at a time */ + tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CFG_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) + + tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) + + /* + * Peripheral base + */ + tlbentry(CFG_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbtab_end diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c new file mode 100644 index 0000000..0587e39 --- /dev/null +++ b/board/amcc/redwood/redwood.c @@ -0,0 +1,496 @@ +/* + * This is the main board level file for the Redwood AMCC board. + * + * (C) Copyright 2008 + * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include "redwood.h" +#include <ppc4xx.h> +#include <asm/processor.h> +#include <i2c.h> +#include <asm-ppc/io.h> + +int compare_to_true(char *str); +char *remove_l_w_space(char *in_str); +char *remove_t_w_space(char *in_str); +int get_console_port(void); + +static void early_init_EBC(void); +static int bootdevice_selected(void); +static void early_reinit_EBC(int); +static void early_init_UIC(void); + +/*----------------------------------------------------------------------------+ +| Define Boot devices ++----------------------------------------------------------------------------*/ +#define BOOT_FROM_8BIT_SRAM 0x00 +#define BOOT_FROM_16BIT_SRAM 0x01 +#define BOOT_FROM_32BIT_SRAM 0x02 +#define BOOT_FROM_8BIT_NAND 0x03 +#define BOOT_FROM_16BIT_NOR 0x04 +#define BOOT_DEVICE_UNKNOWN 0xff + +/*----------------------------------------------------------------------------+ +| EBC Devices Characteristics +| Peripheral Bank Access Parameters - EBC_BxAP +| Peripheral Bank Configuration Register - EBC_BxCR ++----------------------------------------------------------------------------*/ + +/* + * 8 bit width SRAM + * BU Value + * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 + * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000 + * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000 + */ +#define EBC_BXAP_8BIT_SRAM EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED + +#define EBC_BXAP_16BIT_SRAM EBC_BXAP_8BIT_SRAM +#define EBC_BXAP_32BIT_SRAM EBC_BXAP_8BIT_SRAM + +/* + * NAND flash + * BU Value + * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 + * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 + * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 +*/ +#define EBC_BXAP_NAND EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED + +/* + * NOR flash + * BU Value + * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 + * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 + * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 +*/ +#define EBC_BXAP_NOR EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED + +/* + * FPGA + * BU value : + * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000 + * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000 + */ +#define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(11) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(10) | \ + EBC_BXAP_OEN_ENCODE(1) | \ + EBC_BXAP_WBN_ENCODE(1) | \ + EBC_BXAP_WBF_ENCODE(1) | \ + EBC_BXAP_TH_ENCODE(1) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_RW | \ + EBC_BXAP_PEN_DISABLED + +#define EBC_BXCR_8BIT_SRAM_CS0 EBC_BXCR_BAS_ENCODE(0xFFE00000) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_8BIT + +#define EBC_BXCR_32BIT_SRAM_CS0 EBC_BXCR_BAS_ENCODE(0xFFC00000) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_32BIT + +#define EBC_BXCR_NAND_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ + EBC_BXCR_BS_16MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_8BIT + +#define EBC_BXCR_16BIT_SRAM_CS0 EBC_BXCR_BAS_ENCODE(0xFFE00000) | \ + EBC_BXCR_BS_2MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT + +#define EBC_BXCR_NOR_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ + EBC_BXCR_BS_16MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT + +#define EBC_BXCR_NOR_CS1 EBC_BXCR_BAS_ENCODE(0xE0000000) | \ + EBC_BXCR_BS_128MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT + +#define EBC_BXCR_NAND_CS1 EBC_BXCR_BAS_ENCODE(0xE0000000) | \ + EBC_BXCR_BS_128MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_8BIT + +#define EBC_BXCR_NAND_CS2 EBC_BXCR_BAS_ENCODE(0xC0000000) | \ + EBC_BXCR_BS_128MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_8BIT + +#define EBC_BXCR_SRAM_CS2 EBC_BXCR_BAS_ENCODE(0xC0000000) | \ + EBC_BXCR_BS_4MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_32BIT + +#define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \ + EBC_BXCR_BS_16MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT + +#define EBC_BXCR_FPGA_CS3 EBC_BXCR_BAS_ENCODE(0xe2000000) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT + +/***************************************************************************** + * UBOOT initiated board specific function calls + ****************************************************************************/ + +int board_early_init_f(void) +{ + int computed_boot_device = BOOT_DEVICE_UNKNOWN; + + /* + * Initialise EBC + */ + early_init_EBC(); + + /* + * Determine which boot device was selected + */ + computed_boot_device = bootdevice_selected(); + + /* + * Reinit EBC based on selected boot device + */ + early_reinit_EBC(computed_boot_device); + + /* + * Setup for UIC on 460SX redwood board + */ + early_init_UIC(); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Redwood - AMCC 460SX Reference Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +static void early_init_EBC(void) +{ + /*-------------------------------------------------------------------+ + | Initialize EBC CONFIG - + | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC + | default value : + | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 + | + +-------------------------------------------------------------------*/ + mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + EBC_CFG_PTD_ENABLE | + EBC_CFG_RTC_16PERCLK | + EBC_CFG_ATC_PREVIOUS | + EBC_CFG_DTC_PREVIOUS | + EBC_CFG_CTC_PREVIOUS | + EBC_CFG_OEO_PREVIOUS | + EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16); + + /*-------------------------------------------------------------------+ + | + | PART 1 : Initialize EBC Bank 3 + | ============================== + | Bank1 is always associated to the EPLD. + | It has to be initialized prior to other banks settings computation + | since some board registers values may be needed to determine the + | boot type + | + +-------------------------------------------------------------------*/ + mtebc(pb1ap, EBC_BXAP_FPGA); + mtebc(pb1cr, EBC_BXCR_FPGA_CS3); + +} + +static int bootdevice_selected(void) +{ + unsigned long sdr0_pinstp; + unsigned long bootstrap_settings; + int computed_boot_device = BOOT_DEVICE_UNKNOWN; + + /*-------------------------------------------------------------------+ + | + | Determine which boot device was selected + | ================================================= + | + | Read Pin Strap Register in PPC460SX + | Result can either be : + | - Boot strap = boot from EBC 8bits => Small Flash + | - Boot strap = boot from PCI + | - Boot strap = IIC + | In case of boot from IIC, read Serial Device Strap Register1 + | + | Result can either be : + | - Boot from EBC - EBC Bus Width = 8bits => Small Flash + | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM + | - Boot from PCI + | + +-------------------------------------------------------------------*/ + /* Read Pin Strap Register in PPC460SX */ + mfsdr(SDR0_PINSTP, sdr0_pinstp); + bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK; + + switch (bootstrap_settings) { + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: + /* + * Boot from SRAM, 8bit width + */ + computed_boot_device = BOOT_FROM_8BIT_SRAM; + break; + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: + /* + * Boot from SRAM, 32bit width + */ + computed_boot_device = BOOT_FROM_32BIT_SRAM; + break; + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: + /* + * Boot from NAND, 8bit width + */ + computed_boot_device = BOOT_FROM_8BIT_NAND; + break; + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4: + /* + * Boot from SRAM, 16bit width + * Boot setting in IIC EEPROM 0x50 + */ + computed_boot_device = BOOT_FROM_16BIT_SRAM; + break; + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5: + /* + * Boot from NOR, 16bit width + * Boot setting in IIC EEPROM 0x54 + */ + computed_boot_device = BOOT_FROM_16BIT_NOR; + break; + default: + /* should not be */ + computed_boot_device = BOOT_DEVICE_UNKNOWN; + break; + } + + return computed_boot_device; +} + +static void early_reinit_EBC(int computed_boot_device) +{ + /*-------------------------------------------------------------------+ + | + | Compute EBC settings depending on selected boot device + | ====== ====================================================== + | + | Resulting EBC init will be among following configurations : + | + | - Boot from EBC 8bits => boot from Small Flash selected + | EBC-CS0 = Small Flash + | EBC-CS2 = Large Flash and SRAM + | + | - Boot from EBC 16bits => boot from Large Flash or SRAM + | EBC-CS0 = Large Flash or SRAM + | EBC-CS2 = Small Flash + | + | - Boot from PCI + | EBC-CS0 = not initialized to avoid address contention + | EBC-CS2 = same as boot from Small Flash selected + | + +-------------------------------------------------------------------*/ + unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0; + unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0; + unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0; + + switch (computed_boot_device) { + /*-------------------------------------------------------------------*/ + case BOOT_FROM_8BIT_SRAM: + /*-------------------------------------------------------------------*/ + ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM; + ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0; + ebc0_cs1_bxap_value = EBC_BXAP_NOR; + ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; + ebc0_cs2_bxap_value = EBC_BXAP_NAND; + ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2; + break; + + /*-------------------------------------------------------------------*/ + case BOOT_FROM_16BIT_SRAM: + /*-------------------------------------------------------------------*/ + ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM; + ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0; + ebc0_cs1_bxap_value = EBC_BXAP_NOR; + ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; + ebc0_cs2_bxap_value = EBC_BXAP_NAND; + ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2; + break; + + /*-------------------------------------------------------------------*/ + case BOOT_FROM_32BIT_SRAM: + /*-------------------------------------------------------------------*/ + ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM; + ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0; + ebc0_cs1_bxap_value = EBC_BXAP_NOR; + ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; + ebc0_cs2_bxap_value = EBC_BXAP_NAND; + ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2; + break; + + /*-------------------------------------------------------------------*/ + case BOOT_FROM_16BIT_NOR: + /*-------------------------------------------------------------------*/ + ebc0_cs0_bxap_value = EBC_BXAP_NOR; + ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0; + ebc0_cs1_bxap_value = EBC_BXAP_NAND; + ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1; + ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM; + ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2; + break; + + /*-------------------------------------------------------------------*/ + case BOOT_FROM_8BIT_NAND: + /*-------------------------------------------------------------------*/ + ebc0_cs0_bxap_value = EBC_BXAP_NAND; + ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0; + ebc0_cs1_bxap_value = EBC_BXAP_NOR; + ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; + ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM; + ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2; + break; + + /*-------------------------------------------------------------------*/ + default: + /*-------------------------------------------------------------------*/ + /* BOOT_DEVICE_UNKNOWN */ + break; + } + + mtebc(pb0ap, ebc0_cs0_bxap_value); + mtebc(pb0cr, ebc0_cs0_bxcr_value); + mtebc(pb1ap, ebc0_cs1_bxap_value); + mtebc(pb1cr, ebc0_cs1_bxcr_value); + mtebc(pb2ap, ebc0_cs2_bxap_value); + mtebc(pb2cr, ebc0_cs2_bxcr_value); +} + +static void early_init_UIC(void) +{ + /*--------------------------------------------------------------------+ + | Initialise UIC registers. Clear all interrupts. Disable all + | interrupts. + | Set critical interrupt values. Set interrupt polarities. Set + | interrupt trigger levels. Make bit 0 High priority. Clear all + | interrupts again. + +-------------------------------------------------------------------*/ + mtdcr(uic3sr, 0xffffffff); /* Clear all interrupts */ + mtdcr(uic3er, 0x00000000); /* disable all interrupts */ + mtdcr(uic3cr, 0x00000000); /* Set Critical / Non Critical + * interrupts */ + mtdcr(uic3pr, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ + + mtdcr(uic3sr, 0x00000000); /* clear all interrupts */ + mtdcr(uic3sr, 0xffffffff); /* clear all interrupts */ + + mtdcr(uic2sr, 0xffffffff); /* Clear all interrupts */ + mtdcr(uic2er, 0x00000000); /* disable all interrupts */ + mtdcr(uic2cr, 0x00000000); /* Set Critical / Non Critical + * interrupts */ + mtdcr(uic2pr, 0xebebebff); /* Set Interrupt Polarities */ + mtdcr(uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ + + mtdcr(uic2sr, 0x00000000); /* clear all interrupts */ + mtdcr(uic2sr, 0xffffffff); /* clear all interrupts */ + + mtdcr(uic1sr, 0xffffffff); /* Clear all interrupts */ + mtdcr(uic1er, 0x00000000); /* disable all interrupts */ + mtdcr(uic1cr, 0x00000000); /* Set Critical / Non Critical + * interrupts */ + mtdcr(uic1pr, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(uic1tr, 0x001fc0ff); /* Set Interrupt Trigger Levels */ + + mtdcr(uic1sr, 0x00000000); /* clear all interrupts */ + mtdcr(uic1sr, 0xffffffff); /* clear all interrupts */ + + mtdcr(uic0sr, 0xffffffff); /* Clear all interrupts */ + mtdcr(uic0er, 0x00000000); /* disable all interrupts excepted + * cascade to be checked */ + mtdcr(uic0cr, 0x00104001); /* Set Critical / Non Critical + * interrupts */ + mtdcr(uic0pr, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(uic0tr, 0x000f003c); /* Set Interrupt Trigger Levels */ + + mtdcr(uic0sr, 0x00000000); /* clear all interrupts */ + mtdcr(uic0sr, 0xffffffff); /* clear all interrupts */ + +} diff --git a/board/amcc/redwood/redwood.h b/board/amcc/redwood/redwood.h new file mode 100644 index 0000000..89b87e6 --- /dev/null +++ b/board/amcc/redwood/redwood.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2008 + * Feng Kan, Applied Micro Circuit Corp., fkan@amcc.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __REDWOOD_H_ +#define __REDWOOD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------------------------+ +| Defines ++----------------------------------------------------------------------------*/ +/* Pin Straps Reg */ +#define SDR0_PSTRP0 0x0040 +#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ + +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */ + +#ifdef __cplusplus +} +#endif +#endif /* __REDWOOD_H_ */ diff --git a/board/amcc/redwood/u-boot.lds b/board/amcc/redwood/u-boot.lds new file mode 100644 index 0000000..2104cc2 --- /dev/null +++ b/board/amcc/redwood/u-boot.lds @@ -0,0 +1,147 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/redwood/init.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +}