[PATCH 1/5] mtd: spi: renesas: Write DREAR register once
Instead of writing DREAR with 0 first and then overwriting DREAR again in case of 4 byte addressing mode, write DREAR in every case once with the correct content right away. No functional change.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org --- Cc: "Cédric Le Goater" clg@kaod.org Cc: Hai Pham hai.pham.ud@renesas.com Cc: Jagan Teki jagan@amarulasolutions.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: William Zhang william.zhang@broadcom.com Cc: u-boot@lists.denx.de --- drivers/spi/renesas_rpc_spi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index e6b602cf7b4..749c686a6c4 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -277,14 +277,15 @@ static int rpc_spi_mem_exec_op(struct spi_slave *spi, writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR); smenr |= RPC_DRENR_CDE;
- writel(0, priv->regs + RPC_DREAR); if (op->addr.nbytes == 4) { writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1), priv->regs + RPC_DREAR); smenr |= RPC_DRENR_ADE(0xF); } else if (op->addr.nbytes == 3) { + writel(0, priv->regs + RPC_DREAR); smenr |= RPC_DRENR_ADE(0x7); } else { + writel(0, priv->regs + RPC_DREAR); smenr |= RPC_DRENR_ADE(0); }
Instead of writing DRDMCR with 0 first and then overwriting DRDMCR again in case any dummy bytes have to be sent out, write DRDMCR in every case with the amount of dummy bytes that have to be sent out. In case no dummy bytes have to be sent out, the value written into DRDMCR is zero, so no dummy bytes are sent out. No functional change.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org --- Cc: "Cédric Le Goater" clg@kaod.org Cc: Hai Pham hai.pham.ud@renesas.com Cc: Jagan Teki jagan@amarulasolutions.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: William Zhang william.zhang@broadcom.com Cc: u-boot@lists.denx.de --- drivers/spi/renesas_rpc_spi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index 749c686a6c4..a2ac5525b90 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -289,12 +289,10 @@ static int rpc_spi_mem_exec_op(struct spi_slave *spi, smenr |= RPC_DRENR_ADE(0); }
- writel(0, priv->regs + RPC_DRDMCR); - if (op->dummy.nbytes) { - writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); + if (op->dummy.nbytes) smenr |= RPC_DRENR_DME; - }
+ writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); writel(0, priv->regs + RPC_DROPR); writel(smenr, priv->regs + RPC_DRENR);
Make sure DRDRENR register is configured before performing external address space read. This register might have been configured by a prior stage bootloader and leaving it unconfigured would interfere with U-Boot operation. Since U-Boot RPC SPI driver does not support DDR data transfer mode yet, set this register unconditionally to 0.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org --- Cc: "Cédric Le Goater" clg@kaod.org Cc: Hai Pham hai.pham.ud@renesas.com Cc: Jagan Teki jagan@amarulasolutions.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: William Zhang william.zhang@broadcom.com Cc: u-boot@lists.denx.de --- drivers/spi/renesas_rpc_spi.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index a2ac5525b90..50890981149 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -294,6 +294,7 @@ static int rpc_spi_mem_exec_op(struct spi_slave *spi,
writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); writel(0, priv->regs + RPC_DROPR); + writel(0, priv->regs + RPC_DRDRENR); writel(smenr, priv->regs + RPC_DRENR);
memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes);
Make sure RPC PHY timing registers are configured before performing bus access. These registers might have been left unconfigured or may have been configured by a prior stage bootloader and leaving them unconfigured or misconfigured would interfere with U-Boot operation.
Set PHYOFFSET1 DDRTMG field to 3 which enables DDR timing adjustment when SPIDRE or DRDRE = 0 and set PHYOFFSET2 OCTTMG field to 4 which makes the interface operate in Serial flash or HyperFlash mode.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org --- Cc: "Cédric Le Goater" clg@kaod.org Cc: Hai Pham hai.pham.ud@renesas.com Cc: Jagan Teki jagan@amarulasolutions.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: William Zhang william.zhang@broadcom.com Cc: u-boot@lists.denx.de --- drivers/spi/renesas_rpc_spi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index 50890981149..9aab71db1de 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -145,6 +145,12 @@ #define RPC_PHYCNT_WBUF BIT(2) #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
+#define RPCIF_PHYOFFSET1 0x0080 /* R/W */ +#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28) + +#define RPCIF_PHYOFFSET2 0x0084 /* R/W */ +#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8) + #define RPC_PHYINT 0x0088 /* R/W */ #define RPC_PHYINT_RSTEN BIT(18) #define RPC_PHYINT_WPEN BIT(17) @@ -227,6 +233,12 @@ static int rpc_spi_claim_bus(struct udevice *dev, bool manual) struct udevice *bus = dev->parent; struct rpc_spi_priv *priv = dev_get_priv(bus);
+ setbits_le32(priv->regs + RPCIF_PHYOFFSET1, + RPCIF_PHYOFFSET1_DDRTMG(3)); + clrsetbits_le32(priv->regs + RPCIF_PHYOFFSET2, + RPCIF_PHYOFFSET2_OCTTMG(7), + RPCIF_PHYOFFSET2_OCTTMG(4)); + /* NOTE: The 0x260 are undocumented bits, but they must be set. */ writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260, priv->regs + RPC_PHYCNT);
Add device tree compatible string "renesas,rcar-gen4-rpc-if" to the driver to match on upstream RPC DT node in R-Car Gen4 DTs.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org --- Cc: "Cédric Le Goater" clg@kaod.org Cc: Hai Pham hai.pham.ud@renesas.com Cc: Jagan Teki jagan@amarulasolutions.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: William Zhang william.zhang@broadcom.com Cc: u-boot@lists.denx.de --- drivers/spi/renesas_rpc_spi.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index 9aab71db1de..f1e6f9f4e01 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -465,6 +465,7 @@ static const struct dm_spi_ops rpc_spi_ops = { static const struct udevice_id rpc_spi_ids[] = { { .compatible = "renesas,r7s72100-rpc-if" }, { .compatible = "renesas,rcar-gen3-rpc-if" }, + { .compatible = "renesas,rcar-gen4-rpc-if" }, { } };
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Marek Vasut