Internal memory controller counters can reach a bad state after training in DDR4 mode if accumulated ECC or DBI mode is eanbled.

Signed-off-by: York Sun yorksun@freescale.com --- arch/arm/include/asm/arch-ls102xa/config.h | 1 + drivers/ddr/fsl/fsl_ddr_gen4.c | 8 ++++++++ 2 files changed, 9 insertions(+)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ba86eea..7bd3d2f 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -88,6 +88,7 @@ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_FSL_ERRATUM_A008378 #else #error SoC not defined #endif diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index e024db9..43b454a 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -157,6 +157,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[i], regs->debug[i]); } } +#ifdef CONFIG_SYS_FSL_ERRATUM_A008378 + /* Erratum applies when accumulated ECC is used, or DBI is enabled */ +#define IS_ACC_ECC_EN(v) (v & 0x4) +#define IS_DBI(v) ((v >> 12) & 0x3 == 0x2) + if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || + IS_DBI(regs->ddr_sdram_cfg_3)) + ddr_setbits32(ddr->debug[28], 0x9 << 20); +#endif

/* * For RDIMMs, JEDEC spec requires clocks to be stable before reset is