[U-Boot] [PATCH 0/10] Drop mpc8xx, mpc82xx boards which are orphaned or have no maintainers
I built all the other boards and compared MD5SUM.
I confirmed this series has no impact against them.
I'd like to drop as many unmaintained (or old enough) boards as possible before switching to Kconfig.
I believe this would make our migration and test easier.
Masahiro Yamada (10): powerpc: mpc8xx: remove some of tqm8xx board family without maintainers powerpc: mpc8260: remove ppmc8260 board support powerpc: mpc824x: remove MUSENKI and Sandpoint8245 board support powerpc: mpc8xx: remove stxxtc board support powerpc: mpc8xx: remove svm_sc8xx board powerpc: mpc8xx: remove SXNI855T board support powerpc: mpc8xx: remove GEN860T, GEN806T_SC board support powerpc: mpc8xx: remove FLAGADM board support powerpc: mpc8260: remove sacsng board support powerpc: mpc8260: remove ep8260 board support
CREDITS | 2 +- arch/powerpc/cpu/mpc824x/cpu_init.c | 21 - arch/powerpc/cpu/mpc8260/ether_fcc.c | 17 - arch/powerpc/cpu/mpc8xx/cpu_init.c | 4 - arch/powerpc/cpu/mpc8xx/fec.c | 79 +- arch/powerpc/cpu/mpc8xx/speed.c | 3 +- arch/powerpc/lib/board.c | 3 +- board/ep8260/Makefile | 8 - board/ep8260/ep8260.c | 304 ------ board/ep8260/ep8260.h | 24 - board/ep8260/flash.c | 395 -------- board/ep8260/mii_phy.c | 107 --- board/flagadm/Makefile | 8 - board/flagadm/flagadm.c | 134 --- board/flagadm/flash.c | 687 -------------- board/flagadm/u-boot.lds | 82 -- board/flagadm/u-boot.lds.debug | 121 --- board/gen860t/Makefile | 8 - board/gen860t/README | 131 --- board/gen860t/beeper.c | 183 ---- board/gen860t/beeper.h | 13 - board/gen860t/flash.c | 628 ------------- board/gen860t/fpga.c | 362 ------- board/gen860t/fpga.h | 26 - board/gen860t/gen860t.c | 278 ------ board/gen860t/ioport.c | 331 ------- board/gen860t/ioport.h | 26 - board/gen860t/u-boot-flashenv.lds | 92 -- board/gen860t/u-boot.lds | 87 -- board/musenki/Makefile | 8 - board/musenki/README | 298 ------ board/musenki/flash.c | 496 ---------- board/musenki/musenki.c | 94 -- board/ppmc8260/Makefile | 8 - board/ppmc8260/ppmc8260.c | 291 ------ board/sacsng/Makefile | 8 - board/sacsng/clkinit.c | 1009 -------------------- board/sacsng/clkinit.h | 103 -- board/sacsng/flash.c | 507 ---------- board/sacsng/ioconfig.h | 217 ----- board/sacsng/sacsng.c | 848 ----------------- board/sixnet/Makefile | 8 - board/sixnet/flash.c | 774 --------------- board/sixnet/fpgadata.c | 1719 ---------------------------------- board/sixnet/sixnet.c | 578 ------------ board/sixnet/sixnet.h | 20 - board/sixnet/u-boot.lds | 82 -- board/stx/stxxtc/Makefile | 8 - board/stx/stxxtc/README.stxxtc | 59 -- board/stx/stxxtc/stxxtc.c | 592 ------------ board/stx/stxxtc/u-boot.lds | 82 -- board/stx/stxxtc/u-boot.lds.debug | 121 --- board/svm_sc8xx/Makefile | 8 - board/svm_sc8xx/flash.c | 666 ------------- board/svm_sc8xx/svm_sc8xx.c | 144 --- board/svm_sc8xx/u-boot.lds | 99 -- board/svm_sc8xx/u-boot.lds.debug | 114 --- board/tqc/tqm8xx/tqm8xx.c | 57 -- boards.cfg | 22 - common/board_f.c | 3 +- doc/README.scrapyard | 31 +- drivers/i2c/soft_i2c.c | 3 - drivers/pcmcia/mpc8xx_pcmcia.c | 2 +- drivers/pcmcia/tqm8xx_pcmcia.c | 54 +- drivers/rtc/Makefile | 1 - drivers/rtc/ds1306.c | 443 --------- drivers/serial/usbtty.h | 4 +- drivers/usb/gadget/Makefile | 1 - drivers/usb/gadget/mpc8xx_udc.c | 1386 --------------------------- include/common.h | 28 +- include/commproc.h | 117 +-- include/configs/FLAGADM.h | 296 ------ include/configs/GEN860T.h | 712 -------------- include/configs/MUSENKI.h | 275 ------ include/configs/NSCU.h | 463 --------- include/configs/SXNI855T.h | 378 -------- include/configs/Sandpoint8245.h | 376 -------- include/configs/TK885D.h | 490 ---------- include/configs/TQM823M.h | 464 --------- include/configs/TQM850M.h | 454 --------- include/configs/TQM855M.h | 491 ---------- include/configs/TQM860M.h | 464 --------- include/configs/TQM862L.h | 464 --------- include/configs/TQM862M.h | 465 --------- include/configs/TQM866M.h | 483 ---------- include/configs/TQM885D.h | 482 ---------- include/configs/ep8260.h | 744 --------------- include/configs/ppmc8260.h | 986 ------------------- include/configs/sacsng.h | 1039 -------------------- include/configs/stxxtc.h | 485 ---------- include/configs/svm_sc8xx.h | 450 --------- include/configs/virtlab2.h | 469 ---------- include/pcmcia.h | 2 +- include/status_led.h | 42 - include/usb/mpc8xx_udc.h | 178 ---- include/usb/udc.h | 4 +- 96 files changed, 44 insertions(+), 26389 deletions(-) delete mode 100644 board/ep8260/Makefile delete mode 100644 board/ep8260/ep8260.c delete mode 100644 board/ep8260/ep8260.h delete mode 100644 board/ep8260/flash.c delete mode 100644 board/ep8260/mii_phy.c delete mode 100644 board/flagadm/Makefile delete mode 100644 board/flagadm/flagadm.c delete mode 100644 board/flagadm/flash.c delete mode 100644 board/flagadm/u-boot.lds delete mode 100644 board/flagadm/u-boot.lds.debug delete mode 100644 board/gen860t/Makefile delete mode 100644 board/gen860t/README delete mode 100644 board/gen860t/beeper.c delete mode 100644 board/gen860t/beeper.h delete mode 100644 board/gen860t/flash.c delete mode 100644 board/gen860t/fpga.c delete mode 100644 board/gen860t/fpga.h delete mode 100644 board/gen860t/gen860t.c delete mode 100644 board/gen860t/ioport.c delete mode 100644 board/gen860t/ioport.h delete mode 100644 board/gen860t/u-boot-flashenv.lds delete mode 100644 board/gen860t/u-boot.lds delete mode 100644 board/musenki/Makefile delete mode 100644 board/musenki/README delete mode 100644 board/musenki/flash.c delete mode 100644 board/musenki/musenki.c delete mode 100644 board/ppmc8260/Makefile delete mode 100644 board/ppmc8260/ppmc8260.c delete mode 100644 board/sacsng/Makefile delete mode 100644 board/sacsng/clkinit.c delete mode 100644 board/sacsng/clkinit.h delete mode 100644 board/sacsng/flash.c delete mode 100644 board/sacsng/ioconfig.h delete mode 100644 board/sacsng/sacsng.c delete mode 100644 board/sixnet/Makefile delete mode 100644 board/sixnet/flash.c delete mode 100644 board/sixnet/fpgadata.c delete mode 100644 board/sixnet/sixnet.c delete mode 100644 board/sixnet/sixnet.h delete mode 100644 board/sixnet/u-boot.lds delete mode 100644 board/stx/stxxtc/Makefile delete mode 100644 board/stx/stxxtc/README.stxxtc delete mode 100644 board/stx/stxxtc/stxxtc.c delete mode 100644 board/stx/stxxtc/u-boot.lds delete mode 100644 board/stx/stxxtc/u-boot.lds.debug delete mode 100644 board/svm_sc8xx/Makefile delete mode 100644 board/svm_sc8xx/flash.c delete mode 100644 board/svm_sc8xx/svm_sc8xx.c delete mode 100644 board/svm_sc8xx/u-boot.lds delete mode 100644 board/svm_sc8xx/u-boot.lds.debug delete mode 100644 drivers/rtc/ds1306.c delete mode 100644 drivers/usb/gadget/mpc8xx_udc.c delete mode 100644 include/configs/FLAGADM.h delete mode 100644 include/configs/GEN860T.h delete mode 100644 include/configs/MUSENKI.h delete mode 100644 include/configs/NSCU.h delete mode 100644 include/configs/SXNI855T.h delete mode 100644 include/configs/Sandpoint8245.h delete mode 100644 include/configs/TK885D.h delete mode 100644 include/configs/TQM823M.h delete mode 100644 include/configs/TQM850M.h delete mode 100644 include/configs/TQM855M.h delete mode 100644 include/configs/TQM860M.h delete mode 100644 include/configs/TQM862L.h delete mode 100644 include/configs/TQM862M.h delete mode 100644 include/configs/TQM866M.h delete mode 100644 include/configs/TQM885D.h delete mode 100644 include/configs/ep8260.h delete mode 100644 include/configs/ppmc8260.h delete mode 100644 include/configs/sacsng.h delete mode 100644 include/configs/stxxtc.h delete mode 100644 include/configs/svm_sc8xx.h delete mode 100644 include/configs/virtlab2.h delete mode 100644 include/usb/mpc8xx_udc.h
Remove NSCU, TK885D, TQM823M, TQM850M, TQM855M, TQM860M, TQM862L, TQM826M, TQM866M, TQM885D boards support.
These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
arch/powerpc/cpu/mpc8xx/speed.c | 3 +- arch/powerpc/lib/board.c | 3 +- board/tqc/tqm8xx/tqm8xx.c | 57 ----- boards.cfg | 11 - common/board_f.c | 3 +- drivers/i2c/soft_i2c.c | 3 - drivers/pcmcia/mpc8xx_pcmcia.c | 2 +- drivers/pcmcia/tqm8xx_pcmcia.c | 48 +--- include/common.h | 25 +- include/commproc.h | 14 +- include/configs/NSCU.h | 463 ------------------------------------- include/configs/TK885D.h | 490 --------------------------------------- include/configs/TQM823M.h | 464 ------------------------------------- include/configs/TQM850M.h | 454 ------------------------------------- include/configs/TQM855M.h | 491 ---------------------------------------- include/configs/TQM860M.h | 464 ------------------------------------- include/configs/TQM862L.h | 464 ------------------------------------- include/configs/TQM862M.h | 465 ------------------------------------- include/configs/TQM866M.h | 483 --------------------------------------- include/configs/TQM885D.h | 482 --------------------------------------- include/configs/virtlab2.h | 469 -------------------------------------- 21 files changed, 16 insertions(+), 5342 deletions(-) delete mode 100644 include/configs/NSCU.h delete mode 100644 include/configs/TK885D.h delete mode 100644 include/configs/TQM823M.h delete mode 100644 include/configs/TQM850M.h delete mode 100644 include/configs/TQM855M.h delete mode 100644 include/configs/TQM860M.h delete mode 100644 include/configs/TQM862L.h delete mode 100644 include/configs/TQM862M.h delete mode 100644 include/configs/TQM866M.h delete mode 100644 include/configs/TQM885D.h delete mode 100644 include/configs/virtlab2.h
diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c index 42442b8..513ad7b 100644 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ b/arch/powerpc/cpu/mpc8xx/speed.c @@ -370,8 +370,7 @@ static long init_pll_866 (long clk)
#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ - && !defined(CONFIG_TQM885D) +#if defined(CONFIG_TQM8xxL) /* * Adjust sdram refresh rate to actual CPU clock * and set timebase source according to actual CPU clock diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 300ab12..c973fc2 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -251,8 +251,7 @@ static init_fnc_t *init_sequence[] = { #endif #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) get_clocks, /* get CPU and bus clocks (etc.) */ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ - && !defined(CONFIG_TQM885D) +#if defined(CONFIG_TQM8xxL) adjust_sdram_tbs_8xx, #endif init_timebase, diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 9ce2a57..aec61f8 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -118,9 +118,6 @@ int checkboard (void) break; putc (buf[i]); } -#ifdef CONFIG_VIRTLAB2 - puts (" (Virtlab2)"); -#endif putc ('\n');
return (0); @@ -512,14 +509,6 @@ int misc_init_r (void) immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */ # endif
-#ifdef CONFIG_NSCU - /* wake up ethernet module */ - immap->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ - immap->im_ioport.iop_pcdir |= 0x0004; /* output */ - immap->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ - immap->im_ioport.iop_pcdat |= 0x0004; /* enable */ -#endif /* CONFIG_NSCU */ - return (0); } #endif /* CONFIG_MISC_INIT_R */ @@ -680,49 +669,3 @@ void ft_board_setup(void *blob, bd_t *bd) ft_blob_update(blob, bd); } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ - -/* ---------------------------------------------------------------------------- */ -/* TK885D specific initializaion */ -/* ---------------------------------------------------------------------------- */ -#ifdef CONFIG_TK885D -#include <miiphy.h> -int last_stage_init(void) -{ - const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY}; - unsigned short reg; - int ret, i = 100; - char *s; - - mii_init(); - /* Without this delay 0xff is read from the UART buffer later in - * abortboot() and autoboot is aborted */ - udelay(10000); - while (tstc() && i--) - (void)getc(); - - /* Check if auto-negotiation is prohibited */ - s = getenv("phy_auto_nego"); - - if (!s || !strcmp(s, "on")) - /* Nothing to do - autonegotiation by default */ - return 0; - - for (i = 0; i < 2; i++) { - ret = miiphy_read("FEC", phy[i], MII_BMCR, ®); - if (ret) { - printf("Cannot read BMCR on PHY %d\n", phy[i]); - return 0; - } - /* Auto-negotiation off, hard set full duplex, 100Mbps */ - ret = miiphy_write("FEC", phy[i], - MII_BMCR, (reg | BMCR_SPEED100 | - BMCR_FULLDPLX) & ~BMCR_ANENABLE); - if (ret) { - printf("Cannot write BMCR on PHY %d\n", phy[i]); - return 0; - } - } - - return 0; -} -#endif diff --git a/boards.cfg b/boards.cfg index 1ba2081..1b4feb8 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1002,24 +1002,13 @@ Active powerpc mpc8xx - LEOX elpt860 Active powerpc mpc8xx - manroland uc100 uc100 - Stefan Roese sr@denx.de Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk wd@denx.de Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk wd@denx.de -Active powerpc mpc8xx - tqc tqm8xx NSCU - - Active powerpc mpc8xx - tqc tqm8xx SM850 - Wolfgang Denk wd@denx.de -Active powerpc mpc8xx - tqc tqm8xx TK885D - - Active powerpc mpc8xx - tqc tqm8xx TQM823L - Wolfgang Denk wd@denx.de Active powerpc mpc8xx - tqc tqm8xx TQM823L_LCD TQM823L:LCD,NEC_NL6448BC20 Wolfgang Denk wd@denx.de -Active powerpc mpc8xx - tqc tqm8xx TQM823M - - Active powerpc mpc8xx - tqc tqm8xx TQM850L - Wolfgang Denk wd@denx.de -Active powerpc mpc8xx - tqc tqm8xx TQM850M - - Active powerpc mpc8xx - tqc tqm8xx TQM855L - Wolfgang Denk wd@denx.de -Active powerpc mpc8xx - tqc tqm8xx TQM855M - - Active powerpc mpc8xx - tqc tqm8xx TQM860L - Wolfgang Denk wd@denx.de -Active powerpc mpc8xx - tqc tqm8xx TQM860M - - -Active powerpc mpc8xx - tqc tqm8xx TQM862L - - -Active powerpc mpc8xx - tqc tqm8xx TQM862M - - -Active powerpc mpc8xx - tqc tqm8xx TQM866M - - -Active powerpc mpc8xx - tqc tqm8xx TQM885D - - Active powerpc mpc8xx - tqc tqm8xx TTTech TQM823L:LCD,SHARP_LQ104V7DS01 Wolfgang Denk wd@denx.de -Active powerpc mpc8xx - tqc tqm8xx virtlab2 - - Active powerpc mpc8xx - tqc tqm8xx wtk TQM823L:LCD,SHARP_LQ065T9DR51U Wolfgang Denk wd@denx.de Active powerpc ppc4xx - - csb272 csb272 - Tolunay Orkun torkun@nextio.com Active powerpc ppc4xx - - csb472 csb472 - Tolunay Orkun torkun@nextio.com diff --git a/common/board_f.c b/common/board_f.c index bdab38e..c14fa91 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -795,8 +795,7 @@ static init_fnc_t init_sequence_f[] = { /* TODO: can any of this go into arch_cpu_init()? */ #if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT) get_clocks, /* get CPU and bus clocks (etc.) */ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ - && !defined(CONFIG_TQM885D) +#if defined(CONFIG_TQM8xxL) adjust_sdram_tbs_8xx, #endif /* TODO: can we rename this to timer_init()? */ diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index db9b402..5ebccc2 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -29,9 +29,6 @@ #include <asm/arch/gpio.h> #endif #endif -#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866) -#include <asm/io.h> -#endif #include <i2c.h>
#if defined(CONFIG_SOFT_I2C_GPIO_SCL) diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c index af77426..ea88494 100644 --- a/drivers/pcmcia/mpc8xx_pcmcia.c +++ b/drivers/pcmcia/mpc8xx_pcmcia.c @@ -58,7 +58,7 @@ static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
/* -------------------------------------------------------------------- */
-#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU) +#if defined(CONFIG_LWMON) #define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(9) \ | PCMCIA_SST(3) \ | PCMCIA_SL(12)) diff --git a/drivers/pcmcia/tqm8xx_pcmcia.c b/drivers/pcmcia/tqm8xx_pcmcia.c index dda7d37..2f69c1b 100644 --- a/drivers/pcmcia/tqm8xx_pcmcia.c +++ b/drivers/pcmcia/tqm8xx_pcmcia.c @@ -22,53 +22,12 @@ #if defined(CONFIG_PCMCIA) \ && (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx))
-#if defined(CONFIG_VIRTLAB2) -#define PCMCIA_BOARD_MSG "Virtlab2" -#elif defined(CONFIG_TQM8xxL) +#if defined(CONFIG_TQM8xxL) #define PCMCIA_BOARD_MSG "TQM8xxL" #elif defined(CONFIG_SVM_SC8xx) #define PCMCIA_BOARD_MSG "SC8xx" #endif
-#if defined(CONFIG_NSCU) - -static inline void power_config(int slot) {} -static inline void power_off(int slot) {} -static inline void power_on_5_0(int slot) {} -static inline void power_on_3_3(int slot) {} - -#elif defined(CONFIG_VIRTLAB2) - -static inline void power_config(int slot) {} - -static inline void power_off(int slot) -{ - volatile unsigned __iomem *addr; - addr = (volatile unsigned __iomem *)PCMCIA_CTRL; - - out_be32(addr, 0); -} - -static inline void power_on_5_0(int slot) -{ - volatile unsigned __iomem *addr; - addr = (volatile unsigned __iomem *)PCMCIA_CTRL; - - /* Enable 5V Vccout */ - out_be32(addr, 2); -} - -static inline void power_on_3_3(int slot) -{ - volatile unsigned __iomem *addr; - addr = (volatile unsigned __iomem *)PCMCIA_CTRL; - - /* Enable 3.3V Vccout */ - out_be32(addr, 1); -} - -#else - static inline void power_config(int slot) { immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; @@ -100,8 +59,6 @@ static inline void power_on_3_3(int slot) setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004); }
-#endif - /* * Function to retrieve the PIPR register, used for debuging purposes. */ @@ -245,7 +202,6 @@ int pcmcia_hardware_disable(int slot)
int pcmcia_voltage_set(int slot, int vcc, int vpp) { -#ifndef CONFIG_NSCU u_long reg; uint32_t pipr = 0;
@@ -298,7 +254,7 @@ done: udelay(500);
debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A'); -#endif /* CONFIG_NSCU */ + return 0; }
diff --git a/include/common.h b/include/common.h index 82c0a5a..e272ef7 100644 --- a/include/common.h +++ b/include/common.h @@ -28,14 +28,10 @@ typedef volatile unsigned char vu_char; #endif #if defined(CONFIG_8xx) #include <asm/8xx_immap.h> -#if defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \ - defined(CONFIG_MPC866) || \ +#if defined(CONFIG_MPC859T) || \ defined(CONFIG_MPC866P) # define CONFIG_MPC866_FAMILY 1 -#elif defined(CONFIG_MPC870) \ - || defined(CONFIG_MPC875) \ - || defined(CONFIG_MPC880) \ - || defined(CONFIG_MPC885) +#elif defined(CONFIG_MPC875) # define CONFIG_MPC885_FAMILY 1 #endif #if defined(CONFIG_MPC860) \ @@ -150,22 +146,11 @@ typedef void (interrupt_handler_t)(void *); #include <asm/global_data.h> /* global data used for startup functions */
/* - * enable common handling for all TQM8xxL/M boards: - * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards - * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards - * and for the TQM885D board + * enable common handling for all TQM8xxL boards: + * - CONFIG_TQM8xxL will be defined for all TQM8xxL boards */ -#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \ - defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) -# ifndef CONFIG_TQM8xxM -# define CONFIG_TQM8xxM -# endif -#endif #if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \ - defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \ - defined(CONFIG_TQM885D) + defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) # ifndef CONFIG_TQM8xxL # define CONFIG_TQM8xxL # endif diff --git a/include/commproc.h b/include/commproc.h index 52ac4ca..c5610bc 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -931,18 +931,15 @@ typedef struct scc_enet { #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ defined(CONFIG_R360MPI) || \ defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \ - defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ - defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \ - defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2) + defined(CONFIG_TQM850L) || \ + defined(CONFIG_RRVISION)
/* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC2 use. */ #define PROFF_ENET PROFF_SCC2 #define CPM_CR_ENET CPM_CR_CH_SCC2 -#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */ #define SCC_ENET 1 -#endif #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ @@ -970,10 +967,9 @@ typedef struct scc_enet {
/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
-#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ - defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ - defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) +#if defined(CONFIG_TQM855L) || \ + defined(CONFIG_TQM860L) || \ + defined(CONFIG_TQM866L)
# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h deleted file mode 100644 index a9c649a..0000000 --- a/include/configs/NSCU.h +++ /dev/null @@ -1,463 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ -#define CONFIG_NSCU 1 - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=NSCU\0" \ - "bootfile=${hostname}/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "u-boot=${hostname}/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history -*/ -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -/* NSCU use both slots, SLOT_A as "primary". */ -#define CONFIG_PCMCIA_SLOT_A 1 - -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) -#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ -#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ -#undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE buses */ -#define CONFIG_SYS_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) /* starts @ 4th window */ - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -#ifdef CONFIG_ISP1362_USB -#define CONFIG_SYS_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */ -#define CONFIG_SYS_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR5_ISP1362 (CONFIG_SYS_ISP1362_OR_AM | OR_CSNT_SAM | \ - OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK) -#define CONFIG_SYS_BR5_ISP1362 ((CONFIG_SYS_ISP1362_BASE & BR_BA_MSK) | \ - BR_PS_16 | BR_MS_GPCM | BR_V ) -#endif /* CONFIG_ISP1362_USB */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#undef CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h deleted file mode 100644 index 5e1c52d..0000000 --- a/include/configs/TK885D.h +++ /dev/null @@ -1,490 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2006 - * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ -#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ -#define CONFIG_TK885D 1 /* ...in a TK885D base board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ethprime=FEC\0" \ - "ethact=FEC\0" \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/tk885d/uImage\0" \ - "u-boot=/tftpboot/tk885d/u-boot.bin\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 40000000 +${filesize};" \ - "erase 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "protect on 40000000 +${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -# define CONFIG_RTC_DS1337 1 -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ -#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive - memory test.*/ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_6_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) - * - * CPUclock(MHz) * 31.2 - * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 - * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 - * - * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us - * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us - * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us - * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us - * - * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will - * be met also in the default configuration, i.e. if environment variable - * 'cpuclk' is not set. - */ -#define CONFIG_SYS_MAMR_PTA 128 - -/* - * Memory Periodic Timer Prescaler Register (MPTPR) values. - */ -/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 -/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Network configuration - */ -#define CONFIG_FEC_ENET /* enable ethernet on FEC */ -#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ -#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ - -#define CONFIG_LAST_STAGE_INIT 1 /* Have to configure PHYs for Linux */ - -/* CONFIG_SYS_DISCOVER_PHY only works with FEC if only one interface is enabled */ -#if (!defined(CONFIG_ETHER_ON_FEC1) || !defined(CONFIG_ETHER_ON_FEC2)) -#define CONFIG_SYS_DISCOVER_PHY -#endif - -#ifndef CONFIG_SYS_DISCOVER_PHY -/* PHY addresses - hard wired in hardware */ -#define CONFIG_FEC1_PHY 1 -#define CONFIG_FEC2_PHY 2 -#endif - -#define CONFIG_MII_INIT 1 - -#define CONFIG_NET_RETRY_COUNT 3 -#define CONFIG_ETHPRIME "FEC" - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h deleted file mode 100644 index 4fd070f..0000000 --- a/include/configs/TQM823M.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_MPC8XX_LCD -/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM823M\0" \ - "bootfile=TQM823M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM823M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_LCD -# undef CONFIG_STATUS_LED /* disturbs display */ -#else -# define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#endif /* CONFIG_LCD */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h deleted file mode 100644 index 659c9ad..0000000 --- a/include/configs/TQM850M.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM850M\0" \ - "bootfile=TQM850M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM850M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h deleted file mode 100644 index 44d456e..0000000 --- a/include/configs/TQM855M.h +++ /dev/null @@ -1,491 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM855M\0" \ - "bootfile=TQM855M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM855M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#if 0 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h deleted file mode 100644 index 8109379..0000000 --- a/include/configs/TQM860M.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM860M\0" \ - "bootfile=TQM860M/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM860M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h deleted file mode 100644 index da4af93..0000000 --- a/include/configs/TQM862L.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM862L\0" \ - "bootfile=TQM862L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM862L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h deleted file mode 100644 index ec3a57b..0000000 --- a/include/configs/TQM862M.h +++ /dev/null @@ -1,465 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM862M\0" \ - "bootfile=TQM862M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM862M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h deleted file mode 100644 index cb8b84d..0000000 --- a/include/configs/TQM866M.h +++ /dev/null @@ -1,483 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC866 1 /* This is a MPC866 CPU */ -#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */ - /* (function measure_gclk() */ - /* will be called) */ -#ifdef CONFIG_SYS_MEASURE_CPUCLK -#define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM866M\0" \ - "bootfile=TQM866M/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM866M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE - -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_15_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) - * - * CPUclock(MHz) * 31.2 - * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 - * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 - * - * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us - * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us - * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us - * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us - * - * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will - * be met also in the default configuration, i.e. if environment variable - * 'cpuclk' is not set. - */ -#define CONFIG_SYS_MAMR_PTA 97 - -/* - * Memory Periodic Timer Prescaler Register (MPTPR) values. - */ -/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 -/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h deleted file mode 100644 index d1e6c5b..0000000 --- a/include/configs/TQM885D.h +++ /dev/null @@ -1,482 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2006 - * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ -#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM885D/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 40000000 +${filesize};" \ - "erase 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "protect on 40000000 +${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -# define CONFIG_RTC_DS1337 1 -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ -#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive - memory test.*/ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_6_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) - * - * CPUclock(MHz) * 31.2 - * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 - * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 - * - * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us - * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us - * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us - * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us - * - * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will - * be met also in the default configuration, i.e. if environment variable - * 'cpuclk' is not set. - */ -#define CONFIG_SYS_MAMR_PTA 128 - -/* - * Memory Periodic Timer Prescaler Register (MPTPR) values. - */ -/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 -/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Network configuration - */ -#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ -#define CONFIG_FEC_ENET /* enable ethernet on FEC */ -#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ -#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ - -#if defined(CONFIG_CMD_MII) -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII_INIT 1 -#endif - -#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before - switching to another netwok (if the - tried network is unreachable) */ - -#define CONFIG_ETHPRIME "SCC" - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h deleted file mode 100644 index 0457cdf..0000000 --- a/include/configs/virtlab2.h +++ /dev/null @@ -1,469 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */ -#define CONFIG_TQM8xxL 1 - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=virtlab2\0" \ - "bootfile=virtlab2/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=virtlab2/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if defined(CONFIG_LCD) -# undef CONFIG_STATUS_LED /* disturbs display */ -#else -# define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#endif /* CONFIG_LCD */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#if defined(CONFIG_SPLASH_SCREEN) - #define CONFIG_CMD_BMP -#endif - - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* Map peripheral control registers on CS4 */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xA0000000 -#define CONFIG_SYS_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK) -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define PCMCIA_CTRL (CONFIG_SYS_PERIPHERAL_BASE + 0xB00) - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */
Dear Masahiro Yamada,
In message 1406014114-8016-2-git-send-email-yamada.m@jp.panasonic.com you wrote:
Remove NSCU, TK885D, TQM823M, TQM850M, TQM855M, TQM860M, TQM862L, TQM826M, TQM866M, TQM885D boards support.
These boards are old enough and have no maintainers.
NAK for all the TQM boards.
What makes you think these have no maintainer? They are on my list.
Best regards,
Wolfgang Denk
Hi Wolfgang,
On Tue, 22 Jul 2014 11:27:16 +0200 Wolfgang Denk wd@denx.de wrote:
Dear Masahiro Yamada,
In message 1406014114-8016-2-git-send-email-yamada.m@jp.panasonic.com you wrote:
Remove NSCU, TK885D, TQM823M, TQM850M, TQM855M, TQM860M, TQM862L, TQM826M, TQM866M, TQM885D boards support.
These boards are old enough and have no maintainers.
NAK for all the TQM boards.
What makes you think these have no maintainer? They are on my list.
Because the maintainers fields (the rightest fields) of boards.cfg for these boards are blank.
I do not mind retracting this patch, but let me ask you a question.
It is true, for example, your name is on the maintainers field of TQM823L, but is isn't for TQM823M.
If the maintainers fields are blank and you still claim you are their maintainer, what does "the maintainers field" stand for ?
Best Regards Masahiro Yamada
Dear Masahiro,
In message 20140722184445.EF22.AA925319@jp.panasonic.com you wrote:
Because the maintainers fields (the rightest fields) of boards.cfg for these boards are blank.
I don't know why this is the case; it is wrong.
If the maintainers fields are blank and you still claim you are their maintainer, what does "the maintainers field" stand for ?
You ask the wrong question :-) The question is why I'm not listed as maintainer of these boards.
Best regards,
Wolfgang Denk
On Tue, 22 Jul 2014 14:16:43 +0200 Wolfgang Denk wd@denx.de wrote:
Dear Masahiro,
In message 20140722184445.EF22.AA925319@jp.panasonic.com you wrote:
Because the maintainers fields (the rightest fields) of boards.cfg for these boards are blank.
I don't know why this is the case; it is wrong.
If the maintainers fields are blank and you still claim you are their maintainer, what does "the maintainers field" stand for ?
You ask the wrong question :-) The question is why I'm not listed as maintainer of these boards.
OK.
Thanks for your patch: http://patchwork.ozlabs.org/patch/372452/
Anyway I decided to postpone this series.
Changed 1/10 to Rejected, 2/10 thru 10/10 to RFC.
Best Regards Masahiro Yamada
This board has been orphaned for a while and old enough.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
board/ppmc8260/Makefile | 8 - board/ppmc8260/ppmc8260.c | 291 ------------- boards.cfg | 1 - doc/README.scrapyard | 23 +- include/configs/ppmc8260.h | 986 --------------------------------------------- 5 files changed, 12 insertions(+), 1297 deletions(-) delete mode 100644 board/ppmc8260/Makefile delete mode 100644 board/ppmc8260/ppmc8260.c delete mode 100644 include/configs/ppmc8260.h
diff --git a/board/ppmc8260/Makefile b/board/ppmc8260/Makefile deleted file mode 100644 index 3072fb4..0000000 --- a/board/ppmc8260/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ppmc8260.o diff --git a/board/ppmc8260/ppmc8260.c b/board/ppmc8260/ppmc8260.c deleted file mode 100644 index f0f29b2..0000000 --- a/board/ppmc8260/ppmc8260.c +++ /dev/null @@ -1,291 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2001 - * Advent Networks, Inc. http://www.adventnetworks.com - * Jay Monkman jtm@smoothsmoothie.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_A1:L1TSYNC */ - /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* TDN_A1:L1RSYNC */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_A1:L1CLK0 */ - /* PB15 */ { 1, 0, 0, 1, 0, 1 }, /* /FETHRST */ - /* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* FETHDIS */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_B1:L1CLK0 */ - /* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TXD */ - /* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RXD */ - /* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TSYNC */ - /* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RSYNC */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* CLK4 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* CLK7 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[0] */ - /* PC14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[0] */ - /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[1] */ - /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[1] */ - /* PC11 */ { 1, 1, 0, 1, 0, 0 }, /* TDM_D1:L1CLK0 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[2]*/ - /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[2] */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DACK */ - /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DONE */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DREQ */ - /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DREQ */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */ - /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ - /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[3] */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_C1:L1RSYNC */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TXD */ - /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RXD */ - /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TSYNC */ - /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RSYNC*/ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1:TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:RXD */ - /* PD7 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:SMSYN */ - /* PD6 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DACK */ - /* PD5 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DONE */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: Wind River PPMC8260\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0xff; - volatile uchar *ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE); - volatile uchar *ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE); - ulong psdmr = CONFIG_SYS_PSDMR; - volatile uchar *ramaddr2 = (uchar *) (CONFIG_SYS_SDRAM2_BASE); - ulong lsdmr = CONFIG_SYS_LSDMR; - int i; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr0++ = c; - *ramaddr1++ = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - *ramaddr0++ = c; - *ramaddr1++ = c; - } - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE + 0x110); - ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE + 0x110); - *ramaddr0 = c; - *ramaddr1 = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr0 = c; - *ramaddr1 = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA; - *ramaddr2++ = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - *ramaddr2++ = c; - } - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW; - *ramaddr2++ = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr2 = c; -#endif - - /* return total ram size */ - return ((CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE) * 1024 * 1024); -} - -#ifdef CONFIG_MISC_INIT_R -/* ------------------------------------------------------------------------- */ -int misc_init_r (void) -{ -#ifdef CONFIG_SYS_LED_BASE - uchar ds = *(unsigned char *) (CONFIG_SYS_LED_BASE + 1); - uchar ss; - uchar tmp[64]; - int res; - - if ((ds != 0) && (ds != 0xff)) { - res = getenv_f("ethaddr", (char *)tmp, sizeof (tmp)); - if (res > 0) { - ss = ((ds >> 4) & 0x0f); - ss += ss < 0x0a ? '0' : ('a' - 10); - tmp[15] = ss; - - ss = (ds & 0x0f); - ss += ss < 0x0a ? '0' : ('a' - 10); - tmp[16] = ss; - - tmp[17] = '\0'; - setenv ("ethaddr", (char *)tmp); - /* set the led to show the address */ - *((unsigned char *) (CONFIG_SYS_LED_BASE + 1)) = ds; - } - } -#endif /* CONFIG_SYS_LED_BASE */ - return (0); -} -#endif /* CONFIG_MISC_INIT_R */ diff --git a/boards.cfg b/boards.cfg index 1b4feb8..f08ea01 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1184,7 +1184,6 @@ Orphan powerpc mpc8xx - stx stxxtc Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu nyet@zumanetworks.com Orphan powerpc mpc824x - - musenki MUSENKI - Jim Thompson jim@musenki.com Orphan powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson jim@musenki.com -Orphan powerpc mpc8260 - - ppmc8260 ppmc8260 - Brad Kemp Brad.Kemp@seranoa.com # The following were moved to "Orphan" in March, 2014 Orphan blackfin - - - cm-bf527 cm-bf527 - Bluetechnix Tinyboards bluetechnix@blackfin.uclinux.org Orphan blackfin - - - cm-bf533 cm-bf533 - Bluetechnix Tinyboards bluetechnix@blackfin.uclinux.org diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 6a1d2a5..36dc403 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,17 +11,18 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -spc1920 powerpc mpc8xx - - -v37 powerpc mpc8xx - - -fads powerpc mpc8xx - - -netphone powerpc mpc8xx - - -netta2 powerpc mpc8xx - - -netta powerpc mpc8xx - - -rbc823 powerpc mpc8xx - - -quantum powerpc mpc8xx - - -RPXlite_dw powerpc mpc8xx - - -qs850 powerpc mpc8xx - - -qs860t powerpc mpc8xx - - +ppmc8260 powerpc mpc8260 - - Brad Kemp Brad.Kemp@seranoa.com +spc1920 powerpc mpc8xx 98ad54be 2014-07-07 +v37 powerpc mpc8xx b8c1438a 2014-07-07 +fads powerpc mpc8xx 03f9d7d1 2014-07-07 +netphone powerpc mpc8xx c51c1c9a 2014-07-07 +netta2 powerpc mpc8xx c51c1c9a 2014-07-07 +netta powerpc mpc8xx c51c1c9a 2014-07-07 +rbc823 powerpc mpc8xx c750b9c0 2014-07-07 +quantum powerpc mpc8xx 0657e46e 2014-07-07 +RPXlite_dw powerpc mpc8xx 0657e46e 2014-07-07 +qs850 powerpc mpc8xx dab0f762 2014-07-07 +qs860t powerpc mpc8xx dab0f762 2014-07-07 simpc8313 powerpc mpc83xx 7445207f 2014-06-05 Ron Madrid info@sheldoninst.com hidden_dragon powerpc mpc824x 3fe1a854 2014-05-30 Yusdi Santoso yusdi_santoso@adaptec.com debris powerpc mpc824x 7edb1f7b 2014-05-30 Sangmoon Kim dogoil@etinsys.com diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h deleted file mode 100644 index 5dcd9cc..0000000 --- a/include/configs/ppmc8260.h +++ /dev/null @@ -1,986 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen Murray.Jensen@cmst.csiro.au - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2001 - * Advent Networks, Inc. http://www.adventnetworks.com - * Jay Monkman jtm@smoothsmoothie.com - * - * Configuation settings for the WindRiver PPMC8260 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0xfe000000 - -/***************************************************************************** - * - * These settings must match the way _your_ board is set up - * - *****************************************************************************/ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 - * ------- ---------- --- --- ---- ----- ----- ----- - * 0x2 0x2 33 133 133 Close Open Close - * 0x2 0x3 33 133 166 Close Open Open - * 0x2 0x4 33 133 200 Open Close Close - * 0x2 0x5 33 133 233 Open Close Open - * 0x2 0x6 33 133 266 Open Open Close - * - * 0x5 0x5 66 133 133 Open Close Open - * 0x5 0x6 66 133 166 Open Open Close - * 0x5 0x7 66 133 200 Open Open Open - * 0x6 0x0 66 133 233 Close Close Close - * 0x6 0x1 66 133 266 Close Close Open - * 0x6 0x2 66 133 300 Close Open Close - */ -#define CONFIG_SYS_PPMC_MODCK_H 0x05 - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CONFIG_SYS_PPMC_BOOT_LOW 1 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ppmc8260/config.mk - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#define CONFIG_SYS_FLASH0_BASE 0xFE000000 -#define CONFIG_SYS_FLASH0_SIZE 16 - -/* What should be the base address of the first SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM0_BASE 0x00000000 -#define CONFIG_SYS_SDRAM0_SIZE 128 - -/* What should be the base address of the second SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM1_BASE 0x08000000 -#define CONFIG_SYS_SDRAM1_SIZE 128 - -/* What should be the base address of the on board SDRAM and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM2_BASE 0x38000000 -#define CONFIG_SYS_SDRAM2_SIZE 16 - -/* What should be the base address of the MAILBOX and how big is it - * (in Bytes) - * The eeprom lives at CONFIG_SYS_MAILBOX_BASE + 0x80000000 - */ -#define CONFIG_SYS_MAILBOX_BASE 0x32000000 -#define CONFIG_SYS_MAILBOX_SIZE 8192 - -/* What is the base address of the I/O select lines and how big is it - * (In Mbytes)? - */ - -#define CONFIG_SYS_IOSELECT_BASE 0xE0000000 -#define CONFIG_SYS_IOSELECT_SIZE 32 - - -/* What should be the base address of the LEDs and switch S0? - * If you don't want them enabled, don't define this. - */ -#define CONFIG_SYS_LED_BASE 0xF1000000 - -/* - * PPMC8260 with 256 16 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x0FF5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x0FF5 FFB0 Board Info Data - * 0x0FF6 0000 Malloc Arena - * : CONFIG_ENV_SECT_SIZE, 256k - * : CONFIG_SYS_MALLOC_LEN, 128k - * 0x0FFC 0000 RAM Copy of Monitor Code - * : CONFIG_SYS_MONITOR_LEN, 256k - * 0x0FFF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 - */ - - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - * The console can be on SMC1 or SMC2 - */ -#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ - -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CONFIG_ENV_IN_OWN_SECT 1 - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 9600 - -/* Ethernet MAC address */ - -#define CONFIG_ETHADDR 00:a0:1e:90:2b:00 - -/* Define this to set the last octet of the ethernet address - * from the DS0-DS7 switch and light the leds with the result - * The DS0-DS7 switch and the leds are backwards with respect - * to each other. DS7 is on the board edge side of both the - * led strip and the DS0-DS7 switch. - */ -#define CONFIG_MISC_INIT_R - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#if 0 -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -# define CONFIG_AUTOBOOT_KEYED -# define CONFIG_AUTOBOOT_PROMPT \ - "Autobooting in %d seconds, press " " to stop\n", bootdelay -# define CONFIG_AUTOBOOT_STOP_STR " " -# undef CONFIG_AUTOBOOT_DELAY_STR -# define DEBUG_BOOTKEYS 0 -#endif - -/* Define a command string that is automatically executed when no character - * is read on the console interface withing "Boot Delay" after reset. - */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ - -#ifdef CONFIG_BOOT_ROOT_INITRD -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_INITRD */ - -#ifdef CONFIG_BOOT_ROOT_NFS -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_NFS */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS - - -/* undef this to save memory */ -#define CONFIG_SYS_LONGHELP - -/* Monitor Command Prompt */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ELF -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_MEMTEST -#define CONFIG_CMD_MII -#define CONFIG_CMD_IMMAP - -#undef CONFIG_CMD_KGDB - - -/* Where do the internal registers live? */ -#define CONFIG_SYS_IMMR 0xf0000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* - * Miscellaneous configurable options - */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x140000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ - + CONFIG_SYS_MALLOC_LEN \ - + CONFIG_ENV_SECT_SIZE \ - + CONFIG_SYS_STACK_USAGE ) - -#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ - - CONFIG_SYS_MEM_END_USAGE ) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) -/* - * Attention: This is board specific - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\ - CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) -/* - * Attention: this is board-specific - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE -#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE) - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CONFIG_SYS_PPMC_BOOT_LOW) -# define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CONFIG_SYS_PPMC_BOOT_LOW) */ - -/* get the HRCW ISB field from CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PPMC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ - ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ - ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER ( HRCW_EBM | \ - HRCW_BPS11 | \ - HRCW_L2CPC10 | \ - HRCW_DPPC00 | \ - CONFIG_SYS_PPMC_HRCW_IMMR | \ - HRCW_MMR00 | \ - HRCW_LBPC00 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - (CONFIG_SYS_PPMC_MODCK_H & HRCW_MODCK_H1111) | \ - CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS ) - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE 0x0ff80000 -#endif - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - - -#ifndef CONFIG_SYS_RAMBOOT - -# define CONFIG_ENV_IS_IN_FLASH 1 -# ifdef CONFIG_ENV_IN_OWN_SECT -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -# define CONFIG_ENV_SECT_SIZE 0x40000 -# else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ -# endif /* CONFIG_ENV_IN_OWN_SECT */ - -#else -# define CONFIG_ENV_IS_IN_FLASH 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x1000 -# define CONFIG_ENV_SECT_SIZE 0x40000 -#endif /* CONFIG_SYS_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_EBM |\ - 0x30000000) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - * Ref Section 4.3.2.6 page 4-31 - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_SIUMCR (SIUMCR_ESE |\ - SIUMCR_DPPC00 |\ - SIUMCR_L2CPC10 |\ - SIUMCR_LBPC00 |\ - SIUMCR_APPC10 |\ - SIUMCR_CS10PC00 |\ - SIUMCR_BCTLC00 |\ - SIUMCR_MMR00) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Initialize Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) * - * 1 unused - * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB) - * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB) - * 4 Local SDRAM 32 bit SDRAM (on board - 16MB) - * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB) - * 6 60x GPCM 8 bit FLASH (on board - 2MB) * - * 7 60x GPCM 8 bit LEDs, switches - * - * (*) This configuration requires the PPMC8260 be configured - * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to - * the on board FLASH. In other words, JP24 should have - * pins 1 and 2 jumpered and pins 3 and 4 jumpered. - * - */ - -/*----------------------------------------------------------------------- - * BR0,BR1 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR0,OR1 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0,1 - FLASH SIMM - * - * This expects the FLASH SIMM to be connected to *CS0 - * It consists of 4 AM29F080B parts. - * - * Note: For the 4 MB SIMM, *CS1 is unused. - */ - -/* BR0 is configured as follows: - * - * - Base address of 0xFE000000 - * - 32 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR0 is configured as follows: - * - * - 32 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR2,BR3 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2,OR3 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* - * Bank 2,3 - 128 MB SDRAM DIMM - */ - -/* With a 128 MB DIMM, the BR2 is configured as follows: - * - * - Base address of 0x00000000/0x08000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 128 MB DIMM, the OR2 is configured as follows: - * - * - 128 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 13 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ - -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ - -/* With a 128 MB DIMM, the PSDMR is configured as follows: - * - * - Page Based Interleaving, - * - Refresh Enable, - * - Normal Operation - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A13-A15 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - External Address Multiplexing enabled - * - CAS Latency is 2. - */ -#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - - -#define CONFIG_SYS_PSRT 0x0e -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 - - -/*----------------------------------------------------------------------- - * BR4 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR4 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* - * Bank 4 - On board SDRAM - * - */ -/* With 16 MB of onboard SDRAM BR4 is configured as follows - * - * - Base address 0x38000000 - * - 32 bit port size - * - Data error checking disabled - * - Read/Write access - * - SDRAM local bus - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - * - */ - -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_SDRAM2_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_DECC_NONE |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -/* - * With 16MB SDRAM, OR4 is configured as follows - * - 4 internal banks per device - * - Row start address bit is A10 with LSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ - -#define CONFIG_SYS_OR4_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM2_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A10 |\ - ORxS_NUMR_12) - - -/*----------------------------------------------------------------------- - * LSDMR - Local Bus SDRAM Mode Register - * Ref: Section 10.3.4 on page 10-24 - *----------------------------------------------------------------------- - */ - -/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows: - * - * - Page Based Interleaving, - * - Refresh Enable, - * - Normal Operation - * - Address Multiplexing where A5 is output on A13 pin - * (A6 on A15, and so on), - * - use address pins A15-A17 as bank select, - * - A11 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 2 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - SDRAM burst length is 8 - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - External Address Multiplexing disabled - * - CAS Latency is 2. - */ -#define CONFIG_SYS_LSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI0_A11 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -#define CONFIG_SYS_LSRT 0x0e - -/*----------------------------------------------------------------------- - * BR5 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR5 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* - * Bank 5 EEProm and Mailbox - * - * The EEPROM and mailbox live on the same chip select. - * the eeprom is selected if the MSb of the address is set and the mailbox is - * selected if the MSb of the address is clear. - * - */ - -/* BR5 is configured as follows: - * - * - Base address of 0x32000000/0xF2000000 - * - 8 bit - * - Data error checking disabled - * - Read/Write access - * - GPCM 60x Bus - * - SDRAM local bus - * - No data pipelining is done - * - Valid - */ - -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_MAILBOX_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) -/* OR5 is configured as follows - * - buffer control enabled - * - chip select negated normally - * - CS output 1/2 clock after address - * - 15 wait states - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ - -#define CONFIG_SYS_OR5_PRELIM ((P2SZ_TO_AM(CONFIG_SYS_MAILBOX_SIZE) & ~0x80000000) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_15_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR6 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR6 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 6 - I/O select - * - */ - -/* BR6 is configured as follows: - * - * - Base address of 0xE0000000 - * - 16 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_IOSELECT_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR6 is configured as follows - * - buffer control enabled - * - chip select negated normally - * - CS output 1/2 clock after address - * - 15 wait states - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ - -#define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_IOSELECT_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_15_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - - -/*----------------------------------------------------------------------- - * BR7 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR7 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 7 - LEDs and switches - * - * LEDs are at 0x00001 (write only) - * switches are at 0x00001 (read only) - */ -#ifdef CONFIG_SYS_LED_BASE - -/* BR7 is configured as follows: - * - * - Base address of 0xA0000000 - * - 8 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_LED_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR7 is configured as follows: - * - * - 1 byte - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 15 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CONFIG_SYS_OR7_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_15_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) -#endif /* CONFIG_SYS_LED_BASE */ -#endif /* __CONFIG_H */
These boards have been orphaned for a while and old enough.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
arch/powerpc/cpu/mpc824x/cpu_init.c | 21 -- board/musenki/Makefile | 8 - board/musenki/README | 298 ---------------------- board/musenki/flash.c | 496 ------------------------------------ board/musenki/musenki.c | 94 ------- boards.cfg | 2 - doc/README.scrapyard | 1 + include/configs/MUSENKI.h | 275 -------------------- include/configs/Sandpoint8245.h | 376 --------------------------- 9 files changed, 1 insertion(+), 1570 deletions(-) delete mode 100644 board/musenki/Makefile delete mode 100644 board/musenki/README delete mode 100644 board/musenki/flash.c delete mode 100644 board/musenki/musenki.c delete mode 100644 include/configs/MUSENKI.h delete mode 100644 include/configs/Sandpoint8245.h
diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c index 68d88e9..36dad17 100644 --- a/arch/powerpc/cpu/mpc824x/cpu_init.c +++ b/arch/powerpc/cpu/mpc824x/cpu_init.c @@ -50,27 +50,6 @@ cpu_init_f (void) CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
-#if defined(CONFIG_MUSENKI) -/* Why is this here, you ask? Try, just try setting 0x8000 - * in PCIACR with CONFIG_WRITE_HALFWORD() - * this one was a stumper, and we are annoyed - */ - -#define M_CONFIG_WRITE_HALFWORD( addr, data ) \ - __asm__ __volatile__(" \ - stw %2,0(%0)\n \ - sync\n \ - sth %3,2(%1)\n \ - sync\n \ - " \ - : /* no output */ \ - : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \ - "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \ - ); - - M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000); -#endif - CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */ CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */ /* diff --git a/board/musenki/Makefile b/board/musenki/Makefile deleted file mode 100644 index d2b79ff..0000000 --- a/board/musenki/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = musenki.o flash.o diff --git a/board/musenki/README b/board/musenki/README deleted file mode 100644 index 084ab54..0000000 --- a/board/musenki/README +++ /dev/null @@ -1,298 +0,0 @@ -U-Boot for a Musenki M-3/M-1 board ---------------------------- - -Musenki M-1 and M-3 have two banks of flash of 4MB or 8MB each. - -In board's notation, bank 0 is the one at the address of 0xFF800000 -and bank 1 is the one at the address of 0xFF000000. - -On power-up the processor jumps to the address of 0xFFF00100, the last -megabyte of the bank 0 of flash. - -Thus, U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is located in flash separately from -U-Boot, at the address of 0xFF800000. - -There is a Davicom 9102A on-board, but I don't have it working yet. - -U-Boot test results --------------------- - -x.x Operation on all available serial consoles - -x.x.x CONFIG_CONS_INDEX 1 - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> help -base - print or set address offset -bdinfo - print Board Info structure -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -cmp - memory compare -coninfo - print console devices and informations -cp - memory copy -crc32 - checksum calculation -dcache - enable or disable data cache -echo - echo args to console -erase - erase FLASH memory -flinfo - print FLASH memory information -go - start application at address 'addr' -help - print online help -icache - enable or disable instruction cache -iminfo - print header information for application image -loadb - load binary file over serial line (kermit mode) -loads - load S-Record file over serial line -loop - infinite loop on address range -md - memory display -mm - memory modify (auto-incrementing) -mtest - simple RAM test -mw - memory write (fill) -nm - memory modify (constant address) -printenv- print environment variables -protect - enable or disable FLASH write protection -rarpboot- boot image via network using RARP/TFTP protocol -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -source - run script from memory -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -version - print monitor version -? - alias for 'help' - - -x.x.x CONFIG_CONS_INDEX 2 - -**** NOT TESTED **** - -x.x Flash Driver Operation - - -Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> -=> md ff800000 -ff800000: 46989bf8 626f6f74 636d643d 626f6f74 F...bootcmd=boot -ff800010: 6d204646 38323030 30300062 6f6f7464 m FF820000.bootd -ff800020: 656c6179 3d350062 61756472 6174653d elay=5.baudrate= -ff800030: 39363030 00636c6f 636b735f 696e5f6d 9600.clocks_in_m -ff800040: 687a3d31 00737464 696e3d73 65726961 hz=1.stdin=seria -ff800050: 6c007374 646f7574 3d736572 69616c00 l.stdout=serial. -ff800060: 73746465 72723d73 65726961 6c006970 stderr=serial.ip -ff800070: 61646472 3d313932 2e313638 2e302e34 addr=192.168.0.4 -ff800080: 32007365 72766572 69703d31 39322e31 2.serverip=192.1 -ff800090: 36382e30 2e380000 00000000 00000000 68.0.8.......... -ff8000a0: 00000000 00000000 00000000 00000000 ................ -ff8000b0: 00000000 00000000 00000000 00000000 ................ -ff8000c0: 00000000 00000000 00000000 00000000 ................ -ff8000d0: 00000000 00000000 00000000 00000000 ................ -ff8000e0: 00000000 00000000 00000000 00000000 ................ -ff8000f0: 00000000 00000000 00000000 00000000 ................ -=> protect off ff800000 ff81ffff -Un-Protected 1 sectors -=> erase ff800000 ff81ffff -Erase Flash from 0xff800000 to 0xff81ffff - done -Erased 1 sectors -=> md ff800000 -ff800000: ffffffff ffffffff ffffffff ffffffff ................ -ff800010: ffffffff ffffffff ffffffff ffffffff ................ -ff800020: ffffffff ffffffff ffffffff ffffffff ................ -ff800030: ffffffff ffffffff ffffffff ffffffff ................ -ff800040: ffffffff ffffffff ffffffff ffffffff ................ -ff800050: ffffffff ffffffff ffffffff ffffffff ................ -ff800060: ffffffff ffffffff ffffffff ffffffff ................ -ff800070: ffffffff ffffffff ffffffff ffffffff ................ -ff800080: ffffffff ffffffff ffffffff ffffffff ................ -ff800090: ffffffff ffffffff ffffffff ffffffff ................ -ff8000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000f0: ffffffff ffffffff ffffffff ffffffff ................ - -x.x.x Information - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> flinfo - -Bank # 1: Intel 28F320J3A (32Mbit = 128K x 32) - Size: 4 MB in 32 Sectors - Sector Start Addresses: - FF800000 (RO) FF820000 FF840000 FF860000 FF880000 - FF8A0000 FF8C0000 FF8E0000 FF900000 FF920000 - FF940000 FF960000 FF980000 FF9A0000 FF9C0000 - FF9E0000 FFA00000 FFA20000 FFA40000 FFA60000 - FFA80000 FFAA0000 FFAC0000 FFAE0000 FFB00000 - FFB20000 FFB40000 FFB60000 FFB80000 FFBA0000 - FFBC0000 FFBE0000 - -Bank # 2: missing or unknown FLASH type -=> - - -x.x.x Flash Programming - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB - -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> -=> -=> -=> protect off ff800000 ff81ffff -Un-Protected 1 sectors -=> cp 0 ff800000 20 -Copy to Flash... done -=> md ff800000 -ff800000: 37ce33ec 33cc334c 33c031cc 33cc35cc 7.3.3.3L3.1.3.5. -ff800010: 33ec13ce 30ccb3ec b3c833c4 31c836cc 3...0.....3.1.6. -ff800020: 33cc3b9d 31ec33ee 13ecf3cc 338833ec 3.;.1.3.....3.3. -ff800030: 234c33ec 32cc22cc 33883bdc 534433cc #L3.2.".3.;.SD3. -ff800040: 33cc30c8 31cc32ec 338c33cc 330c33dc 3.0.1.2.3.3.3.3. -ff800050: 33cc13dc 334c534c b1c433d8 128c13cc 3...3LSL..3..... -ff800060: 37ec36cd 33dc33cc bbc9f7e8 bbcc77cc 7.6.3.3.......w. -ff800070: 314c0adc 139c30ed 33cc334c 33c833ec 1L....0.3.3L3.3. -ff800080: ffffffff ffffffff ffffffff ffffffff ................ -ff800090: ffffffff ffffffff ffffffff ffffffff ................ -ff8000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000f0: ffffffff ffffffff ffffffff ffffffff ................ - - -x.x.x Storage of environment variables in flash - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> printenv -bootcmd=bootm FF820000 -bootdelay=5 -baudrate=9600 -clocks_in_mhz=1 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 106/16380 bytes -=> setenv myvar 1234 -=> saveenv -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Saving Environment to Flash... -Protected 1 sectors -=> reset - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> printenv -bootcmd=bootm FF820000 -bootdelay=5 -baudrate=9600 -clocks_in_mhz=1 -myvar=1234 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 117/16380 bytes - -x.x Image Download and run over serial port - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> loads -## Ready for S-Record download ... - -## First Load Addr = 0x00040000 -## Last Load Addr = 0x00050177 -## Total Size = 0x00010178 = 65912 Bytes -## Start Addr = 0x00040004 -=> go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "<NULL>" -Hit any key to exit ... - -## Application terminated, rc = 0x0 - - -x.x Image download and run over ethernet interface - -untested (not working yet, actually) diff --git a/board/musenki/flash.c b/board/musenki/flash.c deleted file mode 100644 index 080ec7f..0000000 --- a/board/musenki/flash.c +++ /dev/null @@ -1,496 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info); -static int write_data (flash_info_t *info, uchar *dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/* - * don't ask. its stupid, but more than one soul has had to live with this mistake - * "swaptab[i]" is the value of "i" with the bits reversed. - */ - -#define MUSENKI_BROKEN_FLASH 1 - -#ifdef MUSENKI_BROKEN_FLASH -unsigned char swaptab[256] = { - 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, - 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, - 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, - 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, - 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, - 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, - 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, - 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, - 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, - 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, - 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, - 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, - 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, - 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, - 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, - 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, - 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, - 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, - 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, - 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, - 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, - 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, - 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, - 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, - 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, - 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, - 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, - 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, - 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, - 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, - 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, - 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff, -}; - -#define BS(b) (swaptab[b]) - -#else - -#define BS(b) (b) - -#endif - -#define BYTEME(x) ((x) & 0xFF) - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",CONFIG_SYS_FLASH_BASE0_PRELIM); - - size_b0 = flash_get_size((vu_char *)CONFIG_SYS_FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0: " - "ID 0x%lx, Size = 0x%08lx = %ld MB\n", - flash_info[0].flash_id, - size_b0, size_b0<<20); - } - - DEBUGF("## Get flash bank 2 size @ 0x%08x\n",CONFIG_SYS_FLASH_BASE1_PRELIM); - size_b1 = flash_get_size((vu_char *)CONFIG_SYS_FLASH_BASE1_PRELIM, &flash_info[1]); - - DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b0; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, monitor_flash_len); - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE); - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - flash_info[1].size = size_b1; - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - } - - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x00020000; /* 128k per bank */ - } - return; - - default: - printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id); - return; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_MT: printf ("MT "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: printf ("28F320J3A (32Mbit = 128K x 32)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64Mbit = 128K x 64)\n"); - break; - case FLASH_28F128J3A: printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info) -{ - vu_char manuf, device; - - addr[0] = BS(0x90); - manuf = BS(addr[0]); - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (vu_char *)addr, manuf); - - switch (manuf) { - case BYTEME(AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - case BYTEME(FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - case BYTEME(SST_MANUFACT): - info->flash_id = FLASH_MAN_SST; - break; - case BYTEME(STM_MANUFACT): - info->flash_id = FLASH_MAN_STM; - break; - case BYTEME(INTEL_MANUFACT): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = BS(0xFF); /* restore read mode, (yes, BS is a NOP) */ - return 0; /* no or unknown flash */ - } - - device = BS(addr[2]); /* device ID */ - - DEBUGF("Device ID @ 0x%08x: 0x%08x\n", (&addr[1]), device); - - switch (device) { - case BYTEME(INTEL_ID_28F320J3A): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case BYTEME(INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case BYTEME(INTEL_ID_28F128J3A): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - addr[0] = BS(0xFF); /* restore read mode (yes, a NOP) */ - return 0; /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = BS(0xFF); /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_char *addr = (vu_char *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x50); /* clear status register */ - *addr = BS(0x20); /* erase setup */ - *addr = BS(0xD0); /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = BS(0xB0); /* suspend erase */ - *addr = BS(0xFF); /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = BS(0xFF); /* reset to read mode */ - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 1 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - uchar *wp = (uchar *)addr; - int rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - while (cnt > 0) { - if ((rc = write_data(info, wp, *src)) != 0) { - return rc; - } - wp++; - src++; - cnt--; - } - - return cnt; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, uchar *dest, uchar data) -{ - vu_char *addr = (vu_char *)dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((BS(*addr) & data) != data) { - return 2; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x40); /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - start = get_timer (0); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = BS(0xFF); /* restore read mode */ - return 1; - } - } - - *addr = BS(0xFF); /* restore read mode */ - - return 0; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c deleted file mode 100644 index aa92fc4..0000000 --- a/board/musenki/musenki.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <pci.h> -#include <netdev.h> - -int checkboard (void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - printf("Board: MUSENKI Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; - -} - -#if 0 /* NOT USED */ -int checkflash (void) -{ - /* TODO: XXX XXX XXX */ - printf ("## Test not implemented yet ##\n"); - - return (0); -} -#endif - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_sandpoint_config_table[] = { -#if 0 - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - 0x0, 0x0, 0x0, /* unknown eth0 divice */ - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - 0x0, 0x0, 0x0, /* unknown eth1 device */ - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, -#endif - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_sandpoint_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/boards.cfg b/boards.cfg index f08ea01..dc7ae48 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1182,8 +1182,6 @@ Orphan powerpc mpc8xx - - svm_sc8xx Orphan powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek dan@embeddedalley.com # The following were moved to "Orphan" in April, 2014 Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu nyet@zumanetworks.com -Orphan powerpc mpc824x - - musenki MUSENKI - Jim Thompson jim@musenki.com -Orphan powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson jim@musenki.com # The following were moved to "Orphan" in March, 2014 Orphan blackfin - - - cm-bf527 cm-bf527 - Bluetechnix Tinyboards bluetechnix@blackfin.uclinux.org Orphan blackfin - - - cm-bf533 cm-bf533 - Bluetechnix Tinyboards bluetechnix@blackfin.uclinux.org diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 36dc403..160e385 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +musenki powerpc mpc824x - - Jim Thompson jim@musenki.com ppmc8260 powerpc mpc8260 - - Brad Kemp Brad.Kemp@seranoa.com spc1920 powerpc mpc8xx 98ad54be 2014-07-07 v37 powerpc mpc8xx b8c1438a 2014-07-07 diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h deleted file mode 100644 index c5c9290..0000000 --- a/include/configs/MUSENKI.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * - * Configuration settings for the MUSENKI board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8245 1 -#define CONFIG_MUSENKI 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_BOOTDELAY 5 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - - -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_TULIP - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ -#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM - -/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the - * reset vector is actually located at FFB00100, but the 8245 - * takes care of us. - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x08000000 /* 0 .. 128 MB of (S)DRAM */ - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - - /* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 7 -#define CONFIG_SYS_ROMFAL 11 -#define CONFIG_SYS_DBUS_SIZE 0x3 - - /* Bit-field values for MCCR2. - */ -#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 121 - - /* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ - - /* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ -#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 - -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ - -#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFFF0000 -#define CONFIG_ENV_SIZE 0x00010000 /* Size of the Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h deleted file mode 100644 index 2664d5b..0000000 --- a/include/configs/Sandpoint8245.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8245 1 -#define CONFIG_SANDPOINT 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds" - -#if 0 -#define USE_DINK32 1 -#else -#undef USE_DINK32 -#endif - -#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ -#define CONFIG_BAUDRATE 9600 -#define CONFIG_DRAM_SPEED 100 /* MHz */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NATSEMI -#define CONFIG_NS8382X - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if defined (USE_DINK32) -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE 0x00090000 -#define CONFIG_SYS_RAMBOOT 1 -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else -#undef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#endif - -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#if 0 -#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ -#else -#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ -#endif -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_ISA_MEM 0xFD000000 -#define CONFIG_SYS_ISA_IO 0xFE000000 - -#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ -#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ -#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -#ifdef CONFIG_SYS_I2C_SOFT -#error "Soft I2C is not configured properly. Please review!" -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SYS_I2C_SOFT */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - - -/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ -#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ -#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ -#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -/* - * NS87308 Configuration - */ -#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ - -#define CONFIG_SYS_NS87308_BADDR_10 1 - -#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ - CONFIG_SYS_NS87308_UART2 | \ - CONFIG_SYS_NS87308_POWRMAN | \ - CONFIG_SYS_NS87308_RTC_APC ) - -#undef CONFIG_SYS_NS87308_PS2MOD - -#define CONFIG_SYS_NS87308_CS0_BASE 0x0076 -#define CONFIG_SYS_NS87308_CS0_CONF 0x30 -#define CONFIG_SYS_NS87308_CS1_BASE 0x0075 -#define CONFIG_SYS_NS87308_CS1_CONF 0x30 -#define CONFIG_SYS_NS87308_CS2_BASE 0x0074 -#define CONFIG_SYS_NS87308_CS2_CONF 0x30 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX > 2) -#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000 -#else -#define CONFIG_SYS_NS16550_CLK 1843200 -#endif - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ -#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ - -#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ - -/* the following are for SDRAM only*/ -#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 4 /* data latency from read command */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#if 0 -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ -#endif - -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 - - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x00000000 -#define CONFIG_SYS_BANK4_END 0x00000000 -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x00000000 -#define CONFIG_SYS_BANK5_END 0x00000000 -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x00000000 -#define CONFIG_SYS_BANK6_END 0x00000000 -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x00000000 -#define CONFIG_SYS_BANK7_END 0x00000000 -#define CONFIG_SYS_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CONFIG_SYS_BANK_ENABLE 0x01 - -#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#if defined(USE_DINK32) -#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) -#else -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#endif - -/* PCI memory */ -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -#endif /* __CONFIG_H */
This board has been orphaned for a while and old enough.
Because this is the last board defining CONFIG_MPC885_FAMILY, drivers/usb/gadget/mpc8xx_udc.c has also been dropped.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
arch/powerpc/cpu/mpc8xx/fec.c | 79 +-- board/stx/stxxtc/Makefile | 8 - board/stx/stxxtc/README.stxxtc | 59 -- board/stx/stxxtc/stxxtc.c | 592 ---------------- board/stx/stxxtc/u-boot.lds | 82 --- board/stx/stxxtc/u-boot.lds.debug | 121 ---- boards.cfg | 1 - doc/README.scrapyard | 1 + drivers/serial/usbtty.h | 4 +- drivers/usb/gadget/Makefile | 1 - drivers/usb/gadget/mpc8xx_udc.c | 1386 ------------------------------------- include/common.h | 5 +- include/configs/stxxtc.h | 485 ------------- include/status_led.h | 4 - include/usb/mpc8xx_udc.h | 178 ----- include/usb/udc.h | 4 +- 16 files changed, 6 insertions(+), 3004 deletions(-) delete mode 100644 board/stx/stxxtc/Makefile delete mode 100644 board/stx/stxxtc/README.stxxtc delete mode 100644 board/stx/stxxtc/stxxtc.c delete mode 100644 board/stx/stxxtc/u-boot.lds delete mode 100644 board/stx/stxxtc/u-boot.lds.debug delete mode 100644 drivers/usb/gadget/mpc8xx_udc.c delete mode 100644 include/configs/stxxtc.h delete mode 100644 include/usb/mpc8xx_udc.h
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index d12b3df..60696ba 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -377,54 +377,10 @@ static void fec_pin_init(int fecidx) */ immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
-#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) - /* use MDC for MII */ - immr->im_ioport.iop_pdpar |= 0x0080; - immr->im_ioport.iop_pddir &= ~0x0080; -#endif - if (fecidx == 0) { #if defined(CONFIG_ETHER_ON_FEC1)
-#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ - -#if !defined(CONFIG_RMII) - - immr->im_ioport.iop_papar |= 0xf830; - immr->im_ioport.iop_padir |= 0x0830; - immr->im_ioport.iop_padir &= ~0xf000; - - immr->im_cpm.cp_pbpar |= 0x00001001; - immr->im_cpm.cp_pbdir &= ~0x00001001; - - immr->im_ioport.iop_pcpar |= 0x000c; - immr->im_ioport.iop_pcdir &= ~0x000c; - - immr->im_cpm.cp_pepar |= 0x00000003; - immr->im_cpm.cp_pedir |= 0x00000003; - immr->im_cpm.cp_peso &= ~0x00000003; - - immr->im_cpm.cp_cptr &= ~0x00000100; - -#else - -#if !defined(CONFIG_FEC1_PHY_NORXERR) - immr->im_ioport.iop_papar |= 0x1000; - immr->im_ioport.iop_padir &= ~0x1000; -#endif - immr->im_ioport.iop_papar |= 0xe810; - immr->im_ioport.iop_padir |= 0x0810; - immr->im_ioport.iop_padir &= ~0xe000; - - immr->im_cpm.cp_pbpar |= 0x00000001; - immr->im_cpm.cp_pbdir &= ~0x00000001; - - immr->im_cpm.cp_cptr |= 0x00000100; - immr->im_cpm.cp_cptr &= ~0x00000050; - -#endif /* !CONFIG_RMII */ - -#elif !defined(CONFIG_ICU862) +#if !defined(CONFIG_ICU862) /* * Configure all of port D for MII. */ @@ -474,39 +430,6 @@ static void fec_pin_init(int fecidx) #endif /* !defined(CONFIG_ICU862) */
#endif /* CONFIG_ETHER_ON_FEC1 */ - } else if (fecidx == 1) { - -#if defined(CONFIG_ETHER_ON_FEC2) - -#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ - -#if !defined(CONFIG_RMII) - immr->im_cpm.cp_pepar |= 0x0003fffc; - immr->im_cpm.cp_pedir |= 0x0003fffc; - immr->im_cpm.cp_peso &= ~0x000087fc; - immr->im_cpm.cp_peso |= 0x00037800; - - immr->im_cpm.cp_cptr &= ~0x00000080; -#else - -#if !defined(CONFIG_FEC2_PHY_NORXERR) - immr->im_cpm.cp_pepar |= 0x00000010; - immr->im_cpm.cp_pedir |= 0x00000010; - immr->im_cpm.cp_peso &= ~0x00000010; -#endif - immr->im_cpm.cp_pepar |= 0x00039620; - immr->im_cpm.cp_pedir |= 0x00039620; - immr->im_cpm.cp_peso |= 0x00031000; - immr->im_cpm.cp_peso &= ~0x00008620; - - immr->im_cpm.cp_cptr |= 0x00000080; - immr->im_cpm.cp_cptr &= ~0x00000028; -#endif /* CONFIG_RMII */ - -#endif /* CONFIG_MPC885_FAMILY */ - -#endif /* CONFIG_ETHER_ON_FEC2 */ - } }
diff --git a/board/stx/stxxtc/Makefile b/board/stx/stxxtc/Makefile deleted file mode 100644 index 6738d4e..0000000 --- a/board/stx/stxxtc/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = stxxtc.o diff --git a/board/stx/stxxtc/README.stxxtc b/board/stx/stxxtc/README.stxxtc deleted file mode 100644 index 7d9d4d3..0000000 --- a/board/stx/stxxtc/README.stxxtc +++ /dev/null @@ -1,59 +0,0 @@ - - -First, some build notes on the Silicon Turnkey eXpress XTc. - -This board has both 87x/88x procesor options at various -frequencies. The configuration file has some macros for setting -the clock speed, not all have been tested. They all have -a 10MHz input clock. Please do not check in a configuration -file that selects a high speed not available on all processors. -We chose the 66MHz core and bus speed, which should be OK on -all boards. If you have a processor, lucky you! :-) -Just build a new configuration with that speed, check -the macro configuration to ensure it's correct. If the -macro is updated, please check that in, but keep default -processor speed. - -The board is likely to have more than 1Mbyte of NOR boot flash. -It was also configured with a high boot vector (Dan's fault) -so the standard 8xx mapping doesn't work well. We had to move -the addresses around a little bit so one copy would work. The -flash got fragmented, and we are working on a better solution. -There is an "xtc.cfg" floating around for the BDI2000, use -that for programming a new version of U-Boot. You can probably -find it on the Silicon Turnkey eXpress (www.silicontkx.com), -Embedded Alley Solutions (embeddedalley.com), or Denx (denx.de) -servers. - -The board will also have various SDRAM sizes, but the code -should automatically determine the amount of memory. - -There are a couple of different board versions, visually -they use different BGA or surface mount memory parts. However, -they are logically the same board. - -Now, some operational notes. - -The board has the option of sporting two FEC Ethernet ports. -The second port isn't configured to be automatically available -because it would cause U-Boot to generate a board data structure -(the bd_t) with multiple MAC addresses and be incompatible with -standard 8xx kernel builds. You can use/test the second FEC -in U-Boot by assigning an 'eth1addr' and selecting the second -FEC as the port to use. - -Since this is just a development board and not a product, STx -does not assign unique MAC addresses. We just pilfer the -"default" ones used by Wolfgang on some other boards. Please -ensure you assign unique MAC addresses when using these boards. - -The serial port baud rate is 38400, because that's the way -I like it :-) - -Thanks to Pantelis for lots of the work on this board port. - -Have Fun! - - -- Dan - -15 August 2005 diff --git a/board/stx/stxxtc/stxxtc.c b/board/stx/stxxtc/stxxtc.c deleted file mode 100644 index 1996efb..0000000 --- a/board/stx/stxxtc/stxxtc.c +++ /dev/null @@ -1,592 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2005 - * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * U-Boot port on STx XTc board - * Mostly copied from Netta - */ - -#include <common.h> -#include <miiphy.h> - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include <watchdog.h> -#endif - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Silicon Turnkey eXpress XTc\n"); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define GPL0_AAAA 0x00000000 -#define GPL0_AAA0 0x00200000 -#define GPL0_AAA1 0x00300000 -#define GPL0_000A 0x00800000 -#define GPL0_0000 0x00A00000 -#define GPL0_0001 0x00B00000 -#define GPL0_111A 0x00C00000 -#define GPL0_1110 0x00E00000 -#define GPL0_1111 0x00F00000 - -#define GPL1_0000 0x00000000 -#define GPL1_0001 0x00040000 -#define GPL1_1110 0x00080000 -#define GPL1_1111 0x000C0000 - -#define GPL2_0000 0x00000000 -#define GPL2_0001 0x00010000 -#define GPL2_1110 0x00020000 -#define GPL2_1111 0x00030000 - -#define GPL3_0000 0x00000000 -#define GPL3_0001 0x00004000 -#define GPL3_1110 0x00008000 -#define GPL3_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -#define A10_AAAA GPL0_AAAA -#define A10_AAA0 GPL0_AAA0 -#define A10_AAA1 GPL0_AAA1 -#define A10_000A GPL0_000A -#define A10_0000 GPL0_0000 -#define A10_0001 GPL0_0001 -#define A10_111A GPL0_111A -#define A10_1110 GPL0_1110 -#define A10_1111 GPL0_1111 - -#define RAS_0000 GPL1_0000 -#define RAS_0001 GPL1_0001 -#define RAS_1110 GPL1_1110 -#define RAS_1111 GPL1_1111 - -#define CAS_0000 GPL2_0000 -#define CAS_0001 GPL2_0001 -#define CAS_1110 GPL2_1110 -#define CAS_1111 GPL2_1111 - -#define WE_0000 GPL3_0000 -#define WE_0001 GPL3_0001 -#define WE_1110 GPL3_1110 -#define WE_1111 GPL3_1111 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -static const uint nandcs_table[0x40] = { - /* RSS */ - CS_1000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1110 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111, - CS_0000 | GPL4_0001 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ - - /* RBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_1000 | GPL4_1111 | GPL5_1110 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0001 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, - - /* WBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* UPT */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 , - CS_0001 | LAST, -}; - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 9 */ -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0) - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - u32 d1, d2; - - upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - DO_LOOP; - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - DO_LOOP; - } - - d1 = 0x12345678; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - DO_LOOP; - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - - return size; -} - -/* ------------------------------------------------------------------------- */ - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - udelay(10000); - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - miiphy_read("FEC", phyno, MII_PHYSID1, &v); - if (v == 0xFFFF) - continue; - miiphy_write("FEC", phyno, MII_BMCR, BMCR_PDOWN); - udelay(10000); - miiphy_write("FEC", phyno, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); - udelay(10000); - } -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK _BW(6) -#define PA_GP_OUTMASK (_BW(7)) -#define PA_SP_MASK 0 -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(7)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK 0 -#define PB_GP_OUTMASK (_B(23)) -#define PB_SP_MASK 0 -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_B(23)) -#define PB_SP_DIRVAL 0 - -#define PC_GP_INMASK 0 -#define PC_GP_OUTMASK (_BW(15)) - -#define PC_SP_MASK 0 -#define PC_SOVAL 0 -#define PC_INTVAL 0 -#define PC_GP_OUTVAL 0 -#define PC_SP_DIRVAL 0 - -#define PE_GP_INMASK 0 -#define PE_GP_OUTMASK 0 -#define PE_GP_OUTVAL 0 - -#define PE_SP_MASK 0 -#define PE_ODR_VAL 0 -#define PE_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - (void)ioport; - (void)cpm; -#if 1 - /* NAND chip select */ - upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); - memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB); - memctl->memc_mbmr = 0; /* all clear */ -#endif - - memctl->memc_br5 &= ~BR_V; - memctl->memc_br6 &= ~BR_V; - memctl->memc_br7 &= ~BR_V; - -#if 1 - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - cpm->cp_pedat = PE_GP_OUTVAL; - cpm->cp_peodr = PE_ODR_VAL; - cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; - cpm->cp_pepar = PE_SP_MASK; -#endif - - return 0; -} - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif - -#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - /* printf("overwrite_console called\n"); */ - return 0; -} -#endif - -extern int drv_phone_init(void); -extern int drv_phone_use_me(void); -extern int drv_phone_is_idle(void); - -int misc_init_r(void) -{ - return 0; -} - -int last_stage_init(void) -{ - reset_phys(); - - return 0; -} diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds deleted file mode 100644 index 0dff5a4..0000000 --- a/board/stx/stxxtc/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug deleted file mode 100644 index a198cf9..0000000 --- a/board/stx/stxxtc/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index dc7ae48..eb04251 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1179,7 +1179,6 @@ Orphan powerpc mpc8xx - - gen860t Orphan powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater Keith_Outwater@mvis.com Orphan powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis DGE@sixnetio.com Orphan powerpc mpc8xx - - svm_sc8xx svm_sc8xx - John Zhan zhanz@sinovee.com -Orphan powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek dan@embeddedalley.com # The following were moved to "Orphan" in April, 2014 Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu nyet@zumanetworks.com # The following were moved to "Orphan" in March, 2014 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 160e385..df0b27b 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +stxxtc powerpc mpc8xx - - Dan Malek dan@embeddedalley.com musenki powerpc mpc824x - - Jim Thompson jim@musenki.com ppmc8260 powerpc mpc8260 - - Brad Kemp Brad.Kemp@seranoa.com spc1920 powerpc mpc8xx 98ad54be 2014-07-07 diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index 21a3ef4..898d542 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -12,9 +12,7 @@ #define __USB_TTY_H__
#include <usbdevice.h> -#if defined(CONFIG_PPC) -#include <usb/mpc8xx_udc.h> -#elif defined(CONFIG_OMAP1510) +#if defined(CONFIG_OMAP1510) #include <usb/omap1510_udc.h> #elif defined(CONFIG_CPU_PXA27X) #include <usb/pxa27x_udc.h> diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 66becdc..9604eff 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -33,7 +33,6 @@ obj-y += ep0.o obj-$(CONFIG_DW_UDC) += designware_udc.o obj-$(CONFIG_OMAP1510) += omap1510_udc.o obj-$(CONFIG_OMAP1610) += omap1510_udc.o -obj-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o obj-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o endif endif diff --git a/drivers/usb/gadget/mpc8xx_udc.c b/drivers/usb/gadget/mpc8xx_udc.c deleted file mode 100644 index 7f72972..0000000 --- a/drivers/usb/gadget/mpc8xx_udc.c +++ /dev/null @@ -1,1386 +0,0 @@ -/* - * Copyright (C) 2006 by Bryan O'Donoghue, CodeHermit - * bodonoghue@CodeHermit.ie - * - * References - * DasUBoot/drivers/usb/gadget/omap1510_udc.c, for design and implementation - * ideas. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Notes : - * 1. #define __SIMULATE_ERROR__ to inject a CRC error into every 2nd TX - * packet to force the USB re-transmit protocol. - * - * 2. #define __DEBUG_UDC__ to switch on debug tracing to serial console - * be careful that tracing doesn't create Hiesen-bugs with respect to - * response timeouts to control requests. - * - * 3. This driver should be able to support any higher level driver that - * that wants to do either of the two standard UDC implementations - * Control-Bulk-Interrupt or Bulk-IN/Bulk-Out standards. Hence - * gserial and cdc_acm should work with this code. - * - * 4. NAK events never actually get raised at all, the documentation - * is just wrong ! - * - * 5. For some reason, cbd_datlen is *always* +2 the value it should be. - * this means that having an RX cbd of 16 bytes is not possible, since - * the same size is reported for 14 bytes received as 16 bytes received - * until we can find out why this happens, RX cbds must be limited to 8 - * bytes. TODO: check errata for this behaviour. - * - * 6. Right now this code doesn't support properly powering up with the USB - * cable attached to the USB host my development board the Adder87x doesn't - * have a pull-up fitted to allow this, so it is necessary to power the - * board and *then* attached the USB cable to the host. However somebody - * with a different design in their board may be able to keep the cable - * constantly connected and simply enable/disable a pull-up re - * figure 31.1 in MPC885RM.pdf instead of having to power up the board and - * then attach the cable ! - * - */ -#include <common.h> -#include <config.h> -#include <commproc.h> -#include <usbdevice.h> -#include <usb/mpc8xx_udc.h> -#include <usb/udc.h> - -#include "ep0.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define ERR(fmt, args...)\ - serial_printf("ERROR : [%s] %s:%d: "fmt,\ - __FILE__,__FUNCTION__,__LINE__, ##args) -#ifdef __DEBUG_UDC__ -#define DBG(fmt,args...)\ - serial_printf("[%s] %s:%d: "fmt,\ - __FILE__,__FUNCTION__,__LINE__, ##args) -#else -#define DBG(fmt,args...) -#endif - -/* Static Data */ -#ifdef __SIMULATE_ERROR__ -static char err_poison_test = 0; -#endif -static struct mpc8xx_ep ep_ref[MAX_ENDPOINTS]; -static u32 address_base = STATE_NOT_READY; -static mpc8xx_udc_state_t udc_state = 0; -static struct usb_device_instance *udc_device = 0; -static volatile usb_epb_t *endpoints[MAX_ENDPOINTS]; -static volatile cbd_t *tx_cbd[TX_RING_SIZE]; -static volatile cbd_t *rx_cbd[RX_RING_SIZE]; -static volatile immap_t *immr = 0; -static volatile cpm8xx_t *cp = 0; -static volatile usb_pram_t *usb_paramp = 0; -static volatile usb_t *usbp = 0; -static int rx_ct = 0; -static int tx_ct = 0; - -/* Static Function Declarations */ -static void mpc8xx_udc_state_transition_up (usb_device_state_t initial, - usb_device_state_t final); -static void mpc8xx_udc_state_transition_down (usb_device_state_t initial, - usb_device_state_t final); -static void mpc8xx_udc_stall (unsigned int ep); -static void mpc8xx_udc_flush_tx_fifo (int epid); -static void mpc8xx_udc_flush_rx_fifo (void); -static void mpc8xx_udc_clear_rxbd (volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_init_tx (struct usb_endpoint_instance *epi, - struct urb *tx_urb); -static void mpc8xx_udc_dump_request (struct usb_device_request *request); -static void mpc8xx_udc_clock_init (volatile immap_t * immr, - volatile cpm8xx_t * cp); -static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi); -static int mpc8xx_udc_epn_rx (unsigned int epid, volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_ep0_rx (volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_cbd_init (void); -static void mpc8xx_udc_endpoint_init (void); -static void mpc8xx_udc_cbd_attach (int ep, uchar tx_size, uchar rx_size); -static u32 mpc8xx_udc_alloc (u32 data_size, u32 alignment); -static int mpc8xx_udc_ep0_rx_setup (volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_set_nak (unsigned int ep); -static short mpc8xx_udc_handle_txerr (void); -static void mpc8xx_udc_advance_rx (volatile cbd_t ** rx_cbdp, int epid); - -/****************************************************************************** - Global Linkage - *****************************************************************************/ - -/* udc_init - * - * Do initial bus gluing - */ -int udc_init (void) -{ - /* Init various pointers */ - immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8xx_t *) & (immr->im_cpm); - usb_paramp = (usb_pram_t *) & (cp->cp_dparam[PROFF_USB]); - usbp = (usb_t *) & (cp->cp_scc[0]); - - memset (ep_ref, 0x00, (sizeof (struct mpc8xx_ep) * MAX_ENDPOINTS)); - - udc_device = 0; - udc_state = STATE_NOT_READY; - - usbp->usmod = 0x00; - usbp->uscom = 0; - - /* Set USB Frame #0, Respond at Address & Get a clock source */ - usbp->usaddr = 0x00; - mpc8xx_udc_clock_init (immr, cp); - - /* PA15, PA14 as perhiperal USBRXD and USBOE */ - immr->im_ioport.iop_padir &= ~0x0003; - immr->im_ioport.iop_papar |= 0x0003; - - /* PC11/PC10 as peripheral USBRXP USBRXN */ - immr->im_ioport.iop_pcso |= 0x0030; - - /* PC7/PC6 as perhiperal USBTXP and USBTXN */ - immr->im_ioport.iop_pcdir |= 0x0300; - immr->im_ioport.iop_pcpar |= 0x0300; - - /* Set the base address */ - address_base = (u32) (cp->cp_dpmem + CPM_USB_BASE); - - /* Initialise endpoints and circular buffers */ - mpc8xx_udc_endpoint_init (); - mpc8xx_udc_cbd_init (); - - /* Assign allocated Dual Port Endpoint descriptors */ - usb_paramp->ep0ptr = (u32) endpoints[0]; - usb_paramp->ep1ptr = (u32) endpoints[1]; - usb_paramp->ep2ptr = (u32) endpoints[2]; - usb_paramp->ep3ptr = (u32) endpoints[3]; - usb_paramp->frame_n = 0; - - DBG ("ep0ptr=0x%08x ep1ptr=0x%08x ep2ptr=0x%08x ep3ptr=0x%08x\n", - usb_paramp->ep0ptr, usb_paramp->ep1ptr, usb_paramp->ep2ptr, - usb_paramp->ep3ptr); - - return 0; -} - -/* udc_irq - * - * Poll for whatever events may have occured - */ -void udc_irq (void) -{ - int epid = 0; - volatile cbd_t *rx_cbdp = 0; - volatile cbd_t *rx_cbdp_base = 0; - - if (udc_state != STATE_READY) { - return; - } - - if (usbp->usber & USB_E_BSY) { - /* This shouldn't happen. If it does then it's a bug ! */ - usbp->usber |= USB_E_BSY; - mpc8xx_udc_flush_rx_fifo (); - } - - /* Scan all RX/Bidirectional Endpoints for RX data. */ - for (epid = 0; epid < MAX_ENDPOINTS; epid++) { - if (!ep_ref[epid].prx) { - continue; - } - rx_cbdp = rx_cbdp_base = ep_ref[epid].prx; - - do { - if (!(rx_cbdp->cbd_sc & RX_BD_E)) { - - if (rx_cbdp->cbd_sc & 0x1F) { - /* Corrupt data discard it. - * Controller has NAK'd this packet. - */ - mpc8xx_udc_clear_rxbd (rx_cbdp); - - } else { - if (!epid) { - mpc8xx_udc_ep0_rx (rx_cbdp); - - } else { - /* Process data */ - mpc8xx_udc_set_nak (epid); - mpc8xx_udc_epn_rx (epid, rx_cbdp); - mpc8xx_udc_clear_rxbd (rx_cbdp); - } - } - - /* Advance RX CBD pointer */ - mpc8xx_udc_advance_rx (&rx_cbdp, epid); - ep_ref[epid].prx = rx_cbdp; - } else { - /* Advance RX CBD pointer */ - mpc8xx_udc_advance_rx (&rx_cbdp, epid); - } - - } while (rx_cbdp != rx_cbdp_base); - } - - /* Handle TX events as appropiate, the correct place to do this is - * in a tx routine. Perhaps TX on epn was pre-empted by ep0 - */ - - if (usbp->usber & USB_E_TXB) { - usbp->usber |= USB_E_TXB; - } - - if (usbp->usber & (USB_TX_ERRMASK)) { - mpc8xx_udc_handle_txerr (); - } - - /* Switch to the default state, respond at the default address */ - if (usbp->usber & USB_E_RESET) { - usbp->usber |= USB_E_RESET; - usbp->usaddr = 0x00; - udc_device->device_state = STATE_DEFAULT; - } - - /* if(usbp->usber&USB_E_IDLE){ - We could suspend here ! - usbp->usber|=USB_E_IDLE; - DBG("idle state change\n"); - } - if(usbp->usbs){ - We could resume here when IDLE is deasserted ! - Not worth doing, so long as we are self powered though. - } - */ - - return; -} - -/* udc_endpoint_write - * - * Write some data to an endpoint - */ -int udc_endpoint_write (struct usb_endpoint_instance *epi) -{ - int ep = 0; - short epid = 1, unnak = 0, ret = 0; - - if (udc_state != STATE_READY) { - ERR ("invalid udc_state != STATE_READY!\n"); - return -1; - } - - if (!udc_device || !epi) { - return -1; - } - - if (udc_device->device_state != STATE_CONFIGURED) { - return -1; - } - - ep = epi->endpoint_address & 0x03; - if (ep >= MAX_ENDPOINTS) { - return -1; - } - - /* Set NAK for all RX endpoints during TX */ - for (epid = 1; epid < MAX_ENDPOINTS; epid++) { - - /* Don't set NAK on DATA IN/CONTROL endpoints */ - if (ep_ref[epid].sc & USB_DIR_IN) { - continue; - } - - if (!(usbp->usep[epid] & (USEP_THS_NAK | USEP_RHS_NAK))) { - unnak |= 1 << epid; - } - - mpc8xx_udc_set_nak (epid); - } - - mpc8xx_udc_init_tx (&udc_device->bus->endpoint_array[ep], - epi->tx_urb); - ret = mpc8xx_udc_ep_tx (&udc_device->bus->endpoint_array[ep]); - - /* Remove temporary NAK */ - for (epid = 1; epid < MAX_ENDPOINTS; epid++) { - if (unnak & (1 << epid)) { - udc_unset_nak (epid); - } - } - - return ret; -} - -/* mpc8xx_udc_assign_urb - * - * Associate a given urb to an endpoint TX or RX transmit/receive buffers - */ -static int mpc8xx_udc_assign_urb (int ep, char direction) -{ - struct usb_endpoint_instance *epi = 0; - - if (ep >= MAX_ENDPOINTS) { - goto err; - } - epi = &udc_device->bus->endpoint_array[ep]; - if (!epi) { - goto err; - } - - if (!ep_ref[ep].urb) { - ep_ref[ep].urb = usbd_alloc_urb (udc_device, udc_device->bus->endpoint_array); - if (!ep_ref[ep].urb) { - goto err; - } - } else { - ep_ref[ep].urb->actual_length = 0; - } - - switch (direction) { - case USB_DIR_IN: - epi->tx_urb = ep_ref[ep].urb; - break; - case USB_DIR_OUT: - epi->rcv_urb = ep_ref[ep].urb; - break; - default: - goto err; - } - return 0; - - err: - udc_state = STATE_ERROR; - return -1; -} - -/* udc_setup_ep - * - * Associate U-Boot software endpoints to mpc8xx endpoint parameter ram - * Isochronous endpoints aren't yet supported! - */ -void udc_setup_ep (struct usb_device_instance *device, unsigned int ep, - struct usb_endpoint_instance *epi) -{ - uchar direction = 0; - int ep_attrib = 0; - - if (epi && (ep < MAX_ENDPOINTS)) { - - if (ep == 0) { - if (epi->rcv_attributes != USB_ENDPOINT_XFER_CONTROL - || epi->tx_attributes != - USB_ENDPOINT_XFER_CONTROL) { - - /* ep0 must be a control endpoint */ - udc_state = STATE_ERROR; - return; - - } - if (!(ep_ref[ep].sc & EP_ATTACHED)) { - mpc8xx_udc_cbd_attach (ep, epi->tx_packetSize, - epi->rcv_packetSize); - } - usbp->usep[ep] = 0x0000; - return; - } - - if ((epi->endpoint_address & USB_ENDPOINT_DIR_MASK) - == USB_DIR_IN) { - - direction = 1; - ep_attrib = epi->tx_attributes; - epi->rcv_packetSize = 0; - ep_ref[ep].sc |= USB_DIR_IN; - } else { - - direction = 0; - ep_attrib = epi->rcv_attributes; - epi->tx_packetSize = 0; - ep_ref[ep].sc &= ~USB_DIR_IN; - } - - if (mpc8xx_udc_assign_urb (ep, epi->endpoint_address - & USB_ENDPOINT_DIR_MASK)) { - return; - } - - switch (ep_attrib) { - case USB_ENDPOINT_XFER_CONTROL: - if (!(ep_ref[ep].sc & EP_ATTACHED)) { - mpc8xx_udc_cbd_attach (ep, - epi->tx_packetSize, - epi->rcv_packetSize); - } - usbp->usep[ep] = ep << 12; - epi->rcv_urb = epi->tx_urb = ep_ref[ep].urb; - - break; - case USB_ENDPOINT_XFER_BULK: - case USB_ENDPOINT_XFER_INT: - if (!(ep_ref[ep].sc & EP_ATTACHED)) { - if (direction) { - mpc8xx_udc_cbd_attach (ep, - epi->tx_packetSize, - 0); - } else { - mpc8xx_udc_cbd_attach (ep, - 0, - epi->rcv_packetSize); - } - } - usbp->usep[ep] = (ep << 12) | ((ep_attrib) << 8); - - break; - case USB_ENDPOINT_XFER_ISOC: - default: - serial_printf ("Error endpoint attrib %d>3\n", ep_attrib); - udc_state = STATE_ERROR; - break; - } - } - -} - -/* udc_connect - * - * Move state, switch on the USB - */ -void udc_connect (void) -{ - /* Enable pull-up resistor on D+ - * TODO: fit a pull-up resistor to drive SE0 for > 2.5us - */ - - if (udc_state != STATE_ERROR) { - udc_state = STATE_READY; - usbp->usmod |= USMOD_EN; - } -} - -/* udc_disconnect - * - * Disconnect is not used but, is included for completeness - */ -void udc_disconnect (void) -{ - /* Disable pull-up resistor on D- - * TODO: fix a pullup resistor to control this - */ - - if (udc_state != STATE_ERROR) { - udc_state = STATE_NOT_READY; - } - usbp->usmod &= ~USMOD_EN; -} - -/* udc_enable - * - * Grab an EP0 URB, register interest in a subset of USB events - */ -void udc_enable (struct usb_device_instance *device) -{ - if (udc_state == STATE_ERROR) { - return; - } - - udc_device = device; - - if (!ep_ref[0].urb) { - ep_ref[0].urb = usbd_alloc_urb (device, device->bus->endpoint_array); - } - - /* Register interest in all events except SOF, enable transceiver */ - usbp->usber = 0x03FF; - usbp->usbmr = 0x02F7; - - return; -} - -/* udc_disable - * - * disable the currently hooked device - */ -void udc_disable (void) -{ - int i = 0; - - if (udc_state == STATE_ERROR) { - DBG ("Won't disable UDC. udc_state==STATE_ERROR !\n"); - return; - } - - udc_device = 0; - - for (; i < MAX_ENDPOINTS; i++) { - if (ep_ref[i].urb) { - usbd_dealloc_urb (ep_ref[i].urb); - ep_ref[i].urb = 0; - } - } - - usbp->usbmr = 0x00; - usbp->usmod = ~USMOD_EN; - udc_state = STATE_NOT_READY; -} - -/* udc_startup_events - * - * Enable the specified device - */ -void udc_startup_events (struct usb_device_instance *device) -{ - udc_enable (device); - if (udc_state == STATE_READY) { - usbd_device_event_irq (device, DEVICE_CREATE, 0); - } -} - -/* udc_set_nak - * - * Allow upper layers to signal lower layers should not accept more RX data - * - */ -void udc_set_nak (int epid) -{ - if (epid) { - mpc8xx_udc_set_nak (epid); - } -} - -/* udc_unset_nak - * - * Suspend sending of NAK tokens for DATA OUT tokens on a given endpoint. - * Switch off NAKing on this endpoint to accept more data output from host. - * - */ -void udc_unset_nak (int epid) -{ - if (epid > MAX_ENDPOINTS) { - return; - } - - if (usbp->usep[epid] & (USEP_THS_NAK | USEP_RHS_NAK)) { - usbp->usep[epid] &= ~(USEP_THS_NAK | USEP_RHS_NAK); - __asm__ ("eieio"); - } -} - -/****************************************************************************** - Static Linkage -******************************************************************************/ - -/* udc_state_transition_up - * udc_state_transition_down - * - * Helper functions to implement device state changes. The device states and - * the events that transition between them are: - * - * STATE_ATTACHED - * || /\ - * / || - * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET - * || /\ - * / || - * STATE_POWERED - * || /\ - * / || - * DEVICE_RESET DEVICE_POWER_INTERRUPTION - * || /\ - * / || - * STATE_DEFAULT - * || /\ - * / || - * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET - * || /\ - * / || - * STATE_ADDRESSED - * || /\ - * / || - * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED - * || /\ - * / || - * STATE_CONFIGURED - * - * udc_state_transition_up transitions up (in the direction from STATE_ATTACHED - * to STATE_CONFIGURED) from the specified initial state to the specified final - * state, passing through each intermediate state on the way. If the initial - * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then - * no state transitions will take place. - * - * udc_state_transition_down transitions down (in the direction from - * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the - * specified final state, passing through each intermediate state on the way. - * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final - * state, then no state transitions will take place. - * - */ - -static void mpc8xx_udc_state_transition_up (usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial < final) { - switch (initial) { - case STATE_ATTACHED: - usbd_device_event_irq (udc_device, - DEVICE_HUB_CONFIGURED, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq (udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq (udc_device, - DEVICE_ADDRESS_ASSIGNED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq (udc_device, DEVICE_CONFIGURED, - 0); - case STATE_CONFIGURED: - break; - default: - break; - } - } -} - -static void mpc8xx_udc_state_transition_down (usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial > final) { - switch (initial) { - case STATE_CONFIGURED: - usbd_device_event_irq (udc_device, - DEVICE_DE_CONFIGURED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq (udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq (udc_device, - DEVICE_POWER_INTERRUPTION, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq (udc_device, DEVICE_HUB_RESET, - 0); - case STATE_ATTACHED: - break; - default: - break; - } - } -} - -/* mpc8xx_udc_stall - * - * Force returning of STALL tokens on the given endpoint. Protocol or function - * STALL conditions are permissable here - */ -static void mpc8xx_udc_stall (unsigned int ep) -{ - usbp->usep[ep] |= STALL_BITMASK; -} - -/* mpc8xx_udc_set_nak - * - * Force returning of NAK responses for the given endpoint as a kind of very - * simple flow control - */ -static void mpc8xx_udc_set_nak (unsigned int ep) -{ - usbp->usep[ep] |= NAK_BITMASK; - __asm__ ("eieio"); -} - -/* mpc8xx_udc_handle_txerr - * - * Handle errors relevant to TX. Return a status code to allow calling - * indicative of what if anything happened - */ -static short mpc8xx_udc_handle_txerr () -{ - short ep = 0, ret = 0; - - for (; ep < TX_RING_SIZE; ep++) { - if (usbp->usber & (0x10 << ep)) { - - /* Timeout or underrun */ - if (tx_cbd[ep]->cbd_sc & 0x06) { - ret = 1; - mpc8xx_udc_flush_tx_fifo (ep); - - } else { - if (usbp->usep[ep] & STALL_BITMASK) { - if (!ep) { - usbp->usep[ep] &= ~STALL_BITMASK; - } - } /* else NAK */ - } - usbp->usber |= (0x10 << ep); - } - } - return ret; -} - -/* mpc8xx_udc_advance_rx - * - * Advance cbd rx - */ -static void mpc8xx_udc_advance_rx (volatile cbd_t ** rx_cbdp, int epid) -{ - if ((*rx_cbdp)->cbd_sc & RX_BD_W) { - *rx_cbdp = (volatile cbd_t *) (endpoints[epid]->rbase + CONFIG_SYS_IMMR); - - } else { - (*rx_cbdp)++; - } -} - - -/* mpc8xx_udc_flush_tx_fifo - * - * Flush a given TX fifo. Assumes one tx cbd per endpoint - */ -static void mpc8xx_udc_flush_tx_fifo (int epid) -{ - volatile cbd_t *tx_cbdp = 0; - - if (epid > MAX_ENDPOINTS) { - return; - } - - /* TX stop */ - immr->im_cpm.cp_cpcr = ((epid << 2) | 0x1D01); - __asm__ ("eieio"); - while (immr->im_cpm.cp_cpcr & 0x01); - - usbp->uscom = 0x40 | 0; - - /* reset ring */ - tx_cbdp = (cbd_t *) (endpoints[epid]->tbptr + CONFIG_SYS_IMMR); - tx_cbdp->cbd_sc = (TX_BD_I | TX_BD_W); - - - endpoints[epid]->tptr = endpoints[epid]->tbase; - endpoints[epid]->tstate = 0x00; - endpoints[epid]->tbcnt = 0x00; - - /* TX start */ - immr->im_cpm.cp_cpcr = ((epid << 2) | 0x2D01); - __asm__ ("eieio"); - while (immr->im_cpm.cp_cpcr & 0x01); - - return; -} - -/* mpc8xx_udc_flush_rx_fifo - * - * For the sake of completeness of the namespace, it seems like - * a good-design-decision (tm) to include mpc8xx_udc_flush_rx_fifo(); - * If RX_BD_E is true => a driver bug either here or in an upper layer - * not polling frequently enough. If RX_BD_E is true we have told the host - * we have accepted data but, the CPM found it had no-where to put that data - * which needless to say would be a bad thing. - */ -static void mpc8xx_udc_flush_rx_fifo () -{ - int i = 0; - - for (i = 0; i < RX_RING_SIZE; i++) { - if (!(rx_cbd[i]->cbd_sc & RX_BD_E)) { - ERR ("buf %p used rx data len = 0x%x sc=0x%x!\n", - rx_cbd[i], rx_cbd[i]->cbd_datlen, - rx_cbd[i]->cbd_sc); - - } - } - ERR ("BUG : Input over-run\n"); -} - -/* mpc8xx_udc_clear_rxbd - * - * Release control of RX CBD to CP. - */ -static void mpc8xx_udc_clear_rxbd (volatile cbd_t * rx_cbdp) -{ - rx_cbdp->cbd_datlen = 0x0000; - rx_cbdp->cbd_sc = ((rx_cbdp->cbd_sc & RX_BD_W) | (RX_BD_E | RX_BD_I)); - __asm__ ("eieio"); -} - -/* mpc8xx_udc_tx_irq - * - * Parse for tx timeout, control RX or USB reset/busy conditions - * Return -1 on timeout, -2 on fatal error, else return zero - */ -static int mpc8xx_udc_tx_irq (int ep) -{ - int i = 0; - - if (usbp->usber & (USB_TX_ERRMASK)) { - if (mpc8xx_udc_handle_txerr ()) { - /* Timeout, controlling function must retry send */ - return -1; - } - } - - if (usbp->usber & (USB_E_RESET | USB_E_BSY)) { - /* Fatal, abandon TX transaction */ - return -2; - } - - if (usbp->usber & USB_E_RXB) { - for (i = 0; i < RX_RING_SIZE; i++) { - if (!(rx_cbd[i]->cbd_sc & RX_BD_E)) { - if ((rx_cbd[i] == ep_ref[0].prx) || ep) { - return -2; - } - } - } - } - - return 0; -} - -/* mpc8xx_udc_ep_tx - * - * Transmit in a re-entrant fashion outbound USB packets. - * Implement retry/timeout mechanism described in USB specification - * Toggle DATA0/DATA1 pids as necessary - * Introduces non-standard tx_retry. The USB standard has no scope for slave - * devices to give up TX, however tx_retry stops us getting stuck in an endless - * TX loop. - */ -static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi) -{ - struct urb *urb = epi->tx_urb; - volatile cbd_t *tx_cbdp = 0; - unsigned int ep = 0, pkt_len = 0, x = 0, tx_retry = 0; - int ret = 0; - - if (!epi || (epi->endpoint_address & 0x03) >= MAX_ENDPOINTS || !urb) { - return -1; - } - - ep = epi->endpoint_address & 0x03; - tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CONFIG_SYS_IMMR); - - if (tx_cbdp->cbd_sc & TX_BD_R || usbp->usber & USB_E_TXB) { - mpc8xx_udc_flush_tx_fifo (ep); - usbp->usber |= USB_E_TXB; - }; - - while (tx_retry++ < 100) { - ret = mpc8xx_udc_tx_irq (ep); - if (ret == -1) { - /* ignore timeout here */ - } else if (ret == -2) { - /* Abandon TX */ - mpc8xx_udc_flush_tx_fifo (ep); - return -1; - } - - tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CONFIG_SYS_IMMR); - while (tx_cbdp->cbd_sc & TX_BD_R) { - }; - tx_cbdp->cbd_sc = (tx_cbdp->cbd_sc & TX_BD_W); - - pkt_len = urb->actual_length - epi->sent; - - if (pkt_len > epi->tx_packetSize || pkt_len > EP_MAX_PKT) { - pkt_len = MIN (epi->tx_packetSize, EP_MAX_PKT); - } - - for (x = 0; x < pkt_len; x++) { - *((unsigned char *) (tx_cbdp->cbd_bufaddr + x)) = - urb->buffer[epi->sent + x]; - } - tx_cbdp->cbd_datlen = pkt_len; - tx_cbdp->cbd_sc |= (CBD_TX_BITMASK | ep_ref[ep].pid); - __asm__ ("eieio"); - -#ifdef __SIMULATE_ERROR__ - if (++err_poison_test == 2) { - err_poison_test = 0; - tx_cbdp->cbd_sc &= ~TX_BD_TC; - } -#endif - - usbp->uscom = (USCOM_STR | ep); - - while (!(usbp->usber & USB_E_TXB)) { - ret = mpc8xx_udc_tx_irq (ep); - if (ret == -1) { - /* TX timeout */ - break; - } else if (ret == -2) { - if (usbp->usber & USB_E_TXB) { - usbp->usber |= USB_E_TXB; - } - mpc8xx_udc_flush_tx_fifo (ep); - return -1; - } - }; - - if (usbp->usber & USB_E_TXB) { - usbp->usber |= USB_E_TXB; - } - - /* ACK must be present <= 18bit times from TX */ - if (ret == -1) { - continue; - } - - /* TX ACK : USB 2.0 8.7.2, Toggle PID, Advance TX */ - epi->sent += pkt_len; - epi->last = MIN (urb->actual_length - epi->sent, epi->tx_packetSize); - TOGGLE_TX_PID (ep_ref[ep].pid); - - if (epi->sent >= epi->tx_urb->actual_length) { - - epi->tx_urb->actual_length = 0; - epi->sent = 0; - - if (ep_ref[ep].sc & EP_SEND_ZLP) { - ep_ref[ep].sc &= ~EP_SEND_ZLP; - } else { - return 0; - } - } - } - - ERR ("TX fail, endpoint 0x%x tx bytes 0x%x/0x%x\n", ep, epi->sent, - epi->tx_urb->actual_length); - - return -1; -} - -/* mpc8xx_udc_dump_request - * - * Dump a control request to console - */ -static void mpc8xx_udc_dump_request (struct usb_device_request *request) -{ - DBG ("bmRequestType:%02x bRequest:%02x wValue:%04x " - "wIndex:%04x wLength:%04x ?\n", - request->bmRequestType, - request->bRequest, - request->wValue, request->wIndex, request->wLength); - - return; -} - -/* mpc8xx_udc_ep0_rx_setup - * - * Decode received ep0 SETUP packet. return non-zero on error - */ -static int mpc8xx_udc_ep0_rx_setup (volatile cbd_t * rx_cbdp) -{ - unsigned int x = 0; - struct urb *purb = ep_ref[0].urb; - struct usb_endpoint_instance *epi = - &udc_device->bus->endpoint_array[0]; - - for (; x < rx_cbdp->cbd_datlen; x++) { - *(((unsigned char *) &ep_ref[0].urb->device_request) + x) = - *((unsigned char *) (rx_cbdp->cbd_bufaddr + x)); - } - - mpc8xx_udc_clear_rxbd (rx_cbdp); - - if (ep0_recv_setup (purb)) { - mpc8xx_udc_dump_request (&purb->device_request); - return -1; - } - - if ((purb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) - == USB_REQ_HOST2DEVICE) { - - switch (purb->device_request.bRequest) { - case USB_REQ_SET_ADDRESS: - /* Send the Status OUT ZLP */ - ep_ref[0].pid = TX_BD_PID_DATA1; - purb->actual_length = 0; - mpc8xx_udc_init_tx (epi, purb); - mpc8xx_udc_ep_tx (epi); - - /* Move to the addressed state */ - usbp->usaddr = udc_device->address; - mpc8xx_udc_state_transition_up (udc_device->device_state, - STATE_ADDRESSED); - return 0; - - case USB_REQ_SET_CONFIGURATION: - if (!purb->device_request.wValue) { - /* Respond at default address */ - usbp->usaddr = 0x00; - mpc8xx_udc_state_transition_down (udc_device->device_state, - STATE_ADDRESSED); - } else { - /* TODO: Support multiple configurations */ - mpc8xx_udc_state_transition_up (udc_device->device_state, - STATE_CONFIGURED); - for (x = 1; x < MAX_ENDPOINTS; x++) { - if ((udc_device->bus->endpoint_array[x].endpoint_address & USB_ENDPOINT_DIR_MASK) - == USB_DIR_IN) { - ep_ref[x].pid = TX_BD_PID_DATA0; - } else { - ep_ref[x].pid = RX_BD_PID_DATA0; - } - /* Set configuration must unstall endpoints */ - usbp->usep[x] &= ~STALL_BITMASK; - } - } - break; - default: - /* CDC/Vendor specific */ - break; - } - - /* Send ZLP as ACK in Status OUT phase */ - ep_ref[0].pid = TX_BD_PID_DATA1; - purb->actual_length = 0; - mpc8xx_udc_init_tx (epi, purb); - mpc8xx_udc_ep_tx (epi); - - } else { - - if (purb->actual_length) { - ep_ref[0].pid = TX_BD_PID_DATA1; - mpc8xx_udc_init_tx (epi, purb); - - if (!(purb->actual_length % EP0_MAX_PACKET_SIZE)) { - ep_ref[0].sc |= EP_SEND_ZLP; - } - - if (purb->device_request.wValue == - USB_DESCRIPTOR_TYPE_DEVICE) { - if (le16_to_cpu (purb->device_request.wLength) - > purb->actual_length) { - /* Send EP0_MAX_PACKET_SIZE bytes - * unless correct size requested. - */ - if (purb->actual_length > epi->tx_packetSize) { - purb->actual_length = epi->tx_packetSize; - } - } - } - mpc8xx_udc_ep_tx (epi); - - } else { - /* Corrupt SETUP packet? */ - ERR ("Zero length data or SETUP with DATA-IN phase ?\n"); - return 1; - } - } - return 0; -} - -/* mpc8xx_udc_init_tx - * - * Setup some basic parameters for a TX transaction - */ -static void mpc8xx_udc_init_tx (struct usb_endpoint_instance *epi, - struct urb *tx_urb) -{ - epi->sent = 0; - epi->last = 0; - epi->tx_urb = tx_urb; -} - -/* mpc8xx_udc_ep0_rx - * - * Receive ep0/control USB data. Parse and possibly send a response. - */ -static void mpc8xx_udc_ep0_rx (volatile cbd_t * rx_cbdp) -{ - if (rx_cbdp->cbd_sc & RX_BD_PID_SETUP) { - - /* Unconditionally accept SETUP packets */ - if (mpc8xx_udc_ep0_rx_setup (rx_cbdp)) { - mpc8xx_udc_stall (0); - } - - } else { - - mpc8xx_udc_clear_rxbd (rx_cbdp); - - if ((rx_cbdp->cbd_datlen - 2)) { - /* SETUP with a DATA phase - * outside of SETUP packet. - * Reply with STALL. - */ - mpc8xx_udc_stall (0); - } - } -} - -/* mpc8xx_udc_epn_rx - * - * Receive some data from cbd into USB system urb data abstraction - * Upper layers should NAK if there is insufficient RX data space - */ -static int mpc8xx_udc_epn_rx (unsigned int epid, volatile cbd_t * rx_cbdp) -{ - struct usb_endpoint_instance *epi = 0; - struct urb *urb = 0; - unsigned int x = 0; - - if (epid >= MAX_ENDPOINTS || !rx_cbdp->cbd_datlen) { - return 0; - } - - /* USB 2.0 PDF section 8.6.4 - * Discard data with invalid PID it is a resend. - */ - if (ep_ref[epid].pid != (rx_cbdp->cbd_sc & 0xC0)) { - return 1; - } - TOGGLE_RX_PID (ep_ref[epid].pid); - - epi = &udc_device->bus->endpoint_array[epid]; - urb = epi->rcv_urb; - - for (; x < (rx_cbdp->cbd_datlen - 2); x++) { - *((unsigned char *) (urb->buffer + urb->actual_length + x)) = - *((unsigned char *) (rx_cbdp->cbd_bufaddr + x)); - } - - if (x) { - usbd_rcv_complete (epi, x, 0); - if (ep_ref[epid].urb->status == RECV_ERROR) { - DBG ("RX error unset NAK\n"); - udc_unset_nak (epid); - } - } - return x; -} - -/* mpc8xx_udc_clock_init - * - * Obtain a clock reference for Full Speed Signaling - */ -static void mpc8xx_udc_clock_init (volatile immap_t * immr, - volatile cpm8xx_t * cp) -{ - -#if defined(CONFIG_SYS_USB_EXTC_CLK) - - /* This has been tested with a 48MHz crystal on CLK6 */ - switch (CONFIG_SYS_USB_EXTC_CLK) { - case 1: - immr->im_ioport.iop_papar |= 0x0100; - immr->im_ioport.iop_padir &= ~0x0100; - cp->cp_sicr |= 0x24; - break; - case 2: - immr->im_ioport.iop_papar |= 0x0200; - immr->im_ioport.iop_padir &= ~0x0200; - cp->cp_sicr |= 0x2D; - break; - case 3: - immr->im_ioport.iop_papar |= 0x0400; - immr->im_ioport.iop_padir &= ~0x0400; - cp->cp_sicr |= 0x36; - break; - case 4: - immr->im_ioport.iop_papar |= 0x0800; - immr->im_ioport.iop_padir &= ~0x0800; - cp->cp_sicr |= 0x3F; - break; - default: - udc_state = STATE_ERROR; - break; - } - -#elif defined(CONFIG_SYS_USB_BRGCLK) - - /* This has been tested with brgclk == 50MHz */ - int divisor = 0; - - if (gd->cpu_clk < 48000000L) { - ERR ("brgclk is too slow for full-speed USB!\n"); - udc_state = STATE_ERROR; - return; - } - - /* Assume the brgclk is 'good enough', we want !(gd->cpu_clk%48MHz) - * but, can /probably/ live with close-ish alternative rates. - */ - divisor = (gd->cpu_clk / 48000000L) - 1; - cp->cp_sicr &= ~0x0000003F; - - switch (CONFIG_SYS_USB_BRGCLK) { - case 1: - cp->cp_brgc1 |= (divisor | CPM_BRG_EN); - cp->cp_sicr &= ~0x2F; - break; - case 2: - cp->cp_brgc2 |= (divisor | CPM_BRG_EN); - cp->cp_sicr |= 0x00000009; - break; - case 3: - cp->cp_brgc3 |= (divisor | CPM_BRG_EN); - cp->cp_sicr |= 0x00000012; - break; - case 4: - cp->cp_brgc4 = (divisor | CPM_BRG_EN); - cp->cp_sicr |= 0x0000001B; - break; - default: - udc_state = STATE_ERROR; - break; - } - -#else -#error "CONFIG_SYS_USB_EXTC_CLK or CONFIG_SYS_USB_BRGCLK must be defined" -#endif - -} - -/* mpc8xx_udc_cbd_attach - * - * attach a cbd to and endpoint - */ -static void mpc8xx_udc_cbd_attach (int ep, uchar tx_size, uchar rx_size) -{ - - if (!tx_cbd[ep] || !rx_cbd[ep] || ep >= MAX_ENDPOINTS) { - udc_state = STATE_ERROR; - return; - } - - if (tx_size > USB_MAX_PKT || rx_size > USB_MAX_PKT || - (!tx_size && !rx_size)) { - udc_state = STATE_ERROR; - return; - } - - /* Attach CBD to appropiate Parameter RAM Endpoint data structure */ - if (rx_size) { - endpoints[ep]->rbase = (u32) rx_cbd[rx_ct]; - endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct]; - rx_ct++; - - if (!ep) { - - endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct]; - rx_cbd[rx_ct]->cbd_sc |= RX_BD_W; - rx_ct++; - - } else { - rx_ct += 2; - endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct]; - rx_cbd[rx_ct]->cbd_sc |= RX_BD_W; - rx_ct++; - } - - /* Where we expect to RX data on this endpoint */ - ep_ref[ep].prx = rx_cbd[rx_ct - 1]; - } else { - - ep_ref[ep].prx = 0; - endpoints[ep]->rbase = 0; - endpoints[ep]->rbptr = 0; - } - - if (tx_size) { - endpoints[ep]->tbase = (u32) tx_cbd[tx_ct]; - endpoints[ep]->tbptr = (u32) tx_cbd[tx_ct]; - tx_ct++; - } else { - endpoints[ep]->tbase = 0; - endpoints[ep]->tbptr = 0; - } - - endpoints[ep]->tstate = 0; - endpoints[ep]->tbcnt = 0; - endpoints[ep]->mrblr = EP_MAX_PKT; - endpoints[ep]->rfcr = 0x18; - endpoints[ep]->tfcr = 0x18; - ep_ref[ep].sc |= EP_ATTACHED; - - DBG ("ep %d rbase 0x%08x rbptr 0x%08x tbase 0x%08x tbptr 0x%08x prx = %p\n", - ep, endpoints[ep]->rbase, endpoints[ep]->rbptr, - endpoints[ep]->tbase, endpoints[ep]->tbptr, - ep_ref[ep].prx); - - return; -} - -/* mpc8xx_udc_cbd_init - * - * Allocate space for a cbd and allocate TX/RX data space - */ -static void mpc8xx_udc_cbd_init (void) -{ - int i = 0; - - for (; i < TX_RING_SIZE; i++) { - tx_cbd[i] = (cbd_t *) - mpc8xx_udc_alloc (sizeof (cbd_t), sizeof (int)); - } - - for (i = 0; i < RX_RING_SIZE; i++) { - rx_cbd[i] = (cbd_t *) - mpc8xx_udc_alloc (sizeof (cbd_t), sizeof (int)); - } - - for (i = 0; i < TX_RING_SIZE; i++) { - tx_cbd[i]->cbd_bufaddr = - mpc8xx_udc_alloc (EP_MAX_PKT, sizeof (int)); - - tx_cbd[i]->cbd_sc = (TX_BD_I | TX_BD_W); - tx_cbd[i]->cbd_datlen = 0x0000; - } - - - for (i = 0; i < RX_RING_SIZE; i++) { - rx_cbd[i]->cbd_bufaddr = - mpc8xx_udc_alloc (EP_MAX_PKT, sizeof (int)); - rx_cbd[i]->cbd_sc = (RX_BD_I | RX_BD_E); - rx_cbd[i]->cbd_datlen = 0x0000; - - } - - return; -} - -/* mpc8xx_udc_endpoint_init - * - * Attach an endpoint to some dpram - */ -static void mpc8xx_udc_endpoint_init (void) -{ - int i = 0; - - for (; i < MAX_ENDPOINTS; i++) { - endpoints[i] = (usb_epb_t *) - mpc8xx_udc_alloc (sizeof (usb_epb_t), 32); - } -} - -/* mpc8xx_udc_alloc - * - * Grab the address of some dpram - */ -static u32 mpc8xx_udc_alloc (u32 data_size, u32 alignment) -{ - u32 retaddr = address_base; - - while (retaddr % alignment) { - retaddr++; - } - address_base += data_size; - - return retaddr; -} diff --git a/include/common.h b/include/common.h index e272ef7..da2528b 100644 --- a/include/common.h +++ b/include/common.h @@ -31,13 +31,10 @@ typedef volatile unsigned char vu_char; #if defined(CONFIG_MPC859T) || \ defined(CONFIG_MPC866P) # define CONFIG_MPC866_FAMILY 1 -#elif defined(CONFIG_MPC875) -# define CONFIG_MPC885_FAMILY 1 #endif #if defined(CONFIG_MPC860) \ || defined(CONFIG_MPC860T) \ - || defined(CONFIG_MPC866_FAMILY) \ - || defined(CONFIG_MPC885_FAMILY) + || defined(CONFIG_MPC866_FAMILY) # define CONFIG_MPC86x 1 #endif #elif defined(CONFIG_5xx) diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h deleted file mode 100644 index 4e3b727..0000000 --- a/include/configs/stxxtc.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com - * U-Boot port on STx XTc 8xx board - * Mostly copied from Panto's NETTA2 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC875 1 /* This is a MPC875 CPU */ -#define CONFIG_STXXTC 1 /* ...on a STx XTc board */ - -#define CONFIG_SYS_TEXT_BASE 0x40F00000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */ - -#define CONFIG_XIN 10000000 /* 10 MHz input xtal */ - -/* Select one of few clock rates defined later in this file. -*/ -/* #define MPC8XX_HZ 50000000 */ -#define MPC8XX_HZ 66666666 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_SOURCE -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_NISDOMAIN - - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define FEC_ENET 1 /* eth.c needs it that way... */ -#undef CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII 1 -#define CONFIG_MII_INIT 1 -#undef CONFIG_RMII - -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 1 /* phy address of FEC */ -#undef CONFIG_FEC1_PHY_NORXERR - -#define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 3 -#undef CONFIG_FEC2_PHY_NORXERR - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING - - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "xtc> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif - -/* yes this is weird, I know :) */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE | 0x00F00000) -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_RESET_ADDRESS 0x80000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) -#define CONFIG_ENV_OFFSET 0 -#define CONFIG_ENV_SIZE 0x4000 - -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x00010000) -#define CONFIG_ENV_OFFSET_REDUND 0 -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 } - -#define CONFIG_SYS_FLASH_PROTECTION - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -#if CONFIG_XIN == 10000000 - -#if MPC8XX_HZ == 50000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 66666666 -#define CONFIG_SYS_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 10MHz -#endif -#else -#error unsupported freq for XIN (must be 10MHz) -#endif - - -/* - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: When TBS == 0 the timebase is independent of current cpu clock. - */ - -#define SCCR_MASK SCCR_EBDF11 -#if MPC8XX_HZ > 66666666 -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) -#else -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ - -#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 -#define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -#define CONFIG_SYS_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR4 and OR4 (SDRAM) - * - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CONFIG_SYS_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_MAMR_PTA 234 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ - -/****************************************************************/ - -#define NAND_SIZE 0x00010000 /* 64K */ -#define NAND_BASE 0xF1000000 - -/*****************************************************************************/ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -/*****************************************************************************/ - -/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB, - * CxOE and CxRESET. We use the CxOE. - */ -#define STATUS_LED_BIT 0x00000080 /* bit 24 */ - -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifndef __ASSEMBLY__ - -/* LEDs */ - -/* led_id_t is unsigned int mask */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \ - else \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \ - } while(0) - -#define __led_init(msk, st) __led_set(msk, st) - -#endif - -/******************************************************************************/ - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 - -/******************************************************************************/ - -/* use board specific hardware */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG - -/*****************************************************************************/ - -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_CRC32_VERIFY 1 -#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 - -/*****************************************************************************/ - -/* pass open firmware flattened device tree */ -#define CONFIG_OF_LIBFDT 1 - -#define OF_TBCLK (MPC8XX_HZ / 16) - -#endif /* __CONFIG_H */ diff --git a/include/status_led.h b/include/status_led.h index b8aaaf7..a41d3bc 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -231,10 +231,6 @@ void status_led_set (int led, int state);
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-/***** STx XTc ********************************************************/ -#elif defined(CONFIG_STXXTC) -/* XXX empty just to avoid the error */ -/************************************************************************/ #elif defined(CONFIG_V38B)
# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */ diff --git a/include/usb/mpc8xx_udc.h b/include/usb/mpc8xx_udc.h deleted file mode 100644 index 9906c75..0000000 --- a/include/usb/mpc8xx_udc.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) 2006 Bryan O'Donoghue, CodeHermit - * bodonoghue@codehermit.ie - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <commproc.h> - -/* Mode Register */ -#define USMOD_EN 0x01 -#define USMOD_HOST 0x02 -#define USMOD_TEST 0x04 -#define USMOD_SFTE 0x08 -#define USMOD_RESUME 0x40 -#define USMOD_LSS 0x80 - -/* Endpoint Registers */ -#define USEP_RHS_NORM 0x00 -#define USEP_RHS_IGNORE 0x01 -#define USEP_RHS_NAK 0x02 -#define USEP_RHS_STALL 0x03 - -#define USEP_THS_NORM 0x00 -#define USEP_THS_IGNORE 0x04 -#define USEP_THS_NAK 0x08 -#define USEP_THS_STALL 0x0C - -#define USEP_RTE 0x10 -#define USEP_MF 0x20 - -#define USEP_TM_CONTROL 0x00 -#define USEP_TM_INT 0x100 -#define USEP_TM_BULK 0x200 -#define USEP_TM_ISO 0x300 - -/* Command Register */ -#define USCOM_EP0 0x00 -#define USCOM_EP1 0x01 -#define USCOM_EP2 0x02 -#define USCOM_EP3 0x03 - -#define USCOM_FLUSH 0x40 -#define USCOM_STR 0x80 - -/* Event Register */ -#define USB_E_RXB 0x0001 -#define USB_E_TXB 0x0002 -#define USB_E_BSY 0x0004 -#define USB_E_SOF 0x0008 -#define USB_E_TXE1 0x0010 -#define USB_E_TXE2 0x0020 -#define USB_E_TXE3 0x0040 -#define USB_E_TXE4 0x0080 -#define USB_TX_ERRMASK (USB_E_TXE1|USB_E_TXE2|USB_E_TXE3|USB_E_TXE4) -#define USB_E_IDLE 0x0100 -#define USB_E_RESET 0x0200 - -/* Mask Register */ -#define USBS_IDLE 0x01 - -/* RX Buffer Descriptor */ -#define RX_BD_OV 0x02 -#define RX_BD_CR 0x04 -#define RX_BD_AB 0x08 -#define RX_BD_NO 0x10 -#define RX_BD_PID_DATA0 0x00 -#define RX_BD_PID_DATA1 0x40 -#define RX_BD_PID_SETUP 0x80 -#define RX_BD_F 0x400 -#define RX_BD_L 0x800 -#define RX_BD_I 0x1000 -#define RX_BD_W 0x2000 -#define RX_BD_E 0x8000 - -/* Useful masks */ -#define RX_BD_PID_BITMASK (RX_BD_PID_DATA1 | RX_BD_PID_SETUP) -#define STALL_BITMASK (USEP_THS_STALL | USEP_RHS_STALL) -#define NAK_BITMASK (USEP_THS_NAK | USEP_RHS_NAK) -#define CBD_TX_BITMASK (TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_I | TX_BD_CNF) - -/* TX Buffer Descriptor */ -#define TX_BD_UN 0x02 -#define TX_BD_TO 0x04 -#define TX_BD_NO_PID 0x00 -#define TX_BD_PID_DATA0 0x80 -#define TX_BD_PID_DATA1 0xC0 -#define TX_BD_CNF 0x200 -#define TX_BD_TC 0x400 -#define TX_BD_L 0x800 -#define TX_BD_I 0x1000 -#define TX_BD_W 0x2000 -#define TX_BD_R 0x8000 - -/* Implementation specific defines */ - -#define EP_MIN_PACKET_SIZE 0x08 -#define MAX_ENDPOINTS 0x04 -#define FIFO_SIZE 0x10 -#define EP_MAX_PKT FIFO_SIZE -#define TX_RING_SIZE 0x04 -#define RX_RING_SIZE 0x06 -#define USB_MAX_PKT 0x40 -#define TOGGLE_TX_PID(x) x= ((~x)&0x40)|0x80 -#define TOGGLE_RX_PID(x) x^= 0x40 -#define EP_ATTACHED 0x01 /* Endpoint has a urb attached or not */ -#define EP_SEND_ZLP 0x02 /* Send ZLP y/n ? */ - -#define PROFF_USB 0x00000000 -#define CPM_USB_BASE 0x00000A00 - -/* UDC device defines */ -#define EP0_MAX_PACKET_SIZE EP_MAX_PKT - -#define UDC_OUT_PACKET_SIZE EP_MIN_PACKET_SIZE -#define UDC_IN_PACKET_SIZE EP_MIN_PACKET_SIZE -#define UDC_INT_PACKET_SIZE UDC_IN_PACKET_SIZE -#define UDC_BULK_PACKET_SIZE EP_MIN_PACKET_SIZE - -struct mpc8xx_ep { - struct urb * urb; - unsigned char pid; - unsigned char sc; - volatile cbd_t * prx; -}; - -typedef struct mpc8xx_usb{ - char usmod; /* Mode Register */ - char usaddr; /* Slave Address Register */ - char uscom; /* Command Register */ - char res1; /* Reserved */ - ushort usep[4]; - ulong res2; /* Reserved */ - ushort usber; /* Event Register */ - ushort res3; /* Reserved */ - ushort usbmr; /* Mask Register */ - char res4; /* Reserved */ - char usbs; /* Status Register */ - char res5[8]; /* Reserved */ -}usb_t; - -typedef struct mpc8xx_parameter_ram{ - ushort ep0ptr; /* Endpoint Pointer Register 0 */ - ushort ep1ptr; /* Endpoint Pointer Register 1 */ - ushort ep2ptr; /* Endpoint Pointer Register 2 */ - ushort ep3ptr; /* Endpoint Pointer Register 3 */ - uint rstate; /* Receive state */ - uint rptr; /* Receive internal data pointer */ - ushort frame_n; /* Frame number */ - ushort rbcnt; /* Receive byte count */ - uint rtemp; /* Receive temp cp use only */ - uint rxusb; /* Rx Data Temp */ - ushort rxuptr; /* Rx microcode return address temp */ -}usb_pram_t; - -typedef struct endpoint_parameter_block_pointer{ - ushort rbase; /* RxBD base address */ - ushort tbase; /* TxBD base address */ - char rfcr; /* Rx Function code */ - char tfcr; /* Tx Function code */ - ushort mrblr; /* Maximum Receive Buffer Length */ - ushort rbptr; /* RxBD pointer Next Buffer Descriptor */ - ushort tbptr; /* TxBD pointer Next Buffer Descriptor */ - ulong tstate; /* Transmit internal state */ - ulong tptr; /* Transmit internal data pointer */ - ushort tcrc; /* Transmit temp CRC */ - ushort tbcnt; /* Transmit internal bye count */ - ulong ttemp; /* Tx temp */ - ushort txuptr; /* Tx microcode return address */ - ushort res1; /* Reserved */ -}usb_epb_t; - -typedef enum mpc8xx_udc_state{ - STATE_NOT_READY, - STATE_ERROR, - STATE_READY, -}mpc8xx_udc_state_t; - diff --git a/include/usb/udc.h b/include/usb/udc.h index 1f545ec..b5628db 100644 --- a/include/usb/udc.h +++ b/include/usb/udc.h @@ -12,8 +12,8 @@ #define EP_MAX_PACKET_SIZE 64 #endif
-#if !defined(CONFIG_PPC) && !defined(CONFIG_OMAP1510) -/* omap1510_udc.h and mpc8xx_udc.h will set these values */ +#if !defined(CONFIG_OMAP1510) +/* omap1510_udc.h will set these values */ #define UDC_OUT_PACKET_SIZE EP_MAX_PACKET_SIZE #define UDC_IN_PACKET_SIZE EP_MAX_PACKET_SIZE #define UDC_INT_PACKET_SIZE EP_MAX_PACKET_SIZE
This board has been orphaned for a while and old enough.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
arch/powerpc/cpu/mpc8xx/cpu_init.c | 4 - board/svm_sc8xx/Makefile | 8 - board/svm_sc8xx/flash.c | 666 ------------------------------------- board/svm_sc8xx/svm_sc8xx.c | 144 -------- board/svm_sc8xx/u-boot.lds | 99 ------ board/svm_sc8xx/u-boot.lds.debug | 114 ------- boards.cfg | 1 - doc/README.scrapyard | 1 + drivers/pcmcia/tqm8xx_pcmcia.c | 6 +- include/commproc.h | 51 --- include/configs/svm_sc8xx.h | 450 ------------------------- include/pcmcia.h | 2 +- include/status_led.h | 14 - 13 files changed, 4 insertions(+), 1556 deletions(-) delete mode 100644 board/svm_sc8xx/Makefile delete mode 100644 board/svm_sc8xx/flash.c delete mode 100644 board/svm_sc8xx/svm_sc8xx.c delete mode 100644 board/svm_sc8xx/u-boot.lds delete mode 100644 board/svm_sc8xx/u-boot.lds.debug delete mode 100644 include/configs/svm_sc8xx.h
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index e51fec7..90c7e61 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -44,11 +44,7 @@ void cpu_init_f (volatile immap_t * immr) #endif /* CONFIG_WATCHDOG */
/* SIUMCR - contains debug pin configuration (11-6) */ -#ifndef CONFIG_SVM_SC8xx immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; -#else - immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR; -#endif /* initialize timebase status and control register (11-26) */ /* unlock TBSCRK */
diff --git a/board/svm_sc8xx/Makefile b/board/svm_sc8xx/Makefile deleted file mode 100644 index 4c0b4a3..0000000 --- a/board/svm_sc8xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = svm_sc8xx.o flash.o diff --git a/board/svm_sc8xx/flash.c b/board/svm_sc8xx/flash.c deleted file mode 100644 index 8a04de8..0000000 --- a/board/svm_sc8xx/flash.c +++ /dev/null @@ -1,666 +0,0 @@ -/* - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word(flash_info_t *info, ulong dest, ulong data); - -#ifdef CONFIG_BOOT_8B -static int my_in_8(unsigned char *addr); -static void my_out_8(unsigned char *addr, int val); -#endif -#ifdef CONFIG_BOOT_16B -static int my_in_be16(unsigned short *addr); -static void my_out_be16(unsigned short *addr, int val); -#endif -#ifdef CONFIG_BOOT_32B -static unsigned my_in_be32(unsigned *addr); -static void my_out_be32(unsigned *addr, int val); -#endif -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - size_b0 = 0; - size_b1 = 0; - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - -#ifdef CONFIG_SYS_DOC_BASE -#ifndef CONFIG_FEL8xx_AT - /* 32k bytes */ - memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC); - memctl->memc_br5 = CONFIG_SYS_DOC_BASE | 0x401; -#else - /* 32k bytes */ - memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC); - memctl->memc_br3 = CONFIG_SYS_DOC_BASE | 0x401; -#endif -#endif -#if defined(CONFIG_BOOT_8B) - size_b0 = 0x80000; /* 512 K */ - - flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040; - flash_info[0].sector_count = 8; - flash_info[0].size = 0x00080000; - - /* set up sector start address table */ - for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].start[i] = 0x40000000 + (i * 0x10000); - - /* protect all sectors */ - for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].protect[i] = 0x1; - -#elif defined(CONFIG_BOOT_16B) - size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */ - - flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B; - flash_info[0].sector_count = 67; - flash_info[0].size = 0x00400000; - - /* set up sector start address table */ - flash_info[0].start[0] = 0x40000000; - flash_info[0].start[1] = 0x40000000 + 0x4000; - flash_info[0].start[2] = 0x40000000 + 0x6000; - flash_info[0].start[3] = 0x40000000 + 0x8000; - - for (i = 4; i < flash_info[0].sector_count; i++) { - flash_info[0].start[i] = - 0x40000000 + 0x10000 + ((i - 4) * 0x10000); - } - - /* protect all sectors */ - for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].protect[i] = 0x1; -#endif - -#ifdef CONFIG_BOOT_32B - - /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, - &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - size_b1 = flash_get_size((vu_long *) FLASH_BASE1_PRELIM, - &flash_info[1]); - - if (size_b1 > size_b0) { - printf("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1 << 20, size_b0, size_b0 << 20); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - - return 0; - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | - (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, - &flash_info[0]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | - (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + - size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + - size_b0), &flash_info[1]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE + size_b0, - &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[1]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - -#endif /* CONFIG_BOOT_32B */ - - return size_b0 + size_b1; -} - - -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long *) (info->start[0]); - int flag, prot, sect, l_sect, in_mid, in_did; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if defined(CONFIG_BOOT_8B) - my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); - my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); - my_out_8((unsigned char *)((ulong)addr + 0x555), 0x90); - - in_mid = my_in_8((unsigned char *)addr); - in_did = my_in_8((unsigned char *)((ulong)addr + 1)); - - printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); - - my_out_8((unsigned char *)addr, 0xf0); - udelay(1); - - my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); - my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); - my_out_8((unsigned char *)((ulong)addr + 0x555), 0x80); - my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); - my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - /*addr[0] = 0x00300030; */ - my_out_8((unsigned char *)((ulong)addr), 0x30); - l_sect = sect; - } - } -#elif defined(CONFIG_BOOT_16B) - my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0xaa); - my_out_be16((unsigned short *)((ulong)addr + (0x554)), 0x55); - my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0x90); - in_mid = my_in_be16((unsigned short *)addr); - in_did = my_in_be16((unsigned short *)((ulong)addr + 2)); - printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); - my_out_be16((unsigned short *)addr, 0xf0); - udelay(1); - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); - my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0x80); - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); - my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - my_out_be16((unsigned short *)((ulong)addr), 0x30); - l_sect = sect; - } - } - -#elif defined(CONFIG_BOOT_32B) - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); - my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x90); - - in_mid = my_in_be32((unsigned *)addr); - in_did = my_in_be32((unsigned *)((ulong)addr + 4)); - - printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); - - my_out_be32((unsigned *) addr, 0xf0); - udelay(1); - - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); - my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x80); - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); - my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - my_out_be32((unsigned *)((ulong)addr), 0x00300030); - l_sect = sect; - } - } - -#else -#error CONFIG_BOOT_(size)B missing. -#endif - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_long *) (info->start[l_sect]); -#if defined(CONFIG_BOOT_8B) - while ((my_in_8((unsigned char *) addr) & 0x80) != 0x80) -#elif defined(CONFIG_BOOT_16B) - while ((my_in_be16((unsigned short *) addr) & 0x0080) != 0x0080) -#elif defined(CONFIG_BOOT_32B) - while ((my_in_be32((unsigned *) addr) & 0x00800080) != 0x00800080) -#else -#error CONFIG_BOOT_(size)B missing. -#endif - { - now = get_timer(start); - if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *) info->start[0]; - -#if defined(CONFIG_BOOT_8B) - my_out_8((unsigned char *) addr, 0xf0); -#elif defined(CONFIG_BOOT_16B) - my_out_be16((unsigned short *) addr, 0x00f0); -#elif defined(CONFIG_BOOT_32B) - my_out_be32((unsigned *) addr, 0x00F000F0); /* reset bank */ -#else -#error CONFIG_BOOT_(size)B missing. -#endif - printf(" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - l = addr - wp; - - if (l != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return 0; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - return write_word(info, wp, data); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - ulong addr = (ulong) (info->start[0]); - ulong start; - int flag; - ulong i; - int data_short[2]; - - /* Check if Flash is (sufficiently) erased */ - if (((ulong)*(ulong *)dest & data) != data) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); -#if defined(CONFIG_BOOT_8B) -#ifdef DEBUG - { - int in_mid, in_did; - - my_out_8((unsigned char *) (addr + 0x555), 0xaa); - my_out_8((unsigned char *) (addr + 0x2aa), 0x55); - my_out_8((unsigned char *) (addr + 0x555), 0x90); - - in_mid = my_in_8((unsigned char *) addr); - in_did = my_in_8((unsigned char *) (addr + 1)); - - printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); - - my_out_8((unsigned char *) addr, 0xf0); - udelay(1); - } -#endif - { - int data_ch[4]; - - data_ch[0] = (int) ((data >> 24) & 0xff); - data_ch[1] = (int) ((data >> 16) & 0xff); - data_ch[2] = (int) ((data >> 8) & 0xff); - data_ch[3] = (int) (data & 0xff); - - for (i = 0; i < 4; i++) { - my_out_8((unsigned char *) (addr + 0x555), 0xaa); - my_out_8((unsigned char *) (addr + 0x2aa), 0x55); - my_out_8((unsigned char *) (addr + 0x555), 0xa0); - my_out_8((unsigned char *) (dest + i), data_ch[i]); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - while ((my_in_8((unsigned char *)(dest + i))) != - (data_ch[i])) { - if (get_timer(start) > - CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - } /* for */ - } -#elif defined(CONFIG_BOOT_16B) - data_short[0] = (int) (data >> 16) & 0xffff; - data_short[1] = (int) data & 0xffff; - for (i = 0; i < 2; i++) { - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); - my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xa0); - my_out_be16((unsigned short *)(dest + (i * 2)), - data_short[i]); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - while ((my_in_be16((unsigned short *)(dest + (i * 2)))) != - (data_short[i])) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } - } -#elif defined(CONFIG_BOOT_32B) - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } -#endif - return 0; -} - -#ifdef CONFIG_BOOT_8B -static int my_in_8(unsigned char *addr) -{ - int ret; - __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); - - return ret; -} - -static void my_out_8(unsigned char *addr, int val) -{ - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); -} -#endif -#ifdef CONFIG_BOOT_16B -static int my_in_be16(unsigned short *addr) -{ - int ret; - __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); - - return ret; -} - -static void my_out_be16(unsigned short *addr, int val) -{ - __asm__ __volatile__("sth%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); -} -#endif -#ifdef CONFIG_BOOT_32B -static unsigned my_in_be32(unsigned *addr) -{ - unsigned ret; - __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); - - return ret; -} - -static void my_out_be32(unsigned *addr, int val) -{ - __asm__ __volatile__("stw%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); -} -#endif diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c deleted file mode 100644 index 5db4850..0000000 --- a/board/svm_sc8xx/svm_sc8xx.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -/* ------------------------------------------------------------------------- */ -const uint sdram_table[] = -{ -/*----------------- - UPM A contents: ------------------ */ -/*--------------------------------------------------- - Read Single Beat Cycle. Offset 0 in the RAM array. ----------------------------------------------------- */ -0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00 , -0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35 , -/*------------------------------------------------ - Read Burst Cycle. Offset 0x8 in the RAM array. ------------------------------------------------- */ -0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, -0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, -/*------------------------------------------------------- - Write Single Beat Cycle. Offset 0x18 in the RAM array -------------------------------------------------------- */ -0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47 , -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -/*------------------------------------------------- - Write Burst Cycle. Offset 0x20 in the RAM array -------------------------------------------------- */ -0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, -0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -/*------------------------------------------------------------------------ - Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array ------------------------------------------------------------------------- */ -0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, -0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -/*----------- -* Exception: -* ----------- */ -0x7ffefc07, 0xffffffff, 0xffffffff, 0xffffffff , -}; - -/* ------------------------------------------------------------------------- */ -/* - * Check Board Identity: - * - * Test ID string (SVM8...) - * - * Return 1 for "SC8xx" type, 0 else. - */ - -int checkboard(void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - if (l < 0 || strncmp(buf, "SVM8", 4)) { - printf("### No HW ID - assuming SVM SC8xx\n"); - return (0); - } - - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc(buf[i]); - } - - putc('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0 = 0; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#if defined (CONFIG_SDRAM_16M) - memctl->memc_mamr = 0x00802114 | CONFIG_SYS_MxMR_PTx; - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80002830; - udelay(1); - memctl->memc_mar = 0x00000088; - udelay(1); - memctl->memc_mcr = 0x80002106; - udelay(1); - memctl->memc_or1 = 0xff000a00; - size_b0 = 0x01000000; -#elif defined (CONFIG_SDRAM_32M) - memctl->memc_mamr = 0x00904114 | CONFIG_SYS_MxMR_PTx; - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80002830; - udelay(1); - memctl->memc_mar = 0x00000088; - udelay(1); - memctl->memc_mcr = 0x80002106; - udelay(1); - memctl->memc_or1 = 0xfe000a00; - size_b0 = 0x02000000; -#elif defined (CONFIG_SDRAM_64M) - memctl->memc_mamr = 0x00a04114 | CONFIG_SYS_MxMR_PTx; - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80002830; - udelay(1); - memctl->memc_mar = 0x00000088; - udelay(1); - memctl->memc_mcr = 0x80002106; - udelay(1); - memctl->memc_or1 = 0xfc000a00; - size_b0 = 0x04000000; -#else -#error SDRAM size configuration missing. -#endif - memctl->memc_br1 = 0x00000081; - udelay(200); - return (size_b0 ); -} - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds deleted file mode 100644 index df564e9..0000000 --- a/board/svm_sc8xx/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - lib/built-in.o (.text*) - net/built-in.o (.text*) - arch/powerpc/cpu/mpc8xx/built-in.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - board/svm_sc8xx/built-in.o (.text*) - *(.text.*printf) - *(.text.do_mem_*) - *(.text.flash*) - *(.text.run_command) - *(.text.main_loop) - *(.text.srec_decode) - - . = env_offset; - common/env_embedded.o (.ppcenv*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug deleted file mode 100644 index b2c562c..0000000 --- a/board/svm_sc8xx/u-boot.lds.debug +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index eb04251..a33ab37 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1178,7 +1178,6 @@ Orphan powerpc mpc8xx - - flagadm Orphan powerpc mpc8xx - - gen860t GEN860T - Keith Outwater Keith_Outwater@mvis.com Orphan powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater Keith_Outwater@mvis.com Orphan powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis DGE@sixnetio.com -Orphan powerpc mpc8xx - - svm_sc8xx svm_sc8xx - John Zhan zhanz@sinovee.com # The following were moved to "Orphan" in April, 2014 Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu nyet@zumanetworks.com # The following were moved to "Orphan" in March, 2014 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index df0b27b..2c1865a 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +svm_sc8xx powerpc mpc8xx - - John Zhan zhanz@sinovee.com stxxtc powerpc mpc8xx - - Dan Malek dan@embeddedalley.com musenki powerpc mpc824x - - Jim Thompson jim@musenki.com ppmc8260 powerpc mpc8260 - - Brad Kemp Brad.Kemp@seranoa.com diff --git a/drivers/pcmcia/tqm8xx_pcmcia.c b/drivers/pcmcia/tqm8xx_pcmcia.c index 2f69c1b..df26a1d 100644 --- a/drivers/pcmcia/tqm8xx_pcmcia.c +++ b/drivers/pcmcia/tqm8xx_pcmcia.c @@ -20,12 +20,10 @@ #endif
#if defined(CONFIG_PCMCIA) \ - && (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)) + && defined(CONFIG_TQM8xxL)
#if defined(CONFIG_TQM8xxL) #define PCMCIA_BOARD_MSG "TQM8xxL" -#elif defined(CONFIG_SVM_SC8xx) -#define PCMCIA_BOARD_MSG "SC8xx" #endif
static inline void power_config(int slot) @@ -258,4 +256,4 @@ done: return 0; }
-#endif /* CONFIG_PCMCIA && (CONFIG_TQM8xxL || CONFIG_SVM_SC8xx) */ +#endif /* CONFIG_PCMCIA && CONFIG_TQM8xxL */ diff --git a/include/commproc.h b/include/commproc.h index c5610bc..3802b2e 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -779,57 +779,6 @@ typedef struct scc_enet {
/*** NETVIA *******************************************************/
-/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */ -#if ( defined CONFIG_SVM_SC8xx ) -# ifndef CONFIG_FEC_ENET - -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 - - /* Bits in parallel I/O port registers that have to be set/cleared - * * * * to configure the pins for SCC2 use. - * * * */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - * * * */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003700) - -# else /* Use FEC for Fast Ethernet */ - -#undef SCC_ENET -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -# endif /* CONFIG_FEC_ENET */ -#endif /* CONFIG_SVM_SC8xx */ - - #if defined(CONFIG_NETVIA) /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC2 use. diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h deleted file mode 100644 index b4aa948..0000000 --- a/include/configs/svm_sc8xx.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific, - * for SinoVee Microsystems SC8xx series SBC - * http://www.fel.com.cn (Chinese) - * http://www.sinovee.com (English) - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/* Custom configuration */ -/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */ -/* SC85T,SC860T, FEL8xx-AT(855T/860T) */ -/*#define CONFIG_FEL8xx_AT */ -/*#define CONFIG_LCD */ -/*#define CONFIG_MPC8XX_LCD*/ -/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */ -/* #define CONFIG_50MHz */ -/* #define CONFIG_66MHz */ -/* #define CONFIG_75MHz */ -#define CONFIG_80MHz -/*#define CONFIG_100MHz */ -/* #define CONFIG_BUS_DIV2 1 */ -/* for BOOT device port size */ -/* #define CONFIG_BOOT_8B */ -#define CONFIG_BOOT_16B -/* #define CONFIG_BOOT_32B */ -/* #define CONFIG_CAN_DRIVER */ -/* #define DEBUG */ -#define CONFIG_FEC_ENET - -/* #define CONFIG_SDRAM_16M */ -#define CONFIG_SDRAM_32M -/* #define CONFIG_SDRAM_64M */ -#define CONFIG_SYS_RESET_ADDRESS 0xffffffff -/* - * High Level Configuration Options - * (easy to change) - */ - -/* #define CONFIG_MPC823 1 */ -/* #define CONFIG_MPC850 1 */ -#define CONFIG_MPC855 1 -/* #define CONFIG_MPC860 1 */ -/* #define CONFIG_MPC860T 1 */ - -#undef CONFIG_WATCHDOG /* watchdog */ - -#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type "? or help" to get on-line help;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \ - "bootfile=pImage-sc855t\0" \ - "kernel_addr=48000000\0" \ - "ramdisk_addr=48100000\0" \ - "" -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "tftpboot 0x210000 pImage-sc855t;bootm 0x210000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - - -#ifdef CONFIG_LCD -# undef CONFIG_STATUS_LED /* disturbs display */ -#else -# define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#endif /* CONFIG_LCD */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -#ifdef CONFIG_BOOT_8B -#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#elif defined (CONFIG_BOOT_16B) -#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#elif defined (CONFIG_BOOT_32B) -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -/*#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -*/ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR 0xffffff88 -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -/*#define CONFIG_SYS_SIUMCR 0x00610c00 */ -#define CONFIG_SYS_SIUMCR 0x00000000 -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR 0x0001 - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC 0x00c3 - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR 0x0000 - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#if defined (CONFIG_100MHz) -#define CONFIG_SYS_PLPRCR 0x06301000 -#define CONFIG_8xx_GCLK_FREQ 100000000 -#elif defined (CONFIG_80MHz) -#define CONFIG_SYS_PLPRCR 0x04f01000 -#define CONFIG_8xx_GCLK_FREQ 80000000 -#elif defined(CONFIG_75MHz) -#define CONFIG_SYS_PLPRCR 0x04a00100 -#define CONFIG_8xx_GCLK_FREQ 75000000 -#elif defined(CONFIG_66MHz) -#define CONFIG_SYS_PLPRCR 0x04101000 -#define CONFIG_8xx_GCLK_FREQ 66000000 -#elif defined(CONFIG_50MHz) -#define CONFIG_SYS_PLPRCR 0x03101000 -#define CONFIG_8xx_GCLK_FREQ 50000000 -#endif - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_BUS_DIV2 -#define CONFIG_SYS_SCCR 0x02020000 | SCCR_RTSEL -#else /* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR 0x02000000 | SCCR_RTSEL -#endif - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ -#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100010 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -/*#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O - */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses - */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers - */ -#define CONFIG_ATAPI -#define CONFIG_SYS_PIO_MODE 0 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0x0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#if defined(CONFIG_100MHz) -#define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4 -#define CONFIG_SYS_OR_TIMING_DOC 0x000002f4 -#define CONFIG_SYS_MxMR_PTx 0x61000000 -#define CONFIG_SYS_MPTPR 0x400 - -#elif defined(CONFIG_80MHz) -#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4 -#define CONFIG_SYS_OR_TIMING_DOC 0x000001f4 -#define CONFIG_SYS_MxMR_PTx 0x4e000000 -#define CONFIG_SYS_MPTPR 0x400 - -#elif defined(CONFIG_75MHz) -#define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4 -#define CONFIG_SYS_OR_TIMING_DOC 0x000002f4 -#define CONFIG_SYS_MxMR_PTx 0x49000000 -#define CONFIG_SYS_MPTPR 0x400 - -#elif defined(CONFIG_66MHz) -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -/*#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 */ -#define CONFIG_SYS_OR_TIMING_DOC 0x000003f4 -#define CONFIG_SYS_MxMR_PTx 0x40000000 -#define CONFIG_SYS_MPTPR 0x400 - -#else /* 50 MHz */ -#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4 -#define CONFIG_SYS_OR_TIMING_DOC 0x000001f4 -#define CONFIG_SYS_MxMR_PTx 0x30000000 -#define CONFIG_SYS_MPTPR 0x400 -#endif /*CONFIG_??MHz */ - - -#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */ -#define CONFIG_SYS_OR0_PRELIM (0xffe00000 | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) -#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */ -#define CONFIG_SYS_OR0_PRELIM (0xffc00000 | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) -#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */ -#define CONFIG_SYS_OR0_PRELIM (0xfc000000 | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) -#else -#error Boot device port size missing. -#endif - -/* - * Disk-On-Chip configuration - */ - -#define CONFIG_SYS_DOC_SHORT_TIMEOUT -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CONFIG_SYS_DOC_SUPPORT_2000 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM -#define CONFIG_SYS_DOC_BASE 0x80000000 - -#endif /* __CONFIG_H */ diff --git a/include/pcmcia.h b/include/pcmcia.h index 8aec254..4b667f4 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -21,7 +21,7 @@
#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
-#if defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx) +#if defined(CONFIG_TQM8xxL) # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ #elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */ # define CONFIG_PCMCIA_SLOT_B diff --git a/include/status_led.h b/include/status_led.h index a41d3bc..c9d21d1 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -217,20 +217,6 @@ void status_led_set (int led, int state);
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-#elif defined(CONFIG_SVM_SC8xx) -# define STATUS_LED_PAR im_cpm.cp_pbpar -# define STATUS_LED_DIR im_cpm.cp_pbdir -# define STATUS_LED_ODR im_cpm.cp_pbodr -# define STATUS_LED_DAT im_cpm.cp_pbdat - -# define STATUS_LED_BIT 0x00000001 -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - #elif defined(CONFIG_V38B)
# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */
This board has been orphaned for a while and old enough.
Because this is the last board definint CONFIG_RTC_DS1306, drivers/rtc/ds1306.c has also been removed.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
CREDITS | 2 +- board/sixnet/Makefile | 8 - board/sixnet/flash.c | 774 -------------------- board/sixnet/fpgadata.c | 1719 -------------------------------------------- board/sixnet/sixnet.c | 578 --------------- board/sixnet/sixnet.h | 20 - board/sixnet/u-boot.lds | 82 --- boards.cfg | 1 - doc/README.scrapyard | 1 + drivers/rtc/Makefile | 1 - drivers/rtc/ds1306.c | 443 ------------ include/commproc.h | 10 - include/configs/SXNI855T.h | 378 ---------- 13 files changed, 2 insertions(+), 4015 deletions(-) delete mode 100644 board/sixnet/Makefile delete mode 100644 board/sixnet/flash.c delete mode 100644 board/sixnet/fpgadata.c delete mode 100644 board/sixnet/sixnet.c delete mode 100644 board/sixnet/sixnet.h delete mode 100644 board/sixnet/u-boot.lds delete mode 100644 drivers/rtc/ds1306.c delete mode 100644 include/configs/SXNI855T.h
diff --git a/CREDITS b/CREDITS index 3e5fb7b..43d4764 100644 --- a/CREDITS +++ b/CREDITS @@ -126,7 +126,7 @@ D: Palmtreo680 board, docg4 nand flash driver
N: Dave Ellis E: DGE@sixnetio.com -D: EEPROM Speedup, SXNI855T port +D: EEPROM Speedup
N: Daniel Engstr?m E: daniel@omicron.se diff --git a/board/sixnet/Makefile b/board/sixnet/Makefile deleted file mode 100644 index 25a8d69..0000000 --- a/board/sixnet/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = sixnet.o flash.o diff --git a/board/sixnet/flash.c b/board/sixnet/flash.c deleted file mode 100644 index 75bc3eb..0000000 --- a/board/sixnet/flash.c +++ /dev/null @@ -1,774 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -/* environment.h defines the various CONFIG_ENV_... values in terms - * of whichever ones are given in the configuration file. - */ -#include <environment.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -#ifdef CONFIG_SYS_FLASH_PROTECTION -static void flash_sync_real_protect(flash_info_t *info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b; - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",size_b); - } - - /* Remap FLASH according to real size, so only at proper address */ - memctl->memc_or0 = (memctl->memc_or0 & ~OR_AM_MSK) | ORMASK(size_b); - - /* Do this again (was done already in flast_get_size), just - * in case we move it when remap the FLASH. - */ - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#ifdef CONFIG_SYS_FLASH_PROTECTION - /* read the hardware protection status (if any) into the - * protection array in flash_info. - */ - flash_sync_real_protect(&flash_info[0]); -#endif - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - return (size_b); -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (top boot sector type) */ - for (i = 0; i < info->sector_count - 3; i++) - info->start[i] = base + (i * sect_size); - i = info->sector_count - 1; - info->start[i--] = base + (info->size - 0x00004000) * (sizeof(FPW)/2); - info->start[i--] = base + (info->size - 0x00006000) * (sizeof(FPW)/2); - info->start[i--] = base + (info->size - 0x00008000) * (sizeof(FPW)/2); - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - fmt = "29LV800B%s (8 Mbit, %s)\n"; - break; - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { - - case (FPW)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MiB */ - - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void flash_sync_real_protect(flash_info_t *info) -{ - FPWV *addr = (FPWV *)(info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW)0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *)(info->start[i]); - info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - case FLASH_AM800T: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer(0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - base[0x0555] = (FPW)0x00800080; /* erase mode */ - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - base[0x0555] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset (info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset (info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect (info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/sixnet/fpgadata.c b/board/sixnet/fpgadata.c deleted file mode 100644 index 2d3a7b3..0000000 --- a/board/sixnet/fpgadata.c +++ /dev/null @@ -1,1719 +0,0 @@ - 0xff, 0x87, 0xff, 0x88, 0x7f, 0xff, 0xf9, 0xff, - 0xff, 0xf5, 0xff, 0x8f, 0xff, 0xf0, 0x8f, 0xf9, - 0xff, 0xef, 0xff, 0xff, 0xff, - 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0xff, 0x8f, 0xef, 0xe0, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0x8f, 0x3f, - 0xff, 0xdf, 0xf7, 0xff, 0x0f, 0xfe, 0xf0, 0xff, - 0xff, 0xff, 0xff, 0xef, 0xff, 0xdf, 0x8e, 0x7f, - 0xf1, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xbf, 0xbf, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xef, 0xff, 0xbf, 0x7f, 0xe1, 0xff, - 0xdf, 0xff, 0x7f, 0xff, 0xbf, - 0xff, 0xa7, 0xff, 0x88, 0xff, 0xf1, 0xfe, 0xff, - 0xff, 0xff, 0xff, 0x1f, 0xff, 0xf0, 0xcf, 0xb1, - 0xff, 0xef, 0xff, 0x7f, 0xff, diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c deleted file mode 100644 index 06b2083..0000000 --- a/board/sixnet/sixnet.c +++ /dev/null @@ -1,578 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Dave Ellis, SIXNET, dge@sixnetio.com. - * Based on code by: - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * and other contributors to U-Boot. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <jffs2/jffs2.h> -#include <mpc8xx.h> -#include <net.h> /* for eth_init() */ -#include <rtc.h> -#include "sixnet.h" -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -static long ram_size(ulong *, long); - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress (int status) -{ -#if defined(CONFIG_STATUS_LED) -# if defined(STATUS_LED_BOOT) - if (status == BOOTSTAGE_ID_RUN_OS) { - /* ready to transfer to kernel, make sure LED is proper state */ - status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE); - } -# endif /* STATUS_LED_BOOT */ -#endif /* CONFIG_STATUS_LED */ -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * returns 0 if recognized, -1 if unknown - */ - -int checkboard (void) -{ - puts ("Board: SIXNET SXNI855T\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_CMD_PCMCIA) -#error "SXNI855T has no PCMCIA port" -#endif - -/* ------------------------------------------------------------------------- */ - -#define _not_used_ 0xffffffff - -/* UPMB table for dual UART. */ - -/* this table is for 50MHz operation, it should work at all lower speeds */ -const uint duart_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04, - 0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05, - - /* burst read. (offset 8 in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - 0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04, - 0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05, - - /* burst write. (offset 20 in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, -}; - -/* Load FPGA very early in boot sequence, since it must be - * loaded before the 16C2550 serial channels can be used as - * console channels. - * - * Note: Much of the configuration is not complete. The - * stack is in DPRAM since SDRAM has not been initialized, - * so the stack must be kept small. Global variables - * are still in FLASH, so they cannot be written. - * Only the FLASH, DPRAM, immap and FPGA can be addressed, - * the other chip selects may not have been initialized. - * The clocks have been initialized, so udelay() can be - * used. - */ -#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */ -#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */ -#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */ -#define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG)) /* FPGA port */ - -int board_postclk_init (void) -{ - - /* the data to load to the XCSxxXL FPGA */ - static const unsigned char fpgadata[] = { -# include "fpgadata.c" - }; - - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; -#define porta (immap->im_ioport.iop_padat) - const unsigned char* pdata; - - /* /INITFPGA and DONEFPGA signals are inputs */ - immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE); - - /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */ - porta &= ~FPGA_PROGRAM_L; - - /* Set FPGA as an output */ - immap->im_ioport.iop_padir |= FPGA_PROGRAM_L; - - /* delay a little to make sure FPGA sees it, really - * only need less than a microsecond. - */ - udelay(10); - - /* unassert /PROGRAM */ - porta |= FPGA_PROGRAM_L; - - /* delay while FPGA does last erase, indicated by - * /INITFPGA going high. This should happen within a - * few milliseconds. - */ - /* ### FIXME - a timeout check would be good, maybe flash - * the status LED to indicate the error? - */ - while ((porta & FPGA_INIT_L) == 0) - ; /* waiting */ - - /* write program data to FPGA at the programming address - * so extra /CS1 strobes at end of configuration don't actually - * write to any registers. - */ - fpga = 0xff; /* first write is ignored */ - fpga = 0xff; /* fill byte */ - fpga = 0xff; /* fill byte */ - fpga = 0x4f; /* preamble code */ - fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */ - fpga = 0x4b; /* field check code */ - - pdata = fpgadata; - /* while no error write out each of the 28 byte frames */ - while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L - && pdata < fpgadata + sizeof(fpgadata)) { - - fpga = 0x4f; /* preamble code */ - - /* 21 bytes of data in a frame */ - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); - - fpga = 0x4b; /* field check code */ - fpga = 0xff; /* extended write cycle */ - fpga = 0x4b; /* extended write cycle - * (actually 0x4b from bitgen.exe) - */ - fpga = 0xff; /* extended write cycle */ - fpga = 0xff; /* extended write cycle */ - fpga = 0xff; /* extended write cycle */ - } - - fpga = 0xff; /* startup byte */ - fpga = 0xff; /* startup byte */ - fpga = 0xff; /* startup byte */ - fpga = 0xff; /* startup byte */ - -#if 0 /* ### FIXME */ - /* If didn't load all the data or FPGA_DONE is low the load failed. - * Maybe someday stop here and flash the status LED? The console - * is not configured, so can't print an error message. Can't write - * global variables to set a flag (except gd?). - * For now it must work. - */ -#endif - - /* Now that the FPGA is loaded, set up the Dual UART chip - * selects. Must be done here since it may be used as the console. - */ - upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint)); - - memctl->memc_mbmr = DUART_MBMR; - memctl->memc_or5 = DUART_OR_VALUE; - memctl->memc_br5 = DUART_BR5_VALUE; - memctl->memc_or6 = DUART_OR_VALUE; - memctl->memc_br6 = DUART_BR6_VALUE; - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* base address for SRAM, assume 32-bit port, valid */ -#define NVRAM_BR_VALUE (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V) - -/* up to 64MB - will be adjusted for actual size */ -#define NVRAM_OR_PRELIM (ORMASK(CONFIG_SYS_SRAM_SIZE) \ - | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR) -/* - * Miscellaneous platform dependent initializations after running in RAM. - */ - -int misc_init_r (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - bd_t *bd = gd->bd; - uchar enetaddr[6]; - - memctl->memc_or2 = NVRAM_OR_PRELIM; - memctl->memc_br2 = NVRAM_BR_VALUE; - - /* Is there any SRAM? Is it 16 or 32 bits wide? */ - - /* First look for 32-bit SRAM */ - bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE); - - if (bd->bi_sramsize == 0) { - /* no 32-bit SRAM, but there could be 16-bit SRAM since - * it would report size 0 when configured for 32-bit bus. - * Try again with a 16-bit bus. - */ - memctl->memc_br2 |= BR_PS_16; - bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE); - } - - if (bd->bi_sramsize == 0) { - memctl->memc_br2 = 0; /* disable select since nothing there */ - } - else { - /* adjust or2 for actual size of SRAM */ - memctl->memc_or2 |= ORMASK(bd->bi_sramsize); - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; - printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10); - } - - - /* set standard MPC8xx clock so kernel will see the time - * even if it doesn't have a DS1306 clock driver. - * This helps with experimenting with standard kernels. - */ - { - ulong tim; - struct rtc_time tmp; - - rtc_get(&tmp); /* get time from DS1306 RTC */ - - /* convert to seconds since 1970 */ - tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday, - tmp.tm_hour, tmp.tm_min, tmp.tm_sec); - - immap->im_sitk.sitk_rtck = KAPWR_KEY; - immap->im_sit.sit_rtc = tim; - } - - /* set up ethernet address for SCC ethernet. If eth1addr - * is present it gets a unique address, otherwise it - * shares the FEC address. - */ - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { - eth_getenv_enetaddr("ethaddr", enetaddr); - eth_setenv_enetaddr("eth1addr", enetaddr); - } - - return (0); -} - -#if defined(CONFIG_CMD_NAND) -void nand_init(void) -{ - unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE); - - printf ("%4lu MB\n", totlen >> 20); -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. - * - * The memory size MUST be a power of 2 for this to work. - * - * The only memory modified is 8 bytes at offset 0. This is important - * since for the SRAM this location is reserved for autosizing, so if - * it is modified and the board is reset before ram_size() completes - * no damage is done. Normally even the memory at 0 is preserved. The - * higher SRAM addresses may contain battery backed RAM disk data which - * must never be corrupted. - */ - -static long ram_size(ulong *base, long maxsize) -{ - volatile long *test_addr; - volatile ulong *base_addr = base; - ulong ofs; /* byte offset from base_addr */ - ulong save; /* to make test non-destructive */ - ulong save2; /* to make test non-destructive */ - long ramsize = -1; /* size not determined yet */ - - save = *base_addr; /* save value at 0 so can restore */ - save2 = *(base_addr+1); /* save value at 4 so can restore */ - - /* is any SRAM present? */ - *base_addr = 0x5555aaaa; - - /* It is important to drive the data bus with different data so - * it doesn't remember the value and look like RAM that isn't there. - */ - *(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */ - - if (*base_addr != 0x5555aaaa) - ramsize = 0; /* no RAM present, or defective */ - else { - *base_addr = 0xaaaa5555; - *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */ - if (*base_addr != 0xaaaa5555) - ramsize = 0; /* no RAM present, or defective */ - } - - /* now size it if any is present */ - for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) { - test_addr = (long*)((long)base_addr + ofs); /* location to test */ - - *base_addr = ~*test_addr; - if (*base_addr == *test_addr) - ramsize = ofs; /* wrapped back to 0, so this is the size */ - } - - *base_addr = save; /* restore value at 0 */ - *(base_addr+1) = save2; /* restore value at 4 */ - return (ramsize); -} - -/* ------------------------------------------------------------------------- */ -/* sdram table based on the FADS manual */ -/* for chip MB811171622A-100 */ - -/* this table is for 50MHz operation, it should work at all lower speeds */ - -const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* precharge and Mode Register Set initialization (offset 5). - * This is also entered at offset 6 to do Mode Register Set - * without the precharge. - */ - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - /* FADS had 0x1f27fc04, ... - * but most other boards have 0x1f07fc04, which - * sets GPL0 from A11MPC to 0 1/4 clock earlier, - * like the single read. - * This seems better so I am going with the change. - */ - 0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _not_used_, _not_used_, _not_used_ }; - -/* ------------------------------------------------------------------------- */ - -#define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */ - -/* precharge and set Mode Register */ -#define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ - MCR_MB_CS3 | /* chip select */ \ - MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */ - -/* set Mode Register, no precharge */ -#define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ - MCR_MB_CS3 | /* chip select */ \ - MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */ - -/* runs refresh loop twice so get 8 refresh cycles */ -#define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ - MCR_MB_CS3 | /* chip select */ \ - MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */ - -/* MAMR values work in either mamr or mbmr */ -#define SDRAM_MAMR_BASE /* refresh at 50MHz */ \ - ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \ - | MAMR_DSA_1_CYCL /* 1 cycle disable */ \ - | MAMR_RLFA_1X /* Read loop 1 time */ \ - | MAMR_WLFA_1X /* Write loop 1 time */ \ - | MAMR_TLFA_4X) /* Timer loop 4 times */ -/* 8 column SDRAM */ -#define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \ - | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \ - | MAMR_G0CLA_A11) /* GPL0 A11[MPC] */ - -/* 9 column SDRAM */ -#define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \ - | MAMR_AMA_TYPE_1 /* Address MUX 1 */ \ - | MAMR_G0CLA_A10) /* GPL0 A10[MPC] */ - -/* base address 0, 32-bit port, SDRAM UPM, valid */ -#define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V) - -/* up to 256MB, SAM, G5LS - will be adjusted for actual size */ -#define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS) - -/* This is the Mode Select Register value for the SDRAM. - * Burst length: 4 - * Burst Type: sequential - * CAS Latency: 2 - * Write Burst Length: burst - */ -#define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */ - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - uint size_sdram = 0; - uint size_sdram9 = 0; - uint base = 0; /* SDRAM must start at 0 */ - int i; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* Configure the refresh (mostly). This needs to be - * based upon processor clock speed and optimized to provide - * the highest level of performance. - * - * Preliminary prescaler for refresh. - * This value is selected for four cycles in 31.2 us, - * which gives 8192 cycles in 64 milliseconds. - * This may be too fast, but works for any memory. - * It is adjusted to 4096 cycles in 64 milliseconds if - * possible once we know what memory we have. - * - * We have to be careful changing UPM registers after we - * ask it to run these commands. - * - * PTA - periodic timer period for our design is - * 50 MHz x 31.2us - * --------------- = 195 - * 1 x 8 x 1 - * - * 50MHz clock - * 31.2us refresh interval - * SCCR[DFBRG] 0 - * PTP divide by 8 - * 1 chip select - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */ - memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */ - - /* The SDRAM Mode Register value is shifted left 2 bits since - * A30 and A31 don't connect to the SDRAM for 32-bit wide memory. - */ - memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */ - udelay(200); /* SDRAM needs 200uS before set it up */ - - /* Now run the precharge/nop/mrs commands. */ - memctl->memc_mcr = SDRAM_MCR_PRE; - udelay(2); - - /* Run 8 refresh cycles (2 sets of 4) */ - memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */ - udelay(2); - - /* some brands want Mode Register set after the refresh - * cycles. This shouldn't hurt anything for the brands - * that were happy with the first time we set it. - */ - memctl->memc_mcr = SDRAM_MCR_MRS; - udelay(2); - - memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */ - memctl->memc_or3 = SDRAM_OR_PRELIM; - memctl->memc_br3 = SDRAM_BR_VALUE + base; - - /* Some brands need at least 10 DRAM accesses to stabilize. - * It wont hurt the brands that don't. - */ - for (i=0; i<10; ++i) { - volatile ulong *addr = (volatile ulong *)base; - ulong val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* Check SDRAM memory Size in 8 column mode. - * For a 9 column memory we will get half the actual size. - */ - size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE); - - /* Check SDRAM memory Size in 9 column mode. - * For an 8 column memory we will see at most 4 megabytes. - */ - memctl->memc_mamr = SDRAM_MAMR_9COL; - size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE); - - if (size_sdram < size_sdram9) /* leave configuration at 9 columns */ - size_sdram = size_sdram9; - else /* go back to 8 columns */ - memctl->memc_mamr = SDRAM_MAMR_8COL; - - /* adjust or3 for actual size of SDRAM - */ - memctl->memc_or3 |= ORMASK(size_sdram); - - /* Adjust refresh rate depending on SDRAM type. - * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave - * it at the current (fast) rate. - * For 16, 64 and 128 MBit half the rate will do. - */ - if (size_sdram <= 32 * 1024 * 1024) - memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */ - - return (size_sdram); -} diff --git a/board/sixnet/sixnet.h b/board/sixnet/sixnet.h deleted file mode 100644 index 046c9de..0000000 --- a/board/sixnet/sixnet.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Memory map: - * - * ff100000 -> ff13ffff : FPGA CS1 - * ff030000 -> ff03ffff : EXPANSION CS7 - * ff020000 -> ff02ffff : DATA FLASH CS4 - * ff018000 -> ff01ffff : UART B CS6/UPMB - * ff010000 -> ff017fff : UART A CS5/UPMB - * ff000000 -> ff00ffff : IMAP internal to the MPC855T - * f8000000 -> fbffffff : FLASH CS0 up to 64MB - * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB - * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB - */ diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds deleted file mode 100644 index 7ee2012..0000000 --- a/board/sixnet/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index a33ab37..46cf828 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1177,7 +1177,6 @@ Orphan powerpc mpc86xx - freescale mpc8641hpcn Orphan powerpc mpc8xx - - flagadm FLAGADM - Kári Davíðsson kd@flaga.is Orphan powerpc mpc8xx - - gen860t GEN860T - Keith Outwater Keith_Outwater@mvis.com Orphan powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater Keith_Outwater@mvis.com -Orphan powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis DGE@sixnetio.com # The following were moved to "Orphan" in April, 2014 Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu nyet@zumanetworks.com # The following were moved to "Orphan" in March, 2014 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 2c1865a..5031bd1 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +sixnet powerpc mpc8xx - - Dave Ellis DGE@sixnetio.com svm_sc8xx powerpc mpc8xx - - John Zhan zhanz@sinovee.com stxxtc powerpc mpc8xx - - Dan Malek dan@embeddedalley.com musenki powerpc mpc824x - - Jim Thompson jim@musenki.com diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 003d322..bf8985f 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -13,7 +13,6 @@ obj-y += date.o obj-$(CONFIG_RTC_DAVINCI) += davinci.o obj-$(CONFIG_RTC_DS12887) += ds12887.o obj-$(CONFIG_RTC_DS1302) += ds1302.o -obj-$(CONFIG_RTC_DS1306) += ds1306.o obj-$(CONFIG_RTC_DS1307) += ds1307.o obj-$(CONFIG_RTC_DS1338) += ds1307.o obj-$(CONFIG_RTC_DS1337) += ds1337.o diff --git a/drivers/rtc/ds1306.c b/drivers/rtc/ds1306.c deleted file mode 100644 index 1ec1837..0000000 --- a/drivers/rtc/ds1306.c +++ /dev/null @@ -1,443 +0,0 @@ -/* - * (C) Copyright 2002 SIXNET, dge@sixnetio.com. - * - * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net> - * Stephan Linz linz@li-pro.net - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Date & Time support for DS1306 RTC using SPI: - * - * - SXNI855T: it uses its own soft SPI here in this file - * - all other: use the external spi_xfer() function - * (see include/spi.h) - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <spi.h> - -#if defined(CONFIG_CMD_DATE) - -#define RTC_SECONDS 0x00 -#define RTC_MINUTES 0x01 -#define RTC_HOURS 0x02 -#define RTC_DAY_OF_WEEK 0x03 -#define RTC_DATE_OF_MONTH 0x04 -#define RTC_MONTH 0x05 -#define RTC_YEAR 0x06 - -#define RTC_SECONDS_ALARM0 0x07 -#define RTC_MINUTES_ALARM0 0x08 -#define RTC_HOURS_ALARM0 0x09 -#define RTC_DAY_OF_WEEK_ALARM0 0x0a - -#define RTC_SECONDS_ALARM1 0x0b -#define RTC_MINUTES_ALARM1 0x0c -#define RTC_HOURS_ALARM1 0x0d -#define RTC_DAY_OF_WEEK_ALARM1 0x0e - -#define RTC_CONTROL 0x0f -#define RTC_STATUS 0x10 -#define RTC_TRICKLE_CHARGER 0x11 - -#define RTC_USER_RAM_BASE 0x20 - -/* ************************************************************************* */ -#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */ - -static void soft_spi_send (unsigned char n); -static unsigned char soft_spi_read (void); -static void init_spi (void); - -/*----------------------------------------------------------------------- - * Definitions - */ - -#define PB_SPISCK 0x00000002 /* PB 30 */ -#define PB_SPIMOSI 0x00000004 /* PB 29 */ -#define PB_SPIMISO 0x00000008 /* PB 28 */ -#define PB_SPI_CE 0x00010000 /* PB 15 */ - -/* ------------------------------------------------------------------------- */ - -/* read clock time from DS1306 and return it in *tmp */ -int rtc_get (struct rtc_time *tmp) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - unsigned char spi_byte; /* Data Byte */ - - init_spi (); /* set port B for software SPI */ - - /* Now we can enable the DS1306 RTC */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; - udelay (10); - - /* Shift out the address (0) of the time in the Clock Chip */ - soft_spi_send (0); - - /* Put the clock readings into the rtc_time structure */ - tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */ - tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */ - - /* Hours are trickier */ - spi_byte = soft_spi_read (); /* Read Hours into temporary value */ - if (spi_byte & 0x40) { - /* 12 hour mode bit is set (time is in 1-12 format) */ - if (spi_byte & 0x20) { - /* since PM we add 11 to get 0-23 for hours */ - tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11; - } else { - /* since AM we subtract 1 to get 0-23 for hours */ - tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1; - } - } else { - /* Otherwise, 0-23 hour format */ - tmp->tm_hour = (bcd2bin (spi_byte & 0x3F)); - } - - soft_spi_read (); /* Read and discard Day of week */ - tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */ - tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */ - - /* Read Year and convert to this century */ - tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000; - - /* Now we can disable the DS1306 RTC */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay (10); - - GregorianDay (tmp); /* Determine the day of week */ - - debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* set clock time in DS1306 RTC and in MPC8xx RTC */ -int rtc_set (struct rtc_time *tmp) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - init_spi (); /* set port B for software SPI */ - - /* Now we can enable the DS1306 RTC */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ - udelay (10); - - /* First disable write protect in the clock chip control register */ - soft_spi_send (0x8F); /* send address of the control register */ - soft_spi_send (0x00); /* send control register contents */ - - /* Now disable the DS1306 to terminate the write */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; - udelay (10); - - /* Now enable the DS1306 to initiate a new write */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; - udelay (10); - - /* Next, send the address of the clock time write registers */ - soft_spi_send (0x80); /* send address of the first time register */ - - /* Use Burst Mode to send all of the time data to the clock */ - bin2bcd (tmp->tm_sec); - soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */ - soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */ - soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */ - soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */ - soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */ - soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */ - soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */ - - /* Now we can disable the Clock chip to terminate the burst write */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay (10); - - /* Now we can enable the Clock chip to initiate a new write */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ - udelay (10); - - /* First we Enable write protect in the clock chip control register */ - soft_spi_send (0x8F); /* send address of the control register */ - soft_spi_send (0x40); /* send out Control Register contents */ - - /* Now disable the DS1306 */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay (10); - - /* Set standard MPC8xx clock to the same time so Linux will - * see the time even if it doesn't have a DS1306 clock driver. - * This helps with experimenting with standard kernels. - */ - { - ulong tim; - - tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - immap->im_sitk.sitk_rtck = KAPWR_KEY; - immap->im_sit.sit_rtc = tim; - } - - debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Initialize Port B for software SPI */ -static void init_spi (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* Force output pins to begin at logic 0 */ - immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK); - - /* Set these 3 signals as outputs */ - immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK); - - immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */ - udelay (10); -} - -/* ------------------------------------------------------------------------- */ - -/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */ -static void soft_spi_send (unsigned char n) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - unsigned char bitpos; /* bit position to receive */ - unsigned char i; /* Loop Control */ - - /* bit position to send, start with most significant bit */ - bitpos = 0x80; - - /* Send 8 bits to software SPI */ - for (i = 0; i < 8; i++) { /* Loop for 8 bits */ - immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ - - if (n & bitpos) - immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */ - else - immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */ - udelay (10); - - immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ - udelay (10); - - bitpos >>= 1; /* Shift for next bit position */ - } -} - -/* ------------------------------------------------------------------------- */ - -/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */ -static unsigned char soft_spi_read (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - unsigned char spi_byte = 0; /* Return value, assume success */ - unsigned char bitpos; /* bit position to receive */ - unsigned char i; /* Loop Control */ - - /* bit position to receive, start with most significant bit */ - bitpos = 0x80; - - /* Read 8 bits here */ - for (i = 0; i < 8; i++) { /* Do 8 bits in loop */ - immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ - udelay (10); - if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */ - spi_byte |= bitpos; /* Set data accordingly */ - immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ - udelay (10); - bitpos >>= 1; /* Shift for next bit position */ - } - - return spi_byte; /* Return the byte read */ -} - -/* ------------------------------------------------------------------------- */ - -void rtc_reset (void) -{ - return; /* nothing to do */ -} - -#else /* not CONFIG_SXNI855T */ -/* ************************************************************************* */ - -static unsigned char rtc_read (unsigned char reg); -static void rtc_write (unsigned char reg, unsigned char val); - -static struct spi_slave *slave; - -/* read clock time from DS1306 and return it in *tmp */ -int rtc_get (struct rtc_time *tmp) -{ - unsigned char sec, min, hour, mday, wday, mon, year; - - /* - * Assuming Vcc = 2.0V (lowest speed) - * - * REVISIT: If we add an rtc_init() function we can do this - * step just once. - */ - if (!slave) { - slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, - SPI_MODE_3 | SPI_CS_HIGH); - if (!slave) - return; - } - - if (spi_claim_bus(slave)) - return; - - sec = rtc_read (RTC_SECONDS); - min = rtc_read (RTC_MINUTES); - hour = rtc_read (RTC_HOURS); - mday = rtc_read (RTC_DATE_OF_MONTH); - wday = rtc_read (RTC_DAY_OF_WEEK); - mon = rtc_read (RTC_MONTH); - year = rtc_read (RTC_YEAR); - - spi_release_bus(slave); - - debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, hour, min, sec); - debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n", - rtc_read (RTC_DAY_OF_WEEK_ALARM0), - rtc_read (RTC_HOURS_ALARM0), - rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0)); - debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n", - rtc_read (RTC_DAY_OF_WEEK_ALARM1), - rtc_read (RTC_HOURS_ALARM1), - rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1)); - - tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */ - tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */ - - /* convert Hours */ - tmp->tm_hour = (hour & 0x40) - ? ((hour & 0x20) /* 12 hour mode */ - ? bcd2bin (hour & 0x1F) + 11 /* PM */ - : bcd2bin (hour & 0x1F) - 1 /* AM */ - ) - : bcd2bin (hour & 0x3F); /* 24 hour mode */ - - tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */ - tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */ - tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */ - tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */ - tmp->tm_yday = 0; - tmp->tm_isdst = 0; - - debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* set clock time from *tmp in DS1306 RTC */ -int rtc_set (struct rtc_time *tmp) -{ - /* Assuming Vcc = 2.0V (lowest speed) */ - if (!slave) { - slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, - SPI_MODE_3 | SPI_CS_HIGH); - if (!slave) - return; - } - - if (spi_claim_bus(slave)) - return; - - debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec)); - rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min)); - rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour)); - rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1)); - rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday)); - rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon)); - rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000)); - - spi_release_bus(slave); -} - -/* ------------------------------------------------------------------------- */ - -/* reset the DS1306 */ -void rtc_reset (void) -{ - /* Assuming Vcc = 2.0V (lowest speed) */ - if (!slave) { - slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, - SPI_MODE_3 | SPI_CS_HIGH); - if (!slave) - return; - } - - if (spi_claim_bus(slave)) - return; - - /* clear the control register */ - rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */ - rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */ - - /* reset all alarms */ - rtc_write (RTC_SECONDS_ALARM0, 0x00); - rtc_write (RTC_SECONDS_ALARM1, 0x00); - rtc_write (RTC_MINUTES_ALARM0, 0x00); - rtc_write (RTC_MINUTES_ALARM1, 0x00); - rtc_write (RTC_HOURS_ALARM0, 0x00); - rtc_write (RTC_HOURS_ALARM1, 0x00); - rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00); - rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00); - - spi_release_bus(slave); -} - -/* ------------------------------------------------------------------------- */ - -static unsigned char rtc_read (unsigned char reg) -{ - int ret; - - ret = spi_w8r8(slave, reg); - return ret < 0 ? 0 : ret; -} - -/* ------------------------------------------------------------------------- */ - -static void rtc_write (unsigned char reg, unsigned char val) -{ - unsigned char dout[2]; /* SPI Output Data Bytes */ - unsigned char din[2]; /* SPI Input Data Bytes */ - - dout[0] = 0x80 | reg; - dout[1] = val; - - spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); -} - -#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */ - -#endif diff --git a/include/commproc.h b/include/commproc.h index 3802b2e..4904311 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -865,16 +865,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002E00) #endif /* CONFIG_SPD823TS */
-/*** SXNI855T ******************************************************/ - -#if defined(CONFIG_SXNI855T) - -#ifdef CONFIG_FEC_ENET -#define FEC_ENET /* use FEC for Ethernet */ -#endif /* CONFIG_FEC_ETHERNET */ - -#endif /* CONFIG_SXNI855T */ - /*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h deleted file mode 100644 index 3894019..0000000 --- a/include/configs/SXNI855T.h +++ /dev/null @@ -1,378 +0,0 @@ -/* - * U-Boot configuration for SIXNET SXNI855T CPU board. - * This board is based (loosely) on the Motorola FADS board, so this - * file is based (loosely) on config_FADS860T.h, see it for additional - * credits. - * - * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Memory map: - * - * ff100000 -> ff13ffff : FPGA CS1 - * ff030000 -> ff03ffff : EXPANSION CS7 - * ff020000 -> ff02ffff : DATA FLASH CS4 - * ff018000 -> ff01ffff : UART B CS6/UPMB - * ff010000 -> ff017fff : UART A CS5/UPMB - * ff000000 -> ff00ffff : IMAP internal to the MPC855T - * f8000000 -> fbffffff : FLASH CS0 up to 64MB - * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB - * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#include <mpc8xx_irq.h> - -#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */ - -/* The 855T is just a stripped 860T and needs code for 860, so for now - * at least define 860, 860T and 855T - */ -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC855T 1 - -#define CONFIG_SYS_TEXT_BASE 0xF8000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_SCC1 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_HAS_ETH1 - -/*----------------------------------------------------------------------- - * Definitions for status LED - */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */ -# define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifdef DEV /* development (debug) settings */ -#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF -#else /* production settings */ -#define CONFIG_BOOT_LED_STATE STATUS_LED_ON -#endif - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram ip=off" - -#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ -#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */ -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ - -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CONFIG_MII 1 - -#define CONFIG_SYS_DISCOVER_PHY - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_DATE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save a little memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SRAM_BASE 0xF4000000 -#define CONFIG_SYS_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */ - -#define CONFIG_SYS_FLASH_BASE 0xF8000000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CONFIG_SYS_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */ -#define CONFIG_SYS_DFLASH_SIZE 0x00010000 - -#define CONFIG_SYS_FPGA_BASE 0xFF100000 /* Xilinx FPGA */ -#define CONFIG_SYS_FPGA_PROG 0xFF130000 /* Programming address */ -#define CONFIG_SYS_FPGA_SIZE 0x00040000 /* 256KiB usable */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks. - * AMD 29LV641 has 128 64K sectors in 8MB - */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the - * entire address space, we have to set the memory controller - * differently. Normally, you write the option register - * first, and then enable the chip select by writing the - * base register. For CS0, you must write the base register - * first, followed by the option register. - */ - -/* - * Init Memory Controller: - * - ********************************************************** - * BR0 and OR0 (FLASH) - */ - -#define CONFIG_SYS_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR0_AM | CONFIG_SYS_OR_TIMING_FLASH) - -#define CONFIG_FLASH_16BIT -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) -#define CONFIG_SYS_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */ - -/********************************************************** - * BR1 and OR1 (FPGA) - * These preliminary values are also the final values. - */ -#define CONFIG_SYS_OR_TIMING_FPGA \ - (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX) -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CONFIG_SYS_OR1_PRELIM (((-CONFIG_SYS_FPGA_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_FPGA) - -/********************************************************** - * BR4 and OR4 (data flash) - * These preliminary values are also the final values. - */ -#define CONFIG_SYS_OR_TIMING_DFLASH \ - (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX) -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CONFIG_SYS_OR4_PRELIM (((-CONFIG_SYS_DFLASH_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_DFLASH) - -/********************************************************** - * BR5/6 and OR5/6 (Dual UART) - */ -#define CONFIG_SYS_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */ -#define CONFIG_SYS_DUARTA_BASE 0xff010000 -#define CONFIG_SYS_DUARTB_BASE 0xff018000 - -#define DUART_MBMR 0 -#define DUART_OR_VALUE (ORMASK(CONFIG_SYS_DUART_SIZE) | OR_G5LS| OR_BI) -#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V) -#define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE) -#define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE) - -#define CONFIG_RESET_ON_PANIC /* reset if system panic() */ - -#define CONFIG_ENV_IS_IN_FLASH -#ifdef CONFIG_ENV_IS_IN_FLASH - /* environment is in FLASH */ - #define CONFIG_ENV_ADDR 0xF8040000 /* AM29LV641 or AM29LV800BT */ - #define CONFIG_ENV_ADDR_REDUND 0xF8050000 /* AM29LV641 or AM29LV800BT */ - #define CONFIG_ENV_SECT_SIZE 0x00010000 - #define CONFIG_ENV_SIZE 0x00002000 -#else - /* environment is in EEPROM */ - #define CONFIG_ENV_IS_IN_EEPROM 1 - #define CONFIG_ENV_OFFSET 0 /* at beginning of EEPROM */ - #define CONFIG_ENV_SIZE 1024 /* Use only a part of it*/ -#endif - -#if 1 -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "delayabit" -#define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */ -#endif - -#endif /* __CONFIG_H */
These boards have been orphaned for a while and old enough.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
board/gen860t/Makefile | 8 - board/gen860t/README | 131 ------- board/gen860t/beeper.c | 183 ---------- board/gen860t/beeper.h | 13 - board/gen860t/flash.c | 628 --------------------------------- board/gen860t/fpga.c | 362 ------------------- board/gen860t/fpga.h | 26 -- board/gen860t/gen860t.c | 278 --------------- board/gen860t/ioport.c | 331 ------------------ board/gen860t/ioport.h | 26 -- board/gen860t/u-boot-flashenv.lds | 92 ----- board/gen860t/u-boot.lds | 87 ----- boards.cfg | 2 - doc/README.scrapyard | 1 + include/commproc.h | 21 -- include/configs/GEN860T.h | 712 -------------------------------------- include/status_led.h | 24 -- 17 files changed, 1 insertion(+), 2924 deletions(-) delete mode 100644 board/gen860t/Makefile delete mode 100644 board/gen860t/README delete mode 100644 board/gen860t/beeper.c delete mode 100644 board/gen860t/beeper.h delete mode 100644 board/gen860t/flash.c delete mode 100644 board/gen860t/fpga.c delete mode 100644 board/gen860t/fpga.h delete mode 100644 board/gen860t/gen860t.c delete mode 100644 board/gen860t/ioport.c delete mode 100644 board/gen860t/ioport.h delete mode 100644 board/gen860t/u-boot-flashenv.lds delete mode 100644 board/gen860t/u-boot.lds delete mode 100644 include/configs/GEN860T.h
diff --git a/board/gen860t/Makefile b/board/gen860t/Makefile deleted file mode 100644 index 86ae5e8..0000000 --- a/board/gen860t/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = gen860t.o flash.o beeper.o fpga.o ioport.o diff --git a/board/gen860t/README b/board/gen860t/README deleted file mode 100644 index 3ef8ae1..0000000 --- a/board/gen860t/README +++ /dev/null @@ -1,131 +0,0 @@ -This directory contains board specific code for a generic MPC860T based -embedded computer, called 'GEN860T'. The design is generic in the sense that -common, readily available components are used and that the architecture of the -system is relatively straightforward: - - One eight bit wide boot (FLASH) memory - 32 bit main memory using SDRAM - DOC 2000+ - Ethernet PHY - Some I2C peripheral devices: Atmel AT24C256 EEPROM, Maxim DS1337 RTC. - Some other miscellaneous peripherals - -NOTE: There are references to a XIlinx FPGA and Mil-Std 1553 databus in this -port. I guess the computer is not as generic as I first said 8) However, -these extras can be safely ignored. - -Given the GEN860T files, it should be pretty easy to reverse engineer the -hardware configuration, if that's useful to you. Hopefully, this code will -be useful to someone as a basis for a port to a new system or as a head start -on a custom design. If you end up using any of this, I would appreciate -hearing from you, especially if you discover bugs or find ways to improve the -quality of this U-Boot port. - -Here are the salient features of the system: -Clock : 33.3 Mhz oscillator -Processor core frequency : 66.6 Mhz if in 1:2:1 mode; can also run 1:1 -Bus frequency : 33.3 Mhz - -Main memory: - Type : SDRAM - Width : 32 bits - Size : 64 mibibytes - Chip : Two Micron MT48LC16M16A2TG-7E - CS : MPC860T CS1*/UPMA - UPMA CONNECTIONS: - SDRAM A10 : GPLA0* - SDRAM CAS* : GPLA2* - SDRAM WE* : GPLA3* - SDRAM RAS* : GPLA4* - -Boot memory: - Type : FLASH - Width : 8 bits - Size : 16 mibibytes - Chip : One Intel 28F128J3A (StrataFlash) - CS : MPC860T CS0*/GPCM (this is the "boot" chip select) - -EEPROM memory: - Type : Serial I2C EEPROM - Width : 8 bits - Size : 32 kibibytes - Chip : One Atmel AT25C256 - CS : 0x50 (external I2C address pins on device are tied to GND) - -Filesystem memory: - Type : NAND FLASH (Toshiba) - Width : 8 bits (i.e. interface to DOC is 8 bits) - Size : 32 mibibytes - Chip : One DiskOnCHip Millenium Plus (DOC 2000+) - CS : MPC860T CS2*/GPCM - -Network support: - MAC : MPC86OT FEC (Fast Ethernet Controller) - PHY : Intel LXT971A - MII Addr: 0x0 (hardwired on the board) - MII IRQ : - -Console: - RS-232 on SMC1 (Maxim MAX3232 LVCMOS-RS232 level shifter) - -Real Time Clock: - Type : Low power, I2C interface - Chip : Maxim DS1337 - CS : Address 0x68 on I2C bus - - The MPC860T's internal RTC has a defect in Mask rev D that increases - the current drain on the KAPWR line to 10 mA. Since this is an - unreasonable amount of current draw for a RTC, and Motorola does not - plan to fix this in future mask revisions, a serial (I2C) RTC that - works has been included instead. NOTE that the DS1337 can be - configured to output a 32768 Hz clock while the main power is on. - This clock output has been routed to the MPC860T's EXTAL pin to allow - the internal RTC to be used. NOTE also that due to yet another - defect in the rev D mask, the RTC does not operate reliably when the - internal RTC divisor is set to use a 32768 Hz reference. So just use - the I2C RTC. - -Miscellaneous: - Xilinx Virtex FPGA on CS3*/GPCM. - Virtex FPGA slave SelectMap interface on cs4*/UPMB. - Mil-Std 1553 databus interface on CS5*/GPCM. - Audio sounder (beeper) with digital volume control connected to SPKROUT. - -SC variant: - A reduced-feature version of the GEN860T port is also supported: GEN860T_SC. - The 'SC' variant only provides support for the Virtex FPGA, SDRAM main - memory, EEPROM and flash memory. The system clock frequency is reduced - to 24 MHz. - -Issues: - The DOC 2000+ returns 0x40 as its device ID when probed using the method - desxribed in the DOC datasheet. Unfortunately, the U-Boot DOC driver - does not recognize this device. As of this writing, it seems that MTD - does not support the DOC 2000+ either. - -Status: - Everything appears to work except DOC support. As of this writing, - David Woodhouse has stated on the MTD mailing list that he has no - knowledge of the DOC Millineum Plus and therfore there is no support - in MTD for this device. I wish I had known this sooner :( - -The GEN860T board specific files and configuration is based on the work -of others who have contributed to U-Boot. The copyright and license notices -of these authors have been retained wherever their code has been reused. -All new code to support the GEN860T board is: - - (C) Copyright 2001-2003 - Keith Outwater (keith_outwater@mvis.com) - -and the following license applies: - -SPDX-License-Identifier: GPL-2.0+ - -Thanks to Wolfgang Denk for a great software package and to everyone -who contributed to its development. - -Keith Outwater -Sr. Staff Engineer -Microvision, Inc. -keith_outwater@mvis.com -outwater@eskimo.com diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c deleted file mode 100644 index 0bebca9..0000000 --- a/board/gen860t/beeper.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * (C) Copyright 2002 - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <asm/8xx_immap.h> -#include <linux/ctype.h> - -/* - * Basic beeper support for the GEN860T board. The GEN860T includes - * an audio sounder driven by a Phillips TDA8551 amplifier. The - * TDA8551 features a digital volume control which uses a "trinary" - * input (high/high-Z/low) to set volume. The 860's SPKROUT pin - * drives the amplifier input. - */ - -/* - * Initialize beeper-related hardware. Initialize timer 1 for use with - * the beeper. Use 66 MHz internal clock with prescale of 33 to get - * 1 uS period per count. - * FIXME: we should really compute the prescale based on the reported - * core clock frequency. - */ -void init_beeper (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1; - immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK) - | TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN; - immap->im_cpmtimer.cpmt_tcn1 = 0; - immap->im_cpmtimer.cpmt_ter1 = 0xffff; - immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1; -} - -/* - * Set beeper frequency. Max allowed frequency is 2.5 KHz. This limit - * is mostly arbitrary, but the beeper isn't really much good beyond this - * frequency. - */ -void set_beeper_frequency (uint frequency) -{ -#define FREQ_LIMIT 2500 - - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* - * Compute timer ticks given desired frequency. The timer is set up - * to count 0.5 uS per tick and it takes two ticks per cycle (Hz). - */ - if (frequency > FREQ_LIMIT) - frequency = FREQ_LIMIT; - frequency = 1000000 / frequency; - immap->im_cpmtimer.cpmt_trr1 = (ushort) frequency; -} - -/* - * Turn the beeper on - */ -void beeper_on (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1; -} - -/* - * Turn the beeper off - */ -void beeper_off (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1; -} - -/* - * Increase or decrease the beeper volume. Volume can be set - * from off to full in 64 steps. To increase volume, the output - * pin is actively driven high, then returned to tristate. - * To decrease volume, output a low on the port pin (no need to - * change pin mode to tristate) then output a high to go back to - * tristate. - */ -void set_beeper_volume (int steps) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - int i; - - if (steps >= 0) { - for (i = 0; i < (steps >= 64 ? 64 : steps); i++) { - immap->im_cpm.cp_pbodr &= ~(0x80000000 >> 19); - udelay (1); - immap->im_cpm.cp_pbodr |= (0x80000000 >> 19); - udelay (1); - } - } else { - for (i = 0; i > (steps <= -64 ? -64 : steps); i--) { - immap->im_cpm.cp_pbdat &= ~(0x80000000 >> 19); - udelay (1); - immap->im_cpm.cp_pbdat |= (0x80000000 >> 19); - udelay (1); - } - } -} - -/* - * Check the environment to see if the beeper needs beeping. - * Controlled by a sequence of the form: - * freq/delta volume/on time/off time;... where: - * freq = frequency in Hz (0 - 2500) - * delta volume = volume steps up or down (-64 <= vol <= 64) - * on time = time in mS - * off time = time in mS - * - * Return 1 on success, 0 on failure - */ -int do_beeper (char *sequence) -{ -#define DELIMITER ';' - - int args[4]; - int i; - int val; - char *p = sequence; - char *tp; - - /* - * Parse the control sequence. This is a really simple parser - * without any real error checking. You can probably blow it - * up really easily. - */ - if (*p == '\0' || !isdigit (*p)) { - printf ("%s:%d: null or invalid string (%s)\n", - __FILE__, __LINE__, p); - return 0; - } - - i = 0; - while (*p != '\0') { - while (*p != DELIMITER) { - if (i > 3) - i = 0; - val = (int) simple_strtol (p, &tp, 0); - if (tp == p) { - printf ("%s:%d: no digits or bad format\n", - __FILE__, __LINE__); - return 0; - } else { - args[i] = val; - } - - i++; - if (*tp == DELIMITER) - p = tp; - else - p = ++tp; - } - p++; - - /* - * Well, we got something that has a chance of being correct - */ -#if 0 - for (i = 0; i < 4; i++) { - printf ("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i, - args[i]); - } - printf ("\n"); -#endif - set_beeper_frequency (args[0]); - set_beeper_volume (args[1]); - beeper_on (); - udelay (1000 * args[2]); - beeper_off (); - udelay (1000 * args[3]); - } - return 1; -} diff --git a/board/gen860t/beeper.h b/board/gen860t/beeper.h deleted file mode 100644 index 0734fca..0000000 --- a/board/gen860t/beeper.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * (C) Copyright 2002 - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void init_beeper(void); -void set_beeper_frequency(uint frequency); -void beeper_on(void); -void beeper_off(void); -void set_beeper_volume(int steps); -int do_beeper(char *sequence); diff --git a/board/gen860t/flash.c b/board/gen860t/flash.c deleted file mode 100644 index ca1ed3d..0000000 --- a/board/gen860t/flash.c +++ /dev/null @@ -1,628 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvsi.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/* - * Use buffered writes to flash by default - they are about 32x faster than - * single byte writes. - */ -#ifndef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER -#define CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER -#endif - -/* - * Max time to wait (in mS) for flash device to allocate a write buffer. - */ -#ifndef CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT -#define CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT 100 -#endif - -/* - * These functions support a single Intel StrataFlash device (28F128J3A) - * in byte mode only!. The flash routines are very basic and simple - * since there isn't really any remapping necessary. - */ - -/* - * Intel SCS (Scalable Command Set) command definitions - * (taken from 28F128J3A datasheet) - */ -#define SCS_READ_CMD 0xff -#define SCS_READ_ID_CMD 0x90 -#define SCS_QUERY_CMD 0x98 -#define SCS_READ_STATUS_CMD 0x70 -#define SCS_CLEAR_STATUS_CMD 0x50 -#define SCS_WRITE_BUF_CMD 0xe8 -#define SCS_PROGRAM_CMD 0x40 -#define SCS_BLOCK_ERASE_CMD 0x20 -#define SCS_BLOCK_ERASE_RESUME_CMD 0xd0 -#define SCS_PROGRAM_RESUME_CMD 0xd0 -#define SCS_BLOCK_ERASE_SUSPEND_CMD 0xb0 -#define SCS_SET_BLOCK_LOCK_CMD 0x60 -#define SCS_CLR_BLOCK_LOCK_CMD 0x60 - -/* - * SCS status/extended status register bit definitions - */ -#define SCS_SR7 0x80 -#define SCS_XSR7 0x80 - -/*---------------------------------------------------------------------*/ -#if 0 -#define DEBUG_FLASH -#endif - -#ifdef DEBUG_FLASH -#define PRINTF(fmt,args...) printf(fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info); -static int write_data8 (flash_info_t *info, ulong dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - * Initialize the flash memory. - */ -unsigned long -flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - for (i= 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* - * The gen860t board only has one FLASH memory device, so the - * FLASH Bank configuration is done statically. - */ - PRINTF("\n## Get flash bank 1 size @ 0x%08x\n", FLASH_BASE0_PRELIM); - size_b0 = flash_get_size((vu_char *)FLASH_BASE0_PRELIM, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0: " - "ID 0x%lx, Size = 0x%08lx = %ld MB\n", - flash_info[0].flash_id,size_b0, size_b0 << 20); - } - - PRINTF("## Before remap:\n" - " BR0: 0x%08x OR0: 0x%08x\n BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* - * Remap FLASH according to real size - */ - memctl->memc_or0 |= (-size_b0 & 0xFFFF8000); - memctl->memc_br0 |= (CONFIG_SYS_FLASH_BASE & BR_BA_MSK); - - PRINTF("## After remap:\n" - " BR0: 0x%08x OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0); - - /* - * Re-do sizing to get full correct info - */ - size_b0 = flash_get_size ((vu_char *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_info[0].size = size_b0; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* - * Monitor protection is ON by default - */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* - * Environment protection ON by default - */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - PRINTF("## Final Flash bank size: 0x%08lx\n",size_b0); - return (size_b0); -} - - -/*----------------------------------------------------------------------- - * Fill in the FLASH offset table - */ -static void -flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 1024 * 128; - } - return; - - default: - printf ("Don't know sector offsets for FLASH" - " type 0x%lx\n", info->flash_id); - return; - } -} - - -/*----------------------------------------------------------------------- - * Display FLASH device info - */ -void -flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("Intel "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1024 * 1024)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - - -/*----------------------------------------------------------------------- - * Get size and other information for a FLASH device. - * NOTE: The following code cannot be run from FLASH! - */ -static -ulong flash_get_size (vu_char *addr, flash_info_t *info) -{ -#define NO_FLASH 0 - - vu_char value[2]; - - /* - * Try to read the manufacturer ID - */ - addr[0] = SCS_READ_CMD; - addr[0] = SCS_READ_ID_CMD; - value[0] = addr[0]; - value[1] = addr[2]; - addr[0] = SCS_READ_CMD; - - PRINTF("Manuf. ID @ 0x%08lx: 0x%02x\n", (ulong)addr, value[0]); - switch (value[0]) { - case (INTEL_MANUFACT & 0xff): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (NO_FLASH); - } - - /* - * Read the device ID - */ - PRINTF("Device ID @ 0x%08lx: 0x%02x\n", (ulong)(&addr[2]), value[1]); - switch (value[1]) { - case (INTEL_ID_28F128J3A & 0xff): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 16 * 1024 * 1024; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (NO_FLASH); - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - return (info->size); -} - - -/*----------------------------------------------------------------------- - * Erase the specified sectors in the specified FLASH device - */ -int -flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* - * Start erase on unprotected sectors - */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_char *addr = (uchar *)(info->start[sect]); - vu_char status; - - /* - * Disable interrupts which might cause a timeout - */ - flag = disable_interrupts(); - - *addr = SCS_CLEAR_STATUS_CMD; - *addr = SCS_BLOCK_ERASE_CMD; - *addr = SCS_BLOCK_ERASE_RESUME_CMD; - - /* - * Re-enable interrupts if necessary - */ - if (flag) - enable_interrupts(); - - /* - * Wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - while (((status = *addr) & SCS_SR7) != SCS_SR7) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = SCS_BLOCK_ERASE_SUSPEND_CMD; - *addr = SCS_READ_CMD; - return 1; - } - - /* - * Show that we're waiting - */ - if ((now - last) > 1000) { /* 1 second */ - putc ('.'); - last = now; - } - } - *addr = SCS_READ_CMD; - } - } - printf (" done\n"); - return 0; -} - - -#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER -/* - * Allocate a flash buffer, fill it with data and write it to the flash. - * 0 - OK - * 1 - Timeout on buffer request - * - * NOTE: After the last call to this function, WSM status needs to be checked! - */ -static int -write_flash_buffer8(flash_info_t *info_p, vu_char *src_p, vu_char *dest_p, - uint count) -{ - vu_char *block_addr_p = NULL; - vu_char *start_addr_p = NULL; - ulong blocksize = info_p->size / (ulong)info_p->sector_count; - - int i; - uint time = get_timer(0); - - PRINTF("%s:%d: src: 0x%p dest: 0x%p count: %d\n", - __FUNCTION__, __LINE__, src_p, dest_p, count); - - /* - * What block are we in? We already know that the source address is - * in the flash address range, but we also can't cross a block boundary. - * We assume that the block does not cross a boundary (we'll check before - * calling this function). - */ - for (i = 0; i < info_p->sector_count; ++i) { - if ( ((ulong)dest_p >= info_p->start[i]) && - ((ulong)dest_p < (info_p->start[i] + blocksize)) ) { - PRINTF("%s:%d: Dest addr 0x%p is in block %d @ 0x%.8lx\n", - __FUNCTION__, __LINE__, dest_p, i, info_p->start[i]); - block_addr_p = (vu_char *)info_p->start[i]; - break; - } - } - - /* - * Request a buffer - */ - *block_addr_p = SCS_WRITE_BUF_CMD; - while ((*block_addr_p & SCS_XSR7) != SCS_XSR7) { - if (get_timer(time) > CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT) { - PRINTF("%s:%d: Buffer allocation timeout @ 0x%p (waited %d mS)\n", - __FUNCTION__, __LINE__, block_addr_p, - CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT); - return 1; - } - *block_addr_p = SCS_WRITE_BUF_CMD; - } - - /* - * Fill the buffer with data - */ - start_addr_p = dest_p; - *block_addr_p = count - 1; /* flash device wants count - 1 */ - PRINTF("%s:%d: Fill buffer at block addr 0x%p\n", - __FUNCTION__, __LINE__, block_addr_p); - for (i = 0; i < count; i++) { - *start_addr_p++ = *src_p++; - } - - /* - * Flush buffer to flash - */ - *block_addr_p = SCS_PROGRAM_RESUME_CMD; -#if 1 - time = get_timer(0); - while ((*block_addr_p & SCS_SR7) != SCS_SR7) { - if (get_timer(time) > CONFIG_SYS_FLASH_WRITE_TOUT) { - PRINTF("%s:%d: Write timeout @ 0x%p (waited %d mS)\n", - __FUNCTION__, __LINE__, block_addr_p, CONFIG_SYS_FLASH_WRITE_TOUT); - return 1; - } - } - -#endif - return 0; -} -#endif - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ -int -write_buff(flash_info_t *info_p, uchar *src_p, ulong addr, ulong count) -{ - int rc = 0; -#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER -#define FLASH_WRITE_BUF_SIZE 0x00000020 /* 32 bytes */ - int i; - uint bufs; - ulong buf_count; - vu_char *sp; - vu_char *dp; -#else - ulong wp; -#endif - - PRINTF("\n%s:%d: src: 0x%.8lx dest: 0x%.8lx size: %d (0x%.8lx)\n", - __FUNCTION__, __LINE__, (ulong)src_p, addr, (uint)count, count); - - if (info_p->flash_id == FLASH_UNKNOWN) { - return 4; - } - -#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER - sp = src_p; - dp = (uchar *)addr; - - /* - * For maximum performance, we want to align the start address to - * the beginning of a write buffer boundary (i.e. A4-A0 of the - * start address = 0). See how many bytes are required to get to a - * write-buffer-aligned address. If that number is non-zero, do - * non buffered writes of the non-aligned data. By doing non-buffered - * writes, we avoid the problem of crossing a block (sector) boundary - * with buffered writes. - */ - buf_count = FLASH_WRITE_BUF_SIZE - (addr & (FLASH_WRITE_BUF_SIZE - 1)); - if (buf_count == FLASH_WRITE_BUF_SIZE) { /* already on a boundary */ - buf_count = 0; - } - if (buf_count > count) { /* not a full buffers worth of data to write */ - buf_count = count; - } - count -= buf_count; - - PRINTF("%s:%d: Write buffer alignment count = %ld\n", - __FUNCTION__, __LINE__, buf_count); - while (buf_count-- >= 1) { - if ((rc = write_data8(info_p, (ulong)dp++, *sp++)) != 0) { - return (rc); - } - } - - PRINTF("%s:%d: count = %ld\n", __FUNCTION__, __LINE__, count); - if (count == 0) { /* all done */ - PRINTF("%s:%d: Less than 1 buffer (%d) worth of bytes\n", - __FUNCTION__, __LINE__, FLASH_WRITE_BUF_SIZE); - return (rc); - } - - /* - * Now that we are write buffer aligned, write full or partial buffers. - * The fact that we are write buffer aligned automatically avoids - * crossing a block address during a write buffer operation. - */ - bufs = count / FLASH_WRITE_BUF_SIZE; - PRINTF("%s:%d: %d (0x%x) buffers to write\n", __FUNCTION__, __LINE__, - bufs, bufs); - while (bufs >= 1) { - rc = write_flash_buffer8(info_p, sp, dp, FLASH_WRITE_BUF_SIZE); - if (rc != 0) { - PRINTF("%s:%d: ** Error writing buf %d\n", - __FUNCTION__, __LINE__, bufs); - return (rc); - } - bufs--; - sp += FLASH_WRITE_BUF_SIZE; - dp += FLASH_WRITE_BUF_SIZE; - } - - /* - * Do the leftovers - */ - i = count % FLASH_WRITE_BUF_SIZE; - PRINTF("%s:%d: %d (0x%x) leftover bytes\n", __FUNCTION__, __LINE__, i, i); - if (i > 0) { - rc = write_flash_buffer8(info_p, sp, dp, i); - } - - sp = (vu_char*)info_p->start[0]; - *sp = SCS_READ_CMD; - return (rc); - -#else - wp = addr; - while (count-- >= 1) { - if((rc = write_data8(info_p, wp++, *src_p++)) != 0) - return (rc); - } - return 0; -#endif -} - - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_data8 (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *)dest; - vu_char status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = SCS_PROGRAM_CMD; - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (((status = *addr) & SCS_SR7) != SCS_SR7) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = SCS_READ_CMD; - return (1); - } - } - *addr = SCS_READ_CMD; - return (0); -} - -/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c deleted file mode 100644 index dd0ef70..0000000 --- a/board/gen860t/fpga.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Virtex2 FPGA configuration support for the GEN860T computer - */ - -#include <common.h> -#include <virtex2.h> -#include <command.h> -#include "fpga.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_FPGA) - -#if 0 -#define GEN860T_FPGA_DEBUG -#endif - -#ifdef GEN860T_FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* - * Port bit numbers for the Selectmap controls - */ -#define FPGA_INIT_BIT_NUM 22 /* PB22 */ -#define FPGA_RESET_BIT_NUM 11 /* PC11 */ -#define FPGA_DONE_BIT_NUM 16 /* PB16 */ -#define FPGA_PROGRAM_BIT_NUM 7 /* PA7 */ - -/* Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - */ -xilinx_virtex2_slave_selectmap_fns fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_init_fn, - fpga_err_fn, - fpga_done_fn, - fpga_clk_fn, - fpga_cs_fn, - fpga_wr_fn, - fpga_read_data_fn, - fpga_write_data_fn, - fpga_busy_fn, - fpga_abort_fn, - fpga_post_config_fn -}; - -xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - {xilinx_virtex2, - slave_selectmap, - XILINX_XC2V3000_SIZE, - (void *) &fpga_fns, - 0} -}; - -/* - * Display FPGA revision information - */ -void print_fpga_revision (void) -{ - vu_long *rev_p = (vu_long *) 0x60000008; - - printf ("FPGA Revision 0x%.8lx" - " (Date %.2lx/%.2lx/%.2lx, Status "%.1lx", Version %.3lu)\n", - *rev_p, - ((*rev_p >> 28) & 0xf), - ((*rev_p >> 20) & 0xff), - ((*rev_p >> 12) & 0xff), - ((*rev_p >> 8) & 0xf), (*rev_p & 0xff)); -} - - -/* - * Perform a simple test of the FPGA to processor interface using the FPGA's - * inverting bus test register. The great thing about doing a read/write - * test on a register that inverts it's contents is that you avoid any - * problems with bus charging. - * Return 0 on failure, 1 on success. - */ -int test_fpga_ibtr (void) -{ - vu_long *ibtr_p = (vu_long *) 0x60000010; - vu_long readback; - vu_long compare; - int i; - int j; - int k; - int pass = 1; - - static const ulong bitpattern[] = { - 0xdeadbeef, /* magic ID pattern for debug */ - 0x00000001, /* single bit */ - 0x00000003, /* two adjacent bits */ - 0x00000007, /* three adjacent bits */ - 0x0000000F, /* four adjacent bits */ - 0x00000005, /* two non-adjacent bits */ - 0x00000015, /* three non-adjacent bits */ - 0x00000055, /* four non-adjacent bits */ - 0xaaaaaaaa, /* alternating 1/0 */ - }; - - for (i = 0; i < 1024; i++) { - for (j = 0; j < 31; j++) { - for (k = 0; - k < sizeof (bitpattern) / sizeof (bitpattern[0]); - k++) { - *ibtr_p = compare = (bitpattern[k] << j); - readback = *ibtr_p; - if (readback != ~compare) { - printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback); - pass = 0; - break; - } - } - if (!pass) - break; - } - if (!pass) - break; - } - if (pass) { - printf ("FPGA inverting bus test passed\n"); - print_fpga_revision (); - } else { - printf ("** FPGA inverting bus test failed\n"); - } - return pass; -} - - -/* - * Set the active-low FPGA reset signal. - */ -void fpga_reset (int assert) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__); - if (assert) { - immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM); - PRINTF ("asserted\n"); - } else { - immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM); - PRINTF ("deasserted\n"); - } -} - - -/* - * Initialize the SelectMap interface. We assume that the mode and the - * initial state of all of the port pins have already been set! - */ -void fpga_selectmap_init (void) -{ - PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, - __LINE__); - fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */ -} - - -/* - * Initialize the fpga. Return 1 on success, 0 on failure. - */ -int gen860t_init_fpga (void) -{ - int i; - - PRINTF ("%s:%d: Initialize FPGA interface\n", - __FUNCTION__, __LINE__); - fpga_init (); - fpga_selectmap_init (); - - for (i = 0; i < CONFIG_FPGA_COUNT; i++) { - PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); - fpga_add (fpga_xilinx, &fpga[i]); - } - return 1; -} - - -/* - * Set the FPGA's active-low SelectMap program line to the specified level - */ -int fpga_pgm_fn (int assert, int flush, int cookie) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__); - - if (assert) { - immap->im_ioport.iop_padat &= - ~(0x8000 >> FPGA_PROGRAM_BIT_NUM); - PRINTF ("asserted\n"); - } else { - immap->im_ioport.iop_padat |= - (0x8000 >> FPGA_PROGRAM_BIT_NUM); - PRINTF ("deasserted\n"); - } - return assert; -} - - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int fpga_init_fn (int cookie) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__); - if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) { - PRINTF ("high\n"); - return 0; - } else { - PRINTF ("low\n"); - return 1; - } -} - - -/* - * Test the state of the active-high FPGA DONE pin - */ -int fpga_done_fn (int cookie) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__); - if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) { - PRINTF ("high\n"); - return FPGA_SUCCESS; - } else { - PRINTF ("low\n"); - return FPGA_FAIL; - } -} - - -/* - * Read FPGA SelectMap data. - */ -int fpga_read_data_fn (unsigned char *data, int cookie) -{ - vu_char *p = (vu_char *) SELECTMAP_BASE; - - *data = *p; -#if 0 - PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data); -#endif - return (int) data; -} - - -/* - * Write data to the FPGA SelectMap port - */ -int fpga_write_data_fn (unsigned char data, int flush, int cookie) -{ - vu_char *p = (vu_char *) SELECTMAP_BASE; - -#if 0 - PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data); -#endif - *p = data; - return (int) data; -} - - -/* - * Abort and FPGA operation - */ -int fpga_abort_fn (int cookie) -{ - PRINTF ("%s:%d: FPGA program sequence aborted\n", - __FUNCTION__, __LINE__); - return FPGA_FAIL; -} - - -/* - * FPGA pre-configuration function. Just make sure that - * FPGA reset is asserted to keep the FPGA from starting up after - * configuration. - */ -int fpga_pre_config_fn (int cookie) -{ - PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - fpga_reset(true); - return 0; -} - - -/* - * FPGA post configuration function. Blip the FPGA reset line and then see if - * the FPGA appears to be running. - */ -int fpga_post_config_fn (int cookie) -{ - int rc; - - PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); - fpga_reset(true); - udelay (1000); - fpga_reset(false); - udelay (1000); - - /* - * Use the FPGA,s inverting bus test register to do a simple test of the - * processor interface. - */ - rc = test_fpga_ibtr (); - return rc; -} - - -/* - * Clock, chip select and write signal assert functions and error check - * and busy functions. These are only stubs because the GEN860T selectmap - * interface handles sequencing of control signals automatically (it uses - * a memory-mapped interface to the FPGA SelectMap port). The design of - * the interface guarantees that the SelectMap port cannot be overrun so - * no busy check is needed. A configuration error is signalled by INIT - * going low during configuration, so there is no need for a separate error - * function. - */ -int fpga_clk_fn (int assert_clk, int flush, int cookie) -{ - return assert_clk; -} - -int fpga_cs_fn (int assert_cs, int flush, int cookie) -{ - return assert_cs; -} - -int fpga_wr_fn (int assert_write, int flush, int cookie) -{ - return assert_write; -} - -int fpga_err_fn (int cookie) -{ - return 0; -} - -int fpga_busy_fn (int cookie) -{ - return 0; -} -#endif diff --git a/board/gen860t/fpga.h b/board/gen860t/fpga.h deleted file mode 100644 index 95c15c4..0000000 --- a/board/gen860t/fpga.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Virtex2 FPGA configuration support for the GEN860T computer - */ - -extern int gen860t_init_fpga(void); -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_init_fn(int cookie); -extern int fpga_err_fn(int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_cs_fn(int assert_cs, int flush, int cookie); -extern int fpga_wr_fn(int assert_write, int flush, int cookie); -extern int fpga_read_data_fn(unsigned char *data, int cookie); -extern int fpga_write_data_fn(unsigned char data, int flush, int cookie); -extern int fpga_busy_fn(int cookie); -extern int fpga_abort_fn(int cookie ); -extern int fpga_pre_config_fn(int cookie ); -extern int fpga_post_config_fn(int cookie ); diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c deleted file mode 100644 index fe139f4..0000000 --- a/board/gen860t/gen860t.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <virtex2.h> -#include <common.h> -#include <mpc8xx.h> -#include <asm/8xx_immap.h> -#include "beeper.h" -#include "fpga.h" -#include "ioport.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_STATUS_LED -#include <status_led.h> -#endif - -#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII) -#include <net.h> -#endif - -#if 0 -#define GEN860T_DEBUG -#endif - -#ifdef GEN860T_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* - * The following UPM init tables were generated automatically by - * Motorola's MCUINIT program. See the README file for UPM to - * SDRAM pin assignments if you want to type this data into - * MCUINIT in order to reverse engineer the waveforms. - */ - -/* - * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices - * (UPMA) and Virtex FPGA SelectMap interface (UPMB). - * NOTE that unused areas of the table are used to hold NOP, precharge - * and mode register set sequences. - * - */ -#define UPMA_NOP_ADDR 0x5 -#define UPMA_PRECHARGE_ADDR 0x6 -#define UPMA_MRS_ADDR 0x12 - -#define UPM_SINGLE_READ_ADDR 0x00 -#define UPM_BURST_READ_ADDR 0x08 -#define UPM_SINGLE_WRITE_ADDR 0x18 -#define UPM_BURST_WRITE_ADDR 0x20 -#define UPM_REFRESH_ADDR 0x30 - -const uint sdram_upm_table[] = { - /* single read (offset 0x00 in upm ram) */ - 0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05, - 0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff, - /* burst read (offset 0x08 in upm ram) */ - 0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00, - 0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff, - 0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4, - 0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff, - /* single write (offset 0x18 in upm ram) */ - 0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* burst write (offset 0x20 in upm ram) */ - 0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00, - 0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* refresh (offset 0x30 in upm ram) */ - 0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84, - 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* exception (offset 0x3C in upm ram) */ -}; - -const uint selectmap_upm_table[] = { - /* single read (offset 0x00 in upm ram) */ - 0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00, - 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff, - /* burst read (offset 0x08 in upm ram) */ - 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* single write (offset 0x18 in upm ram) */ - 0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* burst write (offset 0x20 in upm ram) */ - 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* refresh (offset 0x30 in upm ram) */ - 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* exception (offset 0x3C in upm ram) */ - 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff -}; - -/* - * Check board identity. Always successful (gives information only) - */ -int checkboard (void) -{ - char *s; - char buf[64]; - int i; - - i = getenv_f("board_id", buf, sizeof (buf)); - s = (i > 0) ? buf : NULL; - - if (s) { - printf ("%s ", s); - } else { - printf ("<unknown> "); - } - - i = getenv_f("serial#", buf, sizeof (buf)); - s = (i > 0) ? buf : NULL; - - if (s) { - printf ("S/N %s\n", s); - } else { - printf ("S/N <unknown>\n"); - } - - printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk)); - printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk)); - return (0); -} - -/* - * Initialize SDRAM - */ -phys_size_t initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - upmconfig (UPMA, - (uint *) sdram_upm_table, - sizeof (sdram_upm_table) / sizeof (uint) - ); - - /* - * Setup MAMR register - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - /* - * Map CS1* to SDRAM bank - */ - memctl->memc_or1 = CONFIG_SYS_OR1; - memctl->memc_br1 = CONFIG_SYS_BR1; - - /* - * Perform SDRAM initialization sequence: - * 1. Apply at least one NOP command - * 2. 100 uS delay (JEDEC standard says 200 uS) - * 3. Issue 4 precharge commands - * 4. Perform two refresh cycles - * 5. Program mode register - * - * Program SDRAM for standard operation, sequential burst, burst length - * of 4, CAS latency of 2. - */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (0) | UPMA_NOP_ADDR; - udelay (200); - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (4) | UPMA_PRECHARGE_ADDR; - - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (2) | UPM_REFRESH_ADDR; - - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (1) | UPMA_MRS_ADDR; - - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (0) | UPMA_NOP_ADDR; - /* - * Enable refresh - */ - memctl->memc_mamr |= MAMR_PTAE; - - return (SDRAM_SIZE); -} - -/* - * Disk On Chip (DOC) Millenium initialization. - * The DOC lives in the CS2* space - */ -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - printf ("Probing at 0x%.8x: ", DOC_BASE); - doc_probe (DOC_BASE); -} -#endif - -/* - * Miscellaneous intialization - */ -int misc_init_r (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - /* - * Set up UPMB to handle the Virtex FPGA SelectMap interface - */ - upmconfig (UPMB, (uint *) selectmap_upm_table, - sizeof (selectmap_upm_table) / sizeof (uint)); - - memctl->memc_mbmr = 0x0; - - config_mpc8xx_ioports (immr); - -#if defined(CONFIG_CMD_MII) - mii_init (); -#endif - -#if defined(CONFIG_FPGA) - gen860t_init_fpga (); -#endif - return 0; -} - -/* - * Final init hook before entering command loop. - */ -int last_stage_init (void) -{ -#if !defined(CONFIG_SC) - char buf[256]; - int i; - - /* - * Turn the beeper volume all the way down in case this is a warm boot. - */ - set_beeper_volume (-64); - init_beeper (); - - /* - * Read the environment to see what to do with the beeper - */ - i = getenv_f("beeper", buf, sizeof (buf)); - if (i > 0) { - do_beeper (buf); - } -#endif - return 0; -} - -/* - * Stub to make POST code happy. Can't self-poweroff, so just hang. - */ -void board_poweroff (void) -{ - puts ("### Please power off the board ###\n"); - while (1); -} diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c deleted file mode 100644 index 7cd209b..0000000 --- a/board/gen860t/ioport.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <asm/8xx_immap.h> -#include "ioport.h" - -#if 0 -#define IOPORT_DEBUG -#endif - -#ifdef IOPORT_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* - * The ioport configuration table. - */ -const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { - /* - * Port A configuration - * Pin Signal Type Active Initial state - * PA7 fpgaProgramLowOut Out Low High - * PA1 fpgaCoreVoltageFailLow In Low N/A - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ - /* PA15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA11 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA10 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA9 */ { 1, 0, 0, 1, 0, 0, 0 }, /* grn bicolor LED 1*/ - /* PA8 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 1*/ - /* PA7 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaProgramLow */ - /* PA6 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA5 */ { 1, 0, 0, 1, 0, 0, 0 }, /* grn bicolor LED 0*/ - /* PA4 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 0*/ - /* PA3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA2 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PA1 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaCoreVoltageFail*/ -#else - /* PA1 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#endif - /* PA0 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - }, - - /* - * Port B configuration - * Pin Signal Type Active Initial state - * PB14 docBusyLowIn In Low X - * PB15 gpio1Sig Out High Low - * PB16 fpgaDoneBi In High X - * PB17 swBitOkLowOut Out Low High - * PB19 speakerVolSig Out/Hi-Z High/Low High (Hi-Z) - * PB22 fpgaInitLowBi In Low X - * PB23 batteryOkSig In High X - * PB31 pulseCatcherClr Out High 0 - */ - { /* conf ppar psor pdir podr pdat pint function */ -#if !defined(CONFIG_SC) - /* PB31 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#else - /* PB31 */ { 1, 0, 0, 1, 0, 0, 0 }, /* pulseCatcherClr */ -#endif - /* PB30 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB29 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB28 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB27 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB26 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB25 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB24 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PB23 */ { 1, 0, 0, 0, 0, 0, 0 }, /* batteryOk */ -#else - /* PB23 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#endif - /* PB22 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaInitLowBi */ - /* PB21 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB20 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PB19 */ { 1, 0, 0, 1, 1, 1, 0 }, /* speakerVol */ -#else - /* PB19 */ { 0, 0, 0, 1, 1, 1, 0 }, /* */ -#endif - /* PB18 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB17 */ { 1, 0, 0, 1, 0, 1, 0 }, /* swBitOkLow */ - /* PB16 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaDone */ - /* PB15 */ { 1, 0, 0, 1, 0, 0, 0 }, /* gpio1 */ -#if !defined(CONFIG_SC) - /* PB14 */ { 1, 0, 0, 0, 0, 0, 0 } /* docBusyLow */ -#else - /* PB14 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ -#endif - }, - - /* - * Port C configuration - * Pin Signal Type Active Initial state - * PC4 i2cBus1EnSig Out High High - * PC5 i2cBus2EnSig Out High High - * PC6 gpio0Sig Out High Low - * PC8 i2cBus3EnSig Out High High - * PC10 i2cBus4EnSig Out High High - * PC11 fpgaResetLowOut Out Low High - * PC12 systemBitOkIn In High X - * PC15 selfDreqLow In Low X - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PC15 */ { 1, 0, 0, 0, 0, 0, 0 }, /* selfDreqLowIn */ - /* PC14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PC13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PC12 */ { 1, 0, 0, 0, 0, 0, 0 }, /* systemBitOkIn */ -#else - /* PC12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#endif - /* PC11 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaResetLowOut */ -#if !defined(CONFIG_SC) - /* PC10 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus4EnSig */ -#else - /* PC10 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ -#endif - /* PC9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PC8 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus3EnSig */ -#else - /* PC8 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ -#endif - /* PC7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PC6 */ { 1, 0, 0, 1, 0, 1, 0 }, /* gpio0 */ -#if !defined(CONFIG_SC) - /* PC5 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus2EnSig */ - /* PC4 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus1EnSig */ -#else - /* PC5 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ - /* PC4 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ -#endif - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - }, - - /* - * Port D configuration - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD11 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD10 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD8 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD6 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD5 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD4 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - } -}; - -/* - * Configure the MPC8XX I/O ports per the ioport configuration table - * (taken from ./arch/powerpc/cpu/mpc8260/cpu_init.c) - */ -void config_mpc8xx_ioports (volatile immap_t * immr) -{ - int portnum; - - for (portnum = 0; portnum < NUM_PORTS; portnum++) { - uint pmsk = 0, ppar = 0, psor = 0, pdir = 0; - uint podr = 0, pdat = 0, pint = 0; - uint msk = 1; - mpc8xx_iop_conf_t *iopc = - (mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0]; - mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS; - - /* - * For all ports except port B, ignore the two don't care entries - * in the configuration tables. - */ - if (portnum != 1) { - iopc = (mpc8xx_iop_conf_t *) & - iop_conf_tab[portnum][2]; - } - - /* - * NOTE: index 0 refers to pin 17, index 17 refers to pin 0 - */ - while (iopc < eiopc) { - if (iopc->conf) { - pmsk |= msk; - if (iopc->ppar) - ppar |= msk; - if (iopc->psor) - psor |= msk; - if (iopc->pdir) - pdir |= msk; - if (iopc->podr) - podr |= msk; - if (iopc->pdat) - pdat |= msk; - if (iopc->pint) - pint |= msk; - } - msk <<= 1; - iopc++; - } - - PRINTF ("%s:%d:\n portnum=%d ", __FUNCTION__, __LINE__, - portnum); -#ifdef IOPORT_DEBUG - switch (portnum) { - case 0: - printf ("(A)\n"); - break; - case 1: - printf ("(B)\n"); - break; - case 2: - printf ("(C)\n"); - break; - case 3: - printf ("(D)\n"); - break; - default: - printf ("(?)\n"); - break; - } -#endif - PRINTF (" ppar=0x%.8x pdir=0x%.8x podr=0x%.8x\n" - " pdat=0x%.8x psor=0x%.8x pint=0x%.8x pmsk=0x%.8x\n", - ppar, pdir, podr, pdat, psor, pint, pmsk); - - /* - * Have to handle the ioports on a port-by-port basis since there - * are three different flavors. - */ - if (pmsk != 0) { - uint tpmsk = ~pmsk; - - if (0 == portnum) { /* port A */ - immr->im_ioport.iop_papar &= tpmsk; - immr->im_ioport.iop_padat = - (immr->im_ioport. - iop_padat & tpmsk) | pdat; - immr->im_ioport.iop_padir = - (immr->im_ioport. - iop_padir & tpmsk) | pdir; - immr->im_ioport.iop_paodr = - (immr->im_ioport. - iop_paodr & tpmsk) | podr; - immr->im_ioport.iop_papar |= ppar; - } else if (1 == portnum) { /* port B */ - immr->im_cpm.cp_pbpar &= tpmsk; - immr->im_cpm.cp_pbdat = - (immr->im_cpm. - cp_pbdat & tpmsk) | pdat; - immr->im_cpm.cp_pbdir = - (immr->im_cpm. - cp_pbdir & tpmsk) | pdir; - immr->im_cpm.cp_pbodr = - (immr->im_cpm. - cp_pbodr & tpmsk) | podr; - immr->im_cpm.cp_pbpar |= ppar; - } else if (2 == portnum) { /* port C */ - immr->im_ioport.iop_pcpar &= tpmsk; - immr->im_ioport.iop_pcdat = - (immr->im_ioport. - iop_pcdat & tpmsk) | pdat; - immr->im_ioport.iop_pcdir = - (immr->im_ioport. - iop_pcdir & tpmsk) | pdir; - immr->im_ioport.iop_pcint = - (immr->im_ioport. - iop_pcint & tpmsk) | pint; - immr->im_ioport.iop_pcso = - (immr->im_ioport. - iop_pcso & tpmsk) | psor; - immr->im_ioport.iop_pcpar |= ppar; - } else if (3 == portnum) { /* port D */ - immr->im_ioport.iop_pdpar &= tpmsk; - immr->im_ioport.iop_pddat = - (immr->im_ioport. - iop_pddat & tpmsk) | pdat; - immr->im_ioport.iop_pddir = - (immr->im_ioport. - iop_pddir & tpmsk) | pdir; - immr->im_ioport.iop_pdpar |= ppar; - } - } - } - - PRINTF ("%s:%d: Port A:\n papar=0x%.4x padir=0x%.4x" - " paodr=0x%.4x\n padat=0x%.4x\n", __FUNCTION__, __LINE__, - immr->im_ioport.iop_papar, immr->im_ioport.iop_padir, - immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat); - PRINTF ("%s:%d: Port B:\n pbpar=0x%.8x pbdir=0x%.8x" - " pbodr=0x%.8x\n pbdat=0x%.8x\n", __FUNCTION__, __LINE__, - immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir, - immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat); - PRINTF ("%s:%d: Port C:\n pcpar=0x%.4x pcdir=0x%.4x" - " pcdat=0x%.4x\n pcso=0x%.4x pcint=0x%.4x\n ", - __FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar, - immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat, - immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint); - PRINTF ("%s:%d: Port D:\n pdpar=0x%.4x pddir=0x%.4x" - " pddat=0x%.4x\n", __FUNCTION__, __LINE__, - immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir, - immr->im_ioport.iop_pddat); -} diff --git a/board/gen860t/ioport.h b/board/gen860t/ioport.h deleted file mode 100644 index 4ac2aa4..0000000 --- a/board/gen860t/ioport.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define NUM_PORTS 4 -#define PORT_BITS 18 - -/* - * This structure provides configuration information for one port pin. - * We include all fields needed to initialize any of the ioports. - */ -typedef struct { - unsigned char conf:1; /* If 1, configure this port */ - unsigned char ppar:1; /* Port Pin Assignment Register */ - unsigned char psor:1; /* Port Special Options Register */ - unsigned char pdir:1; /* Port Data Direction Register */ - unsigned char podr:1; /* Port Open Drain Register */ - unsigned char pdat:1; /* Port Data Register */ - unsigned char pint:1; /* Port Interrupt Register */ -} mpc8xx_iop_conf_t; - -extern void config_mpc8xx_ioports(volatile immap_t *immr); diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds deleted file mode 100644 index 7a4a763..0000000 --- a/board/gen860t/u-boot-flashenv.lds +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Linker command file for the GEN860T board when the environment is - * stored in flash memory. - * - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* - * Read-only sections, merged into text segment: - */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* - * Read-write section, merged into data segment: - */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data: - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); - - .ppcenv: - { - . = env_offset; - common/env_embedded.o - } -} diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds deleted file mode 100644 index 3371c0a..0000000 --- a/board/gen860t/u-boot.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Linker command file for the GEN860T board. - * - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* - * Read-only sections, merged into text segment: - */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* - * Read-write section, merged into data segment: - */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index 46cf828..ea2b631 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1175,8 +1175,6 @@ Orphan powerpc mpc85xx - stx stxssa Orphan powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala kumar.gala@freescale.com Orphan powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala kumar.gala@freescale.com Orphan powerpc mpc8xx - - flagadm FLAGADM - Kári Davíðsson kd@flaga.is -Orphan powerpc mpc8xx - - gen860t GEN860T - Keith Outwater Keith_Outwater@mvis.com -Orphan powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater Keith_Outwater@mvis.com # The following were moved to "Orphan" in April, 2014 Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu nyet@zumanetworks.com # The following were moved to "Orphan" in March, 2014 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 5031bd1..ecfcd49 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +gen860t powerpc mpc8xx - - Keith Outwater Keith_Outwater@mvis.com sixnet powerpc mpc8xx - - Dave Ellis DGE@sixnetio.com svm_sc8xx powerpc mpc8xx - - John Zhan zhanz@sinovee.com stxxtc powerpc mpc8xx - - Dan Malek dan@embeddedalley.com diff --git a/include/commproc.h b/include/commproc.h index 4904311..b97cd24 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -556,27 +556,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002600) #endif /* CONFIG_FPS850L, CONFIG_FPS860L */
-/*** GEN860T **********************************************************/ -#if defined(CONFIG_GEN860T) -#undef SCC_ENET -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ -#endif /* CONFIG_GEN860T */ - /*** HERMES-PRO ******************************************************/
/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h deleted file mode 100644 index fd6c976..0000000 --- a/include/configs/GEN860T.h +++ /dev/null @@ -1,712 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config_GEN860T.h - board specific configuration options - */ - -#ifndef __CONFIG_GEN860T_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC860 -#define CONFIG_GEN860T - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/* - * Identify the board - */ -#if !defined(CONFIG_SC) -#define CONFIG_IDENT_STRING " B2" -#else -#define CONFIG_IDENT_STRING " SC" -#endif - -/* - * Don't depend on the RTC clock to determine clock frequency - - * the 860's internal rtc uses a 32.768 KHz clock which is - * generated by the DS1337 - and the DS1337 clock can be turned off. - */ -#if !defined(CONFIG_SC) -#define CONFIG_8xx_GCLK_FREQ 66600000 -#else -#define CONFIG_8xx_GCLK_FREQ 48000000 -#endif - -/* - * The RS-232 console port is on SMC1 - */ -#define CONFIG_8xx_CONS_SMC1 -#define CONFIG_BAUDRATE 38400 - -/* - * Print console information - */ -#undef CONFIG_SYS_CONSOLE_INFO_QUIET - -/* - * Set the autoboot delay in seconds. A delay of -1 disables autoboot - */ -#define CONFIG_BOOTDELAY 5 - -/* - * Pass the clock frequency to the Linux kernel in units of MHz - */ -#define CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_PREBOOT \ - "echo;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* - * Turn off echo for serial download by default. Allow baud rate to be changed - * for downloads - */ -#undef CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * Turn off the watchdog timer - */ -#undef CONFIG_WATCHDOG - -/* - * Do not reboot if a panic occurs - */ -#define CONFIG_PANIC_HANG - -/* - * Enable the status LED - */ -#define CONFIG_STATUS_LED - -/* - * Reset address. We pick an address such that when an instruction - * is executed at that address, a machine check exception occurs - */ -#define CONFIG_SYS_RESET_ADDRESS ((ulong) -1) - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * The GEN860T network interface uses the on-chip 10/100 FEC with - * an Intel LXT971A PHY connected to the 860T's MII. The PHY's - * MII address is hardwired on the board to zero. - */ -#define CONFIG_FEC_ENET -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII -#define CONFIG_MII_INIT 1 -#define CONFIG_PHY_ADDR 0 - -/* - * Set default IP stuff just to get bootstrap entries into the - * environment so that we can source the full default environment. - */ -#define CONFIG_ETHADDR 9a:52:63:15:85:25 -#define CONFIG_SERVERIP 10.0.4.201 -#define CONFIG_IPADDR 10.0.4.111 - -/* - * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to - * the MPC860T I2C interface. - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */ -#define CONFIG_ENV_EEPROM_SIZE (32 * 1024) - -/* - * Enable I2C and select the hardware/software driver - */ -#define CONFIG_HARD_I2C 1 /* CPM based I2C */ -#undef CONFIG_SYS_I2C_SOFT /* Bit-banged I2C */ - -#ifdef CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 /* clock speed in Hz */ -#define CONFIG_SYS_I2C_SLAVE 0xFE /* I2C slave address */ -#endif - -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if (bit) \ - immr->im_cpm.cp_pbdat |= PB_SDA; \ - else \ - immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if (bit) \ - immr->im_cpm.cp_pbdat |= PB_SCL; \ - else \ - immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -/* - * Allow environment overwrites by anyone - */ -#define CONFIG_ENV_OVERWRITE - -#if !defined(CONFIG_SC) -/* - * The MPC860's internal RTC is horribly broken in rev D masks. Three - * internal MPC860T circuit nodes were inadvertently left floating; this - * causes KAPWR current in power down mode to be three orders of magnitude - * higher than specified in the datasheet (from 10 uA to 10 mA). No - * reasonable battery can keep that kind RTC running during powerdown for any - * length of time, so we use an external RTC on the I2C bus instead. - */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -#else -/* - * No external RTC on SC variant, so we're stuck with the internal one. - */ -#define CONFIG_RTC_MPC8xx -#endif - -/* - * Power On Self Test support - */ -#define CONFIG_POST ( CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_UART | \ - CONFIG_SYS_POST_SPR ) - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_MII -#define CONFIG_CMD_BEDBUG - -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG -#endif - -/* - * There is no IDE/PCMCIA hardware support on the board. - */ -#undef CONFIG_IDE_PCMCIA -#undef CONFIG_IDE_LED -#undef CONFIG_IDE_RESET - -/* - * Enable the call to misc_init_r() for miscellaneous platform - * dependent initialization. - */ -#define CONFIG_MISC_INIT_R - -/* - * Enable call to last_stage_init() so we can twiddle some LEDS :) - */ -#define CONFIG_LAST_STAGE_INIT - -/* - * Virtex2 FPGA configuration support - */ -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_VIRTEX2 -#define CONFIG_SYS_FPGA_PROG_FEEDBACK - -/* - * Verbose help from command monitor. - */ -#define CONFIG_SYS_LONGHELP -#if !defined(CONFIG_SC) -#define CONFIG_SYS_PROMPT "B2> " -#else -#define CONFIG_SYS_PROMPT "SC> " -#endif - - -/* - * Use the "hush" command parser - */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Set buffer size for console I/O - */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif - -/* - * Print buffer size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* - * Maximum number of arguments that a command can accept - */ -#define CONFIG_SYS_MAXARGS 16 - -/* - * Boot argument buffer size - */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Default memory test range - */ -#define CONFIG_SYS_MEMTEST_START 0x0100000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (128 * 1024)) - -/* - * Select the more full-featured memory test - */ -#define CONFIG_SYS_ALT_MEMTEST - -/* - * Default load address - */ -#define CONFIG_SYS_LOAD_ADDR 0x01000000 - -/* - * Device memory map (after SDRAM remap to 0x0): - * - * CS Device Base Addr Size - * ---------------------------------------------------- - * CS0* Flash 0x40000000 64 M - * CS1* SDRAM 0x00000000 16 M - * CS2* Disk-On-Chip 0x50000000 32 K - * CS3* FPGA 0x60000000 64 M - * CS4* SelectMap 0x70000000 32 K - * CS5* Mil-Std 1553 I/F 0x80000000 32 K - * CS6* Unused - * CS7* Unused - * IMMR 860T Registers 0xfff00000 - */ - -/* - * Base addresses and block sizes - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -#define SDRAM_BASE 0x00000000 -#define SDRAM_SIZE (64 * 1024 * 1024) - -#define FLASH_BASE 0x40000000 -#define FLASH_SIZE (16 * 1024 * 1024) - -#define DOC_BASE 0x50000000 -#define DOC_SIZE (32 * 1024) - -#define FPGA_BASE 0x60000000 -#define FPGA_SIZE (64 * 1024 * 1024) - -#define SELECTMAP_BASE 0x70000000 -#define SELECTMAP_SIZE (32 * 1024) - -#define M1553_BASE 0x80000000 -#define M1553_SIZE (64 * 1024) - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE SDRAM_BASE - -/* - * FLASH organization - */ -#define CONFIG_SYS_FLASH_BASE FLASH_BASE -#define CONFIG_SYS_FLASH_SIZE FLASH_SIZE -#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -/* - * The timeout values are for an entire chip and are in milliseconds. - * Yes I know that the write timeout is huge. Accroding to the - * datasheet a single byte takes 630 uS (round to 1 ms) max at worst - * case VCC and temp after 100K programming cycles. It works out - * to 280 minutes (might as well be forever). - */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 5000) -#define CONFIG_SYS_FLASH_WRITE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1) - -/* - * Allow direct writes to FLASH from tftp transfers (** dangerous **) - */ -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -/* - * Reserve memory for U-Boot. - */ -#define CONFIG_SYS_MAX_UBOOT_SECTS 4 -#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -/* - * Select environment placement. NOTE that u-boot.lds must - * be edited if this is changed! - */ -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_IS_IN_EEPROM - -#if defined(CONFIG_ENV_IS_IN_EEPROM) -#define CONFIG_ENV_SIZE (2 * 1024) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_EEPROM_SIZE - (8 * 1024)) -#else -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE - -/* - * This ultimately gets passed right into the linker script, so we have to - * use a number :( - */ -#define CONFIG_ENV_OFFSET 0x060000 -#endif - -/* - * Reserve memory for malloc() - */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of above value */ -#endif - -/*------------------------------------------------------------------------ - * SYPCR - System Protection Control UM 11-9 - * ----------------------------------------------------------------------- - * SYPCR can only be written once after reset! - * - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ - SYPCR_SWE | \ - SYPCR_SWRI | \ - SYPCR_SWP \ - ) -#else -#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ - SYPCR_SWP \ - ) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration UM 11-6 - *----------------------------------------------------------------------- - * Set debug pin mux, enable SPKROUT and GPLB5*. - */ -#define CONFIG_SYS_SIUMCR ( SIUMCR_DBGC11 | \ - SIUMCR_DBPC11 | \ - SIUMCR_MLRC11 | \ - SIUMCR_GB5E \ - ) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control UM 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freeze enabled - */ -#define CONFIG_SYS_TBSCR ( TBSCR_REFA | \ - TBSCR_REFB | \ - TBSCR_TBF \ - ) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register UM 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC ( RTCSC_SEC | \ - RTCSC_ALR | \ - RTCSC_RTF | \ - RTCSC_RTE \ - ) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control UM 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR ( PISCR_PS | \ - PISCR_PITF \ - ) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit. Set MF for 1:2:1 mode. - */ -#define CONFIG_SYS_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \ - PLPRCR_SPLSS | \ - PLPRCR_TEXPS | \ - PLPRCR_TMIST \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register UM 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 - -#if !defined(CONFIG_SC) -#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ - SCCR_DFNL000 | \ - SCCR_DFNH000 \ - ) -#else -#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ - SCCR_DFNL000 | \ - SCCR_DFNH000 | \ - SCCR_RTDIV | \ - SCCR_RTSEL \ - ) -#endif - -/*----------------------------------------------------------------------- - * DER - Debug Enable Register UM 37-46 - *----------------------------------------------------------------------- - * Mask all events that can cause entry into debug mode - */ -#define CONFIG_SYS_DER 0 - -/* - * Initialize Memory Controller: - * - * BR0 and OR0 (FLASH memory) - */ -#define FLASH_BASE0_PRELIM FLASH_BASE - -/* - * Flash address mask - */ -#define CONFIG_SYS_PRELIM_OR_AM 0xfe000000 - -/* - * FLASH timing: - * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 - */ -#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | \ - OR_ACS_DIV2 | \ - OR_BI | \ - OR_SCY_2_CLK | \ - OR_TRLX | \ - OR_EHTR \ - ) - -#define CONFIG_SYS_OR0_PRELIM ( CONFIG_SYS_PRELIM_OR_AM | \ - CONFIG_SYS_OR_TIMING_FLASH \ - ) - -#define CONFIG_SYS_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \ - BR_MS_GPCM | \ - BR_PS_8 | \ - BR_V \ - ) - -/* - * SDRAM configuration - */ -#define CONFIG_SYS_OR1_AM 0xfc000000 -#define CONFIG_SYS_OR1 ( (CONFIG_SYS_OR1_AM & OR_AM_MSK) | \ - OR_CSNT_SAM \ - ) - -#define CONFIG_SYS_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \ - BR_MS_UPMA | \ - BR_PS_32 | \ - BR_V \ - ) - -/* - * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank - * of 256 MBit SDRAM - */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 - -/* - * Periodic timer for refresh @ 33 MHz system clock - */ -#define CONFIG_SYS_MAMR_PTA 64 - -/* - * MAMR settings for SDRAM - */ -#define CONFIG_SYS_MAMR_8COL ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \ - MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | \ - MAMR_DSA_1_CYCL | \ - MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | \ - MAMR_WLFA_1X | \ - MAMR_TLFA_4X \ - ) - -/* - * CS2* configuration for Disk On Chip: - * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, - * no burst. - */ -#define CONFIG_SYS_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ - OR_CSNT_SAM | \ - OR_ACS_DIV2 | \ - OR_BI | \ - OR_SCY_2_CLK | \ - OR_TRLX | \ - OR_EHTR \ - ) - -#define CONFIG_SYS_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V \ - ) - -/* - * CS3* configuration for FPGA: - * 33 MHz bus with SCY=15, no burst. - * The FPGA uses TA and TEA to terminate bus cycles, but we - * clear SETA and set the cycle length to a large number so that - * the cycle will still complete even if there is a configuration - * error that prevents TA from asserting on FPGA accesss. - */ -#define CONFIG_SYS_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \ - OR_SCY_15_CLK | \ - OR_BI \ - ) - -#define CONFIG_SYS_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \ - BR_PS_32 | \ - BR_MS_GPCM | \ - BR_V \ - ) -/* - * CS4* configuration for FPGA SelectMap configuration interface. - * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge - * of GCLK1_50 - */ -#define CONFIG_SYS_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ - OR_G5LS | \ - OR_BI \ - ) - -#define CONFIG_SYS_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \ - BR_PS_8 | \ - BR_MS_UPMB | \ - BR_V \ - ) - -/* - * CS5* configuration for Mil-Std 1553 databus interface. - * 33 MHz bus, GPCM, no burst. - * The 1553 interface uses TA and TEA to terminate bus cycles, - * but we clear SETA and set the cycle length to a large number so that - * the cycle will still complete even if there is a configuration - * error that prevents TA from asserting on FPGA accesss. - */ -#define CONFIG_SYS_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ - OR_SCY_15_CLK | \ - OR_EHTR | \ - OR_TRLX | \ - OR_CSNT_SAM | \ - OR_BI \ - ) - -#define CONFIG_SYS_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V \ - ) - -/* - * FEC interrupt assignment - */ -#define FEC_INTERRUPT SIU_LEVEL1 - -/* - * Sanity checks - */ -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#endif /* __CONFIG_GEN860T_H */ diff --git a/include/status_led.h b/include/status_led.h index c9d21d1..c1d2242 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -56,30 +56,6 @@ void status_led_set (int led, int state);
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-/***** GEN860T *********************************************************/ -#elif defined(CONFIG_GEN860T) - -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x0800 /* Red LED 0 is on PA.4 */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) -# define STATUS_LED_STATE STATUS_LED_OFF -# define STATUS_LED_BIT1 0x0400 /* Grn LED 1 is on PA.5 */ -# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 8) -# define STATUS_LED_STATE1 STATUS_LED_BLINKING -# define STATUS_LED_BIT2 0x0080 /* Red LED 2 is on PA.8 */ -# define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 4) -# define STATUS_LED_STATE2 STATUS_LED_OFF -# define STATUS_LED_BIT3 0x0040 /* Grn LED 3 is on PA.9 */ -# define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 4) -# define STATUS_LED_STATE3 STATUS_LED_OFF - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ -# define STATUS_LED_BOOT 1 /* Boot status on LED 1 */ - /***** IVMS8 **********************************************************/ #elif defined(CONFIG_IVMS8)
This board has been orphaned for a while and old enough.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
board/flagadm/Makefile | 8 - board/flagadm/flagadm.c | 134 -------- board/flagadm/flash.c | 687 ----------------------------------------- board/flagadm/u-boot.lds | 82 ----- board/flagadm/u-boot.lds.debug | 121 -------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/commproc.h | 21 -- include/configs/FLAGADM.h | 296 ------------------ 9 files changed, 1 insertion(+), 1350 deletions(-) delete mode 100644 board/flagadm/Makefile delete mode 100644 board/flagadm/flagadm.c delete mode 100644 board/flagadm/flash.c delete mode 100644 board/flagadm/u-boot.lds delete mode 100644 board/flagadm/u-boot.lds.debug delete mode 100644 include/configs/FLAGADM.h
diff --git a/board/flagadm/Makefile b/board/flagadm/Makefile deleted file mode 100644 index f2377c8..0000000 --- a/board/flagadm/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = flagadm.o flash.o diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c deleted file mode 100644 index 343cb77..0000000 --- a/board/flagadm/flagadm.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -#define _NOT_USED_ 0xFFFFFFFF - -/*Orginal table, GPL4 disabled*/ -const uint sdram_table[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00, - 0x1ff74c47, - /* Precharge */ - 0x1FF74C05, - _NOT_USED_, - _NOT_USED_, - /* burst read (offset 0x08 in upm ram) */ - 0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00, - 0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* single write (offset 0x18 in upm ram) */ - 0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47, - /* Load moderegister */ - 0x1FF74C34, /*Precharge*/ - 0xEFEA8C34, /*NOP*/ - 0x1FB54C35, /*Load moderegister*/ - _NOT_USED_, - - /* burst write (offset 0x20 in upm ram) */ - 0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00, - 0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - 0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04, - 0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - 0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* GPL5 driven every cycle */ -/* the display and the DSP */ -const uint dsp_disp_table[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004, - 0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05, - /* burst read (offset 0x08 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* single write (offset 0x18 in upm ram) */ - 0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004, - 0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05, - /* burst write (offset 0x20 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -int checkboard (void) -{ - puts ("Board: FlagaDM V3.0\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0; - - memctl->memc_or2 = CONFIG_SYS_OR2; - memctl->memc_br2 = CONFIG_SYS_BR2; - - udelay(100); - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = MPTPR_PTP_DIV16; - memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X; - - /*Do the initialization of the SDRAM*/ - /*Start with the precharge cycle*/ - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ - MCR_MLCF(1) | MCR_MAD(0x5)); - - /*Then we need two refresh cycles*/ - memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X; - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ - MCR_MLCF(2) | MCR_MAD(0x30)); - - /*Mode register programming*/ - memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/ - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ - MCR_MLCF(1) | MCR_MAD(0x1C)); - - /* That should do it, just enable the periodic refresh in burst of 4*/ - memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X; - memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS); - - size_b0 = 16*1024*1024; - - /* - * No bank 1 or 3 - * invalidate bank - */ - memctl->memc_br1 = 0; - memctl->memc_br3 = 0; - - upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint)); - - memctl->memc_mbmr = MBMR_GPL_B4DIS; - - memctl->memc_or4 = CONFIG_SYS_OR4; - memctl->memc_br4 = CONFIG_SYS_BR4; - - return (size_b0); -} diff --git a/board/flagadm/flash.c b/board/flagadm/flash.c deleted file mode 100644 index 46a2c9a..0000000 --- a/board/flagadm/flash.c +++ /dev/null @@ -1,687 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <flash.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -ulong flash_recognize (vu_long *base); -int write_word (flash_info_t *info, ulong dest, ulong data); -void flash_get_geometry (vu_long *base, flash_info_t *info); -void flash_unprotect(flash_info_t *info); -int _flash_real_protect(flash_info_t *info, long idx, int on); - - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - int i; - int rec; - - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff; - - flash_get_geometry ((vu_long*)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br0 & ~(BR_BA_MSK)); - - rec = flash_recognize((vu_long*)CONFIG_SYS_FLASH_BASE); - - if (rec == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - flash_info[0].size, flash_info[0].size<<20); - } - -#if CONFIG_SYS_FLASH_PROTECTION - /*Unprotect all the flash memory*/ - flash_unprotect(&flash_info[0]); -#endif - - *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff; - - return (flash_info[0].size); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_OFFSET, - CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - return (flash_info[0].size); -} - - -int flash_get_protect_status(flash_info_t * info, long idx) -{ - vu_short * base; - ushort res; - -#ifdef DEBUG - printf("\n Attempting to set protection info with %d sectors\n", info->sector_count); -#endif - - - base = (vu_short*)info->start[idx]; - - *(base) = 0xffff; - - *(base + 0x55) = 0x0098; - res = base[0x2]; - - *(base) = 0xffff; - - if(res != 0) - res = 1; - else - res = 0; - - return res; -} - -void flash_get_geometry (vu_long *base, flash_info_t *info) -{ - int i,j; - ulong ner = 0; - vu_short * sb = (vu_short*)base; - ulong offset = (ulong)base; - - /* Read Device geometry */ - - *sb = 0xffff; - - *sb = 0x0090; - - info->flash_id = ((ulong)base[0x0]); -#ifdef DEBUG - printf("Id is %x\n", (uint)(ulong)info->flash_id); -#endif - - *sb = 0xffff; - - *(sb+0x55) = 0x0098; - - info->size = 1 << (sb[0x27]); /* Read flash size */ - -#ifdef DEBUG - printf("Size is %x\n", (uint)(ulong)info->size); -#endif - - *sb = 0xffff; - - *(sb + 0x55) = 0x0098; - ner = sb[0x2c] ; /*Number of erase regions*/ - -#ifdef DEBUG - printf("Number of erase regions %x\n", (uint)ner); -#endif - - info->sector_count = 0; - - for(i = 0; i < ner; i++) - { - uint s; - uint count; - uint t1,t2,t3,t4; - - *sb = 0xffff; - - *(sb + 0x55) = 0x0098; - - t1 = sb[0x2d + i*4]; - t2 = sb[0x2e + i*4]; - t3 = sb[0x2f + i*4]; - t4 = sb[0x30 + i*4]; - - count = ((t1 & 0x00ff) | (((t2 & 0x00ff) << 8) & 0xff00) )+ 1; /*sector count*/ - s = ((t3 & 0x00ff) | (((t4 & 0x00ff) << 8) & 0xff00)) * 256;; /*Sector size*/ - -#ifdef DEBUG - printf("count and size %x, %x\n", count, s); - printf("sector count for erase region %d is %d\n", i, count); -#endif - for(j = 0; j < count; j++) - { -#ifdef DEBUG - printf("%x, ", (uint)offset); -#endif - info->start[ info->sector_count + j] = offset; - offset += s; - } - info->sector_count += count; - } - - if ((offset - (ulong)base) != info->size) - printf("WARNING reported size %x does not match to calculted size %x.\n" - , (uint)info->size, (uint)(offset - (ulong)base) ); - - /* Next check if there are any sectors protected.*/ - - for(i = 0; i < info->sector_count; i++) - info->protect[i] = flash_get_protect_status(info, i); - - *sb = 0xffff; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return ; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case INTEL_MANUFACT & FLASH_VENDMASK: - printf ("Intel "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case INTEL_ID_28F320C3B & FLASH_TYPEMASK: - printf ("28F320RC3(4 MB)\n"); - break; - case INTEL_ID_28F320J3A: - printf("28F320J3A (4 MB)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 4) == 0) - printf ("\n "); - printf (" %02d %08lX%s", - i, info->start[i], - info->protect[i]!=0 ? " (RO)" : " " - ); - } - printf ("\n"); - return ; -} - -ulong flash_recognize (vu_long *base) -{ - ulong id; - ulong res = FLASH_UNKNOWN; - vu_short * sb = (vu_short*)base; - - *sb = 0xffff; - - *sb = 0x0090; - id = base[0]; - - switch (id & 0x00FF0000) - { - case (MT_MANUFACT & 0x00FF0000): /* MT or => Intel */ - case (INTEL_ALT_MANU & 0x00FF0000): - res = FLASH_MAN_INTEL; - break; - default: - res = FLASH_UNKNOWN; - } - - *sb = 0xffff; - - return res; -} - -/*-----------------------------------------------------------------------*/ -#define INTEL_FLASH_STATUS_BLS 0x02 -#define INTEL_FLASH_STATUS_PSS 0x04 -#define INTEL_FLASH_STATUS_VPPS 0x08 -#define INTEL_FLASH_STATUS_PS 0x10 -#define INTEL_FLASH_STATUS_ES 0x20 -#define INTEL_FLASH_STATUS_ESS 0x40 -#define INTEL_FLASH_STATUS_WSMS 0x80 - -int flash_decode_status_bits(char status) -{ - int err = 0; - - if(!(status & INTEL_FLASH_STATUS_WSMS)) { - printf("Busy\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_ESS) { - printf("Erase suspended\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_ES) { - printf("Error in block erase\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_PS) { - printf("Error in programming\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_VPPS) { - printf("Vpp low, operation aborted\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_PSS) { - printf("Program is suspended\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_BLS) { - printf("Attempting to program/erase a locked sector\n"); - err = -1; - } - - if((status & INTEL_FLASH_STATUS_PS) && - (status & INTEL_FLASH_STATUS_ES) && - (status & INTEL_FLASH_STATUS_ESS)) { - printf("A command sequence error\n"); - return -1; - } - - return err; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr; - int flag, prot, sect; - ulong start, now; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - char tmp; - - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short *)(info->start[sect]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Single Block Erase Command */ - *addr = 0x0020; - /* Confirm */ - *addr = 0x00D0; - /* Resume Command, as per errata update */ - *addr = 0x00D0; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - *addr = 0x70; /*Read status register command*/ - tmp = (short)*addr & 0x00FF; /* Read the status */ - while (!(tmp & INTEL_FLASH_STATUS_WSMS)) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - start) > 1000) { /* every second */ - putc ('.'); - } - udelay(100000); /* 100 ms */ - *addr = 0x0070; /*Read status register command*/ - tmp = (short)*addr & 0x00FF; /* Read status */ - start = get_timer(0); - } - if( tmp & INTEL_FLASH_STATUS_ES ) - flash_decode_status_bits(tmp); - - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; /* Reset to read mode */ - } - } - - - printf (" done\n"); - return rcode; -} - -void flash_unprotect (flash_info_t *info) -{ - /*We can only unprotect the whole flash at once*/ - /*Therefore we must prevent the _flash_real_protect()*/ - /*from re-protecting sectors, that ware protected before */ - /*we called flash_real_protect();*/ - - int i; - - for(i = 0; i < info->sector_count; i++) - info->protect[i] = 0; - -#ifdef CONFIG_SYS_FLASH_PROTECTION - _flash_real_protect(info, 0, 0); -#endif -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_word (flash_info_t *info, ulong dest, ulong da) -{ - vu_short *addr = (vu_short *)dest; - ulong start; - char csr; - int flag; - int i; - union { - u32 data32; - u16 data16[2]; - } data; - - data.data32 = da; - - /* Check if Flash is (sufficiently) erased */ - if (((*addr & data.data16[0]) != data.data16[0]) || - ((*(addr+1) & data.data16[1]) != data.data16[1])) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for(i = 0; i < 2; i++) - { - /* Write Command */ - *addr = 0x0010; - - /* Write Data */ - *addr = data.data16[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - *addr = 0x0070; /*Read statusregister command */ - while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - *addr = 0x0070; /*Read statusregister command */ - } - if (csr & INTEL_FLASH_STATUS_PSS) { - printf ("CSR indicates write error (%0x) at %08lx\n", - csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x0050; - /* Reset to read array mode */ - *addr = 0xffff; - addr++; - } - - return (flag); -} - -int flash_real_protect(flash_info_t *info, long offset, int prot) -{ - int i, idx; - - for(idx = 0; idx < info->sector_count; idx++) - if(info->start[idx] == offset) - break; - - if(idx==info->sector_count) - return -1; - - if(prot == 0) { - /* Unprotect one sector, which means unprotect all flash - * and reprotect the other protected sectors. - */ - _flash_real_protect(info, 0, 0); /* Unprotects the whole flash*/ - info->protect[idx] = 0; - - for(i = 0; i < info->sector_count; i++) - if(info->protect[i]) - _flash_real_protect(info, i, 1); - } - else { - /* We can protect individual sectors */ - _flash_real_protect(info, idx, 1); - } - - for( i = 0; i < info->sector_count; i++) - info->protect[i] = flash_get_protect_status(info, i); - - return 0; -} - -int _flash_real_protect(flash_info_t *info, long idx, int prot) -{ - vu_short *addr; - int flag; - ushort cmd; - ushort tmp; - ulong now, start; - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) { - printf ("Can't change protection for unknown flash type %08lx - aborted\n", - info->flash_id); - return -1; - } - - if(prot == 0) { - /*Unlock the sector*/ - cmd = 0x00D0; - } - else { - /*Lock the sector*/ - cmd = 0x0001; - } - - addr = (vu_short *)(info->start[idx]); - - /* If chip is busy, wait for it */ - start = get_timer(0); - *addr = 0x0070; /*Read status register command*/ - tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/ - while(!(tmp & INTEL_FLASH_STATUS_WSMS)) { - /*Write State Machine Busy*/ - /*Wait untill done or timeout.*/ - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; /* Reset the chip */ - printf ("TTimeout\n"); - return 1; - } - *addr = 0x0070; - tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/ - start = get_timer(0); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Unlock block*/ - *addr = 0x0060; - - *addr = cmd; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - *addr = 0x0070; /*Read status register command*/ - tmp = ((ushort)(*addr)) & 0x00FF; /* Read the status */ - while (!(tmp & INTEL_FLASH_STATUS_WSMS)) { - /* Write State Machine Busy */ - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - start) > 1000) { /* every second */ - putc ('.'); - } - udelay(100000); /* 100 ms */ - *addr = 0x70; /*Read status register command*/ - tmp = (short)*addr & 0x00FF; /* Read status */ - start = get_timer(0); - } - if( tmp & INTEL_FLASH_STATUS_PS ) - flash_decode_status_bits(tmp); - - *addr =0x0050; /*Clear status register*/ - - /* reset to read mode */ - *addr = 0xffff; - - return 0; -} diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds deleted file mode 100644 index 7ae91ff..0000000 --- a/board/flagadm/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug deleted file mode 100644 index b0091db..0000000 --- a/board/flagadm/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index ea2b631..bdc3784 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1174,7 +1174,6 @@ Orphan powerpc mpc85xx - stx stxssa Orphan powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek dan@embeddedalley.com Orphan powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala kumar.gala@freescale.com Orphan powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala kumar.gala@freescale.com -Orphan powerpc mpc8xx - - flagadm FLAGADM - Kári Davíðsson kd@flaga.is # The following were moved to "Orphan" in April, 2014 Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu nyet@zumanetworks.com # The following were moved to "Orphan" in March, 2014 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index ecfcd49..be730f2 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +flagadm powerpc mpc8xx - - Kári Davíðsson kd@flaga.is gen860t powerpc mpc8xx - - Keith Outwater Keith_Outwater@mvis.com sixnet powerpc mpc8xx - - Dave Ellis DGE@sixnetio.com svm_sc8xx powerpc mpc8xx - - John Zhan zhanz@sinovee.com diff --git a/include/commproc.h b/include/commproc.h index b97cd24..b6a57ba 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -456,27 +456,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002c00) #endif /* CONFIG_BSEIP */
-/*** BSEIP **********************************************************/ - -#ifdef CONFIG_FLAGADM -/* Enet configuration for the FLAGADM */ -/* Enet on SCC2 */ - -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0400) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003400) -#endif /* CONFIG_FLAGADM */ - /*** ELPT860 *********************************************************/
#ifdef CONFIG_ELPT860 diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h deleted file mode 100644 index d93223f..0000000 --- a/include/configs/FLAGADM.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_FLAGADM 1 /* ...on a FLAGA DM */ -#define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */ -#define CONFIG_8xx_CONS_SMC2 1 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#undef CONFIG_CLOCKS_IN_MHZ - -#if 0 -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp" -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/ram ip=off panic=1;" \ - "bootm 40040000 400e0000" -#else -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp panic=1" -#define CONFIG_BOOTCOMMAND "bootp 0x400000; bootm 0x400000" -#endif /* 0|1*/ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -/*#define CONFIG_WATCHDOG*/ /* watchdog enabled */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_IMI -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_NET - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "EEG> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x40040000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This is a litlebit wasteful, but one sector is 128kb and we have to - * assigne a whole sector for the environment, so that we can safely - * erase and write it without disturbing the boot sector - */ -#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif -#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before - * running in RAM. - */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#ifdef CONFIG_WATCHDOG -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \ - SIUMCR_MLRC01 | SIUMCR_GB5E) -#define CONFIG_SYS_SIUMCR (CONFIG_SYS_PRE_SIUMCR | SIUMCR_DLK) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit miltiplier of 0x00b i.e. operation clock is - * 4MHz * (0x00b+1) = 4MHz * 12 = 48MHz - */ -#define CONFIG_SYS_PLPRCR (0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR ( SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -#define CONFIG_SYS_DER 0 - -/* - * In the Flaga DM we have: - * Flash on BR0/OR0/CS0a at 0x40000000 - * Display on BR1/OR1/CS1 at 0x20000000 - * SDRAM on BR2/OR2/CS2 at 0x00000000 - * Free BR3/OR3/CS3 - * DSP1 on BR4/OR4/CS4 at 0x80000000 - * DSP2 on BR5/OR5/CS5 at 0xa0000000 - * - * For now we just configure the Flash and the SDRAM and leave the others - * untouched. -*/ - -#define CONFIG_SYS_FLASH_PROTECTION 0 - -#define FLASH_BASE0 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_OR_AM 0xff000000 /* OR addr mask */ -#define CONFIG_SYS_OR_ATM 0x00006000 - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | \ - OR_SCY_3_CLK | OR_TRLX | OR_EHTR ) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_ATM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR2 and OR2 (SDRAM) - * - */ -#define SDRAM_BASE2 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM ( 0x00000800 ) - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CONFIG_SYS_BR2 CONFIG_SYS_BR2_PRELIM -#define CONFIG_SYS_OR2 CONFIG_SYS_OR2_PRELIM - -/* - * MAMR settings for SDRAM - */ -#define CONFIG_SYS_MAMR_48_SDR (CONFIG_SYS_MAMR_PTA | MAMR_WLFA_1X | MAMR_RLFA_1X \ - | MAMR_G0CLA_A11) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 0x0F000000 - -/* - * BR4 and OR4 (DSP1) - * - * We do not wan't preliminary setup of the DSP, anyway we need the - * UPMB setup correctly before we can access the DSP. - * -*/ -#define DSP_BASE 0x80000000 - -#define CONFIG_SYS_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS) -#define CONFIG_SYS_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V ) - -#endif /* __CONFIG_H */
This board has been orphaned for a while and old enough.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
arch/powerpc/cpu/mpc8260/ether_fcc.c | 17 - board/sacsng/Makefile | 8 - board/sacsng/clkinit.c | 1009 --------------------------------- board/sacsng/clkinit.h | 103 ---- board/sacsng/flash.c | 507 ----------------- board/sacsng/ioconfig.h | 217 ------- board/sacsng/sacsng.c | 848 --------------------------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/sacsng.h | 1039 ---------------------------------- 10 files changed, 1 insertion(+), 3749 deletions(-) delete mode 100644 board/sacsng/Makefile delete mode 100644 board/sacsng/clkinit.c delete mode 100644 board/sacsng/clkinit.h delete mode 100644 board/sacsng/flash.c delete mode 100644 board/sacsng/ioconfig.h delete mode 100644 board/sacsng/sacsng.c delete mode 100644 include/configs/sacsng.h
diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c index d93a991..c641cf3 100644 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c @@ -670,23 +670,6 @@ eth_loopback_test (void) immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\ CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\ CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16; -#elif defined(CONFIG_SACSng) - /* - * Attention: this is board-specific - * 1, FCC2 - */ -# define FCC_START_LOOP 1 -# define FCC_END_LOOP 1 - - /* - * Attention: this is board-specific - * - FCC2 Rx-CLK is CLK13 - * - FCC2 Tx-CLK is CLK14 - */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14; #else #error "eth_loopback_test not supported on your board" #endif diff --git a/board/sacsng/Makefile b/board/sacsng/Makefile deleted file mode 100644 index 95e6b8d..0000000 --- a/board/sacsng/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := sacsng.o flash.o clkinit.o diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c deleted file mode 100644 index 2a28037..0000000 --- a/board/sacsng/clkinit.c +++ /dev/null @@ -1,1009 +0,0 @@ -/* - * (C) Copyright 2002 - * Custom IDEAS, Inc. <www.cideas.com> - * Jon Diekema diekema@cideas.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> -#include <asm/cpm_8260.h> -#include <configs/sacsng.h> - -#include "clkinit.h" - -DECLARE_GLOBAL_DATA_PTR; - -int Daq64xSampling = 0; - - -void Daq_BRG_Reset(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - *brg_ptr |= CPM_BRG_RST; - *brg_ptr &= ~CPM_BRG_RST; -} - -void Daq_BRG_Disable(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - *brg_ptr &= ~CPM_BRG_EN; -} - -void Daq_BRG_Enable(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - *brg_ptr |= CPM_BRG_EN; -} - -uint Daq_BRG_Get_Div16(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - if (*brg_ptr & CPM_BRG_DIV16) { - /* DIV16 active */ - return true; - } - else { - /* DIV16 inactive */ - return false; - } -} - -void Daq_BRG_Set_Div16(uint brg, uint div16) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - if (div16) { - /* DIV16 active */ - *brg_ptr |= CPM_BRG_DIV16; - } - else { - /* DIV16 inactive */ - *brg_ptr &= ~CPM_BRG_DIV16; - } -} - -uint Daq_BRG_Get_Count(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - uint brg_cnt; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - /* Get the clock divider - * - * Note: A clock divider of 0 means divide by 1, - * therefore we need to add 1 to the count. - */ - brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT; - brg_cnt++; - if (*brg_ptr & CPM_BRG_DIV16) { - brg_cnt *= 16; - } - - return (brg_cnt); -} - -void Daq_BRG_Set_Count(uint brg, uint brg_cnt) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - /* - * Note: A clock divider of 0 means divide by 1, - * therefore we need to subtract 1 from the count. - */ - if (brg_cnt > 4096) { - /* Prescale = Divide by 16 */ - *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) | - (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT); - *brg_ptr |= CPM_BRG_DIV16; - } - else { - /* Prescale = Divide by 1 */ - *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) | - ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT); - *brg_ptr &= ~CPM_BRG_DIV16; - } -} - -uint Daq_BRG_Get_ExtClk(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT); -} - -char* Daq_BRG_Get_ExtClk_Description(uint brg) -{ - uint extc; - - extc = Daq_BRG_Get_ExtClk(brg); - - switch (brg + 1) { - case 1: - case 2: - case 5: - case 6: { - switch (extc) { - case 0: { - return ("BRG_INT"); - } - case 1: { - return ("CLK3"); - } - case 2: { - return ("CLK5"); - } - } - return ("??1245??"); - } - case 3: - case 4: - case 7: - case 8: { - switch (extc) { - case 0: { - return ("BRG_INT"); - } - case 1: { - return ("CLK9"); - } - case 2: { - return ("CLK15"); - } - } - return ("??3478??"); - } - } - return ("??9876??"); -} - -void Daq_BRG_Set_ExtClk(uint brg, uint extc) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) | - ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK); -} - -uint Daq_BRG_Rate(uint brg) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint *brg_ptr; - uint brg_cnt; - uint brg_freq = 0; - - brg_ptr = (uint *)&immr->im_brgc1; - brg_ptr += brg; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg_ptr += (brg - 4); - } - - brg_cnt = Daq_BRG_Get_Count(brg); - - switch (Daq_BRG_Get_ExtClk(brg)) { - case CPM_BRG_EXTC_CLK3: - case CPM_BRG_EXTC_CLK5: { - brg_freq = brg_cnt; - break; - } - default: { - brg_freq = (uint)BRG_INT_CLK / brg_cnt; - } - } - return (brg_freq); -} - -uint Daq_Get_SampleRate(void) -{ - /* - * Read the BRG's to return the actual sample rate. - */ - return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR)); -} - -void Daq_Init_Clocks(int sample_rate, int sample_64x) -{ - volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */); - uint mclk_divisor; /* MCLK divisor */ - int flag; /* Interrupt state */ - - /* Save off the clocking data */ - Daq64xSampling = sample_64x; - - /* - * Limit the sample rate to some sensible values. - */ - if (sample_rate > MAX_64x_SAMPLE_RATE) { - sample_rate = MAX_64x_SAMPLE_RATE; - } - if (sample_rate < MIN_SAMPLE_RATE) { - sample_rate = MIN_SAMPLE_RATE; - } - - /* - * Initialize the MCLK/SCLK/LRCLK baud rate generators. - */ - - /* Setup MCLK */ - Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK); - - /* Setup SCLK */ -# ifdef RUN_SCLK_ON_BRG_INT - Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK); -# else - Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9); -# endif - - /* Setup LRCLK */ -# ifdef RUN_LRCLK_ON_BRG_INT - Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK); -# else - Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5); -# endif - - /* - * Dynamically adjust MCLK based on the new sample rate. - */ - - /* Compute the divisors */ - mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR); - - /* - * Disable interrupt and save the current state - */ - flag = disable_interrupts(); - - /* Setup MCLK */ - Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor); - - /* Setup SCLK */ -# ifdef RUN_SCLK_ON_BRG_INT - Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR); -# else - Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR); -# endif - -# ifdef RUN_LRCLK_ON_BRG_INT - Daq_BRG_Set_Count(LRCLK_BRG, - mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR); -# else - Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR); -# endif - - /* - * Restore the Interrupt state - */ - if (flag) { - enable_interrupts(); - } - - /* Enable the clock drivers */ - iopa->pdat &= ~SLRCLK_EN_MASK; -} - -void Daq_Stop_Clocks(void) - -{ -#ifdef TIGHTEN_UP_BRG_TIMING - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - register uint mclk_brg; /* MCLK BRG value */ - register uint sclk_brg; /* SCLK BRG value */ - register uint lrclk_brg; /* LRCLK BRG value */ - unsigned long flag; /* Interrupt flags */ -#endif - -# ifdef TIGHTEN_UP_BRG_TIMING - /* - * Obtain MCLK BRG reset/disabled value - */ -# if (MCLK_BRG == 0) - mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 1) - mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 2) - mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 3) - mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 4) - mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 5) - mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 6) - mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 7) - mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif - - /* - * Obtain SCLK BRG reset/disabled value - */ -# if (SCLK_BRG == 0) - sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 1) - sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 2) - sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 3) - sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 4) - sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 5) - sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 6) - sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 7) - sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif - - /* - * Obtain LRCLK BRG reset/disabled value - */ -# if (LRCLK_BRG == 0) - lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 1) - lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 2) - lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 3) - lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 4) - lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 5) - lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 6) - lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 7) - lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif - - /* - * Disable interrupt and save the current state - */ - flag = disable_interrupts(); - - /* - * Set reset on MCLK BRG - */ -# if (MCLK_BRG == 0) - *IM_BRGC1 = mclk_brg; -# endif -# if (MCLK_BRG == 1) - *IM_BRGC2 = mclk_brg; -# endif -# if (MCLK_BRG == 2) - *IM_BRGC3 = mclk_brg; -# endif -# if (MCLK_BRG == 3) - *IM_BRGC4 = mclk_brg; -# endif -# if (MCLK_BRG == 4) - *IM_BRGC5 = mclk_brg; -# endif -# if (MCLK_BRG == 5) - *IM_BRGC6 = mclk_brg; -# endif -# if (MCLK_BRG == 6) - *IM_BRGC7 = mclk_brg; -# endif -# if (MCLK_BRG == 7) - *IM_BRGC8 = mclk_brg; -# endif - - /* - * Set reset on SCLK BRG - */ -# if (SCLK_BRG == 0) - *IM_BRGC1 = sclk_brg; -# endif -# if (SCLK_BRG == 1) - *IM_BRGC2 = sclk_brg; -# endif -# if (SCLK_BRG == 2) - *IM_BRGC3 = sclk_brg; -# endif -# if (SCLK_BRG == 3) - *IM_BRGC4 = sclk_brg; -# endif -# if (SCLK_BRG == 4) - *IM_BRGC5 = sclk_brg; -# endif -# if (SCLK_BRG == 5) - *IM_BRGC6 = sclk_brg; -# endif -# if (SCLK_BRG == 6) - *IM_BRGC7 = sclk_brg; -# endif -# if (SCLK_BRG == 7) - *IM_BRGC8 = sclk_brg; -# endif - - /* - * Set reset on LRCLK BRG - */ -# if (LRCLK_BRG == 0) - *IM_BRGC1 = lrclk_brg; -# endif -# if (LRCLK_BRG == 1) - *IM_BRGC2 = lrclk_brg; -# endif -# if (LRCLK_BRG == 2) - *IM_BRGC3 = lrclk_brg; -# endif -# if (LRCLK_BRG == 3) - *IM_BRGC4 = lrclk_brg; -# endif -# if (LRCLK_BRG == 4) - *IM_BRGC5 = lrclk_brg; -# endif -# if (LRCLK_BRG == 5) - *IM_BRGC6 = lrclk_brg; -# endif -# if (LRCLK_BRG == 6) - *IM_BRGC7 = lrclk_brg; -# endif -# if (LRCLK_BRG == 7) - *IM_BRGC8 = lrclk_brg; -# endif - - /* - * Clear reset on MCLK BRG - */ -# if (MCLK_BRG == 0) - *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 1) - *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 2) - *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 3) - *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 4) - *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 5) - *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 6) - *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 7) - *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST; -# endif - - /* - * Clear reset on SCLK BRG - */ -# if (SCLK_BRG == 0) - *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 1) - *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 2) - *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 3) - *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 4) - *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 5) - *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 6) - *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 7) - *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST; -# endif - - /* - * Clear reset on LRCLK BRG - */ -# if (LRCLK_BRG == 0) - *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 1) - *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 2) - *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 3) - *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 4) - *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 5) - *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 6) - *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 7) - *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST; -# endif - - /* - * Restore the Interrupt state - */ - if (flag) { - enable_interrupts(); - } -# else - /* - * Reset the clocks - */ - Daq_BRG_Reset(MCLK_BRG); - Daq_BRG_Reset(SCLK_BRG); - Daq_BRG_Reset(LRCLK_BRG); -# endif -} - -void Daq_Start_Clocks(int sample_rate) - -{ -#ifdef TIGHTEN_UP_BRG_TIMING - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - register uint mclk_brg; /* MCLK BRG value */ - register uint sclk_brg; /* SCLK BRG value */ - register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */ - register uint real_lrclk_brg; /* Permanent LRCLK BRG value */ - uint lrclk_brg; /* LRCLK BRG value */ - unsigned long flags; /* Interrupt flags */ - uint sclk_cnt; /* SCLK count */ - uint delay_cnt; /* Delay count */ -#endif - -# ifdef TIGHTEN_UP_BRG_TIMING - /* - * Obtain the enabled MCLK BRG value - */ -# if (MCLK_BRG == 0) - mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 1) - mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 2) - mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 3) - mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 4) - mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 5) - mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 6) - mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 7) - mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif - - /* - * Obtain the enabled SCLK BRG value - */ -# if (SCLK_BRG == 0) - sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 1) - sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 2) - sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 3) - sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 4) - sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 5) - sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 6) - sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 7) - sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif - - /* - * Obtain the enabled LRCLK BRG value - */ -# if (LRCLK_BRG == 0) - lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 1) - lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 2) - lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 3) - lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 4) - lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 5) - lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 6) - lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 7) - lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif - - /* Save off the real LRCLK value */ - real_lrclk_brg = lrclk_brg; - - /* Obtain the current SCLK count */ - sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1; - - /* Compute the delay as a function of SCLK count */ - delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6; - if (DaqSampleRate == 43402) { - delay_cnt++; - } - - /* Clear out the count */ - temp_lrclk_brg = sclk_brg & ~0x00001FFE; - - /* Insert the count */ - temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE; - - /* - * Disable interrupt and save the current state - */ - flag = disable_interrupts(); - - /* - * Enable MCLK BRG - */ -# if (MCLK_BRG == 0) - *IM_BRGC1 = mclk_brg; -# endif -# if (MCLK_BRG == 1) - *IM_BRGC2 = mclk_brg; -# endif -# if (MCLK_BRG == 2) - *IM_BRGC3 = mclk_brg; -# endif -# if (MCLK_BRG == 3) - *IM_BRGC4 = mclk_brg; -# endif -# if (MCLK_BRG == 4) - *IM_BRGC5 = mclk_brg; -# endif -# if (MCLK_BRG == 5) - *IM_BRGC6 = mclk_brg; -# endif -# if (MCLK_BRG == 6) - *IM_BRGC7 = mclk_brg; -# endif -# if (MCLK_BRG == 7) - *IM_BRGC8 = mclk_brg; -# endif - - /* - * Enable SCLK BRG - */ -# if (SCLK_BRG == 0) - *IM_BRGC1 = sclk_brg; -# endif -# if (SCLK_BRG == 1) - *IM_BRGC2 = sclk_brg; -# endif -# if (SCLK_BRG == 2) - *IM_BRGC3 = sclk_brg; -# endif -# if (SCLK_BRG == 3) - *IM_BRGC4 = sclk_brg; -# endif -# if (SCLK_BRG == 4) - *IM_BRGC5 = sclk_brg; -# endif -# if (SCLK_BRG == 5) - *IM_BRGC6 = sclk_brg; -# endif -# if (SCLK_BRG == 6) - *IM_BRGC7 = sclk_brg; -# endif -# if (SCLK_BRG == 7) - *IM_BRGC8 = sclk_brg; -# endif - - /* - * Enable LRCLK BRG (1st time - temporary) - */ -# if (LRCLK_BRG == 0) - *IM_BRGC1 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 1) - *IM_BRGC2 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 2) - *IM_BRGC3 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 3) - *IM_BRGC4 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 4) - *IM_BRGC5 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 5) - *IM_BRGC6 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 6) - *IM_BRGC7 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 7) - *IM_BRGC8 = temp_lrclk_brg; -# endif - - /* - * Enable LRCLK BRG (2nd time - permanent) - */ -# if (LRCLK_BRG == 0) - *IM_BRGC1 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 1) - *IM_BRGC2 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 2) - *IM_BRGC3 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 3) - *IM_BRGC4 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 4) - *IM_BRGC5 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 5) - *IM_BRGC6 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 6) - *IM_BRGC7 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 7) - *IM_BRGC8 = real_lrclk_brg; -# endif - - /* - * Restore the Interrupt state - */ - if (flag) { - enable_interrupts(); - } -# else - /* - * Enable the clocks - */ - Daq_BRG_Enable(LRCLK_BRG); - Daq_BRG_Enable(SCLK_BRG); - Daq_BRG_Enable(MCLK_BRG); -# endif -} - -void Daq_Display_Clocks(void) - -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint mclk_divisor; /* Detected MCLK divisor */ - uint sclk_divisor; /* Detected SCLK divisor */ - - printf("\nBRG:\n"); - if (immr->im_brgc4 != 0) { - printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n", - immr->im_brgc4, - (uint)&(immr->im_brgc4), - Daq_BRG_Get_Count(3), - Daq_BRG_Get_ExtClk(3), - Daq_BRG_Get_ExtClk_Description(3)); - } - if (immr->im_brgc8 != 0) { - printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n", - immr->im_brgc8, - (uint)&(immr->im_brgc8), - Daq_BRG_Get_Count(7), - Daq_BRG_Get_ExtClk(7), - Daq_BRG_Get_ExtClk_Description(7)); - } - if (immr->im_brgc6 != 0) { - printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n", - immr->im_brgc6, - (uint)&(immr->im_brgc6), - Daq_BRG_Get_Count(5), - Daq_BRG_Get_ExtClk(5), - Daq_BRG_Get_ExtClk_Description(5)); - } - if (immr->im_brgc1 != 0) { - printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n", - immr->im_brgc1, - (uint)&(immr->im_brgc1), - Daq_BRG_Get_Count(0), - Daq_BRG_Get_ExtClk(0), - Daq_BRG_Get_ExtClk_Description(0)); - } - if (immr->im_brgc2 != 0) { - printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n", - immr->im_brgc2, - (uint)&(immr->im_brgc2), - Daq_BRG_Get_Count(1), - Daq_BRG_Get_ExtClk(1), - Daq_BRG_Get_ExtClk_Description(1)); - } - if (immr->im_brgc3 != 0) { - printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n", - immr->im_brgc3, - (uint)&(immr->im_brgc3), - Daq_BRG_Get_Count(2), - Daq_BRG_Get_ExtClk(2), - Daq_BRG_Get_ExtClk_Description(2)); - } - if (immr->im_brgc5 != 0) { - printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n", - immr->im_brgc5, - (uint)&(immr->im_brgc5), - Daq_BRG_Get_Count(4), - Daq_BRG_Get_ExtClk(4), - Daq_BRG_Get_ExtClk_Description(4)); - } - if (immr->im_brgc7 != 0) { - printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n", - immr->im_brgc7, - (uint)&(immr->im_brgc7), - Daq_BRG_Get_Count(6), - Daq_BRG_Get_ExtClk(6), - Daq_BRG_Get_ExtClk_Description(6)); - } - -# ifdef RUN_SCLK_ON_BRG_INT - mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG); -# else - mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG); -# endif -# ifdef RUN_LRCLK_ON_BRG_INT - sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG); -# else - sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG); -# endif - - printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor); - printf("\tMCLK %8d Hz, or %3dx SCLK, or %3dx LRCLK\n", - Daq_BRG_Rate(MCLK_BRG), - mclk_divisor, - mclk_divisor * sclk_divisor); -# ifdef RUN_SCLK_ON_BRG_INT - printf("\tSCLK %8d Hz, or %3dx LRCLK\n", - Daq_BRG_Rate(SCLK_BRG), - sclk_divisor); -# else - printf("\tSCLK %8d Hz, or %3dx LRCLK\n", - Daq_BRG_Rate(MCLK_BRG) / mclk_divisor, - sclk_divisor); -# endif -# ifdef RUN_LRCLK_ON_BRG_INT - printf("\tLRCLK %8d Hz\n", - Daq_BRG_Rate(LRCLK_BRG)); -# else -# ifdef RUN_SCLK_ON_BRG_INT - printf("\tLRCLK %8d Hz\n", - Daq_BRG_Rate(SCLK_BRG) / sclk_divisor); -# else - printf("\tLRCLK %8d Hz\n", - Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor)); -# endif -# endif - printf("\n"); -} diff --git a/board/sacsng/clkinit.h b/board/sacsng/clkinit.h deleted file mode 100644 index 3f759dd..0000000 --- a/board/sacsng/clkinit.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2002 - * Custom IDEAS, Inc. <www.cideas.com> - * Jon Diekema diekema@cideas.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SLRCLK_EN_MASK 0x00040000 /* PA13 - SLRCLK_EN* */ - -#define MIN_SAMPLE_RATE 4000 /* Minimum sample rate */ -#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */ -#define MAX_64x_SAMPLE_RATE 86805 /* Maximum 64x sample rate */ - -#define KHZ ((uint)1000) -#define MHZ ((uint)(1000 * KHZ)) - -#define MCLK_BRG 3 /* MCLK, Master CLocK for the A/D & D/A */ -#define SCLK_BRG 7 /* SCLK, Sample CLocK for the A/D & D/A */ -#define LRCLK_BRG 5 /* LRCLK, L/R CLocK for the A/D & D/A */ - /* 0 == BRG1 (used for SMC1) */ - /* 1 == BRG2 (used for SMC2) */ - /* 2 == BRG3 (used for SCC1) */ - /* 3 == BRG4 (MCLK) */ - /* 4 == BRG5 */ - /* 5 == BRG6 (LRCLK) */ - /* 6 == BRG7 */ - /* 7 == BRG8 (SCLK) */ - -#define MCLK_DIVISOR 4 /* SCLK = MCLK / MCLK_DIVISOR */ -#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128) - /* LRCLK = SCLK / SCLK_DIVISOR */ - -#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing */ -#define RUN_SCLK_ON_BRG_INT /* Run SCLK on BRG_INT instead of MCLK */ - /* The 8260 (Mask B.3) seems to have */ - /* problems generating SCLK from MCLK */ - /* via CLK9. */ -#define RUN_LRCLK_ON_BRG_INT /* Run LRCLK on BRG_INT instead of SCLK */ - /* The 8260 (Mask B.3) seems to have */ - /* problems generating LRCLK from SCLK */ - -#define NUM_LRCLKS_TO_STABILIZE 1 /* Number of LRCLK period (sample) */ - /* to wait for the clock to stabilize */ - -#define CPM_CLK (gd->bd->bi_cpmfreq) -#define DFBRG 4 -#define BRG_INT_CLK (CPM_CLK * 2 / DFBRG) - /* BRG = CPM * 2 / DFBRG (Sect 9.8) */ - /* BRG = CPM * 2 / 4 */ - /* BRG = CPM / 2 */ - -#define CPM_BRG_EXTC_MASK ((uint)0x0000C000) -#define CPM_BRG_EXTC_SHIFT 14 - -#define CPM_BRG_DIV16_MASK ((uint)0x00000001) -#define CPM_BRG_DIV16_SHIFT 1 - -#define CPM_BRG_EXTC_BRGCLK 0 -#define CPM_BRG_EXTC_CLK3 1 -#define CPM_BRG_EXTC_CLK9 CPM_BRG_EXTC_CLK3 -#define CPM_BRG_EXTC_CLK5 2 -#define CPM_BRG_EXTC_CLK15 CPM_BRG_EXTC_CLK5 - -#define IM_BRGC1 ((uint *)0xf00119f0) -#define IM_BRGC2 ((uint *)0xf00119f4) -#define IM_BRGC3 ((uint *)0xf00119f8) -#define IM_BRGC4 ((uint *)0xf00119fc) -#define IM_BRGC5 ((uint *)0xf00115f0) -#define IM_BRGC6 ((uint *)0xf00115f4) -#define IM_BRGC7 ((uint *)0xf00115f8) -#define IM_BRGC8 ((uint *)0xf00115fc) - -/* - * External declarations - */ - -extern int Daq64xSampling; - -extern void Daq_BRG_Reset(uint brg); -extern void Daq_BRG_Run(uint brg); - -extern void Daq_BRG_Disable(uint brg); -extern void Daq_BRG_Enable(uint brg); - -extern uint Daq_BRG_Get_Div16(uint brg); -extern void Daq_BRG_Set_Div16(uint brg, uint div16); - -extern uint Daq_BRG_Get_Count(uint brg); -extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt); - -extern uint Daq_BRG_Get_ExtClk(uint brg); -extern char* Daq_BRG_Get_ExtClk_Description(uint brg); -extern void Daq_BRG_Set_ExtClk(uint brg, uint extc); - -extern uint Daq_BRG_Rate(uint brg); - -extern uint Daq_Get_SampleRate(void); - -extern void Daq_Init_Clocks(int sample_rate, int sample_64x); -extern void Daq_Stop_Clocks(void); -extern void Daq_Start_Clocks(int sample_rate); -extern void Daq_Display_Clocks(void); diff --git a/board/sacsng/flash.c b/board/sacsng/flash.c deleted file mode 100644 index 686fb22..0000000 --- a/board/sacsng/flash.c +++ /dev/null @@ -1,507 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <configs/sacsng.h> - - -#undef DEBUG - -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif -#ifndef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#endif - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_short *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b0 = flash_get_size((vu_short *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - size_b1 = flash_get_size((vu_short *)CONFIG_SYS_FLASH1_BASE, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[1]); -#endif - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - /* - * We only report the primary flash for U-Boot's use. - */ - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_short *addr, flash_info_t *info) -{ - short i; - ushort value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAAAA; - addr[0x02AA] = 0x5555; - addr[0x0555] = 0x9090; - __asm__ __volatile__(" sync\n "); - - value = addr[0]; -#ifdef DEBUG - printf("Flash manufacturer 0x%04X\n", value); -#endif - - if(value == (ushort)AMD_MANUFACT) { - info->flash_id = FLASH_MAN_AMD; - } else if (value == (ushort)FUJ_MANUFACT) { - info->flash_id = FLASH_MAN_FUJ; - } else { -#ifdef DEBUG - printf("Unknown flash manufacturer 0x%04X\n", value); -#endif - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ -#ifdef DEBUG - printf("Flash type 0x%04X\n", value); -#endif - - if(value == (ushort)AMD_ID_LV400T) { - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; /* => 0.5 MB */ - } else if(value == (ushort)AMD_ID_LV400B) { - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; /* => 0.5 MB */ - } else if(value == (ushort)AMD_ID_LV800T) { - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; /* => 1 MB */ - } else if(value == (ushort)AMD_ID_LV800B) { - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; /* => 1 MB */ - } else if(value == (ushort)AMD_ID_LV160T) { - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; /* => 2 MB */ - } else if(value == (ushort)AMD_ID_LV160B) { - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; /* => 2 MB */ - } else if(value == (ushort)AMD_ID_LV320T) { - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; /* => 4 MB */ - } else if(value == (ushort)AMD_ID_LV320B) { - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; /* => 4 MB */ - } else { -#ifdef DEBUG - printf("Unknown flash type 0x%04X\n", value); - info->size = CONFIG_SYS_FLASH_SIZE; -#else - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ -#endif - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i - 3) * 0x00010000); - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + (i * 0x00010000); - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned short *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned short *)info->start[0]; - - } - - addr[0] = 0xF0F0; /* reset bank */ - __asm__ __volatile__(" sync\n "); - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAA; - addr[0x02AA] = 0x5555; - addr[0x0555] = 0x8080; - addr[0x0555] = 0xAAAA; - addr[0x02AA] = 0x5555; - __asm__ __volatile__(" sync\n "); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short*)(info->start[sect]); - addr[0] = 0x3030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_short*)(info->start[l_sect]); - while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - addr[0] = 0xF0F0; /* reset bank */ - __asm__ __volatile__(" sync\n "); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_short*)info->start[0]; - addr[0] = 0xF0F0; /* reset bank */ - __asm__ __volatile__(" sync\n "); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - ulong start; - int flag; - int j; - - /* Check if Flash is (sufficiently) erased */ - if (((*(vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* The original routine was designed to write 32 bit words to - * 32 bit wide memory. We have 16 bit wide memory so we do - * two writes. We write the LSB first at dest+2 and then the - * MSB at dest (lousy big endian). - */ - dest += 2; - for(j = 0; j < 2; j++) { - addr[0x0555] = 0xAAAA; - addr[0x02AA] = 0x5555; - addr[0x0555] = 0xA0A0; - __asm__ __volatile__(" sync\n "); - - *((vu_short *)dest) = (ushort)data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while (*(vu_short *)dest != (ushort)data) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - dest -= 2; - data >>= 16; - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/sacsng/ioconfig.h b/board/sacsng/ioconfig.h deleted file mode 100644 index ac8f152..0000000 --- a/board/sacsng/ioconfig.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * I/O Port configuration table - * - * If conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#ifdef SKIP -#undef SKIP -#endif - -#ifdef CONF -#undef CONF -#endif - -#ifdef DIN -#undef DIN -#endif - -#ifdef DOUT -#undef DOUT -#endif - -#ifdef GPIO -#undef GPIO -#endif - -#ifdef SPEC -#undef SPEC -#endif - -#ifdef ACTV -#undef ACTV -#endif - -#ifdef OPEN -#undef OPEN -#endif - -#define SKIP 0 /* SKIP over this port */ -#define CONF 1 /* CONFiguration the port */ - -#define DIN 0 /* PDIRx 0: Direction IN */ -#define DOUT 1 /* PDIRx 1: Direction OUT */ - -#define GPIO 0 /* PPARx 0: General Purpose I/O */ -#define SPEC 1 /* PPARx 1: dedicated to a peripheral function, */ - /* i.e. the port has a SPECial use. */ - -#define ACTV 0 /* PODRx 0: ACTiVely driven as an output */ -#define OPEN 1 /* PODRx 1: OPEN-drain driver */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS8* */ - /* PA30 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS7* */ - /* PA29 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS6* */ - /* PA28 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS5* */ - /* PA27 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS4* */ - /* PA26 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS3* */ - /* PA25 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS2* */ - /* PA24 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS1* */ - /* PA23 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* ODIS_EN* */ - /* PA22 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED2_EN* */ - /* PA21 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED1_EN* */ - /* PA20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED3_EN* */ - /* PA19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED2_EN* */ - /* PA18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* PLED1_EN* */ - /* PA17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PA16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* DAC_RST* */ - /* PA15 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH34SDATA_PU */ - /* PA14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH12SDATA_PU */ - /* PA13 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SLRCLK_EN* */ - /* PA12 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4ACDC* */ - /* PA11 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4TEDS* */ - /* PA10 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4XTDS* */ - /* PA9 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3ACDC* */ - /* PA8 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3TEDS* */ - /* PA7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3XTDS* */ - /* PA6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2ACDC* */ - /* PA5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2TEDS* */ - /* PA4 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2XTDS* */ - /* PA3 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PA2 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1ACDC* */ - /* PA1 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1TEDS* */ - /* PA0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 } /* MTRX_1XTDS* */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TX_ER */ - /* PB30 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_DV */ - /* PB29 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* FCC2 MII_TX_EN */ - /* PB28 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_ER */ - /* PB27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_COL */ - /* PB26 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_CRS */ - /* PB25 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD3 */ - /* PB24 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD2 */ - /* PB23 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD1 */ - /* PB22 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD0 */ - /* PB21 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD0 */ - /* PB20 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD1 */ - /* PB19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD2 */ - /* PB18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD3 */ - /* PB17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB14 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDC1, BSDATA_ADC12 */ - /* PB13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB12 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCC1, LRCLK */ - /* PB11 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1TXDD1, RSDATA_DAC12 */ - /* PB10 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDD1, BSDATA_ADC34 */ - /* PB9 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB8 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCD1, LRCLK */ - /* PB7 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* XCITE_SHDN */ - /* PB5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* TRIGGER */ - /* PB4 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* ARM */ - /* PB3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PB2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PB1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PB0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC30 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC29 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK3, MCLK */ - /* PC28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* TOUT2* */ -#ifdef QQQ - /* PC28 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TOUT2* */ -#endif - /* PC27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK5, SCLK */ - /* PC26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC25 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK7, SCLK */ - /* PC24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC23 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK9, MCLK */ - /* PC22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC21 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO6 (LRCLK) */ - /* PC20 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK13, MII_RXCLK */ - /* PC18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK14, MII_TXCLK */ - /* PC17 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO8 (SCLK) */ - /* PC16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC15 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC2_TX */ - /* PC14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB3 */ - /* PC11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* TDM_STRB4 */ - /* PC9 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN3 */ - /* PC8 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN2 */ - /* PC7 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN1 */ - /* PC6 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC5 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN2* */ - /* PC4 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN1* */ - /* PC3 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* MUSH_STAT */ - /* PC2 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* OUTDRV_STAT */ - /* PC1 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* PHY_MDIO */ - /* PC0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PHY_MDC */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SCC1_RX */ - /* PD30 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SCC1_TX */ - /* PD29 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD27 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD25 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD23 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD21 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_ADC_CS* */ - /* PD19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_DAC_CS* */ -#if defined(CONFIG_SOFT_SPI) - /* PD18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_CLK */ - /* PD17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_MOSI */ - /* PD16 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* SPI_MISO */ -#else - /* PD18 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_CLK */ - /* PD17 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_MOSI */ - /* PD16 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* SPI_MISO */ -#endif -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* I2C_SDA */ - /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* I2C_SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SDA */ - /* PD14 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SDA */ - /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SCL */ -#endif -#endif - /* PD13 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB1 */ - /* PD12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB2 */ - /* PD11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* BRGO4 (MCLK) */ - /* PD9 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC1_TX */ - /* PD8 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SMC1_RX */ - /* PD7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */ - /* PD6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */ - /* PD5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */ - /* PD4 */ { CONF, SPEC, 1, DOUT, ACTV, 1 }, /* SMC2_RX */ - /* PD3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PD2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PD1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PD0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */ - } -}; diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c deleted file mode 100644 index 91c4987..0000000 --- a/board/sacsng/sacsng.c +++ /dev/null @@ -1,848 +0,0 @@ -/* - * (C) Copyright 2002 - * Custom IDEAS, Inc. <www.cideas.com> - * Gerald Van Baren vanbaren@cideas.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/u-boot.h> -#include <ioports.h> -#include <mpc8260.h> -#include <i2c.h> -#include <spi.h> -#include <command.h> - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -#include <status_led.h> -#endif - -#ifdef CONFIG_ETHER_LOOPBACK_TEST -extern void eth_loopback_test(void); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - -#include "clkinit.h" -#include "ioconfig.h" /* I/O configuration table */ - -/* - * PBI Page Based Interleaving - * PSDMR_PBI page based interleaving - * 0 bank based interleaving - * External Address Multiplexing (EAMUX) adds a clock to address cycles - * (this can help with marginal board layouts) - * PSDMR_EAMUX adds a clock - * 0 no extra clock - * Buffer Command (BUFCMD) adds a clock to command cycles. - * PSDMR_BUFCMD adds a clock - * 0 no extra clock - */ -#define CONFIG_PBI PSDMR_PBI -#define PESSIMISTIC_SDRAM 0 -#define EAMUX 0 /* EST requires EAMUX */ -#define BUFCMD 0 - -/* - * ADC/DAC Defines: - */ -#define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */ -#define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */ -#define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */ -#define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */ -#define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */ - -/* - * ADC Defines: - */ -#define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */ -#define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */ - -#define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */ -#define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */ - -#define ADC_VREF_CAP 100 /* VREF capacitor in uF */ -#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */ -#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */ -#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500) - /* Wait at least 4100 LRCLK's */ - -#define ADC_REG1_FRAME_START 0x80 /* Frame start */ -#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */ -#define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */ -#define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */ - -#define ADC_REG2_128x 0x80 /* Oversample at 128x */ -#define ADC_REG2_CAL 0x40 /* System calibration enable */ -#define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */ -#define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */ -#define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */ -#define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */ -#define ADC_REG2_DFS 0x02 /* Digital format select */ -#define ADC_REG2_MUTE 0x01 /* Mute */ - -#define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */ -#define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */ -#define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */ -#define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */ -#define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */ -#define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */ -#define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */ - -/* - * DAC Defines: - */ - -#define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */ - -#define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */ -#define DAC_RESET_DELAY 100 /* DAC reset delay in usec */ -#define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */ - -#define DAC_REG1_AMUTE 0x80 /* Auto-mute */ - -#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */ -#define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */ -#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */ -#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */ -#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */ -#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */ - -#define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */ -#define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */ -#define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */ -#define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */ - -#define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */ -#define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */ -#define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */ -#define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */ - -#define DAC_REG5_INVERT_A 0x80 /* Invert channel A */ -#define DAC_REG5_INVERT_B 0x40 /* Invert channel B */ -#define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */ -#define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */ -#define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */ -#define DAC_REG5_FREEZE 0x04 /* Freeze */ -#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */ -#define DAC_REG5_RESERVED 0x01 /* Reserved */ - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ - printf("SACSng\n"); - - return 0; -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0; - volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8); - uint psdmr = CONFIG_SYS_PSDMR; - int i; - uint psrt = 14; /* for no SPD */ - uint chipselects = 1; /* for no SPD */ - uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ - -#ifdef SDRAM_SPD_ADDR - uint data_width; - uint rows; - uint banks; - uint cols; - uint caslatency; - uint width; - uint rowst; - uint sdam; - uint bsma; - uint sda10; - u_char data; - u_char cksum; - int j; -#endif - -#ifdef SDRAM_SPD_ADDR - /* Keep the compiler from complaining about potentially uninitialized vars */ - data_width = chipselects = rows = banks = cols = caslatency = psrt = - 0; - - /* - * Read the SDRAM SPD EEPROM via I2C. - */ - i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); - cksum = data; - for (j = 1; j < 64; j++) { /* read only the checksummed bytes */ - /* note: the I2C address autoincrements when alen == 0 */ - i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); - if (j == 5) - chipselects = data & 0x0F; - else if (j == 6) - data_width = data; - else if (j == 7) - data_width |= data << 8; - else if (j == 3) - rows = data & 0x0F; - else if (j == 4) - cols = data & 0x0F; - else if (j == 12) { - /* - * Refresh rate: this assumes the prescaler is set to - * approximately 1uSec per tick. - */ - switch (data & 0x7F) { - default: - case 0: - psrt = 14; /* 15.625uS */ - break; - case 1: - psrt = 2; /* 3.9uS */ - break; - case 2: - psrt = 6; /* 7.8uS */ - break; - case 3: - psrt = 29; /* 31.3uS */ - break; - case 4: - psrt = 60; /* 62.5uS */ - break; - case 5: - psrt = 120; /* 125uS */ - break; - } - } else if (j == 17) - banks = data; - else if (j == 18) { - caslatency = 3; /* default CL */ -#if(PESSIMISTIC_SDRAM) - if ((data & 0x04) != 0) - caslatency = 3; - else if ((data & 0x02) != 0) - caslatency = 2; - else if ((data & 0x01) != 0) - caslatency = 1; -#else - if ((data & 0x01) != 0) - caslatency = 1; - else if ((data & 0x02) != 0) - caslatency = 2; - else if ((data & 0x04) != 0) - caslatency = 3; -#endif - else { - printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", data); - } - } else if (j == 63) { - if (data != cksum) { - printf("WARNING: Configuration data checksum failure:" " is 0x%02x, calculated 0x%02x\n", data, cksum); - } - } - cksum += data; - } - - /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ - if (caslatency < 2) { - printf("WARNING: CL was %d, forcing to 2\n", caslatency); - caslatency = 2; - } - if (rows > 14) { - printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", - rows); - rows = 14; - } - if (cols > 11) { - printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", - cols); - cols = 11; - } - - if ((data_width != 64) && (data_width != 72)) { - printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", - data_width); - } - width = 3; /* 2^3 = 8 bytes = 64 bits wide */ - /* - * Convert banks into log2(banks) - */ - if (banks == 2) - banks = 1; - else if (banks == 4) - banks = 2; - else if (banks == 8) - banks = 3; - - sdram_size = 1 << (rows + cols + banks + width); - -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - rowst = ((32 - 6) - (rows + cols + width)) * 2; -#else - rowst = 32 - (rows + banks + cols + width); -#endif - - or = ~(sdram_size - 1) | /* SDAM address mask */ - ((banks - 1) << 13) | /* banks per device */ - (rowst << 9) | /* rowst */ - ((rows - 9) << 6); /* numr */ - - memctl->memc_or2 = or; - - /* - * SDAM specifies the number of columns that are multiplexed - * (reference AN2165/D), defined to be (columns - 6) for page - * interleave, (columns - 8) for bank interleave. - * - * BSMA is 14 - max(rows, cols). The bank select lines come - * into play above the highest "address" line going into the - * the SDRAM. - */ -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - sdam = cols - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam + 2; -#else - sdam = cols - 6; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam; -#endif -#if(PESSIMISTIC_SDRAM) - psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK | - PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C | - PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency | - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ - (sdam << 24) | (bsma << 21) | (sda10 << 18); -#else - psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK | - PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ - PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ - PSDMR_WRC_1C | /* 1 clock + 7nSec */ - EAMUX | BUFCMD) | - caslatency | ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ - (sdam << 24) | (bsma << 21) | (sda10 << 18); -#endif -#endif - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * Quote from Micron MT48LC8M16A2 data sheet: - * - * "...the SDRAM requires a 100uS delay prior to issuing any - * command other than a COMMAND INHIBIT or NOP. Starting at some - * point during this 100uS period and continuing at least through - * the end of this period, COMMAND INHIBIT or NOP commands should - * be applied." - * - * "Once the 100uS delay has been satisfied with at least one COMMAND - * INHIBIT or NOP command having been applied, a /PRECHARGE command/ - * should be applied. All banks must then be precharged, thereby - * placing the device in the all banks idle state." - * - * "Once in the idle state, /two/ AUTO REFRESH cycles must be - * performed. After the AUTO REFRESH cycles are complete, the - * SDRAM is ready for mode register programming." - * - * (/emphasis/ mine, gvb) - * - * The way I interpret this, Micron start up sequence is: - * 1. Issue a PRECHARGE-BANK command (initial precharge) - * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") - * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands - * 4. Issue a MODE-SET command to initialize the mode register - * - * -------- - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psrt = psrt; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* - * Do it a second time for the second set of chips if the DIMM has - * two chip selects (double sided). - */ - if (chipselects > 1) { - ramaddr += sdram_size; - - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; - memctl->memc_or3 = or; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - } - - /* return total ram size */ - return (sdram_size * chipselects); -} - -/*----------------------------------------------------------------------- - * Board Control Functions - */ -void board_poweroff(void) -{ - while (1); /* hang forever */ -} - - -#ifdef CONFIG_MISC_INIT_R -/* ------------------------------------------------------------------------- */ -int misc_init_r(void) -{ - /* - * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization. - */ - volatile ioport_t *iopa = - ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */ ); - volatile ioport_t *iop = - ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); - - int reg; /* I2C register value */ - char *ep; /* Environment pointer */ - char str_buf[12]; /* sprintf output buffer */ - int sample_rate; /* ADC/DAC sample rate */ - int sample_64x; /* Use 64/4 clocking for the ADC/DAC */ - int sample_128x; /* Use 128/4 clocking for the ADC/DAC */ - int right_just; /* Is the data to the DAC right justified? */ - int mclk_divide; /* MCLK Divide */ - int quiet; /* Quiet or minimal output mode */ - - quiet = 0; - - if ((ep = getenv("quiet")) != NULL) - quiet = simple_strtol(ep, NULL, 10); - else - setenv("quiet", "0"); - - /* - * SACSng custom initialization: - * Start the ADC and DAC clocks, since the Crystal parts do not - * work on the I2C bus until the clocks are running. - */ - - sample_rate = INITIAL_SAMPLE_RATE; - if ((ep = getenv("DaqSampleRate")) != NULL) - sample_rate = simple_strtol(ep, NULL, 10); - - sample_64x = INITIAL_SAMPLE_64X; - sample_128x = INITIAL_SAMPLE_128X; - if ((ep = getenv("Daq64xSampling")) != NULL) { - sample_64x = simple_strtol(ep, NULL, 10); - if (sample_64x) - sample_128x = 0; - else - sample_128x = 1; - } else { - if ((ep = getenv("Daq128xSampling")) != NULL) { - sample_128x = simple_strtol(ep, NULL, 10); - if (sample_128x) - sample_64x = 0; - else - sample_64x = 1; - } - } - - /* - * Stop the clocks and wait for at least 1 LRCLK period - * to make sure the clocking has really stopped. - */ - Daq_Stop_Clocks(); - udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); - - /* - * Initialize the clocks with the new rates - */ - Daq_Init_Clocks(sample_rate, sample_64x); - sample_rate = Daq_Get_SampleRate(); - - /* - * Start the clocks and wait for at least 1 LRCLK period - * to make sure the clocking has become stable. - */ - Daq_Start_Clocks(sample_rate); - udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); - - sprintf(str_buf, "%d", sample_rate); - setenv("DaqSampleRate", str_buf); - - if (sample_64x) { - setenv("Daq64xSampling", "1"); - setenv("Daq128xSampling", NULL); - } else { - setenv("Daq64xSampling", NULL); - setenv("Daq128xSampling", "1"); - } - - /* - * Display the ADC/DAC clocking information - */ - if (!quiet) - Daq_Display_Clocks(); - - /* - * Determine the DAC data justification - */ - - right_just = INITIAL_RIGHT_JUST; - if ((ep = getenv("DaqDACRightJustified")) != NULL) - right_just = simple_strtol(ep, NULL, 10); - - sprintf(str_buf, "%d", right_just); - setenv("DaqDACRightJustified", str_buf); - - /* - * Determine the DAC MCLK Divide - */ - - mclk_divide = INITIAL_MCLK_DIVIDE; - if ((ep = getenv("DaqDACMClockDivide")) != NULL) - mclk_divide = simple_strtol(ep, NULL, 10); - - sprintf(str_buf, "%d", mclk_divide); - setenv("DaqDACMClockDivide", str_buf); - - /* - * Initializing the I2C address in the Crystal A/Ds: - * - * 1) Wait for VREF cap to settle (10uSec per uF) - * 2) Release pullup on SDATA - * 3) Write the I2C address to register 6 - * 4) Enable address matching by setting the MSB in register 7 - */ - - if (!quiet) - printf("Initializing the ADC...\n"); - - udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */ - - iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */ - udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ - - i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */ - i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */ - ADC_REG7_ADDR_ENABLE); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE); - - reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F; - if (reg != I2C_ADC_1_ADDR) { - printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n", - reg, I2C_ADC_1_ADDR); - } - - iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */ - udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ - - /* set address (do not set ADDREN yet) */ - i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); - - i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE); - - reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F; - if (reg != I2C_ADC_2_ADDR) { - printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n", - reg, I2C_ADC_2_ADDR); - } - - i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */ - ADC_REG1_FRAME_START | ADC_REG1_GROUND_CAL); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_CAL | - ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE); - - udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */ - i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */ - - /* - * Now that we have synchronized the ADC's, enable address - * selection on the second ADC as well as the first. - */ - i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE); - - /* - * Initialize the Crystal DAC - * - * Two of the config lines are used for I2C so we have to set them - * to the proper initialization state without inadvertantly - * sending an I2C "start" sequence. When we bring the I2C back to - * the normal state, we send an I2C "stop" sequence. - */ - if (!quiet) - printf("Initializing the DAC...\n"); - - /* - * Bring the I2C clock and data lines low for initialization - */ - I2C_SCL(0); - I2C_DELAY; - I2C_SDA(0); - I2C_ACTIVE; - I2C_DELAY; - - /* Reset the DAC */ - iopa->pdat &= ~DAC_RST_MASK; - udelay(DAC_RESET_DELAY); - - /* Release the DAC reset */ - iopa->pdat |= DAC_RST_MASK; - udelay(DAC_INITIAL_DELAY); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Going into power down - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | DAC_REG5_POWER_DOWN); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Going into power down - * . MCLK divide by 1 - * . MCLK divide by 2 - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - DAC_REG5_POWER_DOWN | - (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); - - /* - * Cause the DAC to: - * Auto-mute disabled - * . Format 0, left justified 24 bits - * . Format 3, right justified 24 bits - * No de-emphasis - * . Single speed mode - * . Double speed mode - */ - i2c_reg_write(I2C_DAC_ADDR, 0x01, - (right_just ? DAC_REG1_RIGHT_JUST_24BIT : - DAC_REG1_LEFT_JUST_24_BIT) | - DAC_REG1_DEM_NO | - (sample_rate >= - 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE)); - - sprintf(str_buf, "%d", - sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE); - setenv("DaqDACFunctionalMode", str_buf); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Remove power down - * . MCLK divide by 1 - * . MCLK divide by 2 - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); - - /* - * Create a I2C stop condition: - * low->high on data while clock is high. - */ - I2C_SCL(1); - I2C_DELAY; - I2C_SDA(1); - I2C_DELAY; - I2C_TRISTATE; - - if (!quiet) - printf("\n"); -#ifdef CONFIG_ETHER_LOOPBACK_TEST - /* - * Run the Ethernet loopback test - */ - eth_loopback_test(); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - -#ifdef CONFIG_SHOW_BOOT_PROGRESS - /* - * Turn off the RED fail LED now that we are up and running. - */ - status_led_set(STATUS_LED_RED, STATUS_LED_OFF); -#endif - - return 0; -} - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -/* - * Show boot status: flash the LED if something goes wrong, indicating - * that last thing that worked and thus, by implication, what is broken. - * - * This stores the last OK value in RAM so this will not work properly - * before RAM is initialized. Since it is being used for indicating - * boot status (i.e. after RAM is initialized), that is OK. - */ -static void flash_code(uchar number, uchar modulo, uchar digits) -{ - int j; - - /* - * Recursively do upper digits. - */ - if (digits > 1) - flash_code(number / modulo, modulo, digits - 1); - - number = number % modulo; - - /* - * Zero is indicated by one long flash (dash). - */ - if (number == 0) { - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); - udelay(1000000); - status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); - udelay(200000); - } else { - /* - * Non-zero is indicated by short flashes, one per count. - */ - for (j = 0; j < number; j++) { - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); - udelay(100000); - status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); - udelay(200000); - } - } - /* - * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total - */ - udelay(700000); -} - -static int last_boot_progress; - -void show_boot_progress(int status) -{ - int i, j; - - if (status > 0) { - last_boot_progress = status; - } else { - /* - * If a specific failure code is given, flash this code - * else just use the last success code we've seen - */ - if (status < -1) - last_boot_progress = -status; - - /* - * Flash this code 5 times - */ - for (j = 0; j < 5; j++) { - /* - * Houston, we have a problem. - * Blink the last OK status which indicates where things failed. - */ - status_led_set(STATUS_LED_RED, STATUS_LED_ON); - flash_code(last_boot_progress, 5, 3); - - /* - * Delay 5 seconds between repetitions, - * with the fault LED blinking - */ - for (i = 0; i < 5; i++) { - status_led_set(STATUS_LED_RED, - STATUS_LED_OFF); - udelay(500000); - status_led_set(STATUS_LED_RED, STATUS_LED_ON); - udelay(500000); - } - } - - /* - * Reset the board to retry initialization. - */ - do_reset(NULL, 0, 0, NULL); - } -} -#endif /* CONFIG_SHOW_BOOT_PROGRESS */ - - -/* - * The following are used to control the SPI chip selects for the SPI command. - */ -#if defined(CONFIG_CMD_SPI) - -#define SPI_ADC_CS_MASK 0x00000800 -#define SPI_DAC_CS_MASK 0x00001000 - -static const u32 cs_mask[] = { - SPI_ADC_CS_MASK, - SPI_DAC_CS_MASK, -}; - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]); -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile ioport_t *iopd = - ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ ); - - iopd->pdat &= ~cs_mask[slave->cs]; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile ioport_t *iopd = - ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ ); - - iopd->pdat |= cs_mask[slave->cs]; -} - -#endif - -#endif /* CONFIG_MISC_INIT_R */ diff --git a/boards.cfg b/boards.cfg index bdc3784..facc240 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1160,7 +1160,6 @@ Orphan m68k mcf52x2 - freescale m5253evbe Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt emillbrandt@dekaresearch.com Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt emillbrandt@dekaresearch.com Orphan powerpc mpc8260 - - ep8260 ep8260 - Frank Panno fpanno@delphintech.com -Orphan powerpc mpc8260 - - sacsng sacsng - Jerry Van Baren gerald.vanbaren@smiths-aerospace.com Orphan powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio ljd015@freescale.com Orphan powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett Kyle.D.Moffett@boeing.com Orphan powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala kumar.gala@freescale.com diff --git a/doc/README.scrapyard b/doc/README.scrapyard index be730f2..664c95c 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +sacsng powerpc mpc8260 - - Jerry Van Baren gerald.vanbaren@smiths-aerospace.com flagadm powerpc mpc8xx - - Kári Davíðsson kd@flaga.is gen860t powerpc mpc8xx - - Keith Outwater Keith_Outwater@mvis.com sixnet powerpc mpc8xx - - Dave Ellis DGE@sixnetio.com diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h deleted file mode 100644 index b5064ab..0000000 --- a/include/configs/sacsng.h +++ /dev/null @@ -1,1039 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen Murray.Jensen@cmst.csiro.au - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2001 - * Advent Networks, Inc. http://www.adventnetworks.com - * Jay Monkman jtm@smoothsmoothie.com - * - * Configuration settings for the SACSng 8260 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ - -#undef CONFIG_LOGBUFFER /* External logbuffer support */ - -/***************************************************************************** - * - * These settings must match the way _your_ board is set up - * - *****************************************************************************/ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN 66666600 - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 - * ------- ---------- --- --- ---- ----- ----- ----- - * 0x1 0x5 33 100 133 Open Close Open - * 0x1 0x6 33 100 166 Open Open Close - * 0x1 0x7 33 100 200 Open Open Open - * - * 0x2 0x2 33 133 133 Close Open Close - * 0x2 0x3 33 133 166 Close Open Open - * 0x2 0x4 33 133 200 Open Close Close - * 0x2 0x5 33 133 233 Open Close Open - * 0x2 0x6 33 133 266 Open Open Close - * - * 0x5 0x5 66 133 133 Open Close Open - * 0x5 0x6 66 133 166 Open Open Close - * 0x5 0x7 66 133 200 Open Open Open - * 0x6 0x0 66 133 233 Close Close Close - * 0x6 0x1 66 133 266 Close Close Open - * 0x6 0x2 66 133 300 Close Open Close - */ -#define CONFIG_SYS_SBC_MODCK_H 0x05 - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CONFIG_SYS_SBC_BOOT_LOW 1 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 2 - -/* What should the base address of the secondary FLASH be and how big - * is it (in Mbytes)? The secondary FLASH is whichever is connected - * to *CS6. - */ -#define CONFIG_SYS_FLASH1_BASE 0x60000000 -#define CONFIG_SYS_FLASH1_SIZE 2 - -/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes - */ -#define CONFIG_VERY_BIG_RAM 1 - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? This will normally auto-configure via the SPD. -*/ -#define CONFIG_SYS_SDRAM0_BASE 0x00000000 -#define CONFIG_SYS_SDRAM0_SIZE 64 - -/* - * Memory map example with 64 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x03F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x03F5 FFB0 Board Info Data - * 0x03F6 0000 Malloc Arena - * : CONFIG_ENV_SECT_SIZE, 16k - * : CONFIG_SYS_MALLOC_LEN, 128k - * 0x03FC 0000 RAM Copy of Monitor Code - * : CONFIG_SYS_MONITOR_LEN, 256k - * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 - */ - -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU) - - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ - -#undef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_ON_FCC -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ - -#ifdef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif /* CONFIG_ETHER_ON_SCC */ - -#ifdef CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ - -#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x40000000) -#define MDIO_TRISTATE (iop->pdir &= ~0x40000000) -#define MDIO_READ ((iop->pdat & 0x40000000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \ - else iop->pdat &= ~0x40000000 - -#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \ - else iop->pdat &= ~0x80000000 - -#define MIIDELAY udelay(50) -#endif /* CONFIG_ETHER_ON_FCC */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */ - -/* - * Configure for RAM tests. - */ -#undef CONFIG_SYS_DRAM_TEST /* calls other tests in board.c */ - - -/* - * Status LED for power up status feedback. - */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define STATUS_LED_PAR im_ioport.iop_ppara -#define STATUS_LED_DIR im_ioport.iop_pdira -#define STATUS_LED_ODR im_ioport.iop_podra -#define STATUS_LED_DAT im_ioport.iop_pdata - -#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */ -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ) -#define STATUS_LED_STATE STATUS_LED_OFF -#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */ -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ) -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */ -#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ/2) -#define STATUS_LED_STATE2 STATUS_LED_ON - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ - -#define STATUS_LED_YELLOW 0 -#define STATUS_LED_GREEN 1 -#define STATUS_LED_RED 2 -#define STATUS_LED_BOOT 1 - - -/* - * Select SPI support configuration - */ -#define CONFIG_SOFT_SPI /* Enable SPI driver */ -#define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */ -#undef DEBUG_SPI /* Disable SPI debugging */ - -/* - * Software (bit-bang) SPI driver configuration - */ -#ifdef CONFIG_SOFT_SPI - -/* - * Software (bit-bang) SPI driver configuration - */ -#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */ -#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */ -#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */ - -#undef SPI_INIT /* no port initialization needed */ -#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0) -#define SPI_SDA(bit) do { \ - if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ - else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \ - } while (0) -#define SPI_SCL(bit) do { \ - if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ - else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \ - } while (0) -#define SPI_DELAY /* No delay is needed */ -#endif /* CONFIG_SOFT_SPI */ - - -/* - * select I2C support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */ - -/* Define this to reserve an entire FLASH sector for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CONFIG_ENV_IN_OWN_SECT 1 - -/* Define this to contain any number of null terminated strings that - * will be part of the default environment compiled into the boot image. - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ -"quiet=0\0" \ -"serverip=192.168.123.205\0" \ -"ipaddr=192.168.123.203\0" \ -"checkhostname=VR8500\0" \ -"reprog="\ - "bootp; " \ - "tftpboot 0x140000 /bdi2000/u-boot.bin; " \ - "protect off 60000000 6003FFFF; " \ - "erase 60000000 6003FFFF; " \ - "cp.b 140000 60000000 ${filesize}; " \ - "protect on 60000000 6003FFFF\0" \ -"copyenv="\ - "protect off 60040000 6004FFFF; " \ - "erase 60040000 6004FFFF; " \ - "cp.b 40040000 60040000 10000; " \ - "protect on 60040000 6004FFFF\0" \ -"copyprog="\ - "protect off 60000000 6003FFFF; " \ - "erase 60000000 6003FFFF; " \ - "cp.b 40000000 60000000 40000; " \ - "protect on 60000000 6003FFFF\0" \ -"zapenv="\ - "protect off 40040000 4004FFFF; " \ - "erase 40040000 4004FFFF; " \ - "protect on 40040000 4004FFFF\0" \ -"zapotherenv="\ - "protect off 60040000 6004FFFF; " \ - "erase 60040000 6004FFFF; " \ - "protect on 60040000 6004FFFF\0" \ -"root-on-initrd="\ - "setenv bootcmd "\ - "version\;" \ - "echo\;" \ - "bootp\;" \ - "setenv bootargs root=/dev/ram0 rw quiet " \ - "ip=\${ipaddr}:\${serverip}:\${gatewayip}:\${netmask}:\${hostname}::off\;" \ - "run boot-hook\;" \ - "bootm\0" \ -"root-on-initrd-debug="\ - "setenv bootcmd "\ - "version\;" \ - "echo\;" \ - "bootp\;" \ - "setenv bootargs root=/dev/ram0 rw debug " \ - "ip=\${ipaddr}:\${serverip}:\${gatewayip}:\${netmask}:\${hostname}::off\;" \ - "run debug-hook\;" \ - "run boot-hook\;" \ - "bootm\0" \ -"root-on-nfs="\ - "setenv bootcmd "\ - "version\;" \ - "echo\;" \ - "bootp\;" \ - "setenv bootargs root=/dev/nfs rw quiet " \ - "nfsroot=\${serverip}:\${rootpath} " \ - "ip=\${ipaddr}:\${serverip}:\${gatewayip}:\${netmask}:\${hostname}::off\;" \ - "run boot-hook\;" \ - "bootm\0" \ -"root-on-nfs-debug="\ - "setenv bootcmd "\ - "version\;" \ - "echo\;" \ - "bootp\;" \ - "setenv bootargs root=/dev/nfs rw debug " \ - "nfsroot=\${serverip}:\${rootpath} " \ - "ip=\${ipaddr}:\${serverip}:\${gatewayip}:\${netmask}:\${hostname}::off\;" \ - "run debug-hook\;" \ - "run boot-hook\;" \ - "bootm\0" \ -"debug-checkout="\ - "setenv checkhostname;" \ - "setenv ethaddr 00:09:70:00:00:01;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run debug-hook;" \ - "run boot-hook;" \ - "bootm\0" \ -"debug-hook="\ - "echo ipaddr ${ipaddr};" \ - "echo serverip ${serverip};" \ - "echo gatewayip ${gatewayip};" \ - "echo netmask ${netmask};" \ - "echo hostname ${hostname}\0" \ -"ana=run adc ; run dac\0" \ -"adc=run adc-12 ; run adc-34\0" \ -"adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \ -"adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \ -"dac=echo ### DAC ; i2c md 11 81 5\0" \ -"boot-hook=echo\0" - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 9600 - -/* Ethernet MAC address */ -#define CONFIG_ETHADDR 00:09:70:00:00:00 - -/* The default Ethernet MAC address can be overwritten just once */ -#ifdef CONFIG_ETHADDR -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#endif - -/* - * Define this to do some miscellaneous board-specific initialization. - */ -#define CONFIG_MISC_INIT_R - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n" -#define CONFIG_AUTOBOOT_STOP_STR " " -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define DEBUG_BOOTKEYS 0 - -/* Define a command string that is automatically executed when no character - * is read on the console interface withing "Boot Delay" after reset. - */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ - -#ifdef CONFIG_BOOT_ROOT_INITRD -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw quiet " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run boot-hook;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_INITRD */ - -#ifdef CONFIG_BOOT_ROOT_NFS -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run boot-hook;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_NFS */ - -#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */ -#define CONFIG_LIB_RAND - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - - -/* undef this to save memory */ -#define CONFIG_SYS_LONGHELP - -/* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time) - * of an image is printed by image commands like bootm or iminfo. - */ -#define CONFIG_TIMESTAMP - -/* If this variable is defined, an environment variable named "ver" - * is created by U-Boot showing the U-Boot version. - */ -#define CONFIG_VERSION_VARIABLE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ELF -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING - -#undef CONFIG_CMD_KGDB - -#ifdef CONFIG_ETHER_ON_FCC -#define CONFIG_CMD_MII -#endif - - -/* Where do the internal registers live? */ -#define CONFIG_SYS_IMMR 0xF0000000 - -#undef CONFIG_WATCHDOG /* disable the watchdog */ - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_SACSng 1 /* munged for the SACSng */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */ - /* in the bootm command. */ -#define CONFIG_SYS_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */ - /* "## <message>" from the bootm cmd */ -#define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */ - /* defined, then the hostname param */ - /* validated against checkhostname. */ -#define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */ -#define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */ - /* (limited to maximum of 1024 msec) */ -#define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1 - /* Check for abort key presses */ - /* at least once in dependent of the */ - /* CONFIG_BOOTDELAY value. */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */ - /* state to the fault LED. */ -#define CONFIG_SYS_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */ - /* the Ethernet link state. */ -#define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */ - /* until the TFTP is successful. */ -#define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */ - /* turn off the STATUS LEDs. */ -#define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */ - /* incoming data. */ -#define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */ - /* to signify that tftp is moving. */ -#define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */ - /* flash the status LED. */ -#define CONFIG_SYS_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */ - /* during the tftp file transfer. */ -#define CONFIG_SYS_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */ - /* '#'s from the tftp command. */ -#define CONFIG_SYS_TFTP_STATUS_QUIET 1 /* Suppress the status displays */ - /* issued during the tftp command. */ -#define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */ - /* before it gives up. */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -#define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */ -#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ - + CONFIG_SYS_MALLOC_LEN \ - + CONFIG_ENV_SECT_SIZE \ - + CONFIG_SYS_STACK_USAGE ) - -#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ - - CONFIG_SYS_MEM_END_USAGE ) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CONFIG_SYS_SBC_BOOT_LOW) -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ - -/* get the HRCW ISB field from CONFIG_SYS_IMMR */ -#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ - ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ - ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS10 | \ - HRCW_DPPC11 | \ - CONFIG_SYS_SBC_HRCW_IMMR | \ - HRCW_MMR00 | \ - HRCW_LBPC11 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \ - CONFIG_SYS_SBC_HRCW_BOOT_FLAGS ) - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#undef CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -#ifndef CONFIG_SYS_RAMBOOT -# define CONFIG_ENV_IS_IN_FLASH 1 - -# ifdef CONFIG_ENV_IN_OWN_SECT -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -# define CONFIG_ENV_SECT_SIZE 0x10000 -# else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -# endif /* CONFIG_ENV_IN_OWN_SECT */ - -#else -# define CONFIG_ENV_IS_IN_NVRAM 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -# define CONFIG_ENV_SIZE 0x200 -#endif /* CONFIG_SYS_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\ - SIUMCR_L2CPC00 |\ - SIUMCR_APPC10 |\ - SIUMCR_MMR00) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP |\ - SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Initialize Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 16 bit FLASH (primary flash - 2MB) - * 1 60x GPCM -- bit (Unused) - * 2 60x SDRAM 64 bit SDRAM (DIMM) - * 3 60x SDRAM 64 bit SDRAM (DIMM) - * 4 60x GPCM -- bit (Unused) - * 5 60x GPCM -- bit (Unused) - * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB) - */ - -/*----------------------------------------------------------------------- - * BR0,BR1 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR0,OR1 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0 - Primary FLASH - */ - -/* BR0 is configured as follows: - * - * - Base address of 0x40000000 - * - 16 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR0 is configured as follows: - * - * - 4 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR2,BR3 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2,OR3 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* Bank 2,3 - SDRAM DIMM - */ - -/* The BR2 is configured as follows: - * - * - Base address of 0x00000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 64 MB DIMM, the OR2 is configured as follows: - * - * - 64 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CONFIG_SYS_SDRAM0_SIZE == 64) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12) -#else -#error "INVALID SDRAM CONFIGURATION" -#endif - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ - -/* Address that the DIMM SPD memory lives at. - */ -#define SDRAM_SPD_ADDR 0x50 - -#if (CONFIG_SYS_SDRAM0_SIZE == 64) -/* With a 64 MB DIMM, the PSDMR is configured as follows: - * - * - Bank Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A14-A16 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ -#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#else -#error "INVALID SDRAM CONFIGURATION" -#endif - -/* - * Shoot for approximately 1MHz on the prescaler. - */ -#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000)) -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64 -#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000)) -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 -#else -#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK" -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 -#endif -#define CONFIG_SYS_PSRT 14 - - -/*----------------------------------------------------------------------- - * BR6 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR6 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 6 - Secondary FLASH - * - * The secondary FLASH is connected to *CS6 - */ -#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) - -/* BR6 is configured as follows: - * - * - Base address of 0x60000000 - * - 16 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -# define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR6 is configured as follows: - * - * - 2 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -# define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) -#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */ - -#endif /* __CONFIG_H */
This board has been orphaned for a while and old enough.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---
board/ep8260/Makefile | 8 - board/ep8260/ep8260.c | 304 ------------------- board/ep8260/ep8260.h | 24 -- board/ep8260/flash.c | 395 ------------------------- board/ep8260/mii_phy.c | 107 ------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/ep8260.h | 744 ----------------------------------------------- 8 files changed, 1 insertion(+), 1583 deletions(-) delete mode 100644 board/ep8260/Makefile delete mode 100644 board/ep8260/ep8260.c delete mode 100644 board/ep8260/ep8260.h delete mode 100644 board/ep8260/flash.c delete mode 100644 board/ep8260/mii_phy.c delete mode 100644 include/configs/ep8260.h
diff --git a/board/ep8260/Makefile b/board/ep8260/Makefile deleted file mode 100644 index dd08b74..0000000 --- a/board/ep8260/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = ep8260.o flash.o mii_phy.o diff --git a/board/ep8260/ep8260.c b/board/ep8260/ep8260.c deleted file mode 100644 index 3697d24..0000000 --- a/board/ep8260/ep8260.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Frank Panno fpanno@delphintech.com, Delphin Technology AG - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> -#include "ep8260.h" -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* */ - /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK15 */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK16 */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Setup CS4 to enable the Board Control/Status registers. - * Otherwise the smcs won't work. -*/ -int board_early_init_f (void) -{ - volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */ - regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */ - return 0; -} - -void reset_phy (void) -{ - volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE; - - regs->bcsr4 = 0xC0; -} - -/* - * Check Board Identity: - * I don' know, how the next board revisions will be coded. - * Thats why its a static interpretation ... -*/ - -int checkboard (void) -{ - volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE; - uint major = 0, minor = 0; - - switch (regs->bcsr0) { - case 0x02: - major = 1; - break; - case 0x03: - major = 1; - minor = 1; - break; - case 0x06: - major = 1; - minor = 3; - break; - default: - break; - } - printf ("Board: Embedded Planet EP8260, Revision %d.%d\n", - major, minor); - return 0; -} - - -/* ------------------------------------------------------------------------- */ - - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0; - volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE) + 0x110; - -/* - ulong psdmr = CONFIG_SYS_PSDMR; -#ifdef CONFIG_SYS_LSDRAM - ulong lsdmr = CONFIG_SYS_LSDMR; -#endif -*/ - long size = CONFIG_SYS_SDRAM0_SIZE; - int i; - - -/* -* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): -* -* "At system reset, initialization software must set up the -* programmable parameters in the memory controller banks registers -* (ORx, BRx, P/LSDMR). After all memory parameters are configured, -* system software should execute the following initialization sequence -* for each SDRAM device. -* -* 1. Issue a PRECHARGE-ALL-BANKS command -* 2. Issue eight CBR REFRESH commands -* 3. Issue a MODE-SET command to initialize the mode register -* -* The initial commands are executed by setting P/LSDMR[OP] and -* accessing the SDRAM with a single-byte transaction." -* -* The appropriate BRx/ORx registers have already been set when we -* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. -*/ - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - -#ifndef CONFIG_SYS_RAMBOOT -#ifdef CONFIG_SYS_LSDRAM - size += CONFIG_SYS_SDRAM1_SIZE; - ramaddr = (uchar *) (CONFIG_SYS_SDRAM1_BASE) + 0x8c; - memctl->memc_lsrt = CONFIG_SYS_LSRT; - - memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; -#endif /* CONFIG_SYS_LSDRAM */ -#endif /* CONFIG_SYS_RAMBOOT */ - return (size * 1024 * 1024); -} diff --git a/board/ep8260/ep8260.h b/board/ep8260/ep8260.h deleted file mode 100644 index 3032b14..0000000 --- a/board/ep8260/ep8260.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef __EP8260_H__ -#define __EP8260_H__ - -typedef struct tt_ep_regs { - volatile unsigned char bcsr0; - volatile unsigned char bcsr1; - volatile unsigned char bcsr2; - volatile unsigned char bcsr3; - volatile unsigned char bcsr4; - volatile unsigned char bcsr5; - volatile unsigned char bcsr6; - volatile unsigned char bcsr7; - volatile unsigned char bcsr8; - volatile unsigned char bcsr9; - volatile unsigned char bcsr10; - volatile unsigned char bcsr11; - volatile unsigned char bcsr12; - volatile unsigned char bcsr13; - volatile unsigned char bcsr14; - volatile unsigned char bcsr15; -} t_ep_regs; -typedef t_ep_regs *tp_ep_regs; - -#endif diff --git a/board/ep8260/flash.c b/board/ep8260/flash.c deleted file mode 100644 index 44f63ee..0000000 --- a/board/ep8260/flash.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Frank Panno fpanno@delphintech.com, Delphin Technology AG - * - * Flash Routines for AMD device AM29DL323DB on the EP8260 board. - * - * This file is based on board/tqm8260/flash.c. - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -#define V_ULONG(a) (*(volatile unsigned long *)( a )) -#define V_BYTE(a) (*(volatile unsigned char *)( a )) - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ -void flash_reset(void) -{ - if( flash_info[0].flash_id != FLASH_UNKNOWN ) { - V_ULONG( flash_info[0].start[0] ) = 0x00F000F0; - V_ULONG( flash_info[0].start[0] + 4 ) = 0x00F000F0; - } -} - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size( ulong baseaddr, flash_info_t *info ) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - /* Write auto select command sequence and test FLASH answer */ - V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00AA00AA; - V_ULONG(baseaddr + ((ulong)0x02AA << 3)) = 0x00550055; - V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00900090; - V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00AA00AA; - V_ULONG(baseaddr + 4 + ((ulong)0x02AA << 3)) = 0x00550055; - V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00900090; - - flashtest_h = V_ULONG(baseaddr); /* manufacturer ID */ - flashtest_l = V_ULONG(baseaddr + 4); - - if ((int)flashtest_h == AMD_MANUFACT) { - info->flash_id = FLASH_MAN_AMD; - } else { - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - flashtest_h = V_ULONG(baseaddr + 8); /* device ID */ - flashtest_l = V_ULONG(baseaddr + 12); - if (flashtest_h != flashtest_l) { - info->flash_id = FLASH_UNKNOWN; - return(0); - } - - switch((int)flashtest_h) { - case AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; /* 4 * 4 MB = 16 MB */ - break; - case AMD_ID_LV640U: /* AMDLV640 and AMDLV641 have same ID */ - info->flash_id += FLASH_AMLV640U; - info->sector_count = 128; - info->size = 0x02000000; /* 4 * 8 MB = 32 MB */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return(0); /* no or unknown flash */ - } - - if(flashtest_h == AMD_ID_LV640U) { - /* set up sector start adress table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = baseaddr + (i * 0x00040000); - } else { - /* set up sector start adress table (bottom sector type) */ - for (i = 0; i < 8; i++) { - info->start[i] = baseaddr + (i * 0x00008000); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000; - } - } - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - if ((V_ULONG( info->start[i] + 16 ) & 0x00010001) || - (V_ULONG( info->start[i] + 20 ) & 0x00010001)) { - info->protect[i] = 1; /* D0 = 1 if protected */ - } else { - info->protect[i] = 0; - } - } - - flash_reset(); - return(info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0>>20); - } - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL323B: printf ("29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AMLV640U: printf ("29LV640U (64 M, uniform sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00800080; - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00800080; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055; - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - V_ULONG( info->start[sect] ) = 0x00300030; - V_ULONG( info->start[sect] + 4 ) = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 || - (V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080) - { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - flash_reset (); - - printf (" done\n"); - return 0; -} - -static int write_dword (flash_info_t *, ulong, unsigned char *); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong dp; - static unsigned char bb[8]; - int i, l, rc, cc = cnt; - - dp = (addr & ~7); /* get lower dword aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - dp) != 0) { - for (i = 0; i < 8; i++) - bb[i] = (i < l || (i-l) >= cc) ? V_BYTE(dp+i) : *src++; - if ((rc = write_dword(info, dp, bb)) != 0) - { - return (rc); - } - dp += 8; - cc -= 8 - l; - } - - /* - * handle word aligned part - */ - while (cc >= 8) { - if ((rc = write_dword(info, dp, src)) != 0) { - return (rc); - } - dp += 8; - src += 8; - cc -= 8; - } - - if (cc <= 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - for (i = 0; i < 8; i++) { - bb[i] = (i < cc) ? *src++ : V_BYTE(dp+i); - } - return (write_dword(info, dp, bb)); -} - -/*----------------------------------------------------------------------- - * Write a dword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_dword (flash_info_t *info, ulong dest, unsigned char * pdata) -{ - ulong start; - ulong cl = 0, ch =0; - int flag, i; - - for (ch=0, i=0; i < 4; i++) - ch = (ch << 8) + *pdata++; /* high word */ - for (cl=0, i=0; i < 4; i++) - cl = (cl << 8) + *pdata++; /* low word */ - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & ch) != ch - ||(*((vu_long *)(dest + 4)) & cl) != cl) - { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00A000A0; - V_ULONG( dest ) = ch; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00A000A0; - V_ULONG( dest + 4 ) = cl; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) || - ((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/ep8260/mii_phy.c b/board/ep8260/mii_phy.c deleted file mode 100644 index c7aa275..0000000 --- a/board/ep8260/mii_phy.c +++ /dev/null @@ -1,107 +0,0 @@ -#include <common.h> -#include <mii_phy.h> -#include "ep8260.h" - -#define MII_MDIO 0x01 -#define MII_MDCK 0x02 -#define MII_MDIR 0x04 - -void -mii_discover_phy(void) -{ - int known; - unsigned short phy_reg; - unsigned long phy_id; - - known = 0; - printf("Discovering phy @ 0: "); - phy_id = mii_phy_read(2) << 16; - phy_id |= mii_phy_read(3); - if ((phy_id & 0xFFFFFC00) == 0x00137800) { - printf("Level One "); - if ((phy_id & 0x000003F0) == 0xE0) { - printf("LXT971A Revision %d\n", (int)(phy_id & 0xF)); - known = 1; - } - else printf("unknown type\n"); - } - else printf("unknown OUI = 0x%08lX\n", phy_id); - - phy_reg = mii_phy_read(1); - if (!(phy_reg & 0x0004)) printf("Link is down\n"); - if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n"); - if (phy_reg & 0x0002) printf("Jabber condition detected\n"); - if (phy_reg & 0x0010) printf("Remote fault condition detected \n"); - - if (known) { - phy_reg = mii_phy_read(17); - if (phy_reg & 0x0400) - printf("Phy operating at %d MBit/s in %s-duplex mode\n", - phy_reg & 0x4000 ? 100 : 10, - phy_reg & 0x0200 ? "full" : "half"); - else - printf("bad link!!\n"); -/* -left off: no link, green 100MBit, yellow 10MBit -right off: no activity, green full-duplex, yellow half-duplex -*/ - mii_phy_write(20, 0x0452); - } -} - -unsigned short -mii_phy_read(unsigned short reg) -{ - int i; - unsigned short tmp, val = 0, adr = 0; - t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE; - - tmp = 0x6002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - regs->bcsr4 |= MII_MDIR; - for (i = 0; i < 16; i++) { - val <<= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK); - if (regs->bcsr4 & MII_MDIO) val |= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK); - } - return val; -} - -void -mii_phy_write(unsigned short reg, unsigned short val) -{ - int i; - unsigned short tmp, adr = 0; - t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE; - - tmp = 0x5002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (val & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - val <<= 1; - } -} diff --git a/boards.cfg b/boards.cfg index facc240..3be1e0d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1159,7 +1159,6 @@ Orphan blackfin - - - ip04 Orphan m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser Hayden.Fraser@freescale.com Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt emillbrandt@dekaresearch.com Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt emillbrandt@dekaresearch.com -Orphan powerpc mpc8260 - - ep8260 ep8260 - Frank Panno fpanno@delphintech.com Orphan powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio ljd015@freescale.com Orphan powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett Kyle.D.Moffett@boeing.com Orphan powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala kumar.gala@freescale.com diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 664c95c..a535b0d 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +ep8260 powerpc mpc8260 - - Frank Panno fpanno@delphintech.com sacsng powerpc mpc8260 - - Jerry Van Baren gerald.vanbaren@smiths-aerospace.com flagadm powerpc mpc8xx - - Kári Davíðsson kd@flaga.is gen860t powerpc mpc8xx - - Keith Outwater Keith_Outwater@mvis.com diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h deleted file mode 100644 index 9cd3054..0000000 --- a/include/configs/ep8260.h +++ /dev/null @@ -1,744 +0,0 @@ -/* - * (C) Copyright 2002 - * Frank Panno fpanno@delphintech.com, Delphin Technology AG - * - * This file is based on similar values for other boards found in other - * U-Boot config files, and some that I found in the EP8260 manual. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - * - * "EP8260 H, V.1.1" - * - 64M 60x Bus SDRAM - * - 32M Local Bus SDRAM - * - 16M Flash (4 x AM29DL323DB90WDI) - * - 128k NVRAM with RTC - * - * "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2) - * - 300MHz/133MHz/66MHz - * - 64M 60x Bus SDRAM - * - 32M Local Bus SDRAM - * - 32M Flash - * - 128k NVRAM with RTC - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Define this to enable support the EP8260 H2 version */ -#define CONFIG_SYS_EP8260_H2 1 -/* #undef CONFIG_SYS_EP8260_H2 */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core - * ------- ---------- --- --- ---- - * 0x2 0x2 33 133 133 - * 0x2 0x3 33 133 166 - * 0x2 0x4 33 133 200 - * 0x2 0x5 33 133 233 - * 0x2 0x6 33 133 266 - * - * 0x5 0x5 66 133 133 - * 0x5 0x6 66 133 166 - * 0x5 0x7 66 133 200 * - * 0x6 0x0 66 133 233 - * 0x6 0x1 66 133 266 - * 0x6 0x2 66 133 300 - */ -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110) -#else -#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110) -#endif - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -/* #define CONFIG_SYS_SBC_BOOT_LOW 1 */ /* only for HRCW */ -/* #undef CONFIG_SYS_SBC_BOOT_LOW */ - -/* The reset command will not work as expected if the reset address does - * not point to the correct address. - */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ep8260/config.mk - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_FLASH0_BASE 0xFE000000 -#define CONFIG_SYS_FLASH0_SIZE 32 -#else -#define CONFIG_SYS_FLASH0_BASE 0xFF000000 -#define CONFIG_SYS_FLASH0_SIZE 16 -#endif - -/* What should the base address of the secondary FLASH be and how big - * is it (in Mbytes)? The secondary FLASH is whichever is connected - * to *CS6. U-Boot expects this to be the on board FLASH. If you don't - * want it enabled, don't define these constants. - */ -#define CONFIG_SYS_FLASH1_BASE 0 -#define CONFIG_SYS_FLASH1_SIZE 0 -#undef CONFIG_SYS_FLASH1_BASE -#undef CONFIG_SYS_FLASH1_SIZE - -/* What should be the base address of SDRAM DIMM (60x bus) and how big is - * it (in Mbytes)? -*/ -#define CONFIG_SYS_SDRAM0_BASE 0x00000000 -#define CONFIG_SYS_SDRAM0_SIZE 64 - -/* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the - * local bus (8260 local bus is NOT cacheable!) -*/ -/* #define CONFIG_SYS_LSDRAM */ -#undef CONFIG_SYS_LSDRAM - -#ifdef CONFIG_SYS_LSDRAM -/* What should be the base address of SDRAM DIMM (local bus) and how big is - * it (in Mbytes)? -*/ - #define CONFIG_SYS_SDRAM1_BASE 0x04000000 - #define CONFIG_SYS_SDRAM1_SIZE 32 -#else - #define CONFIG_SYS_SDRAM1_BASE 0 - #define CONFIG_SYS_SDRAM1_SIZE 0 - #undef CONFIG_SYS_SDRAM1_BASE - #undef CONFIG_SYS_SDRAM1_SIZE -#endif /* CONFIG_SYS_LSDRAM */ - -/* What should be the base address of NVRAM and how big is - * it (in Bytes) - */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000 -#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16 - -/* The RTC is a Dallas DS1556 - */ -#define CONFIG_RTC_DS1556 - -/* What should be the base address of the LEDs and switch S0? - * If you don't want them enabled, don't define this. - */ -#define CONFIG_SYS_LED_BASE 0x00000000 -#undef CONFIG_SYS_LED_BASE - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ - -#if ( CONFIG_ETHER_INDEX == 3 ) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the local Bus (see 28-13) - * - Enable Half Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) - -/* - * - RAM for BD/Buffers is on the local Bus (see 28-13) - */ -#ifdef CONFIG_SYS_LSDRAM - #define CONFIG_SYS_CPMFCR_RAMTYPE 3 -#else /* CONFIG_SYS_LSDRAM */ - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#endif /* CONFIG_SYS_LSDRAM */ - -/* - Enable Half Duplex in FSMR */ -/* # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ -# define CONFIG_SYS_FCC_PSMR 0 - -#else /* CONFIG_ETHER_INDEX */ -# error "on EP8260 ethernet must be FCC3" -#endif /* CONFIG_ETHER_INDEX */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F /* This is for HARD, must go */ - -/* - * Software (bit-bang) I2C driver configuration - */ -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SYS_I2C_SOFT */ - -/* #define CONFIG_RTC_DS174x */ - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CONFIG_ENV_IN_OWN_SECT - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_BAUDRATE 9600 -#else -#define CONFIG_BAUDRATE 115200 -#endif - -/* Ethernet MAC address */ -#define CONFIG_ETHADDR 00:10:EC:00:30:8C - -#define CONFIG_IPADDR 192.168.254.130 -#define CONFIG_SERVERIP 192.168.254.49 - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY -1 - -/* undef this to save memory */ -#define CONFIG_SYS_LONGHELP - -/* Monitor Command Prompt */ - -/* Define this variable to enable the "hush" shell (from - Busybox) as command line interpreter, thus enabling - powerful command line syntax like - if...then...else...fi conditionals or `&&' and '||' - constructs ("shell scripts"). - If undefined, you get the old, much simpler behaviour - with a somewhat smapper memory footprint. -*/ -#define CONFIG_SYS_HUSH_PARSER - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_XIMG - -/* Where do the internal registers live? */ -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_DEFAULT_IMMR 0x00010000 - -/* Where do the on board registers (CS4) live? */ -#define CONFIG_SYS_REGS_BASE 0xFA000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* - * Miscellaneous configurable options - */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#ifdef CONFIG_SYS_LSDRAM - #define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */ - #define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ -#else - #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ - #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */ -#endif /* CONFIG_SYS_LSDRAM */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ - -#if defined(CONFIG_SYS_SBC_BOOT_LOW) -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0x00000000) -#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ - -#ifdef CONFIG_SYS_EP8260_H2 -/* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */ -#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\ - ((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7) |\ - ((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) ) - -#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM |\ - HRCW_L2CPC01 |\ - CONFIG_SYS_SBC_HRCW_IMMR |\ - HRCW_APPC10 |\ - HRCW_CS10PC01 |\ - CONFIG_SYS_SBC_MODCK_H |\ - CONFIG_SYS_SBC_HRCW_BOOT_FLAGS) -#else -#define CONFIG_SYS_HRCW_MASTER 0x10400245 -#endif - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#else -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#endif - -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#else -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ -#endif - -#ifndef CONFIG_SYS_RAMBOOT -# define CONFIG_ENV_IS_IN_FLASH 1 - -# ifdef CONFIG_ENV_IN_OWN_SECT -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -# define CONFIG_ENV_SECT_SIZE 0x40000 -# else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -# endif /* CONFIG_ENV_IN_OWN_SECT */ -#else -# define CONFIG_ENV_IS_IN_NVRAM 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -# define CONFIG_ENV_SIZE 0x200 -#endif /* CONFIG_SYS_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) -#ifdef CONFIG_SYS_LSDRAM -/* 8260 local bus is NOT cacheable */ -#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#else /* !CONFIG_SYS_LSDRAM */ -#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#endif /* CONFIG_SYS_LSDRAM */ - -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_EBM |\ - BCR_PLDP |\ - BCR_EAV |\ - BCR_NPQM0) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\ - SIUMCR_APPC10 |\ - SIUMCR_CS10PC01) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#ifdef CONFIG_SYS_EP8260_H2 -/* TBD: Find out why setting the BMT to 0xff causes the FCC to - * generate TX buffer underrun errors for large packets under - * Linux - */ -#define CONFIG_SYS_SYPCR_BMT 0x00000600 -#else -#define CONFIG_SYS_SYPCR_BMT SYPCR_BMT -#endif - -#ifdef CONFIG_SYS_LSDRAM -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - CONFIG_SYS_SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ - CONFIG_SYS_SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) -#else -#define CONFIG_SYS_PISCR 0 -#endif - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_SCCR (SCCR_DFBRG00) -#else -#define CONFIG_SYS_SCCR (SCCR_DFBRG01) -#endif - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/*----------------------------------------------------------------------- - * MPTPR - Memory Refresh Timer Prescale Register 10-32 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MPTPR (0x0A00 & MPTPR_PTP_MSK) - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI) - * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG) - * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG) - * 3 unused - * 4 60x GPCM 8 bit Board Regs, NVRTC - * 5 unused - * 6 unused - * 7 unused - * 8 PCMCIA - * 9 unused - * 10 unused - * 11 unused -*/ - -/*----------------------------------------------------------------------- - * BRx - Base Register - * Ref: Section 10.3.1 on page 10-14 - * ORx - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0 - FLASH - * - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_8_CLK |\ - ORxG_EHTR) - -/* Bank 1 - SDRAM - * PSDRAM - */ -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_12) - -#ifdef CONFIG_SYS_EP8260_H2 -#define CONFIG_SYS_PSDMR 0xC34E246E -#else -#define CONFIG_SYS_PSDMR 0xC34E2462 -#endif - -#define CONFIG_SYS_PSRT 0x64 - -#ifdef CONFIG_SYS_LSDRAM -/* Bank 2 - SDRAM - * LSDRAM - */ - - #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - - #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - - #define CONFIG_SYS_LSDMR 0x416A2562 - #define CONFIG_SYS_LSRT 0x64 -#else - #define CONFIG_SYS_LSRT 0x0 -#endif /* CONFIG_SYS_LSDRAM */ - -/* Bank 4 - On board registers - * NVRTC and BCSR - */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) -/* -#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_10_CLK |\ - ORxG_TRLX) -*/ -#define CONFIG_SYS_OR4_PRELIM 0xfff00854 - -#ifdef _NOT_USED_SINCE_NOT_WORKING_ -/* Bank 8 - On board registers - * PCMCIA (currently not working!) - */ -#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR8_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SETA |\ - ORxG_SCY_10_CLK) -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */
participants (2)
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Masahiro Yamada -
Wolfgang Denk