[U-Boot] Pull request: u-boot-riscv/master

Hi Tom,
Please pull some riscv updates:
- Increase stack size to avoid a stack overflow during distro boot. - Add hifive-unleashed-a00.dts for SIFIVE FU540. - Add OF_SEPARATE support for SIFIVE FU540. - Add SPL support for Andes AX25 AE350. - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
https://travis-ci.org/rickchen36/u-boot-riscv/builds/622462488
Thanks Rick
The following changes since commit 0c5c3f293554614416a188d16a8c05e0a6c5bfbb:
arm: -march=armv5t for ARM11 (2019-12-09 10:36:00 -0500)
are available in the Git repository at:
git@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 0e1233ce9069a87a84a4385de456665d2bc9229d:
spl: opensbi: wait for ack from secondary harts before entering OpenSBI (2019-12-10 08:23:10 +0800)
---------------------------------------------------------------- Jagan Teki (1): riscv: dts: Add hifive-unleashed-a00 dts from Linux
Lukas Auer (5): riscv: increase stack size to avoid a stack overflow during distro boot spl: opensbi: specify main hart as preferred boot hart riscv: add functions for reading the IPI status riscv: add option to wait for ack from secondary harts in smp functions spl: opensbi: wait for ack from secondary harts before entering OpenSBI
Rick Chen (11): Use dts support from U-Boot via OF_SEPARATE instead of depending from opensbi. riscv: ax25: add SPL support riscv: ax25-ae350: add SPL configuration riscv: ax25-ae350: Use generic memory size setup riscv: andes_plic: Fix some wrong configurations riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL spl: cache: Allow cache drivers in SPL riscv: Fix clear bss loop in the start-up code riscv: dts: Support four cores SMP riscv: dts: Add #address-cells and #size-cells in nor node doc: update AX25-AE350 RISC-V documentation
arch/riscv/Kconfig | 2 +- arch/riscv/cpu/ax25/Kconfig | 4 ++- arch/riscv/cpu/ax25/cache.c | 60 ++++++++++++++++++++++++++++++++++----------- arch/riscv/cpu/start.S | 6 +++-- arch/riscv/cpu/u-boot-spl.lds | 2 +- arch/riscv/cpu/u-boot.lds | 2 +- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/ae350_32.dts | 61 +++++++++++++++++++++++++++++++++++++++++++--- arch/riscv/dts/ae350_64.dts | 61 +++++++++++++++++++++++++++++++++++++++++++--- arch/riscv/dts/fu540-c000.dtsi | 251 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/riscv/dts/hifive-unleashed-a00.dts | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/riscv/include/asm/smp.h | 3 ++- arch/riscv/lib/andes_plic.c | 22 ++++++++++++++--- arch/riscv/lib/bootm.c | 2 +- arch/riscv/lib/sbi_ipi.c | 11 +++++++++ arch/riscv/lib/sifive_clint.c | 9 +++++++ arch/riscv/lib/smp.c | 43 ++++++++++++++++++++++++++------- arch/riscv/lib/spl.c | 2 +- board/AndesTech/ax25-ae350/Kconfig | 9 +++++++ board/AndesTech/ax25-ae350/MAINTAINERS | 4 +++ board/AndesTech/ax25-ae350/ax25-ae350.c | 48 +++++++++++++++++++++--------------- common/spl/Kconfig | 7 ++++++ common/spl/spl_opensbi.c | 13 +++++++++- configs/ae350_rv32_spl_defconfig | 38 +++++++++++++++++++++++++++++ configs/ae350_rv32_spl_xip_defconfig | 40 ++++++++++++++++++++++++++++++ configs/ae350_rv64_spl_defconfig | 39 ++++++++++++++++++++++++++++++ configs/ae350_rv64_spl_xip_defconfig | 41 +++++++++++++++++++++++++++++++ configs/sifive_fu540_defconfig | 3 ++- doc/board/AndesTech/ax25-ae350.rst | 209 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--- doc/board/sifive/fu540.rst | 5 +--- drivers/Makefile | 1 + include/configs/ax25-ae350.h | 17 +++++++++++++ include/opensbi.h | 18 +++++++++++++- 33 files changed, 1057 insertions(+), 73 deletions(-) create mode 100644 arch/riscv/dts/fu540-c000.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts create mode 100644 configs/ae350_rv32_spl_defconfig create mode 100644 configs/ae350_rv32_spl_xip_defconfig create mode 100644 configs/ae350_rv64_spl_defconfig create mode 100644 configs/ae350_rv64_spl_xip_defconfig

On Tue, Dec 10, 2019 at 09:05:59AM +0800, uboot@andestech.com wrote:
Hi Tom,
Please pull some riscv updates:
- Increase stack size to avoid a stack overflow during distro boot.
- Add hifive-unleashed-a00.dts for SIFIVE FU540.
- Add OF_SEPARATE support for SIFIVE FU540.
- Add SPL support for Andes AX25 AE350.
- Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
https://travis-ci.org/rickchen36/u-boot-riscv/builds/622462488
Thanks Rick
The following changes since commit 0c5c3f293554614416a188d16a8c05e0a6c5bfbb:
arm: -march=armv5t for ARM11 (2019-12-09 10:36:00 -0500)
are available in the Git repository at:
git@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 0e1233ce9069a87a84a4385de456665d2bc9229d:
spl: opensbi: wait for ack from secondary harts before entering OpenSBI (2019-12-10 08:23:10 +0800)
Applied to u-boot/master, thanks!
participants (2)
-
Tom Rini
-
uboot@andestech.com