[PATCH] mx6: peripheral clock from oscillator
In order to be able to run the I2C bus at 400Khz, the chip errata[1] recommends that the peripheral clock runs out of the 24MHz oscillator.
[1] Rev 2, 10/2019, ERR007805
Signed-off-by: Jorge Ramirez-Ortiz jorge@foundries.io --- arch/arm/mach-imx/mx6/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e129286065..1da250bbcd 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -469,7 +469,7 @@ int arch_cpu_init(void) }
/* Set perclk to source from OSC 24MHz */ - if (is_mx6sl()) + if (is_mx6sl() || is_mx6ull()) setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
any thoughts?
On 14/10/20, Jorge Ramirez-Ortiz wrote:
In order to be able to run the I2C bus at 400Khz, the chip errata[1] recommends that the peripheral clock runs out of the 24MHz oscillator.
[1] Rev 2, 10/2019, ERR007805
Signed-off-by: Jorge Ramirez-Ortiz jorge@foundries.io
arch/arm/mach-imx/mx6/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e129286065..1da250bbcd 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -469,7 +469,7 @@ int arch_cpu_init(void) }
/* Set perclk to source from OSC 24MHz */
- if (is_mx6sl())
if (is_mx6sl() || is_mx6ull()) setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
-- 2.17.1
Subject: [PATCH] mx6: peripheral clock from oscillator
In order to be able to run the I2C bus at 400Khz, the chip errata[1] recommends that the peripheral clock runs out of the 24MHz oscillator.
[1] Rev 2, 10/2019, ERR007805
Signed-off-by: Jorge Ramirez-Ortiz jorge@foundries.io
arch/arm/mach-imx/mx6/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e129286065..1da250bbcd 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -469,7 +469,7 @@ int arch_cpu_init(void) }
/* Set perclk to source from OSC 24MHz */
- if (is_mx6sl())
- if (is_mx6sl() || is_mx6ull()) setbits_le32(&ccm->cscmr1,
MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register
*/
Reviewed-by: Peng Fan peng.fan@nxp.com
Hi Jorge,
On Wed, Oct 14, 2020 at 10:07 AM Jorge Ramirez-Ortiz jorge@foundries.io wrote:
In order to be able to run the I2C bus at 400Khz, the chip errata[1] recommends that the peripheral clock runs out of the 24MHz oscillator.
[1] Rev 2, 10/2019, ERR007805
Signed-off-by: Jorge Ramirez-Ortiz jorge@foundries.io
arch/arm/mach-imx/mx6/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e129286065..1da250bbcd 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -469,7 +469,7 @@ int arch_cpu_init(void) }
/* Set perclk to source from OSC 24MHz */
if (is_mx6sl())
if (is_mx6sl() || is_mx6ull())
According to https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf the mx6solo and mx6dl are also affected by ERR007805.
These variants should be handled too.
On 19/10/20, Fabio Estevam wrote:
Hi Jorge,
On Wed, Oct 14, 2020 at 10:07 AM Jorge Ramirez-Ortiz jorge@foundries.io wrote:
In order to be able to run the I2C bus at 400Khz, the chip errata[1] recommends that the peripheral clock runs out of the 24MHz oscillator.
[1] Rev 2, 10/2019, ERR007805
Signed-off-by: Jorge Ramirez-Ortiz jorge@foundries.io
arch/arm/mach-imx/mx6/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e129286065..1da250bbcd 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -469,7 +469,7 @@ int arch_cpu_init(void) }
/* Set perclk to source from OSC 24MHz */
if (is_mx6sl())
if (is_mx6sl() || is_mx6ull())According to https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf the mx6solo and mx6dl are also affected by ERR007805.
ah ok, I'll repost.
just as background info, this is needed in order for OP-TEE to access the EdgeLock SE050 secure element at a decent speed. I couldnt merge the support for the imx6ul i2c driver during the last OP-TEE release but will try again when I find some time (surely before their next release)
These variants should be handled too.
On 19/10/20, Jorge Ramirez-Ortiz, Foundries wrote:
On 19/10/20, Fabio Estevam wrote:
Hi Jorge,
On Wed, Oct 14, 2020 at 10:07 AM Jorge Ramirez-Ortiz jorge@foundries.io wrote:
In order to be able to run the I2C bus at 400Khz, the chip errata[1] recommends that the peripheral clock runs out of the 24MHz oscillator.
[1] Rev 2, 10/2019, ERR007805
Signed-off-by: Jorge Ramirez-Ortiz jorge@foundries.io
arch/arm/mach-imx/mx6/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e129286065..1da250bbcd 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -469,7 +469,7 @@ int arch_cpu_init(void) }
/* Set perclk to source from OSC 24MHz */
if (is_mx6sl())
if (is_mx6sl() || is_mx6ull())According to https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf the mx6solo and mx6dl are also affected by ERR007805.
ah ok, I'll repost.
just as background info, this is needed in order for OP-TEE to access the EdgeLock SE050 secure element at a decent speed. I couldnt merge the support for the imx6ul i2c driver during the last OP-TEE release but will try again when I find some time (surely before their next release)
These variants should be handled too.
I just reposted but realized I forgot to ammend the patch version. let me know if you would like me to repost with that corrected or if that is ok.
participants (4)
-
Fabio Estevam -
Jorge Ramirez-Ortiz -
Jorge Ramirez-Ortiz, Foundries
-
Peng Fan