It is common for one node to reference another via a phandle. Add support for obtaining an attached device by this method. As an example, a node may have a 'power-supply' property which references a regulator, allowing the driver to turn on its power.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/core/uclass.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/dm/uclass.h | 17 +++++++++++++++++ 2 files changed, 59 insertions(+)

diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 7de8173..89532db 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -271,6 +271,37 @@ static int uclass_find_device_by_of_offset(enum uclass_id id, int node, return -ENODEV; }

+static int uclass_find_device_by_phandle(enum uclass_id id, + struct udevice *parent, + const char *name, + struct udevice **devp) +{ + struct udevice *dev; + struct uclass *uc; + int find_phandle; + int ret; + + *devp = NULL; + find_phandle = fdtdec_get_int(gd->fdt_blob, parent->of_offset, name, + -1); + if (find_phandle <= 0) + return -ENOENT; + ret = uclass_get(id, &uc); + if (ret) + return ret; + + list_for_each_entry(dev, &uc->dev_head, uclass_node) { + uint phandle = fdt_get_phandle(gd->fdt_blob, dev->of_offset); + + if (phandle == find_phandle) { + *devp = dev; + return 0; + } + } + + return -ENODEV; +} + int uclass_get_device_tail(struct udevice *dev, int ret, struct udevice **devp) { @@ -336,6 +367,17 @@ int uclass_get_device_by_of_offset(enum uclass_id id, int node, return uclass_get_device_tail(dev, ret, devp); }

+int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent, + const char *name, struct udevice **devp) +{ + struct udevice *dev; + int ret; + + *devp = NULL; + ret = uclass_find_device_by_phandle(id, parent, name, &dev); + return uclass_get_device_tail(dev, ret, devp); +} + int uclass_first_device(enum uclass_id id, struct udevice **devp) { struct udevice *dev; diff --git a/include/dm/uclass.h b/include/dm/uclass.h index 4cfc0df..3fe1739 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -177,6 +177,23 @@ int uclass_get_device_by_of_offset(enum uclass_id id, int node, struct udevice **devp);

/** + * uclass_get_device_by_phandle() - Get a uclass device by phandle + * + * This searches the devices in the uclass for one with the given phandle. + * + * The device is probed to activate it ready for use. + * + * @id: uclass ID to look up + * @parent: Parent device containing the phandle pointer + * @name: Name of property in the parent device node + * @devp: Returns pointer to device (there is only one for each node) + * @return 0 if OK, -ENOENT if there is no @name present in the node, other + * -ve on error + */ +int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent, + const char *name, struct udevice **devp); + +/** * uclass_first_device() - Get the first device in a uclass * * The device returned is probed if necessary, and ready for use

Add a way to dump the contents of an I2C message for debugging purposes.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/i2c/i2c-uclass.c | 16 ++++++++++++++++ include/i2c.h | 10 ++++++++++ 2 files changed, 26 insertions(+)

diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index eaba965..42d6e89 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -18,6 +18,22 @@ DECLARE_GLOBAL_DATA_PTR;

#define I2C_MAX_OFFSET_LEN 4

+/* Useful debugging function */ +void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs) +{ + int i; + + for (i = 0; i < nmsgs; i++) { + struct i2c_msg *m = &msg[i]; + + printf(" %s %x len=%x", m->flags & I2C_M_RD ? "R" : "W", + msg->addr, msg->len); + if (!(m->flags & I2C_M_RD)) + printf(": %x", m->buf[0]); + printf("\n"); + } +} + /** * i2c_setup_offset() - Set up a new message with a chip offset * diff --git a/include/i2c.h b/include/i2c.h index 9300d97..a5498a3 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -473,6 +473,16 @@ int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len, int i2c_chip_ofdata_to_platdata(const void *blob, int node, struct dm_i2c_chip *chip);

+/** + * i2c_dump_msgs() - Dump a list of I2C messages + * + * This may be useful for debugging. + * + * @msg: Message list to dump + * @nmsgs: Number of messages + */ +void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs); + #ifndef CONFIG_DM_I2C

/*

Move the flags and struct definitions higher in the file so that we can reference them with functions declared in the driver model section.

Signed-off-by: Simon Glass sjg@chromium.org ---

include/i2c.h | 86 +++++++++++++++++++++++++++++------------------------------ 1 file changed, 43 insertions(+), 43 deletions(-)

diff --git a/include/i2c.h b/include/i2c.h index e1ad8d8..4c0e263 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -74,6 +74,49 @@ struct dm_i2c_bus { int speed_hz; };

+/* + * Not all of these flags are implemented in the U-Boot API + */ +enum dm_i2c_msg_flags { + I2C_M_TEN = 0x0010, /* ten-bit chip address */ + I2C_M_RD = 0x0001, /* read data, from slave to master */ + I2C_M_STOP = 0x8000, /* send stop after this message */ + I2C_M_NOSTART = 0x4000, /* no start before this message */ + I2C_M_REV_DIR_ADDR = 0x2000, /* invert polarity of R/W bit */ + I2C_M_IGNORE_NAK = 0x1000, /* continue after NAK */ + I2C_M_NO_RD_ACK = 0x0800, /* skip the Ack bit on reads */ + I2C_M_RECV_LEN = 0x0400, /* length is first received byte */ +}; + +/** + * struct i2c_msg - an I2C message + * + * @addr: Slave address + * @flags: Flags (see enum dm_i2c_msg_flags) + * @len: Length of buffer in bytes, may be 0 for a probe + * @buf: Buffer to send/receive, or NULL if no data + */ +struct i2c_msg { + uint addr; + uint flags; + uint len; + u8 *buf; +}; + +/** + * struct i2c_msg_list - a list of I2C messages + * + * This is called i2c_rdwr_ioctl_data in Linux but the name does not seem + * appropriate in U-Boot. + * + * @msg: Pointer to i2c_msg array + * @nmsgs: Number of elements in the array + */ +struct i2c_msg_list { + struct i2c_msg *msgs; + uint nmsgs; +}; + /** * dm_i2c_read() - read bytes from an I2C chip * @@ -294,49 +337,6 @@ void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);

#endif

-/* - * Not all of these flags are implemented in the U-Boot API - */ -enum dm_i2c_msg_flags { - I2C_M_TEN = 0x0010, /* ten-bit chip address */ - I2C_M_RD = 0x0001, /* read data, from slave to master */ - I2C_M_STOP = 0x8000, /* send stop after this message */ - I2C_M_NOSTART = 0x4000, /* no start before this message */ - I2C_M_REV_DIR_ADDR = 0x2000, /* invert polarity of R/W bit */ - I2C_M_IGNORE_NAK = 0x1000, /* continue after NAK */ - I2C_M_NO_RD_ACK = 0x0800, /* skip the Ack bit on reads */ - I2C_M_RECV_LEN = 0x0400, /* length is first received byte */ -}; - -/** - * struct i2c_msg - an I2C message - * - * @addr: Slave address - * @flags: Flags (see enum dm_i2c_msg_flags) - * @len: Length of buffer in bytes, may be 0 for a probe - * @buf: Buffer to send/receive, or NULL if no data - */ -struct i2c_msg { - uint addr; - uint flags; - uint len; - u8 *buf; -}; - -/** - * struct i2c_msg_list - a list of I2C messages - * - * This is called i2c_rdwr_ioctl_data in Linux but the name does not seem - * appropriate in U-Boot. - * - * @msg: Pointer to i2c_msg array - * @nmsgs: Number of elements in the array - */ -struct i2c_msg_list { - struct i2c_msg *msgs; - uint nmsgs; -}; - /** * struct dm_i2c_ops - driver operations for I2C uclass *

Add a new I2C_MUX uclass. Devices in this class can multiplex between several I2C buses, selecting them one at a time for use by the system. The multiplexing mechanism is left to the driver to decide - it may be controlled by GPIOs, for example.

The uclass supports only two methods: select() and deselect().

Signed-off-by: Simon Glass sjg@chromium.org ---

doc/device-tree-bindings/i2c/i2c-mux.txt | 60 ++++++++++ drivers/i2c/Kconfig | 2 + drivers/i2c/Makefile | 2 + drivers/i2c/muxes/Kconfig | 8 ++ drivers/i2c/muxes/Makefile | 6 + drivers/i2c/muxes/i2c-mux-uclass.c | 198 +++++++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + include/i2c.h | 32 +++++ 8 files changed, 309 insertions(+) create mode 100644 doc/device-tree-bindings/i2c/i2c-mux.txt create mode 100644 drivers/i2c/muxes/Kconfig create mode 100644 drivers/i2c/muxes/Makefile create mode 100644 drivers/i2c/muxes/i2c-mux-uclass.c

diff --git a/doc/device-tree-bindings/i2c/i2c-mux.txt b/doc/device-tree-bindings/i2c/i2c-mux.txt new file mode 100644 index 0000000..af84cce --- /dev/null +++ b/doc/device-tree-bindings/i2c/i2c-mux.txt @@ -0,0 +1,60 @@ +Common i2c bus multiplexer/switch properties. + +An i2c bus multiplexer/switch will have several child busses that are +numbered uniquely in a device dependent manner. The nodes for an i2c bus +multiplexer/switch will have one child node for each child +bus. + +Required properties: +- #address-cells = <1>; +- #size-cells = <0>; + +Required properties for child nodes: +- #address-cells = <1>; +- #size-cells = <0>; +- reg : The sub-bus number. + +Optional properties for child nodes: +- Other properties specific to the multiplexer/switch hardware. +- Child nodes conforming to i2c bus binding + + +Example : + + /* + An NXP pca9548 8 channel I2C multiplexer at address 0x70 + with two NXP pca8574 GPIO expanders attached, one each to + ports 3 and 4. + */ + + mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + gpio1: gpio@38 { + compatible = "nxp,pca8574"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + gpio2: gpio@38 { + compatible = "nxp,pca8574"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + }; diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 86fb36b..caee3d8 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -73,3 +73,5 @@ config SYS_I2C_UNIPHIER_F help Support for UniPhier FIFO-builtin I2C controller driver. This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. + +source "drivers/i2c/muxes/Kconfig" diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index d9e912f..dc9e81b 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -37,3 +37,5 @@ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o + +obj-y += muxes/ diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig new file mode 100644 index 0000000..a05b32d --- /dev/null +++ b/drivers/i2c/muxes/Kconfig @@ -0,0 +1,8 @@ +config I2C_MUX + bool "Suport I2C multiplexers" + depends on DM_I2C + help + This enables I2C buses to be multiplexed, so that you can select + one of several buses using some sort of control mechanism. The + bus select is handled automatically when that bus is accessed, + using a suitable I2C MUX driver. diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile new file mode 100644 index 0000000..7583e3a --- /dev/null +++ b/drivers/i2c/muxes/Makefile @@ -0,0 +1,6 @@ +# +# Copyright (c) 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-$(CONFIG_I2C_MUX) += i2c-mux-uclass.o diff --git a/drivers/i2c/muxes/i2c-mux-uclass.c b/drivers/i2c/muxes/i2c-mux-uclass.c new file mode 100644 index 0000000..3f52bff --- /dev/null +++ b/drivers/i2c/muxes/i2c-mux-uclass.c @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <i2c.h> +#include <dm/lists.h> +#include <dm/root.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * struct i2c_mux: Information the uclass stores about an I2C mux + * + * @selected: Currently selected mux, or -1 for none + * @i2c_bus: I2C bus to use for communcation + */ +struct i2c_mux { + int selected; + struct udevice *i2c_bus; +}; + +/** + * struct i2c_mux_bus: Information about each bus the mux controls + * + * @channel: Channel number used to select this bus + */ +struct i2c_mux_bus { + uint channel; +}; + +/* Find out the mux channel number */ +static int i2c_mux_child_post_bind(struct udevice *dev) +{ + struct i2c_mux_bus *plat = dev_get_parent_platdata(dev); + int channel; + + channel = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); + if (channel < 0) + return -EINVAL; + plat->channel = channel; + + return 0; +} + +/* Find the I2C buses selected by this mux */ +static int i2c_mux_post_bind(struct udevice *mux) +{ + const void *blob = gd->fdt_blob; + int ret; + int offset; + + debug("%s: %s\n", __func__, mux->name); + /* + * There is no compatible string in the sub-nodes, so we must manually + * bind these + */ + for (offset = fdt_first_subnode(blob, mux->of_offset); + offset > 0; + offset = fdt_next_subnode(blob, offset)) { + struct udevice *dev; + const char *name; + + name = fdt_get_name(blob, offset, NULL); + ret = device_bind_driver_to_node(mux, "i2c_mux_bus_drv", name, + offset, &dev); + debug(" - bind ret=%d, %s\n", ret, dev ? dev->name : NULL); + if (ret) + return ret; + } + + return 0; +} + +/* Set up the mux ready for use */ +static int i2c_mux_post_probe(struct udevice *mux) +{ + struct i2c_mux *priv = dev_get_uclass_priv(mux); + int ret; + + debug("%s: %s\n", __func__, mux->name); + priv->selected = -1; + + ret = uclass_get_device_by_phandle(UCLASS_I2C, mux, "i2c-parent", + &priv->i2c_bus); + if (ret) + return ret; + debug("%s: bus=%p/%s\n", __func__, priv->i2c_bus, priv->i2c_bus->name); + + return 0; +} + +int i2c_mux_select(struct udevice *dev) +{ + struct i2c_mux_bus *plat = dev_get_parent_platdata(dev); + struct udevice *mux = dev->parent; + struct i2c_mux_ops *ops = i2c_mux_get_ops(mux); + + if (!ops->select) + return -ENOSYS; + + return ops->select(mux, dev, plat->channel); +} + +int i2c_mux_deselect(struct udevice *dev) +{ + struct i2c_mux_bus *plat = dev_get_parent_platdata(dev); + struct udevice *mux = dev->parent; + struct i2c_mux_ops *ops = i2c_mux_get_ops(mux); + + if (!ops->deselect) + return -ENOSYS; + + return ops->deselect(mux, dev, plat->channel); +} + +static int i2c_mux_bus_set_bus_speed(struct udevice *dev, unsigned int speed) +{ + struct udevice *mux = dev->parent; + struct i2c_mux *priv = dev_get_uclass_priv(mux); + int ret, ret2; + + ret = i2c_mux_select(dev); + if (ret) + return ret; + ret = dm_i2c_set_bus_speed(priv->i2c_bus, speed); + ret2 = i2c_mux_deselect(dev); + + return ret ? ret : ret2; +} + +static int i2c_mux_bus_probe(struct udevice *dev, uint chip_addr, + uint chip_flags) +{ + struct udevice *mux = dev->parent; + struct i2c_mux *priv = dev_get_uclass_priv(mux); + struct dm_i2c_ops *ops = i2c_get_ops(priv->i2c_bus); + int ret, ret2; + + debug("%s: %s, bus %s\n", __func__, dev->name, priv->i2c_bus->name); + if (!ops->probe_chip) + return -ENOSYS; + ret = i2c_mux_select(dev); + if (ret) + return ret; + ret = ops->probe_chip(priv->i2c_bus, chip_addr, chip_flags); + ret2 = i2c_mux_deselect(dev); + + return ret ? ret : ret2; +} + +static int i2c_mux_bus_xfer(struct udevice *dev, struct i2c_msg *msg, + int nmsgs) +{ + struct udevice *mux = dev->parent; + struct i2c_mux *priv = dev_get_uclass_priv(mux); + struct dm_i2c_ops *ops = i2c_get_ops(priv->i2c_bus); + int ret, ret2; + + debug("%s: %s, bus %s\n", __func__, dev->name, priv->i2c_bus->name); + if (!ops->xfer) + return -ENOSYS; + ret = i2c_mux_select(dev); + if (ret) + return ret; + ret = ops->xfer(priv->i2c_bus, msg, nmsgs); + ret2 = i2c_mux_deselect(dev); + + return ret ? ret : ret2; +} + +static const struct dm_i2c_ops i2c_mux_bus_ops = { + .xfer = i2c_mux_bus_xfer, + .probe_chip = i2c_mux_bus_probe, + .set_bus_speed = i2c_mux_bus_set_bus_speed, +}; + +U_BOOT_DRIVER(i2c_mux_bus) = { + .name = "i2c_mux_bus_drv", + .id = UCLASS_I2C, + .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), + .ops = &i2c_mux_bus_ops, +}; + +UCLASS_DRIVER(i2c_mux) = { + .id = UCLASS_I2C_MUX, + .name = "i2c_mux", + .post_bind = i2c_mux_post_bind, + .post_probe = i2c_mux_post_probe, + .per_device_auto_alloc_size = sizeof(struct i2c_mux), + .per_child_platdata_auto_alloc_size = sizeof(struct i2c_mux_bus), + .child_post_bind = i2c_mux_child_post_bind, +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 72512b5..e2c3480 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -35,6 +35,7 @@ enum uclass_id { UCLASS_I2C, /* I2C bus */ UCLASS_I2C_EEPROM, /* I2C EEPROM device */ UCLASS_I2C_GENERIC, /* Generic I2C device */ + UCLASS_I2C_MUX, /* I2C multiplexer */ UCLASS_LED, /* Light-emitting diode (LED) */ UCLASS_LPC, /* x86 'low pin count' interface */ UCLASS_MASS_STORAGE, /* Mass storage device */ diff --git a/include/i2c.h b/include/i2c.h index d191829..a59a19a 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -445,6 +445,38 @@ struct dm_i2c_ops { #define i2c_get_ops(dev) ((struct dm_i2c_ops *)(dev)->driver->ops)

/** + * struct i2c_mux_ops - operations for an I2C mux + */ +struct i2c_mux_ops { + /** + * select() - select one of of I2C buses attached to a mux + * + * This will be called when there is no bus currently selected by the + * mux. This method does not need to deselect the old bus. + * + * @mux: Mux device + * @bus: I2C bus to select + * @channel: Channel number correponding to the bus to select + * @return 0 if OK, -ve on error + */ + int (*select)(struct udevice *mux, struct udevice *bus, uint channel); + + /** + * deselect() - select one of of I2C buses attached to a mux + * + * This is used to deselect the currently selected I2C bus. + * + * @mux: Mux device + * @bus: I2C bus to deselect + * @channel: Channel number correponding to the bus to deselect + * @return 0 if OK, -ve on error + */ + int (*deselect)(struct udevice *mux, struct udevice *bus, uint channel); +}; + +#define i2c_mux_get_ops(dev) ((struct i2c_mux_ops *)(dev)->driver->ops) + +/** * i2c_get_chip() - get a device to use to access a chip on a bus * * This returns the device for the given chip address. The device can then

This function should not use mixed case, and it is simpler to use clrbits_le32() when clearing bits. Fix it.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/i2c/s3c24x0_i2c.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 9a04e48..4bbd012 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -258,9 +258,9 @@ static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) return I2C_NOK_TOUT; }

-static void ReadWriteByte(struct s3c24x0_i2c *i2c) +static void read_write_byte(struct s3c24x0_i2c *i2c) { - writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); + clrbits_le32(&i2c->iiccon, I2CCON_IRPND); }

#ifdef CONFIG_SYS_I2C @@ -794,7 +794,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, if (addr && addr_len) { while ((i < addr_len) && (result == I2C_OK)) { writel(addr[i++], &i2c->iicds); - ReadWriteByte(i2c); + read_write_byte(i2c); result = WaitForXfer(i2c); } i = 0; @@ -806,7 +806,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, case I2C_WRITE: while ((i < data_len) && (result == I2C_OK)) { writel(data[i++], &i2c->iicds); - ReadWriteByte(i2c); + read_write_byte(i2c); result = WaitForXfer(i2c); } break; @@ -822,7 +822,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, /* Generate a re-START. */ writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, &i2c->iicstat); - ReadWriteByte(i2c); + read_write_byte(i2c); result = WaitForXfer(i2c);

if (result != I2C_OK) @@ -835,7 +835,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, writel(readl(&i2c->iiccon) & ~I2CCON_ACKGEN, &i2c->iiccon); - ReadWriteByte(i2c); + read_write_byte(i2c); result = WaitForXfer(i2c); data[i++] = readl(&i2c->iicds); } @@ -852,7 +852,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, bailout: /* Send STOP. */ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); - ReadWriteByte(i2c); + read_write_byte(i2c);

return result; }

The kernel uses upper case for I2C unit addresses. Follow the same convention to reduce differences.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/dts/exynos5.dtsi | 34 ++++++++++++++++----------------- arch/arm/dts/exynos5250-arndale.dts | 16 ++++++++-------- arch/arm/dts/exynos5250-smdk5250.dts | 21 ++++++++++---------- arch/arm/dts/exynos5250-snow.dts | 32 +++++++++++++++++-------------- arch/arm/dts/exynos5250.dtsi | 24 +++++++++++------------ arch/arm/dts/exynos5420-peach-pit.dts | 8 ++++---- arch/arm/dts/exynos5420-smdk5420.dts | 4 ++-- arch/arm/dts/exynos54xx.dtsi | 36 +++++++++++++++++------------------ arch/arm/dts/exynos5800-peach-pi.dts | 8 ++++---- 9 files changed, 94 insertions(+), 89 deletions(-)

diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi index 238acb8..179584c 100644 --- a/arch/arm/dts/exynos5.dtsi +++ b/arch/arm/dts/exynos5.dtsi @@ -72,39 +72,39 @@ interrupts = <1 9 0xf04>; };

- i2c@12c60000 { - #address-cells = <1>; - #size-cells = <0>; + i2c_0: i2c@12C60000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C60000 0x100>; interrupts = <0 56 0>; - }; - - i2c@12c70000 { #address-cells = <1>; #size-cells = <0>; + }; + + i2c_1: i2c@12C70000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C70000 0x100>; interrupts = <0 57 0>; - }; - - i2c@12c80000 { #address-cells = <1>; #size-cells = <0>; + }; + + i2c_2: i2c@12C80000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C80000 0x100>; interrupts = <0 58 0>; - }; - - i2c@12c90000 { #address-cells = <1>; #size-cells = <0>; + }; + + i2c_3: i2c@12C90000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C90000 0x100>; interrupts = <0 59 0>; + #address-cells = <1>; + #size-cells = <0>; };

- spi@12d20000 { + spi_0: spi@12d20000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos-spi"; @@ -112,7 +112,7 @@ interrupts = <0 68 0>; };

- spi@12d30000 { + spi_1: spi@12d30000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos-spi"; @@ -120,7 +120,7 @@ interrupts = <0 69 0>; };

- spi@12d40000 { + spi_2: spi@12d40000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos-spi"; @@ -129,7 +129,7 @@ interrupts = <0 70 0>; };

- spi@131a0000 { + spi_3: spi@131a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos-spi"; @@ -137,7 +137,7 @@ interrupts = <0 129 0>; };

- spi@131b0000 { + spi_4: spi@131b0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos-spi"; diff --git a/arch/arm/dts/exynos5250-arndale.dts b/arch/arm/dts/exynos5250-arndale.dts index 21c0a21..031c622 100644 --- a/arch/arm/dts/exynos5250-arndale.dts +++ b/arch/arm/dts/exynos5250-arndale.dts @@ -15,14 +15,14 @@ compatible = "samsung,arndale", "samsung,exynos5250";

aliases { - i2c0 = "/i2c@12c60000"; - i2c1 = "/i2c@12c70000"; - i2c2 = "/i2c@12c80000"; - i2c3 = "/i2c@12c90000"; - i2c4 = "/i2c@12ca0000"; - i2c5 = "/i2c@12cb0000"; - i2c6 = "/i2c@12cc0000"; - i2c7 = "/i2c@12cd0000"; + i2c0 = "/i2c@12C60000"; + i2c1 = "/i2c@12C70000"; + i2c2 = "/i2c@12C80000"; + i2c3 = "/i2c@12C90000"; + i2c4 = "/i2c@12CA0000"; + i2c5 = "/i2c@12CB0000"; + i2c6 = "/i2c@12CC0000"; + i2c7 = "/i2c@12CD0000"; serial0 = "/serial@12C20000"; console = "/serial@12C20000"; }; diff --git a/arch/arm/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts index 3cebfc2..636fec9 100644 --- a/arch/arm/dts/exynos5250-smdk5250.dts +++ b/arch/arm/dts/exynos5250-smdk5250.dts @@ -11,20 +11,21 @@

/dts-v1/; #include "exynos5250.dtsi" +#include <dt-bindings/interrupt-controller/irq.h>

/ { model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; compatible = "samsung,smdk5250", "samsung,exynos5250";

aliases { - i2c0 = "/i2c@12c60000"; - i2c1 = "/i2c@12c70000"; - i2c2 = "/i2c@12c80000"; - i2c3 = "/i2c@12c90000"; - i2c4 = "/i2c@12ca0000"; - i2c5 = "/i2c@12cb0000"; - i2c6 = "/i2c@12cc0000"; - i2c7 = "/i2c@12cd0000"; + i2c0 = "/i2c@12C60000"; + i2c1 = "/i2c@12C70000"; + i2c2 = "/i2c@12C80000"; + i2c3 = "/i2c@12C90000"; + i2c4 = "/i2c@12CA0000"; + i2c5 = "/i2c@12CB0000"; + i2c6 = "/i2c@12CC0000"; + i2c7 = "/i2c@12CD0000"; spi0 = "/spi@12d20000"; spi1 = "/spi@12d30000"; spi2 = "/spi@12d40000"; @@ -58,14 +59,14 @@ status = "disabled"; };

- i2c@12c70000 { + i2c@12C70000 { soundcodec@1a { reg = <0x1a>; compatible = "wolfson,wm8994-codec"; }; };

- i2c@12c60000 { + i2c@12C60000 { pmic@9 { reg = <0x9>; compatible = "maxim,max77686"; diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts index e4b3dc2..9abe0b7 100644 --- a/arch/arm/dts/exynos5250-snow.dts +++ b/arch/arm/dts/exynos5250-snow.dts @@ -7,24 +7,27 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. -*/ + */

/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/input/input.h> #include "exynos5250.dtsi"

/ { model = "Google Snow"; - compatible = "google,snow", "samsung,exynos5250"; + compatible = "google,snow", "samsung,exynos5250", "samsung,exynos5";

aliases { - i2c0 = "/i2c@12c60000"; - i2c1 = "/i2c@12c70000"; - i2c2 = "/i2c@12c80000"; - i2c3 = "/i2c@12c90000"; - i2c4 = "/i2c@12ca0000"; - i2c5 = "/i2c@12cb0000"; - i2c6 = "/i2c@12cc0000"; - i2c7 = "/i2c@12cd0000"; + i2c0 = "/i2c@12C60000"; + i2c1 = "/i2c@12C70000"; + i2c2 = "/i2c@12C80000"; + i2c3 = "/i2c@12C90000"; + i2c4 = "/i2c@12CA0000"; + i2c5 = "/i2c@12CB0000"; + i2c6 = "/i2c@12CC0000"; + i2c7 = "/i2c@12CD0000"; spi0 = "/spi@12d20000"; spi1 = "/spi@12d30000"; spi2 = "/spi@12d40000"; @@ -39,7 +42,7 @@ i2s = "/sound@3830000"; };

- i2c4: i2c@12ca0000 { + i2c4: i2c@12CA0000 { cros_ec: cros-ec@1e { reg = <0x1e>; compatible = "google,cros-ec-i2c"; @@ -66,6 +69,7 @@ spi-max-frequency = <1000000>; spi-deactivate-delay = <100>;

+ /* Snow did support SPI but the released version used I2C */ embedded-controller { compatible = "google,cros-ec-i2c"; reg = <0x1e>; @@ -85,7 +89,7 @@ status = "disabled"; };

- i2c@12cd0000 { + i2c@12CD0000 { soundcodec@22 { reg = <0x22>; compatible = "maxim,max98095-codec"; @@ -105,8 +109,8 @@ }; };

- i2c@12c60000 { - pmic@9 { + i2c@12C60000 { + max77686@09 { reg = <0x9>; compatible = "maxim,max77686"; }; diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index ccbafe9..7eef3e3 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -47,36 +47,36 @@ interrupts = <0 47 0>; };

- i2c@12ca0000 { - #address-cells = <1>; - #size-cells = <0>; + i2c_4: i2c@12CA0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CA0000 0x100>; interrupts = <0 60 0>; - }; - - i2c@12cb0000 { #address-cells = <1>; #size-cells = <0>; + }; + + i2c_5: i2c@12CB0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CB0000 0x100>; interrupts = <0 61 0>; - }; - - i2c@12cc0000 { #address-cells = <1>; #size-cells = <0>; + }; + + i2c_6: i2c@12CC0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CC0000 0x100>; interrupts = <0 62 0>; - }; - - i2c@12cd0000 { #address-cells = <1>; #size-cells = <0>; + }; + + i2c_7: i2c@12CD0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CD0000 0x100>; interrupts = <0 63 0>; + #address-cells = <1>; + #size-cells = <0>; };

sound@3830000 { diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 6fe762d..0f1002e 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -25,7 +25,7 @@ aliases { serial0 = "/serial@12C30000"; console = "/serial@12C30000"; - pmic = "/i2c@12ca0000"; + pmic = "/i2c@12CA0000"; };

dmc { @@ -49,7 +49,7 @@ };

/* MAX77802 is on i2c bus 4 */ - i2c@12ca0000 { + i2c@12CA0000 { clock-frequency = <400000>; power-regulator@9 { compatible = "maxim,max77802-pmic"; @@ -57,7 +57,7 @@ }; };

- i2c@12cd0000 { /* i2c7 */ + i2c@12CD0000 { /* i2c7 */ clock-frequency = <100000>; soundcodec@20 { reg = <0x20>; @@ -76,7 +76,7 @@ samsung,codec-type = "max98090"; };

- i2c@12e10000 { /* i2c9 */ + i2c@12E10000 { /* i2c9 */ clock-frequency = <400000>; tpm@20 { compatible = "infineon,slb9645tt"; diff --git a/arch/arm/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts index 6855027..015ff15 100644 --- a/arch/arm/dts/exynos5420-smdk5420.dts +++ b/arch/arm/dts/exynos5420-smdk5420.dts @@ -37,7 +37,7 @@ };

/* s2mps11 is on i2c bus 4 */ - i2c@12ca0000 { + i2c@12CA0000 { #address-cells = <1>; #size-cells = <0>; pmic@66 { @@ -82,7 +82,7 @@ samsung,codec-type = "wm8994"; };

- i2c@12c70000 { + i2c@12C70000 { soundcodec@1a { reg = <0x1a>; compatible = "wolfson,wm8994-codec"; diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi index 31fabb1..bd3619d 100644 --- a/arch/arm/dts/exynos54xx.dtsi +++ b/arch/arm/dts/exynos54xx.dtsi @@ -14,17 +14,17 @@ };

aliases { - i2c0 = "/i2c@12c60000"; - i2c1 = "/i2c@12c70000"; - i2c2 = "/i2c@12c80000"; - i2c3 = "/i2c@12c90000"; - i2c4 = "/i2c@12ca0000"; - i2c5 = "/i2c@12cb0000"; - i2c6 = "/i2c@12cc0000"; - i2c7 = "/i2c@12cd0000"; - i2c8 = "/i2c@12e00000"; - i2c9 = "/i2c@12e10000"; - i2c10 = "/i2c@12e20000"; + i2c0 = "/i2c@12C60000"; + i2c1 = "/i2c@12C70000"; + i2c2 = "/i2c@12C80000"; + i2c3 = "/i2c@12C90000"; + i2c4 = "/i2c@12CA0000"; + i2c5 = "/i2c@12CB0000"; + i2c6 = "/i2c@12CC0000"; + i2c7 = "/i2c@12CD0000"; + i2c8 = "/i2c@12E00000"; + i2c9 = "/i2c@12E10000"; + i2c10 = "/i2c@12E20000"; pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; @@ -42,7 +42,7 @@ xhci1 = "/xhci@12400000"; };

- i2c@12ca0000 { + i2c@12CA0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos5-hsi2c"; @@ -50,7 +50,7 @@ interrupts = <0 60 0>; };

- i2c@12cb0000 { + i2c@12CB0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos5-hsi2c"; @@ -58,7 +58,7 @@ interrupts = <0 61 0>; };

- i2c@12cc0000 { + i2c@12CC0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos5-hsi2c"; @@ -66,7 +66,7 @@ interrupts = <0 62 0>; };

- i2c@12cd0000 { + i2c@12CD0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos5-hsi2c"; @@ -74,7 +74,7 @@ interrupts = <0 63 0>; };

- i2c@12e00000 { + i2c@12E00000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos5-hsi2c"; @@ -82,7 +82,7 @@ interrupts = <0 87 0>; };

- i2c@12e10000 { + i2c@12E10000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos5-hsi2c"; @@ -90,7 +90,7 @@ interrupts = <0 88 0>; };

- i2c@12e20000 { + i2c@12E20000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos5-hsi2c"; diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index 176ce55..4e548f7 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -25,7 +25,7 @@ aliases { serial0 = "/serial@12C30000"; console = "/serial@12C30000"; - pmic = "/i2c@12ca0000"; + pmic = "/i2c@12CA0000"; };

dmc { @@ -49,7 +49,7 @@ };

/* MAX77802 is on i2c bus 4 */ - i2c@12ca0000 { + i2c@12CA0000 { clock-frequency = <400000>; power-regulator@9 { compatible = "maxim,max77802-pmic"; @@ -57,7 +57,7 @@ }; };

- i2c@12cd0000 { /* i2c7 */ + i2c@12CD0000 { /* i2c7 */ clock-frequency = <100000>; soundcodec@20 { reg = <0x20>; @@ -69,7 +69,7 @@ samsung,codec-type = "max98090"; };

- i2c@12e10000 { /* i2c9 */ + i2c@12E10000 { /* i2c9 */ clock-frequency = <400000>; tpm@20 { compatible = "infineon,slb9645tt";

On pit and pi the TPS65090 regulator is connected only to the EC and we must use a tunnel to get to it. The existing U-Boot support relies on a special driver. Add a tunnel definition so that the new device-model TPS65090 driver can be used unmodified.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/dts/exynos5250-snow.dts | 98 ++++++++++++++++++++++++++- arch/arm/dts/exynos5420-peach-pit.dts | 124 +++++++++++++++++++++++++++------- arch/arm/dts/exynos5800-peach-pi.dts | 123 ++++++++++++++++++++++++++------- 3 files changed, 297 insertions(+), 48 deletions(-)

diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts index 06d675b..653efb4 100644 --- a/arch/arm/dts/exynos5250-snow.dts +++ b/arch/arm/dts/exynos5250-snow.dts @@ -25,6 +25,7 @@ i2c2 = "/i2c@12C80000"; i2c3 = "/i2c@12C90000"; i2c4 = "/i2c@12CA0000"; + i2c104 = &i2c_104; i2c5 = "/i2c@12CB0000"; i2c6 = "/i2c@12CC0000"; i2c7 = "/i2c@12CD0000"; @@ -43,7 +44,7 @@ };

i2c4: i2c@12CA0000 { - cros_ec: cros-ec@1e { + cros_ec_old: cros-ec@1e { reg = <0x1e>; compatible = "google,cros-ec-i2c"; i2c-max-frequency = <100000>; @@ -57,6 +58,101 @@ }; };

+ i2c-arbitrator { + compatible = "i2c-arb-gpio-challenge"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@12CA0000}>; + + our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; + their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; + slew-delay-us = <10>; + wait-retry-us = <3000>; + wait-free-us = <50000>; + + /* Use ID 104 as a hint that we're on physical bus 4 */ + i2c_104: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,poll-retry-count = <1>; + }; + + cros_ec: embedded-controller { + compatible = "google,cros-ec-i2c"; + reg = <0x1e>; + interrupts = <6 IRQ_TYPE_NONE>; + interrupt-parent = <&gpx1>; + wakeup-source; + i2c-max-frequency = <100000>; + u-boot,i2c-offset-len = <0>; + ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>; + }; + + power-regulator { + compatible = "ti,tps65090"; + reg = <0x48>; + + regulators { + dcdc1 { + ti,enable-ext-control; + }; + dcdc2 { + ti,enable-ext-control; + }; + dcdc3 { + ti,enable-ext-control; + }; + fet1: fet1 { + regulator-name = "vcd_led"; + ti,overcurrent-wait = <3>; + }; + tps65090_fet2: fet2 { + regulator-name = "video_mid"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + fet3 { + regulator-name = "wwan_r"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + fet4 { + regulator-name = "sdcard"; + ti,overcurrent-wait = <3>; + }; + fet5 { + regulator-name = "camout"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + fet6: fet6 { + regulator-name = "lcd_vdd"; + ti,overcurrent-wait = <3>; + }; + tps65090_fet7: fet7 { + regulator-name = "video_mid_1a"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + ldo1 { + }; + ldo2 { + }; + }; + + charger { + compatible = "ti,tps65090-charger"; + }; + }; + }; + }; + spi@12d30000 { spi-max-frequency = <50000000>; firmware_storage_spi: flash@0 { diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 0f1002e..5182b2b 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -26,6 +26,7 @@ serial0 = "/serial@12C30000"; console = "/serial@12C30000"; pmic = "/i2c@12CA0000"; + i2c104 = &i2c_tunnel; };

dmc { @@ -101,30 +102,6 @@ }; };

- spi@12d40000 { /* spi2 */ - spi-max-frequency = <4000000>; - spi-deactivate-delay = <200>; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - spi-half-duplex; - spi-max-timeout-ms = <1100>; - ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>; - - /* - * This describes the flash memory within the EC. Note - * that the STM32L flash erases to 0, not 0xff. - */ - #address-cells = <1>; - #size-cells = <1>; - flash@8000000 { - reg = <0x08000000 0x20000>; - erase-value = <0>; - }; - }; - }; - xhci@12000000 { samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; }; @@ -159,4 +136,103 @@ }; };

+&spi_2 { + spi-max-frequency = <3125000>; + spi-deactivate-delay = <200>; + status = "okay"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + cs-gpios = <&gpb1 2 0>; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + interrupt-parent = <&gpx1>; + interrupts = <5 0>; + reg = <0>; + spi-half-duplex; + spi-max-timeout-ms = <1100>; + ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <1>; + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + }; + + controller-data { + samsung,spi-feedback-delay = <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + google,remote-bus = <0>; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,poll-retry-count = <1>; + sbs,i2c-retry-count = <2>; + }; + + power-regulator@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + + regulators { + tps65090_dcdc1: dcdc1 { + ti,enable-ext-control; + }; + tps65090_dcdc2: dcdc2 { + ti,enable-ext-control; + }; + tps65090_dcdc3: dcdc3 { + ti,enable-ext-control; + }; + tps65090_fet1: fet1 { + regulator-name = "vcd_led"; + }; + tps65090_fet2: fet2 { + regulator-name = "video_mid"; + regulator-always-on; + }; + tps65090_fet3: fet3 { + regulator-name = "wwan_r"; + regulator-always-on; + }; + tps65090_fet4: fet4 { + regulator-name = "sdcard"; + regulator-always-on; + }; + tps65090_fet5: fet5 { + regulator-name = "camout"; + regulator-always-on; + }; + tps65090_fet6: fet6 { + regulator-name = "lcd_vdd"; + }; + tps65090_fet7: fet7 { + regulator-name = "video_mid_1a"; + regulator-always-on; + }; + tps65090_ldo1: ldo1 { + }; + tps65090_ldo2: ldo2 { + }; + }; + + charger { + compatible = "ti,tps65090-charger"; + }; + }; + }; + }; +}; + #include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index 4e548f7..600c294 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -26,6 +26,7 @@ serial0 = "/serial@12C30000"; console = "/serial@12C30000"; pmic = "/i2c@12CA0000"; + i2c104 = &i2c_tunnel; };

dmc { @@ -93,29 +94,6 @@ }; };

- spi@12d40000 { /* spi2 */ - spi-max-frequency = <4000000>; - spi-deactivate-delay = <200>; - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - spi-half-duplex; - spi-max-timeout-ms = <1100>; - ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>; - - /* - * This describes the flash memory within the EC. Note - * that the STM32L flash erases to 0, not 0xff. - */ - #address-cells = <1>; - #size-cells = <1>; - flash@8000000 { - reg = <0x08000000 0x20000>; - erase-value = <0>; - }; - }; - }; - xhci@12000000 { samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; }; @@ -153,4 +131,103 @@ }; };

+&spi_2 { + spi-max-frequency = <3125000>; + spi-deactivate-delay = <200>; + status = "okay"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + cs-gpios = <&gpb1 2 0>; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + interrupt-parent = <&gpx1>; + interrupts = <5 0>; + reg = <0>; + spi-half-duplex; + spi-max-timeout-ms = <1100>; + ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>; + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + }; + + controller-data { + samsung,spi-feedback-delay = <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + google,remote-bus = <0>; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,poll-retry-count = <1>; + sbs,i2c-retry-count = <2>; + }; + + power-regulator@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + + regulators { + tps65090_dcdc1: dcdc1 { + ti,enable-ext-control; + }; + tps65090_dcdc2: dcdc2 { + ti,enable-ext-control; + }; + tps65090_dcdc3: dcdc3 { + ti,enable-ext-control; + }; + tps65090_fet1: fet1 { + regulator-name = "vcd_led"; + }; + tps65090_fet2: fet2 { + regulator-name = "video_mid"; + regulator-always-on; + }; + tps65090_fet3: fet3 { + regulator-name = "wwan_r"; + regulator-always-on; + }; + tps65090_fet4: fet4 { + regulator-name = "sdcard"; + regulator-always-on; + }; + tps65090_fet5: fet5 { + regulator-name = "camout"; + regulator-always-on; + }; + tps65090_fet6: fet6 { + regulator-name = "lcd_vdd"; + }; + tps65090_fet7: fet7 { + regulator-name = "video_mid_1a"; + regulator-always-on; + }; + tps65090_ldo1: ldo1 { + }; + tps65090_ldo2: ldo2 { + }; + }; + + charger { + compatible = "ti,tps65090-charger"; + }; + }; + }; + }; +}; + #include "cros-ec-keyboard.dtsi"

The Chrome OS EC supports tunnelling through to an I2C bus on the EC. This currently uses a copy of the I2C command code and a special 'crosec' sub-command.

With driver model we can define an I2C bus which tunnels through to the EC, and use the normal 'i2c' command to access it. This simplifies the code and removes some duplication.

Add an I2C driver which tunnels through to the EC. Adjust the EC code to support binding child devices so that it can be set up. Adjust the existing I2C xfer function to fit driver model better.

For now the old code remains to allow things to still work. It will be removed in a later patch once the new flow is fully enabled.

Signed-off-by: Simon Glass sjg@chromium.org ---

configs/peach-pi_defconfig | 2 + configs/peach-pit_defconfig | 2 + drivers/i2c/Kconfig | 11 +++++ drivers/i2c/Makefile | 1 + drivers/i2c/cros_ec_tunnel.c | 41 +++++++++++++++ drivers/misc/cros_ec.c | 93 +++++++++++++++++++++++++++++++++-- drivers/power/pmic/pmic_tps65090_ec.c | 8 +-- include/cros_ec.h | 14 +++++- 8 files changed, 161 insertions(+), 11 deletions(-) create mode 100644 drivers/i2c/cros_ec_tunnel.c

diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 88f5e97..13295b5 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_CROS_EC_KEYB=y +CONFIG_I2C_MUX=y +CONFIG_I2C_CROS_EC_TUNNEL=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index e6b5bce..78ec49d 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_CROS_EC_KEYB=y +CONFIG_I2C_MUX=y +CONFIG_I2C_CROS_EC_TUNNEL=y diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index caee3d8..e861b53 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -19,6 +19,17 @@ config DM_I2C_COMPAT to convert all code for a board in a single commit. It should not be enabled for any board in an official release.

+config I2C_CROS_EC_TUNNEL + tristate "Chrome OS EC tunnel I2C bus" + depends on CROS_EC + help + This provides an I2C bus that will tunnel i2c commands through to + the other side of the Chrome OS EC to the I2C bus connected there. + This will work whatever the interface used to talk to the EC (SPI, + I2C or LPC). Some Chromebooks use this when the hardware design + does not allow direct access to the main PMIC from the AP. + + config DM_I2C_GPIO bool "Enable Driver Model for software emulated I2C bus driver" depends on DM_I2C && DM_GPIO diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index dc9e81b..7f01fce 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_DM_I2C) += i2c-uclass.o obj-$(CONFIG_DM_I2C_COMPAT) += i2c-uclass-compat.o obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o +obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o

obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o obj-$(CONFIG_I2C_MV) += mv_i2c.o diff --git a/drivers/i2c/cros_ec_tunnel.c b/drivers/i2c/cros_ec_tunnel.c new file mode 100644 index 0000000..7ab1fd8 --- /dev/null +++ b/drivers/i2c/cros_ec_tunnel.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <cros_ec.h> +#include <errno.h> +#include <i2c.h> + +static int cros_ec_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) +{ + return 0; +} + +static int cros_ec_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, + int nmsgs) +{ + return cros_ec_i2c_tunnel(dev->parent, msg, nmsgs); +} + +static const struct dm_i2c_ops cros_ec_i2c_ops = { + .xfer = cros_ec_i2c_xfer, + .set_bus_speed = cros_ec_i2c_set_bus_speed, +}; + +static const struct udevice_id cros_ec_i2c_ids[] = { + { .compatible = "google,cros-ec-i2c-tunnel" }, + { } +}; + +U_BOOT_DRIVER(cros_ec_tunnel) = { + .name = "cros_ec_tunnel", + .id = UCLASS_I2C, + .of_match = cros_ec_i2c_ids, + .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), + .ops = &cros_ec_i2c_ops, +}; diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 4b6ac6a..ae52561 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -26,6 +26,7 @@ #include <asm/io.h> #include <asm-generic/gpio.h> #include <dm/device-internal.h> +#include <dm/root.h> #include <dm/uclass-internal.h>

#ifdef DEBUG_TRACE @@ -1053,8 +1054,8 @@ int cros_ec_decode_ec_flash(const void *blob, int node, return 0; }

-int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr, - int alen, uchar *buffer, int len, int is_read) +int cros_ec_i2c_xfer_old(struct cros_ec_dev *dev, uchar chip, uint addr, + int alen, uchar *buffer, int len, int is_read) { union { struct ec_params_i2c_passthru p; @@ -1134,6 +1135,81 @@ int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr, return 0; }

+int cros_ec_i2c_tunnel(struct udevice *dev, struct i2c_msg *in, int nmsgs) +{ + struct cros_ec_dev *cdev = dev_get_uclass_priv(dev); + union { + struct ec_params_i2c_passthru p; + uint8_t outbuf[EC_PROTO2_MAX_PARAM_SIZE]; + } params; + union { + struct ec_response_i2c_passthru r; + uint8_t inbuf[EC_PROTO2_MAX_PARAM_SIZE]; + } response; + struct ec_params_i2c_passthru *p = &params.p; + struct ec_response_i2c_passthru *r = &response.r; + struct ec_params_i2c_passthru_msg *msg; + uint8_t *pdata, *read_ptr = NULL; + int read_len; + int size; + int rv; + int i; + + p->port = 0; + + p->num_msgs = nmsgs; + size = sizeof(*p) + p->num_msgs * sizeof(*msg); + + /* Create a message to write the register address and optional data */ + pdata = (uint8_t *)p + size; + + read_len = 0; + for (i = 0, msg = p->msg; i < nmsgs; i++, msg++, in++) { + bool is_read = in->flags & I2C_M_RD; + + msg->addr_flags = in->addr; + msg->len = in->len; + if (is_read) { + msg->addr_flags |= EC_I2C_FLAG_READ; + read_len += in->len; + read_ptr = in->buf; + if (sizeof(*r) + read_len > sizeof(response)) { + puts("Read length too big for buffer\n"); + return -1; + } + } else { + if (pdata - (uint8_t *)p + in->len > sizeof(params)) { + puts("Params too large for buffer\n"); + return -1; + } + memcpy(pdata, in->buf, in->len); + pdata += in->len; + } + } + + rv = ec_command(cdev, EC_CMD_I2C_PASSTHRU, 0, p, pdata - (uint8_t *)p, + r, sizeof(*r) + read_len); + if (rv < 0) + return rv; + + /* Parse response */ + if (r->i2c_status & EC_I2C_STATUS_ERROR) { + printf("Transfer failed with status=0x%x\n", r->i2c_status); + return -1; + } + + if (rv < sizeof(*r) + read_len) { + puts("Truncated read response\n"); + return -1; + } + + /* We only support a single read message for each transfer */ + if (read_len) + memcpy(read_ptr, r->data, read_len); + + return 0; +} + #ifdef CONFIG_CMD_CROS_EC

/** @@ -1267,8 +1343,8 @@ static int cros_ec_i2c_md(struct cros_ec_dev *dev, int flag, int argc,

linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;

- if (cros_ec_i2c_xfer(dev, chip, addr, alen, linebuf, linebytes, - 1)) + if (cros_ec_i2c_xfer_old(dev, chip, addr, alen, linebuf, + linebytes, 1)) puts("Error reading the chip.\n"); else { printf("%04x:", addr); @@ -1333,7 +1409,7 @@ static int cros_ec_i2c_mw(struct cros_ec_dev *dev, int flag, int argc, count = 1;

while (count-- > 0) { - if (cros_ec_i2c_xfer(dev, chip, addr++, alen, &byte, 1, 0)) + if (cros_ec_i2c_xfer_old(dev, chip, addr++, alen, &byte, 1, 0)) puts("Error writing the chip.\n"); /* * Wait for the write to complete. The write can take @@ -1633,6 +1709,12 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return ret; }

+int cros_ec_post_bind(struct udevice *dev) +{ + /* Scan for available EC devices (e.g. I2C tunnel) */ + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +} + U_BOOT_CMD( crosec, 6, 1, do_cros_ec, "CROS-EC utility command", @@ -1661,4 +1743,5 @@ UCLASS_DRIVER(cros_ec) = { .id = UCLASS_CROS_EC, .name = "cros_ec", .per_device_auto_alloc_size = sizeof(struct cros_ec_dev), + .post_bind = cros_ec_post_bind, }; diff --git a/drivers/power/pmic/pmic_tps65090_ec.c b/drivers/power/pmic/pmic_tps65090_ec.c index ac0d44f..f79a878 100644 --- a/drivers/power/pmic/pmic_tps65090_ec.c +++ b/drivers/power/pmic/pmic_tps65090_ec.c @@ -56,8 +56,8 @@ enum { */ static int tps65090_read(u32 reg, u8 *val) { - return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, - val, 1, true); + return cros_ec_i2c_xfer_old(config.dev, TPS65090_ADDR, reg, 1, + val, 1, true); }

/** @@ -69,8 +69,8 @@ static int tps65090_read(u32 reg, u8 *val) */ static int tps65090_write(u32 reg, u8 val) { - return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, - &val, 1, false); + return cros_ec_i2c_xfer_old(config.dev, TPS65090_ADDR, reg, 1, + &val, 1, false); }

/** diff --git a/include/cros_ec.h b/include/cros_ec.h index 3b2be2c..41951c3 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -390,6 +390,16 @@ int cros_ec_decode_ec_flash(const void *blob, int node, */ void cros_ec_check_keyboard(struct cros_ec_dev *dev);

+struct i2c_msg; +/* + * Tunnel an I2C transfer to the EC + * + * @param dev CROS-EC device + * @param msg List of messages to transfer + * @param nmsgs Number of messages to transfer + */ +int cros_ec_i2c_tunnel(struct udevice *dev, struct i2c_msg *msg, int nmsgs); + /* * Tunnel an I2C transfer to the EC * @@ -401,7 +411,7 @@ void cros_ec_check_keyboard(struct cros_ec_dev *dev); * @param len Length of buffer * @param is_read 1 if this is a read, 0 if this is a write */ -int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr, - int alen, uchar *buffer, int len, int is_read); +int cros_ec_i2c_xfer_old(struct cros_ec_dev *dev, uchar chip, uint addr, + int alen, uchar *buffer, int len, int is_read);

#endif

The debug UART code needs to perform the same init as the normal UART driver. In preparation for this, move the init code into two functions, one for the basic init and one for setting the baud rate. This will make adding debug UART support easier.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/serial/serial_s5p.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-)

diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 8469afd..7abec53 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -14,8 +14,8 @@ #include <fdtdec.h> #include <linux/compiler.h> #include <asm/io.h> -#include <asm/arch/uart.h> #include <asm/arch/clk.h> +#include <asm/arch/uart.h> #include <serial.h>

DECLARE_GLOBAL_DATA_PTR; @@ -59,11 +59,20 @@ static const int udivslot[] = { 0xffdf, };

-int s5p_serial_setbrg(struct udevice *dev, int baudrate) +static void __maybe_unused s5p_serial_init(struct s5p_uart *uart) +{ + /* enable FIFOs, auto clear Rx FIFO */ + writel(0x3, &uart->ufcon); + writel(0, &uart->umcon); + /* 8N1 */ + writel(0x3, &uart->ulcon); + /* No interrupts, no DMA, pure polling */ + writel(0x245, &uart->ucon); +} + +static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk, + int baudrate) { - struct s5p_serial_platdata *plat = dev->platdata; - struct s5p_uart *const uart = plat->reg; - u32 uclk = get_uart_clk(plat->port_id); u32 val;

val = uclk / baudrate; @@ -74,6 +83,15 @@ int s5p_serial_setbrg(struct udevice *dev, int baudrate) writew(udivslot[val % 16], &uart->rest.slot); else writeb(val % 16, &uart->rest.value); +} + +int s5p_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct s5p_serial_platdata *plat = dev->platdata; + struct s5p_uart *const uart = plat->reg; + u32 uclk = get_uart_clk(plat->port_id); + + s5p_serial_baud(uart, uclk, baudrate);

return 0; } @@ -83,13 +101,7 @@ static int s5p_serial_probe(struct udevice *dev) struct s5p_serial_platdata *plat = dev->platdata; struct s5p_uart *const uart = plat->reg;

- /* enable FIFOs, auto clear Rx FIFO */ - writel(0x3, &uart->ufcon); - writel(0, &uart->umcon); - /* 8N1 */ - writel(0x3, &uart->ulcon); - /* No interrupts, no DMA, pure polling */ - writel(0x245, &uart->ucon); + s5p_serial_init(uart);

return 0; }

Add a debug UART implementation for this serial driver. It does not set up pinmux automatically - this must be done before calling debug_uart_init().

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/serial/Kconfig | 7 +++++++ drivers/serial/serial_s5p.c | 25 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 4829284..e51f915 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -44,6 +44,13 @@ config DEBUG_UART_NS16550 will need to provide parameters to make this work. The driver will be available until the real driver model serial is running.

+config DEBUG_UART_S5P + bool "Samsung S5P" + help + Select this to enable a debug UART using the serial_s5p driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + endchoice

config DEBUG_UART_BASE diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 7abec53..4a553a3 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -200,3 +200,28 @@ U_BOOT_DRIVER(serial_s5p) = { .ops = &s5p_serial_ops, .flags = DM_FLAG_PRE_RELOC, }; + +#ifdef CONFIG_DEBUG_UART_S5P + +#include <debug_uart.h> + +void debug_uart_init(void) +{ + struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE; + + s5p_serial_init(uart); + s5p_serial_baud(uart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); +} + +static inline void _debug_uart_putc(int ch) +{ + struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE; + + while (readl(&uart->ufstat) & TX_FIFO_FULL); + + writeb(ch, &uart->utxh); +} + +DEBUG_UART_FUNCS + +#endif

As a debugging aid, allow UART3 to be used as a debug UART in SPL. This is a precursor to proper UART support, which requires a substantial refactor.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/cpu/armv7/exynos/lowlevel_init.c | 5 +++++ drivers/serial/serial_s5p.c | 2 ++ 2 files changed, 7 insertions(+)

diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c index 120aaf8..3774607 100644 --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c @@ -25,6 +25,7 @@

#include <common.h> #include <config.h> +#include <debug_uart.h> #include <asm/arch/cpu.h> #include <asm/arch/dmc.h> #include <asm/arch/power.h> @@ -216,6 +217,10 @@ int do_lowlevel_init(void)

if (actions & DO_CLOCKS) { system_clock_init(); +#ifdef CONFIG_DEBUG_UART + exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + debug_uart_init(); +#endif mem_ctrl_init(actions & DO_MEM_RESET); tzpc_init(); } diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 4a553a3..21cb566 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -85,6 +85,7 @@ static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk, writeb(val % 16, &uart->rest.value); }

+#ifndef CONFIG_SPL_BUILD int s5p_serial_setbrg(struct udevice *dev, int baudrate) { struct s5p_serial_platdata *plat = dev->platdata; @@ -200,6 +201,7 @@ U_BOOT_DRIVER(serial_s5p) = { .ops = &s5p_serial_ops, .flags = DM_FLAG_PRE_RELOC, }; +#endif

#ifdef CONFIG_DEBUG_UART_S5P

At present the driver model GPIO API does not support pull-up/pull-down on input GPIOs. This is required in some cases.

Add this feature to the API with two new methods that drivers can optionally implement.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/gpio/gpio-uclass.c | 31 +++++++++++++++++++++++++++++++ include/asm-generic/gpio.h | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+)

diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 4efda31..c4ba580 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -374,6 +374,37 @@ int dm_gpio_set_dir(struct gpio_desc *desc) return dm_gpio_set_dir_flags(desc, desc->flags); }

+int dm_gpio_set_pull(struct gpio_desc *desc, enum gpio_pull pull) +{ + struct dm_gpio_ops *ops = gpio_get_ops(desc->dev); + int ret; + + ret = check_reserved(desc, "set_pull"); + if (ret) + return ret; + + if (!ops->set_pull) + return -ENOSYS; + + return ops->set_pull(desc->dev, desc->offset, pull); +} + +int dm_gpio_get_pull(struct gpio_desc *desc, unsigned offset) +{ + struct dm_gpio_ops *ops = gpio_get_ops(desc->dev); + int ret; + + ret = check_reserved(desc, "get_pull"); + if (ret) + return ret; + + if (!ops->get_pull) + return -ENOSYS; + + return ops->get_pull(desc->dev, desc->offset); +} + + /** * gpio_get_value() - [COMPAT] Sample GPIO pin and return it's value * gpio: GPIO number diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 0af599f..db5504f 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -126,6 +126,13 @@ struct gpio_desc { */ };

+/* GPIO pull directions (used for input lines) */ +enum gpio_pull { + GPIO_PULL_NONE, + GPIO_PULL_DOWN, + GPIO_PULL_UP, +}; + /** * dm_gpio_is_valid() - Check if a GPIO is valid * @@ -276,6 +283,26 @@ struct dm_gpio_ops { */ int (*xlate)(struct udevice *dev, struct gpio_desc *desc, struct fdtdec_phandle_args *args); + + /** + * set_pull() - set pull direction + * + * @dev: Device to adjust + * @offset: GPIO offset within device + * @pull: New pull direction + * @return 0 if OK, -ve on error + */ + int (*set_pull)(struct udevice *dev, unsigned offset, + enum gpio_pull pull); + + /** + * get_pull() - get pull direction + * + * @dev: Device to check + * @offset: GPIO offset within device + * @return current pull direction or -ve on error + */ + int (*get_pull)(struct udevice *dev, unsigned offset); };

/** @@ -556,6 +583,25 @@ int dm_gpio_set_dir(struct gpio_desc *desc); int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags);

/** + * dm_gpio_set_pull() - set pull direction + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @pull: New pull direction + * @return 0 if OK, -ve on error + */ +int dm_gpio_set_pull(struct gpio_desc *desc, enum gpio_pull pull); + +/** +* dm_gpio_get_pull() - get pull direction +* + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() +* @return current pull direction or -ve on error +*/ +int dm_gpio_get_pull(struct gpio_desc *desc, unsigned offset); + +/** * gpio_get_number() - Get the global GPIO number of a GPIO * * This should only be used for debugging or interest. It returns the number

The existing TPS65090 driver does not support driver model. Add a new one that does. This can be used as a base for a regulator driver also. It uses the standard device tree binding.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/power/pmic/Kconfig | 9 +++++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/tps65090.c | 94 +++++++++++++++++++++++++++++++++++++++++++ include/power/tps65090.h | 56 ++++++++++++++++++++++++++ 4 files changed, 160 insertions(+) create mode 100644 drivers/power/pmic/tps65090.c create mode 100644 include/power/tps65090.h

diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 164f421..fd8af81 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -41,3 +41,12 @@ config DM_PMIC_SANDBOX - set by i2c emul driver's probe() (defaults in header)

Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt + +config PMIC_TPS65090 + bool "Enable driver for Texas Instruments TPS65090 PMIC" + depends on DM_PMIC + ---help--- + The TPS65090 is a PMIC containing several LDOs, DC to DC convertors, + FETs and a battery charger. This driver provides register access + only, and you can enable the regulator/charger drivers separately if + required. diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index ae86f04..2316e3b 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_DM_PMIC) += pmic-uclass.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o +obj-$(CONFIG_PMIC_TPS65090) += tps65090.o obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o diff --git a/drivers/power/pmic/tps65090.c b/drivers/power/pmic/tps65090.c new file mode 100644 index 0000000..4797f32 --- /dev/null +++ b/drivers/power/pmic/tps65090.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/tps65090.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct pmic_child_info pmic_children_info[] = { + { .prefix = "fet", .driver = TPS65090_FET_DRIVER }, + { }, +}; + +static int tps65090_reg_count(struct udevice *dev) +{ + return TPS65090_NUM_REGS; +} + +static int tps65090_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + if (dm_i2c_write(dev, reg, buff, len)) { + error("write error to device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int tps65090_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buff, len); + if (ret) { + error("read error %d from device: %p register: %#x!", ret, dev, + reg); + return -EIO; + } + + return 0; +} + +static int tps65090_bind(struct udevice *dev) +{ + int regulators_node; + const void *blob = gd->fdt_blob; + int children; + + regulators_node = fdt_subnode_offset(blob, dev->of_offset, + "regulators"); + if (regulators_node <= 0) { + debug("%s: %s regulators subnode not found!", __func__, + dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + debug("%s: %s - no child found\n", __func__, dev->name); + + /* Always return success for this device */ + return 0; +} + +static struct dm_pmic_ops tps65090_ops = { + .reg_count = tps65090_reg_count, + .read = tps65090_read, + .write = tps65090_write, +}; + +static const struct udevice_id tps65090_ids[] = { + { .compatible = "ti,tps65090" }, + { } +}; + +U_BOOT_DRIVER(pmic_tps65090) = { + .name = "tps65090 pmic", + .id = UCLASS_PMIC, + .of_match = tps65090_ids, + .bind = tps65090_bind, + .ops = &tps65090_ops, +}; diff --git a/include/power/tps65090.h b/include/power/tps65090.h new file mode 100644 index 0000000..3a0690b --- /dev/null +++ b/include/power/tps65090.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TPS65090_PMIC_H_ +#define __TPS65090_PMIC_H_ + +/* I2C device address for TPS65090 PMU */ +#define TPS65090_I2C_ADDR 0x48 + +/* TPS65090 register addresses */ +enum { + REG_IRQ1 = 0, + REG_CG_CTRL0 = 4, + REG_CG_STATUS1 = 0xa, + REG_FET_BASE = 0xe, /* Not a real register, FETs count from here */ + REG_FET1_CTRL, + REG_FET2_CTRL, + REG_FET3_CTRL, + REG_FET4_CTRL, + REG_FET5_CTRL, + REG_FET6_CTRL, + REG_FET7_CTRL, + TPS65090_NUM_REGS, +}; + +enum { + IRQ1_VBATG = 1 << 3, + CG_CTRL0_ENC_MASK = 0x01, + + MAX_FET_NUM = 7, + MAX_CTRL_READ_TRIES = 5, + + /* TPS65090 FET_CTRL register values */ + FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ + FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ + FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ + FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ + FET_CTRL_ENFET = 1 << 0, /* Enable FET */ +}; + +enum { + /* Status register fields */ + TPS65090_ST1_OTC = 1 << 0, + TPS65090_ST1_OCC = 1 << 1, + TPS65090_ST1_STATE_SHIFT = 4, + TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT, +}; + +/* Drivers name */ +#define TPS65090_FET_DRIVER "tps65090_fet" + +#endif /* __TPS65090_PMIC_H_ */

This PMIC is used with SoCs which need a combination of BUCKs and LDOs. The driver supports probing and basic register access. It supports the standard device tree binding and supports driver model. A regulator driver can be provided also.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/power/pmic/Kconfig | 9 +++++ drivers/power/pmic/Makefile | 2 + drivers/power/pmic/s5m8767.c | 95 ++++++++++++++++++++++++++++++++++++++++++++ include/power/s5m8767.h | 85 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 191 insertions(+) create mode 100644 drivers/power/pmic/s5m8767.c create mode 100644 include/power/s5m8767.h

diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index fd8af81..7b98189 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -42,6 +42,15 @@ config DM_PMIC_SANDBOX

Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt

+config PMIC_S5M8767 + bool "Enable Driver Model for the Samsung S5M8767 PMIC" + depends on DM_PMIC + ---help--- + The S5M8767 PMIC provides a large array of LDOs and BUCKs for use + as a SoC power controller. It also provides 32KHz clock outputs. This + driver provides basic register access and sets up the attached + regulators if regulator support is enabled. + config PMIC_TPS65090 bool "Enable driver for Texas Instruments TPS65090 PMIC" depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 2316e3b..ee23c26 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -9,6 +9,8 @@ obj-$(CONFIG_DM_PMIC) += pmic-uclass.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o +obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o + obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o diff --git a/drivers/power/pmic/s5m8767.c b/drivers/power/pmic/s5m8767.c new file mode 100644 index 0000000..075fe7e --- /dev/null +++ b/drivers/power/pmic/s5m8767.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/s5m8767.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct pmic_child_info pmic_children_info[] = { + { .prefix = "LDO", .driver = S5M8767_LDO_DRIVER }, + { .prefix = "BUCK", .driver = S5M8767_BUCK_DRIVER }, + { }, +}; + +static int s5m8767_reg_count(struct udevice *dev) +{ + return S5M8767_NUM_OF_REGS; +} + +static int s5m8767_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + if (dm_i2c_write(dev, reg, buff, len)) { + error("write error to device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int s5m8767_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + if (dm_i2c_read(dev, reg, buff, len)) { + error("read error from device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +int s5m8767_enable_32khz_cp(struct udevice *dev) +{ + return pmic_clrsetbits(dev, S5M8767_EN32KHZ_CP, 0, 1 << 1); +} + +static int s5m8767_bind(struct udevice *dev) +{ + int node; + const void *blob = gd->fdt_blob; + int children; + + node = fdt_subnode_offset(blob, dev->of_offset, "regulators"); + if (node <= 0) { + debug("%s: %s regulators subnode not found!", __func__, + dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, node, pmic_children_info); + if (!children) + debug("%s: %s - no child found\n", __func__, dev->name); + + /* Always return success for this device */ + return 0; +} + +static struct dm_pmic_ops s5m8767_ops = { + .reg_count = s5m8767_reg_count, + .read = s5m8767_read, + .write = s5m8767_write, +}; + +static const struct udevice_id s5m8767_ids[] = { + { .compatible = "samsung,s5m8767-pmic" }, + { } +}; + +U_BOOT_DRIVER(pmic_s5m8767) = { + .name = "s5m8767_pmic", + .id = UCLASS_PMIC, + .of_match = s5m8767_ids, + .bind = s5m8767_bind, + .ops = &s5m8767_ops, +}; diff --git a/include/power/s5m8767.h b/include/power/s5m8767.h new file mode 100644 index 0000000..ba88ff7 --- /dev/null +++ b/include/power/s5m8767.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __S5M8767_H_ +#define __S5M8767_H_ + +enum s5m8767_regnum { + S5M8767_BUCK1 = 0, + S5M8767_BUCK2, + S5M8767_BUCK3, + S5M8767_BUCK4, + S5M8767_BUCK5, + S5M8767_BUCK6, + S5M8767_BUCK7, + S5M8767_BUCK8, + S5M8767_BUCK9, + S5M8767_LDO1, + S5M8767_LDO2, + S5M8767_LDO3, + S5M8767_LDO4, + S5M8767_LDO5, + S5M8767_LDO6, + S5M8767_LDO7, + S5M8767_LDO8, + S5M8767_LDO9, + S5M8767_LDO10, + S5M8767_LDO11, + S5M8767_LDO12, + S5M8767_LDO13, + S5M8767_LDO14, + S5M8767_LDO15, + S5M8767_LDO16, + S5M8767_LDO17, + S5M8767_LDO18, + S5M8767_LDO19, + S5M8767_LDO20, + S5M8767_LDO21, + S5M8767_LDO22, + S5M8767_LDO23, + S5M8767_LDO24, + S5M8767_LDO25, + S5M8767_LDO26, + S5M8767_LDO27, + S5M8767_LDO28, + S5M8767_EN32KHZ_CP, + + S5M8767_NUM_OF_REGS, +}; + +struct sec_voltage_desc { + int max; + int min; + int step; +}; + +/** + * struct s5m8767_para - s5m8767 register parameters + * @param vol_addr i2c address of the given buck/ldo register + * @param vol_bitpos bit position to be set or clear within register + * @param vol_bitmask bit mask value + * @param reg_enaddr control register address, which enable the given + * given buck/ldo. + * @param reg_enbiton value to be written to buck/ldo to make it ON + * @param vol Voltage information + */ +struct s5m8767_para { + enum s5m8767_regnum regnum; + u8 vol_addr; + u8 vol_bitpos; + u8 vol_bitmask; + u8 reg_enaddr; + u8 reg_enbiton; + const struct sec_voltage_desc *vol; +}; + +/* Drivers name */ +#define S5M8767_LDO_DRIVER "s5m8767_ldo" +#define S5M8767_BUCK_DRIVER "s5m8767_buck" + +int s5m8767_enable_32khz_cp(struct udevice *dev); + +#endif /* __S5M8767_PMIC_H_ */

The driver name should not have a space in it. Also the regulator names should match the case of the device tree. Fix these problems.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/power/pmic/max77686.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/power/pmic/max77686.c b/drivers/power/pmic/max77686.c index 3523b4a..dc5a54a 100644 --- a/drivers/power/pmic/max77686.c +++ b/drivers/power/pmic/max77686.c @@ -17,8 +17,8 @@ DECLARE_GLOBAL_DATA_PTR;

static const struct pmic_child_info pmic_children_info[] = { - { .prefix = "ldo", .driver = MAX77686_LDO_DRIVER }, - { .prefix = "buck", .driver = MAX77686_BUCK_DRIVER }, + { .prefix = "LDO", .driver = MAX77686_LDO_DRIVER }, + { .prefix = "BUCK", .driver = MAX77686_BUCK_DRIVER }, { }, };

@@ -84,7 +84,7 @@ static const struct udevice_id max77686_ids[] = { };

U_BOOT_DRIVER(pmic_max77686) = { - .name = "max77686 pmic", + .name = "max77686_pmic", .id = UCLASS_PMIC, .of_match = max77686_ids, .bind = max77686_bind,

Some regulators use the wrong voltage register and thus it is not possible to control them. Fix this.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/power/regulator/max77686.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/power/regulator/max77686.c b/drivers/power/regulator/max77686.c index 37ebe94..21173fc 100644 --- a/drivers/power/regulator/max77686.c +++ b/drivers/power/regulator/max77686.c @@ -61,10 +61,14 @@ static struct dm_regulator_mode max77686_buck_mode_onoff[] = { MODE(OPMODE_ON, MAX77686_BUCK_MODE_ON, "ON"), };

-static const char max77686_buck_addr[] = { +static const char max77686_buck_ctrl[] = { 0xff, 0x10, 0x12, 0x1c, 0x26, 0x30, 0x32, 0x34, 0x36, 0x38 };

+static const char max77686_buck_out[] = { + 0xff, 0x11, 0x14, 0x1e, 0x28, 0x31, 0x33, 0x35, 0x37, 0x39 +}; + static int max77686_buck_volt2hex(int buck, int uV) { unsigned int hex = 0; @@ -368,7 +372,7 @@ static int max77686_buck_val(struct udevice *dev, int op, int *uV) *uV = 0;

/* &buck_out = ctrl + 1 */ - adr = max77686_buck_addr[buck] + 1; + adr = max77686_buck_out[buck];

/* mask */ switch (buck) { @@ -549,7 +553,7 @@ static int max77686_buck_mode(struct udevice *dev, int op, int *opmode) return -EINVAL; }

- adr = max77686_buck_addr[buck]; + adr = max77686_buck_ctrl[buck];

/* mask */ switch (buck) {