[PATCH 1/2] mxs: Fix VDDx brownout interrupt disable/enable
HW_POWER_CTRL register contains brownout interrupt enable bits ENIRQ_VDDIO_BO, ENIRQ_VDDA_BO and ENIRQ_VDDD_BO.
Signed-off-by: Cody Green cody@londelec.com Cc: Stefano Babic sbabic@denx.de Cc: Marek Vasut marex@denx.de Cc: Fabio Estevam festevam@gmail.com --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index c33170f06d..33b76533e4 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -1142,8 +1142,9 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
if (adjust_up && cfg->bo_irq) { if (powered_by_linreg) { - bo_int = readl(cfg->reg); - clrbits_le32(cfg->reg, cfg->bo_enirq); + bo_int = readl(&power_regs->hw_power_ctrl); + clrbits_le32(&power_regs->hw_power_ctrl, + cfg->bo_enirq); } setbits_le32(cfg->reg, cfg->bo_offset_mask); } @@ -1185,7 +1186,8 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, if (adjust_up && powered_by_linreg) { writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr); if (bo_int & cfg->bo_enirq) - setbits_le32(cfg->reg, cfg->bo_enirq); + setbits_le32(&power_regs->hw_power_ctrl, + cfg->bo_enirq); }
clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
On Mon, Jul 3, 2023 at 5:40 PM Marek Vasut marex@denx.de wrote:
On 7/3/23 18:33, Cody Green wrote:
HW_POWER_CTRL register contains brownout interrupt enable bits ENIRQ_VDDIO_BO, ENIRQ_VDDA_BO and ENIRQ_VDDD_BO.
So what does this patch do (that is missing in the commit message) ?
There are incorrect registers HW_POWER_VDDIOCTRL, HW_POWER_VDDACTRL and HW_POWER_VDDDCTRL used in the current code to disable/enable brownout interrupts in 'mxs_power_set_vddx()'. This patch ensures the correct register HW_POWER_CTRL is used. Sorry for the unspecific commit message, I will amend the patch.
On 7/3/23 20:33, Cody Green wrote:
On Mon, Jul 3, 2023 at 5:40 PM Marek Vasut marex@denx.de wrote:
On 7/3/23 18:33, Cody Green wrote:
HW_POWER_CTRL register contains brownout interrupt enable bits ENIRQ_VDDIO_BO, ENIRQ_VDDA_BO and ENIRQ_VDDD_BO.
So what does this patch do (that is missing in the commit message) ?
There are incorrect registers HW_POWER_VDDIOCTRL, HW_POWER_VDDACTRL and HW_POWER_VDDDCTRL used in the current code to disable/enable brownout interrupts in 'mxs_power_set_vddx()'. This patch ensures the correct register HW_POWER_CTRL is used. Sorry for the unspecific commit message, I will amend the patch.
Much better, thank you.
Also CC Lukasz (on CC here) on V2.
Incorrect registers HW_POWER_VDDIOCTRL, HW_POWER_VDDACTRL and HW_POWER_VDDDCTRL are used in the current code to disable/enable brownout interrupts in 'mxs_power_set_vddx()'. Change register to HW_POWER_CTRL which contains brownout interrupt enable bits ENIRQ_VDDIO_BO, ENIRQ_VDDA_BO and ENIRQ_VDDD_BO.
Signed-off-by: Cody Green cody@londelec.com Cc: Stefano Babic sbabic@denx.de Cc: Marek Vasut marex@denx.de Cc: Fabio Estevam festevam@gmail.com Cc: Lukasz Majewski lukma@denx.de --- Changes for v2: - Commit message reworded to be more specific.
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index c33170f06d..33b76533e4 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -1142,8 +1142,9 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
if (adjust_up && cfg->bo_irq) { if (powered_by_linreg) { - bo_int = readl(cfg->reg); - clrbits_le32(cfg->reg, cfg->bo_enirq); + bo_int = readl(&power_regs->hw_power_ctrl); + clrbits_le32(&power_regs->hw_power_ctrl, + cfg->bo_enirq); } setbits_le32(cfg->reg, cfg->bo_offset_mask); } @@ -1185,7 +1186,8 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, if (adjust_up && powered_by_linreg) { writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr); if (bo_int & cfg->bo_enirq) - setbits_le32(cfg->reg, cfg->bo_enirq); + setbits_le32(&power_regs->hw_power_ctrl, + cfg->bo_enirq); }
clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
participants (2)
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Cody Green -
Marek Vasut