[PATCH v6 00/20] Add support for MMC higher speed modes for TI's am65x, j721e and j7200 platforms
The following patches add support for higher speeds in the SD card and eMMC for TI's am65x, j721e, j7200 platforms.
With these patches, the following max speeds are supported: j721e: DDR50, HS200 j7200: SDR104, HS200 am65x: SDR104*, HS200
changes since v5: 1. In patch 1 moved the 5ms delay after setting the 1.8V enable bit 2. In patch 1 added a check to confirm if the output has stabilized. 3. Picked up Reviewed-by from Jaehoon Chung for patch 1
changes since v4: 1. removed patch(15 in v4) that adds support for HS400 in J7200 platform, as there are some errors while switching to HS400 mode. 2. changed the function regulator_set_enable() in patch 1 to regulator_set_enable_if_allowed() as there is a possibility of not having an enable gpio. 3. changed the pin direction from PIN_INPUT to PIN_OUTPUT for pins SPI1_CS1 and SPI0_D1 in patches 13 and 15 (in v4) respectively. 4. changed the configs enabled, to HS200 from HS400 for J7200 in patch 18 (in v4).
changes since v3: 1. changed #if to if(IS_ENABLED()) in patch 1 for MMC_IO_VOLTAGE. 2. changed the format for print statements added in v3 to remove warnings arising when DM_REGULATOR variable is not defined 3. Added a patch to add support for HS400 speed mode in J7200 as it is now supported. 4. edited patch 17 (in v3) to add support for HS400 instead of HS200 as it is now supported in J7200 SoC. 4. Added description for sdhci_set_ctrl_reg() function in include/sdhci.h 5. Added comment for mdelay in patch 1 6. Picked up Reviewed-by's from Jaehoon Chung
changes since v2: 1. Added print statements in case of failure for regulator_set_enable and regulator_set_value function calls in patch 1 2. Removed patch 18 (in v2) as it has been applied by commit [1] 3. renamed the function dev_get_platdata() to dev_get_plat in patch 8 4. rebased all the patches in seriesn
changes since v1: 1. Added patches to support UHS modes for the SD card even in am654x platforms. 2. Fixed an issue with patch 1 that was breaking builds on some platforms.
* There's an issue with the am65x base board such that the power cycle circuit to the card takes way longer than the wait time in mmc core. Until this is fixed, am654x-evm and -idk will only support High speed mode at 3.3V (see patch 20) but this shouldn't block us from adding UHS modes in the dtsi as well as in the configs so other boards can still take advantage of the higher speed. UHS modes have been tested by adding the appropriate delay in the power cycle circuit.
[1] - commit 67507e4aab5b ("sandbox: Fix up building for of-platdata")
Link to v1: https://patchwork.ozlabs.org/project/uboot/list/?series=206622
Faiz Abbas (20): mmc: sdhci: Add helper functions for UHS modes mmc: am654_sdhci: Unconditionally switch off DLL in the beginning of ios_post() mmc: am654_sdhci: Convert flag fields to BIT macro mmc: am654_sdhci: Add flag for PHY calibration mmc: am654_sdhci: Add support for AM65x SR2.0 mmc: am654_sdhci: Add support for input tap delay mmc: am654_sdhci: Add support for writing to clkbuf_sel mmc: am654_sdhci: Add support for software tuning mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modes mmc: am654_sdhci: Use sdhci_set_control_reg() arm: dts: k3-am65: Fix mmc nodes arm: dts: k3-j721e-main: Update otap-delay values arm: dts: k3-j721e-common-proc-board: Add support for UHS modes for SD card arm: dts: k3-j7200-main: Add support for gpio0 arm: dts: k3-j7200-common-proc-board: Enable support for UHS modes configs: j721e_evm: Add support for UHS modes configs: j7200_evm: Add support for UHS modes arm: dts: k3-am65-main: Add itapdly and clkbuf-sel values arm: dts: k3-am654-base-board: Limit Sd card to High speed modes configs: am65x_evm: Add configs for UHS modes
arch/arm/dts/k3-am65-main.dtsi | 31 ++ arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 67 +-- arch/arm/dts/k3-am654-base-board.dts | 26 ++ arch/arm/dts/k3-am654-r5-base-board.dts | 20 +- arch/arm/dts/k3-j7200-common-proc-board.dts | 49 ++- arch/arm/dts/k3-j7200-main.dtsi | 23 ++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 15 + arch/arm/dts/k3-j721e-common-proc-board.dts | 32 ++ arch/arm/dts/k3-j721e-main.dtsi | 8 +- configs/am65x_evm_a53_defconfig | 8 + configs/am65x_evm_r5_defconfig | 2 + configs/j7200_evm_a72_defconfig | 8 + configs/j7200_evm_r5_defconfig | 1 + configs/j721e_evm_a72_defconfig | 8 + configs/j721e_evm_r5_defconfig | 1 + drivers/mmc/Kconfig | 1 + drivers/mmc/am654_sdhci.c | 384 +++++++++++++----- drivers/mmc/sdhci.c | 95 +++++ include/sdhci.h | 10 + 19 files changed, 616 insertions(+), 173 deletions(-)
From: Faiz Abbas faiz_abbas@ti.com
Add a set_voltage() function which handles the switch from 3.3V to 1.8V for SD card UHS modes.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com Reviewed-by: Jaehoon Chung jh80.chung@samsung.com --- drivers/mmc/sdhci.c | 95 +++++++++++++++++++++++++++++++++++++++++++++ include/sdhci.h | 10 +++++ 2 files changed, 105 insertions(+)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 06289343124e..ed0dc173253b 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -20,6 +20,7 @@ #include <linux/delay.h> #include <linux/dma-mapping.h> #include <phys2bus.h> +#include <power/regulator.h>
static void sdhci_reset(struct sdhci_host *host, u8 mask) { @@ -509,6 +510,100 @@ void sdhci_set_uhs_timing(struct sdhci_host *host) sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); }
+static void sdhci_set_voltage(struct sdhci_host *host) +{ + if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) { + struct mmc *mmc = (struct mmc *)host->mmc; + u32 ctrl; + + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + + switch (mmc->signal_voltage) { + case MMC_SIGNAL_VOLTAGE_330: +#if CONFIG_IS_ENABLED(DM_REGULATOR) + if (mmc->vqmmc_supply) { + if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) { + pr_err("failed to disable vqmmc-supply\n"); + return; + } + + if (regulator_set_value(mmc->vqmmc_supply, 3300000)) { + pr_err("failed to set vqmmc-voltage to 3.3V\n"); + return; + } + + if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) { + pr_err("failed to enable vqmmc-supply\n"); + return; + } + } +#endif + if (IS_SD(mmc)) { + ctrl &= ~SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + } + + /* Wait for 5ms */ + mdelay(5); + + /* 3.3V regulator output should be stable within 5 ms */ + if (IS_SD(mmc)) { + if (ctrl & SDHCI_CTRL_VDD_180) { + pr_err("3.3V regulator output did not become stable\n"); + return; + } + } + + break; + case MMC_SIGNAL_VOLTAGE_180: +#if CONFIG_IS_ENABLED(DM_REGULATOR) + if (mmc->vqmmc_supply) { + if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) { + pr_err("failed to disable vqmmc-supply\n"); + return; + } + + if (regulator_set_value(mmc->vqmmc_supply, 1800000)) { + pr_err("failed to set vqmmc-voltage to 1.8V\n"); + return; + } + + if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) { + pr_err("failed to enable vqmmc-supply\n"); + return; + } + } +#endif + if (IS_SD(mmc)) { + ctrl |= SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + } + + /* Wait for 5 ms */ + mdelay(5); + + /* 1.8V regulator output has to be stable within 5 ms */ + if (IS_SD(mmc)) { + if (!(ctrl & SDHCI_CTRL_VDD_180)) { + pr_err("1.8V regulator output did not become stable\n"); + return; + } + } + + break; + default: + /* No signal voltage switch required */ + return; + } + } +} + +void sdhci_set_control_reg(struct sdhci_host *host) +{ + sdhci_set_voltage(host); + sdhci_set_uhs_timing(host); +} + #ifdef CONFIG_DM_MMC static int sdhci_set_ios(struct udevice *dev) { diff --git a/include/sdhci.h b/include/sdhci.h index 3e5a64981857..0ae9471ad749 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -491,6 +491,16 @@ void sdhci_set_uhs_timing(struct sdhci_host *host); /* Export the operations to drivers */ int sdhci_probe(struct udevice *dev); int sdhci_set_clock(struct mmc *mmc, unsigned int clock); + +/** + * sdhci_set_control_reg - Set control registers + * + * This is used set up control registers for voltage level and UHS speed + * mode. + * + * @host: SDHCI host structure + */ +void sdhci_set_control_reg(struct sdhci_host *host); extern const struct dm_mmc_ops sdhci_ops; #else #endif
From: Faiz Abbas faiz_abbas@ti.com
There are some speed modes that work without switching the dll on. Unconditionally switch off the DLL before setting clock frequency to support this case. The software will automatically enable DLL for speed modes that require it. This also means the dll_on priv data member is no longer required.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com Reviewed-by: Jaehoon Chung jh80.chung@samsung.com --- drivers/mmc/am654_sdhci.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index baa935e0d5b0..33f658fba719 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -84,7 +84,6 @@ struct am654_sdhci_plat { #define IOMUX_PRESENT (1 << 1) #define FREQSEL_2_BIT (1 << 2) #define STRBSEL_4_BIT (1 << 3) - bool dll_on; };
struct timing_data { @@ -141,12 +140,7 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host) val &= ~SDHCI_CLOCK_CARD_EN; sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
- /* power off phy */ - if (plat->dll_on) { - regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0); - - plat->dll_on = false; - } + regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
/* restart clock */ sdhci_set_clock(host->mmc, speed); @@ -212,8 +206,6 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host) val & DLLRDY_MASK, 1000, 1000000); if (ret) return ret; - - plat->dll_on = true; }
return 0;
From: Faiz Abbas faiz_abbas@ti.com
Convert the flags field defines to use the BIT() macro.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com Reviewed-by: Jaehoon Chung jh80.chung@samsung.com --- drivers/mmc/am654_sdhci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 33f658fba719..e0136dff9711 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -80,10 +80,10 @@ struct am654_sdhci_plat { u32 drv_strength; u32 strb_sel; u32 flags; -#define DLL_PRESENT (1 << 0) -#define IOMUX_PRESENT (1 << 1) -#define FREQSEL_2_BIT (1 << 2) -#define STRBSEL_4_BIT (1 << 3) +#define DLL_PRESENT BIT(0) +#define IOMUX_PRESENT BIT(1) +#define FREQSEL_2_BIT BIT(2) +#define STRBSEL_4_BIT BIT(3) };
struct timing_data {
From: Faiz Abbas faiz_abbas@ti.com
Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB flag to indicate the same.
Also move the write of trm_icp and driver strength to the set_clock() function to match the kernel configuration flow.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com Reviewed-by: Jaehoon Chung jh80.chung@samsung.com --- drivers/mmc/am654_sdhci.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index e0136dff9711..1e0654183811 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -84,6 +84,7 @@ struct am654_sdhci_plat { #define IOMUX_PRESENT BIT(1) #define FREQSEL_2_BIT BIT(2) #define STRBSEL_4_BIT BIT(3) +#define DLL_CALIB BIT(4) };
struct timing_data { @@ -195,6 +196,15 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host) freqsel << FREQSEL_SHIFT); }
+ /* Configure DLL TRIM */ + mask = DLL_TRIM_ICP_MASK; + val = plat->trm_icp << DLL_TRIM_ICP_SHIFT; + + /* Configure DLL driver strength */ + mask |= DR_TY_MASK; + val |= plat->drv_strength << DR_TY_SHIFT; + regmap_update_bits(plat->base, PHY_CTRL1, mask, val); + /* Enable DLL */ regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0x1 << ENDLL_SHIFT); @@ -221,7 +231,7 @@ int am654_sdhci_init(struct am654_sdhci_plat *plat) mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
- if (plat->flags & DLL_PRESENT) { + if (plat->flags & DLL_CALIB) { regmap_read(plat->base, PHY_STAT1, &val); if (~val & CALDONE_MASK) { /* Calibrate IO lines */ @@ -233,15 +243,6 @@ int am654_sdhci_init(struct am654_sdhci_plat *plat) if (ret) return ret; } - - /* Configure DLL TRIM */ - mask = DLL_TRIM_ICP_MASK; - val = plat->trm_icp << DLL_TRIM_ICP_SHIFT; - - /* Configure DLL driver strength */ - mask |= DR_TY_MASK; - val |= plat->drv_strength << DR_TY_SHIFT; - regmap_update_bits(plat->base, PHY_CTRL1, mask, val); }
/* Enable pins by setting IO mux to 0 */ @@ -292,12 +293,13 @@ const struct sdhci_ops am654_sdhci_ops = {
const struct am654_driver_data am654_drv_data = { .ops = &am654_sdhci_ops, - .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT, + .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | DLL_CALIB | + STRBSEL_4_BIT, };
const struct am654_driver_data j721e_8bit_drv_data = { .ops = &am654_sdhci_ops, - .flags = DLL_PRESENT, + .flags = DLL_PRESENT | DLL_CALIB, };
static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
From: Faiz Abbas faiz_abbas@ti.com
Add Support for AM65x PG2.0. Use the SoC bus framework to fixup the platform data and do DLL calibration if the revision is 1.0
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com Reviewed-by: Jaehoon Chung jh80.chung@samsung.com --- drivers/mmc/am654_sdhci.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 1e0654183811..5790fa3d0dbf 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -12,6 +12,7 @@ #include <power-domain.h> #include <regmap.h> #include <sdhci.h> +#include <soc.h> #include <dm/device_compat.h> #include <linux/bitops.h> #include <linux/err.h> @@ -292,6 +293,11 @@ const struct sdhci_ops am654_sdhci_ops = { };
const struct am654_driver_data am654_drv_data = { + .ops = &am654_sdhci_ops, + .flags = DLL_PRESENT | IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT, +}; + +const struct am654_driver_data am654_sr1_drv_data = { .ops = &am654_sdhci_ops, .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | DLL_CALIB | STRBSEL_4_BIT, @@ -326,6 +332,11 @@ const struct am654_driver_data j721e_4bit_drv_data = { .flags = IOMUX_PRESENT, };
+const struct soc_attr am654_sdhci_soc_attr[] = { + { .family = "AM65X", .revision = "SR1.0", .data = &am654_sr1_drv_data}, + {/* sentinel */} +}; + static int sdhci_am654_get_otap_delay(struct udevice *dev, struct mmc_config *cfg) { @@ -365,6 +376,8 @@ static int am654_sdhci_probe(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_host *host = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; + const struct soc_attr *soc; + const struct am654_driver_data *soc_drv_data; struct clk clk; unsigned long clock; int ret; @@ -394,6 +407,14 @@ static int am654_sdhci_probe(struct udevice *dev) return ret;
host->ops = drv_data->ops; + + /* Update ops based on SoC revision */ + soc = soc_device_match(am654_sdhci_soc_attr); + if (soc && soc->data) { + soc_drv_data = soc->data; + host->ops = soc_drv_data->ops; + } + host->mmc->priv = host; upriv->mmc = host->mmc;
@@ -458,9 +479,18 @@ static int am654_sdhci_bind(struct udevice *dev) struct am654_driver_data *drv_data = (struct am654_driver_data *)dev_get_driver_data(dev); struct am654_sdhci_plat *plat = dev_get_plat(dev); + const struct soc_attr *soc; + const struct am654_driver_data *soc_drv_data;
plat->flags = drv_data->flags;
+ /* Update flags based on SoC revision */ + soc = soc_device_match(am654_sdhci_soc_attr); + if (soc && soc->data) { + soc_drv_data = soc->data; + plat->flags = soc_drv_data->flags; + } + return sdhci_bind(dev, &plat->mmc, &plat->cfg); }
From: Faiz Abbas faiz_abbas@ti.com
DLL need only be enabled for speed modes and clock frequencies at or above 50 MHz. For speed modes that don't enable the DLL, we need to configure a static input delay value. This involves reading an optional itap-del-sel-* value from the device tree and configuring it for the appropriate speed mode.
Therefore, move all dll configurations to their own functions and gate it with 50 MHz speed and a minimum mode. If both these conditions are not satisfied then configure delay chain modes.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com Reviewed-by: Jaehoon Chung jh80.chung@samsung.com --- drivers/mmc/am654_sdhci.c | 241 +++++++++++++++++++++++++------------- 1 file changed, 161 insertions(+), 80 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 5790fa3d0dbf..b82558254ebb 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -62,6 +62,16 @@ #define CALDONE_MASK BIT(CALDONE_SHIFT) #define RETRIM_SHIFT 17 #define RETRIM_MASK BIT(RETRIM_SHIFT) +#define SELDLYTXCLK_SHIFT 17 +#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) +#define SELDLYRXCLK_SHIFT 16 +#define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) +#define ITAPDLYSEL_SHIFT 0 +#define ITAPDLYSEL_MASK GENMASK(4, 0) +#define ITAPDLYENA_SHIFT 8 +#define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) +#define ITAPCHGWIN_SHIFT 9 +#define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
#define DRIVER_STRENGTH_50_OHM 0x0 #define DRIVER_STRENGTH_33_OHM 0x1 @@ -70,6 +80,7 @@ #define DRIVER_STRENGTH_40_OHM 0x4
#define AM654_SDHCI_MIN_FREQ 400000 +#define CLOCK_TOO_SLOW_HZ 50000000
struct am654_sdhci_plat { struct mmc_config cfg; @@ -77,6 +88,7 @@ struct am654_sdhci_plat { struct regmap *base; bool non_removable; u32 otap_del_sel[MMC_MODES_END]; + u32 itap_del_sel[MMC_MODES_END]; u32 trm_icp; u32 drv_strength; u32 strb_sel; @@ -89,22 +101,45 @@ struct am654_sdhci_plat { };
struct timing_data { - const char *binding; + const char *otap_binding; + const char *itap_binding; u32 capability; };
static const struct timing_data td[] = { - [MMC_LEGACY] = {"ti,otap-del-sel-legacy", 0}, - [MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP(MMC_HS)}, - [SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP(SD_HS)}, - [UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP(UHS_SDR12)}, - [UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP(UHS_SDR25)}, - [UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP(UHS_SDR50)}, - [UHS_SDR104] = {"ti,otap-del-sel-sdr104", MMC_CAP(UHS_SDR104)}, - [UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP(UHS_DDR50)}, - [MMC_DDR_52] = {"ti,otap-del-sel-ddr52", MMC_CAP(MMC_DDR_52)}, - [MMC_HS_200] = {"ti,otap-del-sel-hs200", MMC_CAP(MMC_HS_200)}, - [MMC_HS_400] = {"ti,otap-del-sel-hs400", MMC_CAP(MMC_HS_400)}, + [MMC_LEGACY] = {"ti,otap-del-sel-legacy", + "ti,itap-del-sel-legacy", + 0}, + [MMC_HS] = {"ti,otap-del-sel-mmc-hs", + "ti,itap-del-sel-mms-hs", + MMC_CAP(MMC_HS)}, + [SD_HS] = {"ti,otap-del-sel-sd-hs", + "ti,itap-del-sel-sd-hs", + MMC_CAP(SD_HS)}, + [UHS_SDR12] = {"ti,otap-del-sel-sdr12", + "ti,itap-del-sel-sdr12", + MMC_CAP(UHS_SDR12)}, + [UHS_SDR25] = {"ti,otap-del-sel-sdr25", + "ti,itap-del-sel-sdr25", + MMC_CAP(UHS_SDR25)}, + [UHS_SDR50] = {"ti,otap-del-sel-sdr50", + NULL, + MMC_CAP(UHS_SDR50)}, + [UHS_SDR104] = {"ti,otap-del-sel-sdr104", + NULL, + MMC_CAP(UHS_SDR104)}, + [UHS_DDR50] = {"ti,otap-del-sel-ddr50", + NULL, + MMC_CAP(UHS_DDR50)}, + [MMC_DDR_52] = {"ti,otap-del-sel-ddr52", + "ti,itap-del-sel-ddr52", + MMC_CAP(MMC_DDR_52)}, + [MMC_HS_200] = {"ti,otap-del-sel-hs200", + NULL, + MMC_CAP(MMC_HS_200)}, + [MMC_HS_400] = {"ti,otap-del-sel-hs400", + NULL, + MMC_CAP(MMC_HS_400)}, };
struct am654_driver_data { @@ -127,12 +162,99 @@ static void am654_sdhci_set_control_reg(struct sdhci_host *host) sdhci_set_uhs_timing(host); }
+static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat, + unsigned int speed) +{ + int sel50, sel100, freqsel; + u32 mask, val; + int ret; + + /* Disable delay chain mode */ + regmap_update_bits(plat->base, PHY_CTRL5, + SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); + + if (plat->flags & FREQSEL_2_BIT) { + switch (speed) { + case 200000000: + sel50 = 0; + sel100 = 0; + break; + case 100000000: + sel50 = 0; + sel100 = 1; + break; + default: + sel50 = 1; + sel100 = 0; + } + + /* Configure PHY DLL frequency */ + mask = SEL50_MASK | SEL100_MASK; + val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); + regmap_update_bits(plat->base, PHY_CTRL5, mask, val); + } else { + switch (speed) { + case 200000000: + freqsel = 0x0; + break; + default: + freqsel = 0x4; + } + regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK, + freqsel << FREQSEL_SHIFT); + } + + /* Configure DLL TRIM */ + mask = DLL_TRIM_ICP_MASK; + val = plat->trm_icp << DLL_TRIM_ICP_SHIFT; + + /* Configure DLL driver strength */ + mask |= DR_TY_MASK; + val |= plat->drv_strength << DR_TY_SHIFT; + regmap_update_bits(plat->base, PHY_CTRL1, mask, val); + + /* Enable DLL */ + regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, + 0x1 << ENDLL_SHIFT); + /* + * Poll for DLL ready. Use a one second timeout. + * Works in all experiments done so far + */ + ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val, + val & DLLRDY_MASK, 1000, 1000000); + + return ret; +} + +static void am654_sdhci_write_itapdly(struct am654_sdhci_plat *plat, + u32 itapdly) +{ + /* Set ITAPCHGWIN before writing to ITAPDLY */ + regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, + 1 << ITAPCHGWIN_SHIFT); + regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYSEL_MASK, + itapdly << ITAPDLYSEL_SHIFT); + regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); +} + +static void am654_sdhci_setup_delay_chain(struct am654_sdhci_plat *plat, + int mode) +{ + u32 mask, val; + + val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; + mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; + regmap_update_bits(plat->base, PHY_CTRL5, mask, val); + + am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode]); +} + static int am654_sdhci_set_ios_post(struct sdhci_host *host) { struct udevice *dev = host->mmc->dev; struct am654_sdhci_plat *plat = dev_get_plat(dev); unsigned int speed = host->mmc->clock; - int sel50, sel100, freqsel; + int mode = host->mmc->selected_mode; u32 otap_del_sel; u32 mask, val; int ret; @@ -148,75 +270,29 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host) sdhci_set_clock(host->mmc, speed);
/* switch phy back on */ - if (speed > AM654_SDHCI_MIN_FREQ) { - otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode]; - mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; - val = (1 << OTAPDLYENA_SHIFT) | - (otap_del_sel << OTAPDLYSEL_SHIFT); - - /* Write to STRBSEL for HS400 speed mode */ - if (host->mmc->selected_mode == MMC_HS_400) { - if (plat->flags & STRBSEL_4_BIT) - mask |= STRBSEL_4BIT_MASK; - else - mask |= STRBSEL_8BIT_MASK; - - val |= plat->strb_sel << STRBSEL_SHIFT; - } + otap_del_sel = plat->otap_del_sel[mode]; + mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; + val = (1 << OTAPDLYENA_SHIFT) | + (otap_del_sel << OTAPDLYSEL_SHIFT);
- regmap_update_bits(plat->base, PHY_CTRL4, mask, val); - - if (plat->flags & FREQSEL_2_BIT) { - switch (speed) { - case 200000000: - sel50 = 0; - sel100 = 0; - break; - case 100000000: - sel50 = 0; - sel100 = 1; - break; - default: - sel50 = 1; - sel100 = 0; - } - - /* Configure PHY DLL frequency */ - mask = SEL50_MASK | SEL100_MASK; - val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); - regmap_update_bits(plat->base, PHY_CTRL5, mask, val); - } else { - switch (speed) { - case 200000000: - freqsel = 0x0; - break; - default: - freqsel = 0x4; - } - regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK, - freqsel << FREQSEL_SHIFT); - } + /* Write to STRBSEL for HS400 speed mode */ + if (host->mmc->selected_mode == MMC_HS_400) { + if (plat->flags & STRBSEL_4_BIT) + mask |= STRBSEL_4BIT_MASK; + else + mask |= STRBSEL_8BIT_MASK;
- /* Configure DLL TRIM */ - mask = DLL_TRIM_ICP_MASK; - val = plat->trm_icp << DLL_TRIM_ICP_SHIFT; - - /* Configure DLL driver strength */ - mask |= DR_TY_MASK; - val |= plat->drv_strength << DR_TY_SHIFT; - regmap_update_bits(plat->base, PHY_CTRL1, mask, val); - - /* Enable DLL */ - regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, - 0x1 << ENDLL_SHIFT); - /* - * Poll for DLL ready. Use a one second timeout. - * Works in all experiments done so far - */ - ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val, - val & DLLRDY_MASK, 1000, 1000000); + val |= plat->strb_sel << STRBSEL_SHIFT; + } + + regmap_update_bits(plat->base, PHY_CTRL4, mask, val); + + if (mode > UHS_SDR25 && speed >= CLOCK_TOO_SLOW_HZ) { + ret = am654_sdhci_setup_dll(plat, speed); if (ret) return ret; + } else { + am654_sdhci_setup_delay_chain(plat, mode); }
return 0; @@ -354,15 +430,20 @@ static int sdhci_am654_get_otap_delay(struct udevice *dev, * value is not found */ for (i = MMC_HS; i <= MMC_HS_400; i++) { - ret = dev_read_u32(dev, td[i].binding, &plat->otap_del_sel[i]); + ret = dev_read_u32(dev, td[i].otap_binding, + &plat->otap_del_sel[i]); if (ret) { - dev_dbg(dev, "Couldn't find %s\n", td[i].binding); + dev_dbg(dev, "Couldn't find %s\n", td[i].otap_binding); /* * Remove the corresponding capability * if an otap-del-sel value is not found */ cfg->host_caps &= ~td[i].capability; } + + if (td[i].itap_binding) + dev_read_u32(dev, td[i].itap_binding, + &plat->itap_del_sel[i]); }
return 0;
From: Faiz Abbas faiz_abbas@ti.com
Add support for writing new clock buffer select property for both the am654x and j721e 4 bit IPs
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com Reviewed-by: Jaehoon Chung jh80.chung@samsung.com --- drivers/mmc/am654_sdhci.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index b82558254ebb..e86ef1a8b218 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -48,6 +48,8 @@ #define SEL100_MASK BIT(SEL100_SHIFT) #define FREQSEL_SHIFT 8 #define FREQSEL_MASK GENMASK(10, 8) +#define CLKBUFSEL_SHIFT 0 +#define CLKBUFSEL_MASK GENMASK(2, 0) #define DLL_TRIM_ICP_SHIFT 4 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) #define DR_TY_SHIFT 20 @@ -92,6 +94,7 @@ struct am654_sdhci_plat { u32 trm_icp; u32 drv_strength; u32 strb_sel; + u32 clkbuf_sel; u32 flags; #define DLL_PRESENT BIT(0) #define IOMUX_PRESENT BIT(1) @@ -295,6 +298,9 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host) am654_sdhci_setup_delay_chain(plat, mode); }
+ regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK, + plat->clkbuf_sel); + return 0; }
@@ -395,6 +401,9 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host) val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT); regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
+ regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK, + plat->clkbuf_sel); + return 0; }
@@ -548,6 +557,8 @@ static int am654_sdhci_of_to_plat(struct udevice *dev) } }
+ dev_read_u32(dev, "ti,clkbuf-sel", &plat->clkbuf_sel); + ret = mmc_of_parse(dev, cfg); if (ret) return ret;
From: Faiz Abbas faiz_abbas@ti.com
With the new SW tuning App note[1], a custom tuning algorithm is required for eMMC HS200, HS400 and SD card UHS modes. The algorithm involves running through the 32 possible input tap delay values and sending the appropriate tuning command (CMD19/21) for each of them to get a fail or pass result for each of the values. Typically, the range will have a small contiguous failing window. Considering the tuning range as a circular buffer, the algorithm then sets a final tuned value directly opposite to the failing window.
[1] https://www.ti.com/lit/pdf/spract9
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com Reviewed-by: Jaehoon Chung jh80.chung@samsung.com --- drivers/mmc/am654_sdhci.c | 45 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index e86ef1a8b218..9549420c6582 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -9,6 +9,7 @@ #include <common.h> #include <dm.h> #include <malloc.h> +#include <mmc.h> #include <power-domain.h> #include <regmap.h> #include <sdhci.h> @@ -368,7 +369,48 @@ static int am654_sdhci_deferred_probe(struct sdhci_host *host) return sdhci_probe(dev); }
+#ifdef MMC_SUPPORTS_TUNING +#define ITAP_MAX 32 +static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) +{ + struct udevice *dev = mmc->dev; + struct am654_sdhci_plat *plat = dev_get_plat(dev); + int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len; + u32 itap; + + /* Enable ITAPDLY */ + regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK, + 1 << ITAPDLYENA_SHIFT); + + for (itap = 0; itap < ITAP_MAX; itap++) { + am654_sdhci_write_itapdly(plat, itap); + + cur_val = !mmc_send_tuning(mmc, opcode, NULL); + if (cur_val && !prev_val) + pass_window = itap; + + if (!cur_val) + fail_len++; + + prev_val = cur_val; + } + /* + * Having determined the length of the failing window and start of + * the passing window calculate the length of the passing window and + * set the final value halfway through it considering the range as a + * circular buffer + */ + pass_len = ITAP_MAX - fail_len; + itap = (pass_window + (pass_len >> 1)) % ITAP_MAX; + am654_sdhci_write_itapdly(plat, itap); + + return 0; +} +#endif const struct sdhci_ops am654_sdhci_ops = { +#ifdef MMC_SUPPORTS_TUNING + .platform_execute_tuning = am654_sdhci_execute_tuning, +#endif .deferred_probe = am654_sdhci_deferred_probe, .set_ios_post = &am654_sdhci_set_ios_post, .set_control_reg = &am654_sdhci_set_control_reg, @@ -408,6 +450,9 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host) }
const struct sdhci_ops j721e_4bit_sdhci_ops = { +#ifdef MMC_SUPPORTS_TUNING + .platform_execute_tuning = am654_sdhci_execute_tuning, +#endif .deferred_probe = am654_sdhci_deferred_probe, .set_ios_post = &j721e_4bit_sdhci_set_ios_post, };
From: Faiz Abbas faiz_abbas@ti.com
According to the AM654x Data Manual[1], the setup timing in lower speed modes can only be met if the controller uses a falling edge data launch.
To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25 speed modes.
Use the sdhci writeb callback to implement this condition.
[1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com Reviewed-by: Jaehoon Chung jh80.chung@samsung.com --- drivers/mmc/Kconfig | 1 + drivers/mmc/am654_sdhci.c | 25 +++++++++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 14d79139864a..f8ea92172e44 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -526,6 +526,7 @@ config MMC_SDHCI_AM654 depends on MMC_SDHCI depends on DM_MMC && OF_CONTROL && BLK depends on REGMAP + select MMC_SDHCI_IO_ACCESSORS help Support for Secure Digital Host Controller Interface (SDHCI) controllers present on TI's AM654 SOCs. diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 9549420c6582..5dea3eb1be4e 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -369,6 +369,26 @@ static int am654_sdhci_deferred_probe(struct sdhci_host *host) return sdhci_probe(dev); }
+static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg) +{ + if (reg == SDHCI_HOST_CONTROL) { + switch (host->mmc->selected_mode) { + /* + * According to the data manual, HISPD bit + * should not be set in these speed modes. + */ + case SD_HS: + case MMC_HS: + case UHS_SDR12: + case UHS_SDR25: + val &= ~SDHCI_CTRL_HISPD; + default: + break; + } + } + + writeb(val, host->ioaddr + reg); +} #ifdef MMC_SUPPORTS_TUNING #define ITAP_MAX 32 static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) @@ -414,6 +434,7 @@ const struct sdhci_ops am654_sdhci_ops = { .deferred_probe = am654_sdhci_deferred_probe, .set_ios_post = &am654_sdhci_set_ios_post, .set_control_reg = &am654_sdhci_set_control_reg, + .write_b = am654_sdhci_write_b, };
const struct am654_driver_data am654_drv_data = { @@ -455,6 +476,7 @@ const struct sdhci_ops j721e_4bit_sdhci_ops = { #endif .deferred_probe = am654_sdhci_deferred_probe, .set_ios_post = &j721e_4bit_sdhci_set_ios_post, + .write_b = am654_sdhci_write_b, };
const struct am654_driver_data j721e_4bit_drv_data = { @@ -532,6 +554,7 @@ static int am654_sdhci_probe(struct udevice *dev) host->max_clk = clock; host->mmc = &plat->mmc; host->mmc->dev = dev; + host->ops = drv_data->ops; ret = sdhci_setup_cfg(cfg, host, cfg->f_max, AM654_SDHCI_MIN_FREQ); if (ret) @@ -541,8 +564,6 @@ static int am654_sdhci_probe(struct udevice *dev) if (ret) return ret;
- host->ops = drv_data->ops; - /* Update ops based on SoC revision */ soc = soc_device_match(am654_sdhci_soc_attr); if (soc && soc->data) {
From: Faiz Abbas faiz_abbas@ti.com
Use the generic sdhci_set_control_reg() instead of duplicating in platform driver.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com Reviewed-by: Jaehoon Chung jh80.chung@samsung.com --- drivers/mmc/am654_sdhci.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 5dea3eb1be4e..11dcde134c5f 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -151,21 +151,6 @@ struct am654_driver_data { u32 flags; };
-static void am654_sdhci_set_control_reg(struct sdhci_host *host) -{ - struct mmc *mmc = (struct mmc *)host->mmc; - u32 reg; - - if (IS_SD(host->mmc) && - mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { - reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); - reg |= SDHCI_CTRL_VDD_180; - sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); - } - - sdhci_set_uhs_timing(host); -} - static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat, unsigned int speed) { @@ -433,7 +418,7 @@ const struct sdhci_ops am654_sdhci_ops = { #endif .deferred_probe = am654_sdhci_deferred_probe, .set_ios_post = &am654_sdhci_set_ios_post, - .set_control_reg = &am654_sdhci_set_control_reg, + .set_control_reg = sdhci_set_control_reg, .write_b = am654_sdhci_write_b, };
@@ -476,6 +461,7 @@ const struct sdhci_ops j721e_4bit_sdhci_ops = { #endif .deferred_probe = am654_sdhci_deferred_probe, .set_ios_post = &j721e_4bit_sdhci_set_ios_post, + .set_control_reg = sdhci_set_control_reg, .write_b = am654_sdhci_write_b, };
From: Faiz Abbas faiz_abbas@ti.com
Because of fundamental interface issues in am65x pg1, only the initial sdhci1 node at 25 MHz was added in the u-boot.dtsi from which both the base-board.dts and r5-base-board.dts inherit the node. Move the node out to k3-am65-main.dtsi where it belongs and add the board specific properties in base-board.dts and r5-base-board.dts
This ensures dts compatibility with the kernel dts in the base-board.dts and enables the SD card interface at 50 MHz and High Speed mode
While we are here, also fix the main_mmc0_pins_default property to be included and inherit from the base-board.dts instead of the u-boot.dtsi
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com --- arch/arm/dts/k3-am65-main.dtsi | 22 +++++++ arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 67 +++----------------- arch/arm/dts/k3-am654-base-board.dts | 25 ++++++++ arch/arm/dts/k3-am654-r5-base-board.dts | 20 +++++- 4 files changed, 74 insertions(+), 60 deletions(-)
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index 028f57379b9f..d151e27028cd 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -113,6 +113,28 @@ dma-coherent; };
+ sdhci1: sdhci@4fa0000 { + compatible = "ti,am654-sdhci-5.1"; + reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; + clock-names = "clk_ahb", "clk_xin"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0x0>; + ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr50 = <0x8>; + ti,otap-del-sel-sdr104 = <0x7>; + ti,otap-del-sel-ddr50 = <0x4>; + ti,otap-del-sel-ddr52 = <0x4>; + ti,otap-del-sel-hs200 = <0x7>; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; + dma-coherent; + }; + main_i2c0: i2c@2000000 { compatible = "ti,am654-i2c", "ti,omap4-i2c"; reg = <0x0 0x2000000 0x0 0x100>; diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index 727bc3e8a0e3..b030d750f2a1 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -21,28 +21,6 @@
&cbass_main{ u-boot,dm-spl; - - sdhci1: sdhci@04FA0000 { - compatible = "ti,am654-sdhci-5.1"; - reg = <0x0 0x4FA0000 0x0 0x1000>, - <0x0 0x4FB0000 0x0 0x400>; - clocks =<&k3_clks 48 0>, <&k3_clks 48 1>; - clock-names = "clk_ahb", "clk_xin"; - power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; - max-frequency = <25000000>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; - ti,otap-del-sel-sdr50 = <0x8>; - ti,otap-del-sel-sdr104 = <0x7>; - ti,otap-del-sel-ddr50 = <0x4>; - ti,otap-del-sel-ddr52 = <0x4>; - ti,otap-del-sel-hs200 = <0x7>; - ti,trm-icp = <0x8>; - }; - };
&cbass_mcu { @@ -109,38 +87,6 @@ u-boot,dm-spl; };
- main_mmc0_pins_default: main_mmc0_pins_default { - pinctrl-single,pins = < - AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ - AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ - AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ - AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ - AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ - AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ - AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ - AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ - AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ - AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ - AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ - AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ - >; - u-boot,dm-spl; - }; - - main_mmc1_pins_default: main_mmc1_pins_default { - pinctrl-single,pins = < - AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ - AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ - AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ - AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ - AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ - AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ - AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ - AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */ - >; - u-boot,dm-spl; - }; - usb0_pins_default: usb0_pins_default { pinctrl-single,pins = < AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ @@ -190,17 +136,20 @@ status = "okay"; };
+&main_mmc0_pins_default { + u-boot,dm-spl; +}; + +&main_mmc1_pins_default { + u-boot,dm-spl; +}; + &sdhci0 { u-boot,dm-spl; };
&sdhci1 { u-boot,dm-spl; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - sdhci-caps-mask = <0x7 0x0>; - ti,driver-strength-ohm = <50>; };
&mcu_cpsw { diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts index 3ebf4af5e47a..33a1b9fdc4b7 100644 --- a/arch/arm/dts/k3-am654-base-board.dts +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -59,6 +59,19 @@ >; };
+ main_mmc1_pins_default: main_mmc1_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ + AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ + AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ + AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ + AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ + AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ + AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ + AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */ + >; + }; + usb1_pins_default: usb1_pins_default { pinctrl-single,pins = < AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ @@ -122,6 +135,18 @@ ti,driver-strength-ohm = <50>; };
+/* + * Because of erratas i2025 and i2026 for silicon revision 1.0, the + * SD card interface might fail. Boards with sr1.0 are recommended to + * disable sdhci1 + */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + &wkup_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index f12510259da4..e0f2d1782fdc 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -6,7 +6,6 @@ /dts-v1/;
#include "k3-am654.dtsi" -#include "k3-am654-base-board-u-boot.dtsi" #include "k3-am654-base-board-ddr4-1600MTs.dtsi" #include "k3-am654-ddr.dtsi"
@@ -214,6 +213,21 @@ AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ >; + u-boot,dm-spl; + }; + + main_mmc1_pins_default: main_mmc1_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ + AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ + AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ + AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ + AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ + AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ + AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ + AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */ + >; + u-boot,dm-spl; }; };
@@ -226,6 +240,7 @@ &sdhci0 { clock-names = "clk_xin"; clocks = <&clk_200mhz>; + pinctrl-0 = <&main_mmc0_pins_default>; /delete-property/ power-domains; ti,driver-strength-ohm = <50>; }; @@ -233,6 +248,7 @@ &sdhci1 { clock-names = "clk_xin"; clocks = <&clk_200mhz>; + pinctrl-0 = <&main_mmc1_pins_default>; /delete-property/ power-domains; ti,driver-strength-ohm = <50>; }; @@ -314,3 +330,5 @@ &scm_conf { u-boot,dm-spl; }; + +#include "k3-am654-base-board-u-boot.dtsi"
From: Faiz Abbas faiz_abbas@ti.com
Update otap delay values to match with the latest Data Manual[1].
[1] https://www.ti.com/lit/gpn/dra829v
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com --- arch/arm/dts/k3-j721e-main.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index 33db74a267a6..e08e74370611 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -235,11 +235,14 @@ ti,trm-icp = <0x8>; dma-coherent; mmc-ddr-1_8v; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-legacy = <0xf>; + ti,otap-del-sel-mmc-hs = <0xf>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x6>; ti,otap-del-sel-hs400 = <0x0>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; };
main_sdhci1: sdhci@4fb0000 { @@ -256,7 +259,6 @@ ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; ti,otap-del-sel-ddr50 = <0xc>; ti,trm-icp = <0x8>; dma-coherent;
From: Faiz Abbas faiz_abbas@ti.com
Add support for regulators to power cycle and switch IO voltage to the SD card. This enables support for UHS modes.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com --- arch/arm/dts/k3-j721e-common-proc-board.dts | 32 +++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts index 496a15e1d1ac..fcfc665f0944 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/;
#include "k3-j721e-som-p0.dtsi" +#include <dt-bindings/gpio/gpio.h>
/ { chosen { @@ -24,6 +25,29 @@ remoteproc7 = &c66_1; remoteproc8 = &c71_0; }; + + vdd_mmc1: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv_alt: gpio-regulator-TLV71033 { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; + regulator-name = "tlv71033"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0 + 3300000 0x1>; + }; };
&wkup_uart0 { @@ -79,6 +103,12 @@ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ >; }; + + vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x1d8, PIN_OUTPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ + >; + }; };
&main_sdhci0 { @@ -92,6 +122,8 @@ pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv_alt>; };
&main_pmx0 {
From: Faiz Abbas faiz_abbas@ti.com
Add support for the main_gpio0 node
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com --- arch/arm/dts/k3-j7200-main.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index c25f03cf23d9..b722204c44ac 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -197,6 +197,28 @@ clock-names = "fclk"; };
+ main_gpio0: gpio@600000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x0 0x00600000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <105 0 IRQ_TYPE_EDGE_RISING>, + <105 1 IRQ_TYPE_EDGE_RISING>, + <105 2 IRQ_TYPE_EDGE_RISING>, + <105 3 IRQ_TYPE_EDGE_RISING>, + <105 4 IRQ_TYPE_EDGE_RISING>, + <105 5 IRQ_TYPE_EDGE_RISING>, + <105 6 IRQ_TYPE_EDGE_RISING>, + <105 7 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 0>; + clock-names = "gpio"; + }; + main_sdhci0: sdhci@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
From: Faiz Abbas faiz_abbas@ti.com
Add support for UHS modes by adding the regulators to power cycle and voltage switch the card. Also add pinmuxes required for each node
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com --- arch/arm/dts/k3-j7200-common-proc-board.dts | 49 ++++++++++++++++++- arch/arm/dts/k3-j7200-main.dtsi | 1 + .../arm/dts/k3-j7200-r5-common-proc-board.dts | 15 ++++++ 3 files changed, 63 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts index cc3d933cbb51..85cb159838e3 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-common-proc-board.dts @@ -7,6 +7,7 @@
#include <dt-bindings/net/ti-dp83867.h> #include "k3-j7200-som-p0.dtsi" +#include <dt-bindings/gpio/gpio.h>
/ { chosen { @@ -20,6 +21,29 @@ remoteproc2 = &main_r5fss0_core0; remoteproc3 = &main_r5fss0_core1; }; + + vdd_mmc1: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: gpio-regulator-vdd-sd-dv { + compatible = "regulator-gpio"; + regulator-name = "vdd_sd_dv"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0 + 3300000 0x1>; + }; };
&wkup_pmx0 { @@ -69,6 +93,25 @@ >; };
+ main_mmc1_pins_default: main_mmc1_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ + J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ + J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ + J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ + J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ + J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ + J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ + J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ + >; + }; + + vdd_sd_dv_pins_default: vdd_sd_dv_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ + >; + }; + main_usbss0_pins_default: main_usbss0_pins_default { pinctrl-single,pins = < J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ @@ -140,10 +183,12 @@
&main_sdhci1 { /* SD card */ + pinctrl-0 = <&main_mmc1_pins_default>; + pinctrl-names = "default"; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; ti,driver-strength-ohm = <50>; disable-wp; - no-1-8-v; - sdhci-caps-mask = <0x8000000F 0x0>; };
&main_i2c0 { diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index b722204c44ac..8150ff6332c2 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -253,6 +253,7 @@ ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x5>; ti,otap-del-sel-ddr50 = <0xc>; + ti,clkbuf-sel = <0x7>; dma-coherent; };
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 2ac887b180c9..04914320609c 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -162,6 +162,19 @@ >; };
+ main_mmc1_pins_default: main_mmc1_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ + J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ + J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ + J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ + J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ + J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ + J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ + J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ + >; + }; + main_usbss0_pins_default: main_usbss0_pins_default { pinctrl-single,pins = < J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ @@ -198,6 +211,8 @@ /delete-property/ power-domains; /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; + pinctrl-0 = <&main_mmc1_pins_default>; + pinctrl-names = "default"; clock-names = "clk_xin"; clocks = <&clk_200mhz>; ti,driver-strength-ohm = <50>;
From: Faiz Abbas faiz_abbas@ti.com
Add configs to support UHS modes for the SD card and HS200 for the eMMC.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com --- configs/j721e_evm_a72_defconfig | 8 ++++++++ configs/j721e_evm_r5_defconfig | 1 + 2 files changed, 9 insertions(+)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 982e3df2f224..e14005c39dd8 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -108,11 +108,16 @@ CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -141,6 +146,9 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_REMOTEPROC_TI_K3_DSP=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 41285481005c..7b4f0afce61f 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -89,6 +89,7 @@ CONFIG_K3_AVS0=y CONFIG_ESM_PMIC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y
From: Faiz Abbas faiz_abbas@ti.com
Add configs to support UHS modes for the SD card and HS200 for the eMMC.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com --- configs/j7200_evm_a72_defconfig | 8 ++++++++ configs/j7200_evm_r5_defconfig | 1 + 2 files changed, 9 insertions(+)
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 1d2526b5f1b2..162bcc8753ff 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -111,11 +111,16 @@ CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -143,6 +148,9 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_REMOTEPROC_TI_K3_R5F=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 3820fc508b38..b20698fd0ed1 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -89,6 +89,7 @@ CONFIG_K3_SEC_PROXY=y CONFIG_FS_LOADER=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y
From: Faiz Abbas faiz_abbas@ti.com
Add the appropriate itapdly and clkbuf-sel values required for some lower speed modes.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com --- arch/arm/dts/k3-am65-main.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index d151e27028cd..a7b03dc66908 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -109,6 +109,11 @@ ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x5>; ti,otap-del-sel-hs400 = <0x0>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-mmc-hs = <0x1>; + ti,itap-del-sel-sdr12 = <0xa>; + ti,itap-del-sel-sdr25 = <0x1>; + ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; }; @@ -130,6 +135,10 @@ ti,otap-del-sel-ddr50 = <0x4>; ti,otap-del-sel-ddr52 = <0x4>; ti,otap-del-sel-hs200 = <0x7>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-mmc-hs = <0x1>; + ti,itap-del-sel-sdr12 = <0xa>; + ti,itap-del-sel-sdr25 = <0x1>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent;
From: Faiz Abbas faiz_abbas@ti.com
There's an issue with the base board in which the power cycle circuit takes way longer to power down than expected by mmc core. code. This prevents the card from enumerating in UHS modes.
Disable UHS modes for this board until a new board revision fixes the issue.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com --- arch/arm/dts/k3-am654-base-board.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts index 33a1b9fdc4b7..830526a1e473 100644 --- a/arch/arm/dts/k3-am654-base-board.dts +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -144,6 +144,7 @@ pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; + sdhci-caps-mask = <0x7 0x0>; disable-wp; };
From: Faiz Abbas faiz_abbas@ti.com
Add configs for voltage switching and UHS modes for the SD card and HS200 for the eMMC.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Signed-off-by: Aswath Govindraju a-govindraju@ti.com --- configs/am65x_evm_a53_defconfig | 8 ++++++++ configs/am65x_evm_r5_defconfig | 2 ++ 2 files changed, 10 insertions(+)
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 941073ce7f19..2ab978b6f37b 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -96,12 +96,17 @@ CONFIG_TI_SCI_PROTOCOL=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -133,6 +138,9 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 96c4351196d2..b9b11010a105 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -85,6 +85,8 @@ CONFIG_K3_SEC_PROXY=y CONFIG_K3_AVS0=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y
On 04/02/21 3:10 pm, Aswath Govindraju wrote:
The following patches add support for higher speeds in the SD card and eMMC for TI's am65x, j721e, j7200 platforms.
With these patches, the following max speeds are supported: j721e: DDR50, HS200 j7200: SDR104, HS200 am65x: SDR104*, HS200
Series applied to u-boot-ti/for-rc branch.
Thanks and regards, Lokesh
changes since v5:
- In patch 1 moved the 5ms delay after setting the 1.8V enable bit
- In patch 1 added a check to confirm if the output has stabilized.
- Picked up Reviewed-by from Jaehoon Chung for patch 1
changes since v4:
- removed patch(15 in v4) that adds support for HS400 in J7200 platform, as there are some errors while switching to HS400 mode.
- changed the function regulator_set_enable() in patch 1 to regulator_set_enable_if_allowed() as there is a possibility of not having an enable gpio.
- changed the pin direction from PIN_INPUT to PIN_OUTPUT for pins SPI1_CS1 and SPI0_D1 in patches 13 and 15 (in v4) respectively.
- changed the configs enabled, to HS200 from HS400 for J7200 in patch 18 (in v4).
changes since v3:
- changed #if to if(IS_ENABLED()) in patch 1 for MMC_IO_VOLTAGE.
- changed the format for print statements added in v3 to remove warnings arising when DM_REGULATOR variable is not defined
- Added a patch to add support for HS400 speed mode in J7200 as it is now supported.
- edited patch 17 (in v3) to add support for HS400 instead of HS200 as it is now supported in J7200 SoC.
- Added description for sdhci_set_ctrl_reg() function in include/sdhci.h
- Added comment for mdelay in patch 1
- Picked up Reviewed-by's from Jaehoon Chung
changes since v2:
- Added print statements in case of failure for regulator_set_enable and regulator_set_value function calls in patch 1
- Removed patch 18 (in v2) as it has been applied by commit [1]
- renamed the function dev_get_platdata() to dev_get_plat in patch 8
- rebased all the patches in seriesn
changes since v1:
- Added patches to support UHS modes for the SD card even in am654x platforms.
- Fixed an issue with patch 1 that was breaking builds on some platforms.
- There's an issue with the am65x base board such that the power cycle
circuit to the card takes way longer than the wait time in mmc core. Until this is fixed, am654x-evm and -idk will only support High speed mode at 3.3V (see patch 20) but this shouldn't block us from adding UHS modes in the dtsi as well as in the configs so other boards can still take advantage of the higher speed. UHS modes have been tested by adding the appropriate delay in the power cycle circuit.
[1] - commit 67507e4aab5b ("sandbox: Fix up building for of-platdata")
Link to v1: https://patchwork.ozlabs.org/project/uboot/list/?series=206622
Faiz Abbas (20): mmc: sdhci: Add helper functions for UHS modes mmc: am654_sdhci: Unconditionally switch off DLL in the beginning of ios_post() mmc: am654_sdhci: Convert flag fields to BIT macro mmc: am654_sdhci: Add flag for PHY calibration mmc: am654_sdhci: Add support for AM65x SR2.0 mmc: am654_sdhci: Add support for input tap delay mmc: am654_sdhci: Add support for writing to clkbuf_sel mmc: am654_sdhci: Add support for software tuning mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modes mmc: am654_sdhci: Use sdhci_set_control_reg() arm: dts: k3-am65: Fix mmc nodes arm: dts: k3-j721e-main: Update otap-delay values arm: dts: k3-j721e-common-proc-board: Add support for UHS modes for SD card arm: dts: k3-j7200-main: Add support for gpio0 arm: dts: k3-j7200-common-proc-board: Enable support for UHS modes configs: j721e_evm: Add support for UHS modes configs: j7200_evm: Add support for UHS modes arm: dts: k3-am65-main: Add itapdly and clkbuf-sel values arm: dts: k3-am654-base-board: Limit Sd card to High speed modes configs: am65x_evm: Add configs for UHS modes
arch/arm/dts/k3-am65-main.dtsi | 31 ++ arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 67 +-- arch/arm/dts/k3-am654-base-board.dts | 26 ++ arch/arm/dts/k3-am654-r5-base-board.dts | 20 +- arch/arm/dts/k3-j7200-common-proc-board.dts | 49 ++- arch/arm/dts/k3-j7200-main.dtsi | 23 ++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 15 + arch/arm/dts/k3-j721e-common-proc-board.dts | 32 ++ arch/arm/dts/k3-j721e-main.dtsi | 8 +- configs/am65x_evm_a53_defconfig | 8 + configs/am65x_evm_r5_defconfig | 2 + configs/j7200_evm_a72_defconfig | 8 + configs/j7200_evm_r5_defconfig | 1 + configs/j721e_evm_a72_defconfig | 8 + configs/j721e_evm_r5_defconfig | 1 + drivers/mmc/Kconfig | 1 + drivers/mmc/am654_sdhci.c | 384 +++++++++++++----- drivers/mmc/sdhci.c | 95 +++++ include/sdhci.h | 10 + 19 files changed, 616 insertions(+), 173 deletions(-)
participants (2)
-
Aswath Govindraju -
Lokesh Vutla