Next step to get rid of the header files in icnlude/configs. Move most of the defines to km83xx.c directly. Some remaining defines which should go to Kconfig are moved to km-mpc83xx.h for now.

Also remove some unused defines and move one define to powerpc.env as we only need it there.

Signed-off-by: Holger Brunck holger.brunck@hitachienergy.com --- board/keymile/km83xx/km83xx.c | 85 +++++++++++++++++++++++++ include/configs/km/km-mpc832x.h | 60 ----------------- include/configs/km/km-mpc8360.h | 68 -------------------- include/configs/km/km-mpc83xx.h | 37 +++++++---- include/configs/kmcoge5ne.h | 1 - include/configs/kmeter1.h | 1 - include/configs/kmopti2.h | 1 - include/configs/kmsupx5.h | 1 - include/configs/kmtepr2.h | 1 - include/configs/tuge1.h | 1 - include/configs/tuxx1.h | 1 - include/environment/pg-wcom/powerpc.env | 2 + 12 files changed, 111 insertions(+), 148 deletions(-) delete mode 100644 include/configs/km/km-mpc832x.h delete mode 100644 include/configs/km/km-mpc8360.h

diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 9ec1dbc6f9..8f2d873bc6 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -35,6 +35,91 @@

DECLARE_GLOBAL_DATA_PTR;

+#if CONFIG_IS_ENABLED(TARGET_KMCOGE5NE) || CONFIG_IS_ENABLED(TARGET_KMETER1) +#define CFG_SYS_DDR_MODE 0x47860452 +#define CFG_SYS_DDR_INTERVAL (\ + (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) +#define CFG_SYS_DDR_TIMING_0 (\ + (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CFG_SYS_DDR_TIMING_2 (\ + (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT)) + +#define CFG_SYS_DDR_TIMING_3 0x00000000 + +#else +#define CFG_SYS_DDR_MODE 0x47860242 +#define CFG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CFG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CFG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CFG_SYS_DDR_TIMING_3 0x00000000 + +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) +#endif + +#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) +#define CFG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CFG_SYS_DDR_CS0_BNDS 0x0000007f +#define CFG_SYS_DDR_MODE2 0x8080c000 + +#define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */ + static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];

static int piggy_present(void) diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h deleted file mode 100644 index f64c0eee1b..0000000000 --- a/include/configs/km/km-mpc832x.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * System IO Config - */ -#define CFG_SYS_SICRL SICRL_IRQ_CKS - -#define CFG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CFG_SYS_DDR_CS0_BNDS 0x0000007f -#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CFG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CFG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CFG_SYS_DDR_MODE 0x47860242 -#define CFG_SYS_DDR_MODE2 0x8080c000 - -#define CFG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CFG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CFG_SYS_DDR_TIMING_3 0x00000000 - -#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CFG_SYS_KMBEC_FPGA_SIZE 128 diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h deleted file mode 100644 index 04d3d352ee..0000000000 --- a/include/configs/km/km-mpc8360.h +++ /dev/null @@ -1,68 +0,0 @@ -/* KMBEC FPGA (PRIO) */ -#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CFG_SYS_KMBEC_FPGA_SIZE 64 - -/* - * High Level Configuration Options - */ - -/* - * System IO Setup - */ -#define CFG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) - -/** - * DDR RAM settings - */ -#define CFG_SYS_DDR_SDRAM_CFG (\ - SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 - -#define CFG_SYS_DDR_CLK_CNTL (\ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_SYS_DDR_INTERVAL (\ - (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CFG_SYS_DDR_CS0_BNDS 0x0000007f - -#define CFG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_Q_DRN) -#define CFG_SYS_DDR_MODE 0x47860452 -#define CFG_SYS_DDR_MODE2 0x8080c000 - -#define CFG_SYS_DDR_TIMING_0 (\ - (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CFG_SYS_DDR_TIMING_2 (\ - (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT)) - -#define CFG_SYS_DDR_TIMING_3 0x00000000 - diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index c939caf2a1..21f707aaf8 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -1,9 +1,3 @@ -/* - * Internal Definitions - */ -#include <linux/stringify.h> -#define BOOTFLASH_START 0xF0000000 - /* * DDR Setup */ @@ -12,13 +6,6 @@ #define CFG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)

-#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */ - /* * The reserved memory */ @@ -48,10 +35,34 @@

#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }

+#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 + #if defined(CONFIG_CMD_NAND) #define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE #endif

+#if defined(CONFIG_TARGET_KMCOGE5NE) || defined(CONFIG_TARGET_KMETER1) +/* + * System IO Setup + */ +#define CFG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) + +#define CFG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_Q_DRN) +#else +/* + * System IO Config + */ +#define CFG_SYS_SICRL SICRL_IRQ_CKS + +#define CFG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) +#endif + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index d52f45ba91..7835332fc0 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -13,7 +13,6 @@

/* include common defines/options for all Keymile boards */ #include "km/km-mpc83xx.h" -#include "km/km-mpc8360.h"

/** * KMCOGE5NE has 512 MB RAM diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 6f67e5a98a..f9be06fd25 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -10,7 +10,6 @@

/* include common defines/options for all Keymile boards */ #include "km/km-mpc83xx.h" -#include "km/km-mpc8360.h"

#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ROW_BIT_13 | \ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index d6a3844bcc..69c28c2035 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -22,6 +22,5 @@

/* include common defines/options for all Keymile boards */ #include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h"

#endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index d6a3844bcc..69c28c2035 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -22,6 +22,5 @@

/* include common defines/options for all Keymile boards */ #include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h"

#endif /* __CONFIG_H */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index d6a3844bcc..69c28c2035 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -22,6 +22,5 @@

/* include common defines/options for all Keymile boards */ #include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h"

#endif /* __CONFIG_H */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index d6a3844bcc..69c28c2035 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -22,6 +22,5 @@

/* include common defines/options for all Keymile boards */ #include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h"

#endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index d6a3844bcc..69c28c2035 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -22,6 +22,5 @@

/* include common defines/options for all Keymile boards */ #include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h"

#endif /* __CONFIG_H */ diff --git a/include/environment/pg-wcom/powerpc.env b/include/environment/pg-wcom/powerpc.env index a57fd93092..744c07388c 100644 --- a/include/environment/pg-wcom/powerpc.env +++ b/include/environment/pg-wcom/powerpc.env @@ -1,3 +1,5 @@ +#define BOOTFLASH_START 0xF0000000 + arch=ppc_82xx bootm_mapsize=CONFIG_SYS_BOOTM_LEN checkfdt=true