On Wed, Feb 1, 2017 at 1:55 PM, ken <Ken Lin> yungching0725@gmail.com wrote:

Apply the previous setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test

Seems reasonable. Was this tested on HW? If so, please add a tested tag.

Thanks, -Joe

---

drivers/net/phy/atheros.c | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index b34cdd3d87..82fe228604 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -28,6 +28,8 @@ static int ar8021_config(struct phy_device *phydev)

static int ar8031_config(struct phy_device *phydev) {

•   int regval;
  

•   if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
        phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
            phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
  

@@ -44,6 +46,10 @@ static int ar8031_config(struct phy_device *phydev) AR803x_RGMII_RX_CLK_DLY); }

•    phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, AR803x_DEBUG_REG_5);
  

•    regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
  

•    phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval | 0x3C47);
  

•   phydev->supported = phydev->drv->features;
  
    genphy_config_aneg(phydev);
  

-- 2.11.0

---

U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

On Wed, Feb 1, 2017 at 1:55 PM, ken <Ken Lin> yungching0725@gmail.com wrote:

Apply the previous setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test

---

drivers/net/phy/atheros.c | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index b34cdd3d87..82fe228604 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -28,6 +28,8 @@ static int ar8021_config(struct phy_device *phydev)

static int ar8031_config(struct phy_device *phydev) {

•   int regval;
  

•   if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
        phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
            phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
  

@@ -44,6 +46,10 @@ static int ar8031_config(struct phy_device *phydev) AR803x_RGMII_RX_CLK_DLY); }

•    phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, AR803x_DEBUG_REG_5);
  

•    regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
  

•    phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval | 0x3C47);
  

It would also be good if you move this "0x3C47" to a #define and include a comment about what it means.

•   phydev->supported = phydev->drv->features;
  
    genphy_config_aneg(phydev);
  

-- 2.11.0

---

U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Apply the previous setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test

Tested on Advantech DMS-BA16 board Tested-by: Ken Lin ken.lin@advantech.com Signed-off-by: Ken Lin ken.lin@advantech.com --- drivers/net/phy/atheros.c | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index b34cdd3d87..87e8fc55d4 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -17,6 +17,8 @@ #define AR803x_DEBUG_REG_0 0x0 #define AR803x_RGMII_RX_CLK_DLY 0x8000

+#define AR803x_SERDES_TEST_DEFAULT 0x3C47 + static int ar8021_config(struct phy_device *phydev) { phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); @@ -28,6 +30,8 @@ static int ar8021_config(struct phy_device *phydev)

static int ar8031_config(struct phy_device *phydev) { + int regval; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, @@ -44,6 +48,10 @@ static int ar8031_config(struct phy_device *phydev) AR803x_RGMII_RX_CLK_DLY); }

+ phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, AR803x_DEBUG_REG_5); + regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG); + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval | AR803x_SERDES_TEST_DEFAULT); + phydev->supported = phydev->drv->features;

genphy_config_aneg(phydev);