[U-Boot] [PATCH 1/9] m68k: add fec base node to devicetrees
From: Angelo Durgehello angelo.dureghello@timesys.com
Add basic ethernet controller devicetree nodes for all ColdFire families.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com --- arch/m68k/dts/mcf5208.dtsi | 10 ++++++++++ arch/m68k/dts/mcf523x.dtsi | 12 ++++++++++++ arch/m68k/dts/mcf5271.dtsi | 10 ++++++++++ arch/m68k/dts/mcf5272.dtsi | 10 ++++++++++ arch/m68k/dts/mcf5275.dtsi | 22 +++++++++++++++++++++- arch/m68k/dts/mcf5282.dtsi | 10 ++++++++++ arch/m68k/dts/mcf5301x.dtsi | 21 +++++++++++++++++++++ arch/m68k/dts/mcf5329.dtsi | 10 ++++++++++ arch/m68k/dts/mcf537x.dtsi | 10 ++++++++++ arch/m68k/dts/mcf5441x.dtsi | 20 ++++++++++++++++++++ arch/m68k/dts/mcf5445x.dtsi | 20 ++++++++++++++++++++ arch/m68k/dts/mcf54xx.dtsi | 32 ++++++++++++++++++++++++++++++++ 12 files changed, 186 insertions(+), 1 deletion(-)
diff --git a/arch/m68k/dts/mcf5208.dtsi b/arch/m68k/dts/mcf5208.dtsi index 558d8bf41a..4802dd3074 100644 --- a/arch/m68k/dts/mcf5208.dtsi +++ b/arch/m68k/dts/mcf5208.dtsi @@ -8,6 +8,7 @@
aliases { serial0 = &uart0; + fec0 = &fec0; };
soc { @@ -32,5 +33,14 @@ reg = <0xfc068000 0x40>; status = "disabled"; }; + + fec0: ethernet@fc030000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc030000 0x400>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/mcf523x.dtsi b/arch/m68k/dts/mcf523x.dtsi index 9e79d472ec..550e824cb1 100644 --- a/arch/m68k/dts/mcf523x.dtsi +++ b/arch/m68k/dts/mcf523x.dtsi @@ -8,6 +8,7 @@
aliases { serial0 = &uart0; + fec0 = &fec0; };
soc { @@ -39,6 +40,17 @@ reg = <0x280 0x40>; status = "disabled"; }; + + fec0: ethernet@1000 { + compatible = "fsl,mcf-fec"; + #address-cells=<2>; + #size-cells=<1>; + reg = <0x1000 0x400>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/m68k/dts/mcf5271.dtsi b/arch/m68k/dts/mcf5271.dtsi index 29355528d0..b3484c2c84 100644 --- a/arch/m68k/dts/mcf5271.dtsi +++ b/arch/m68k/dts/mcf5271.dtsi @@ -8,6 +8,7 @@
aliases { serial0 = &uart0; + fec0 = &fec0; };
soc { @@ -39,6 +40,15 @@ reg = <0x280 0x40>; status = "disabled"; }; + + fec0: ethernet@1000 { + compatible = "fsl,mcf-fec"; + reg = <0x1000 0x400>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/m68k/dts/mcf5272.dtsi b/arch/m68k/dts/mcf5272.dtsi index a56117728b..173baaba3f 100644 --- a/arch/m68k/dts/mcf5272.dtsi +++ b/arch/m68k/dts/mcf5272.dtsi @@ -8,6 +8,7 @@
aliases { serial0 = &uart0; + fec0 = &fec0; };
soc { @@ -33,6 +34,15 @@ reg = <0x140 0x40>; status = "disabled"; }; + + fec0: ethernet@840 { + compatible = "fsl,mcf-fec"; + reg = <0x840 0x400>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/m68k/dts/mcf5275.dtsi b/arch/m68k/dts/mcf5275.dtsi index b375609d4a..99dd7d3924 100644 --- a/arch/m68k/dts/mcf5275.dtsi +++ b/arch/m68k/dts/mcf5275.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + * Copyright (C) 2019 Angelo Dureghello angelo@sysam.it */
/ { @@ -8,6 +8,8 @@
aliases { serial0 = &uart0; + fec0 = &fec0; + fec1 = &fec1; };
soc { @@ -39,6 +41,24 @@ reg = <0x280 0x40>; status = "disabled"; }; + + fec0: ethernet@1000 { + compatible = "fsl,mcf-fec"; + reg = <0x1000 0x800>; + max-speed = <100>; + phy-addr = <(-1)>; + timeout-loop = <50000>; + status = "disabled"; + }; + + fec1: ethernet@1800 { + compatible = "fsl,mcf-fec"; + reg = <0x1800 0x800>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/m68k/dts/mcf5282.dtsi b/arch/m68k/dts/mcf5282.dtsi index 3ad1be7bb5..d9916b1cd9 100644 --- a/arch/m68k/dts/mcf5282.dtsi +++ b/arch/m68k/dts/mcf5282.dtsi @@ -8,6 +8,7 @@
aliases { serial0 = &uart0; + fec0 = &fec0; };
soc { @@ -39,6 +40,15 @@ reg = <0x280 0x40>; status = "disabled"; }; + + fec0: ethernet@1000 { + compatible = "fsl,mcf-fec"; + reg = <0x1000 0x800>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/m68k/dts/mcf5301x.dtsi b/arch/m68k/dts/mcf5301x.dtsi index 0891e4dfd5..f60898aa4a 100644 --- a/arch/m68k/dts/mcf5301x.dtsi +++ b/arch/m68k/dts/mcf5301x.dtsi @@ -9,6 +9,8 @@ aliases { serial0 = &uart0; spi0 = &dspi0; + fec0 = &fec0; + fec1 = &fec1; };
soc { @@ -44,5 +46,24 @@ spi-mode = <0>; status = "disabled"; }; + + fec0: ethernet@fc030000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc030000 0x200>; + mii-base = <0>; + max-speed = <100>; + phy-addr = <(-1)>; + timeout-loop = <50000>; + status = "disabled"; + }; + + fec1: ethernet@fc034000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc034000 0x800>; + mii-base = <1>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/mcf5329.dtsi b/arch/m68k/dts/mcf5329.dtsi index aeaa6430af..de348968b5 100644 --- a/arch/m68k/dts/mcf5329.dtsi +++ b/arch/m68k/dts/mcf5329.dtsi @@ -8,6 +8,7 @@
aliases { serial0 = &uart0; + fec0 = &fec0; };
soc { @@ -32,5 +33,14 @@ reg = <0xfc068000 0x40>; status = "disabled"; }; + + fec0: ethernet@fc030000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc030000 0x800>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/mcf537x.dtsi b/arch/m68k/dts/mcf537x.dtsi index aeaa6430af..2a2a32a59b 100644 --- a/arch/m68k/dts/mcf537x.dtsi +++ b/arch/m68k/dts/mcf537x.dtsi @@ -8,6 +8,7 @@
aliases { serial0 = &uart0; + fec0 = &fec0; };
soc { @@ -32,5 +33,14 @@ reg = <0xfc068000 0x40>; status = "disabled"; }; + + fec0: ethernet@fc030000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc030000 0x400>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi index 71b392adc3..6769bdc270 100644 --- a/arch/m68k/dts/mcf5441x.dtsi +++ b/arch/m68k/dts/mcf5441x.dtsi @@ -9,6 +9,8 @@ aliases { serial0 = &uart0; spi0 = &dspi0; + fec0 = &fec0; + fec1 = &fec1; };
soc { @@ -83,5 +85,23 @@ spi-mode = <0>; status = "disabled"; }; + + fec0: ethernet@fc0d4000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc0d4000 0x4000>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; + + fec1: ethernet@fc0d8000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc0d8000 0x4000>; + mii-base = <1>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi index ccbee29a6c..b7ecc99c09 100644 --- a/arch/m68k/dts/mcf5445x.dtsi +++ b/arch/m68k/dts/mcf5445x.dtsi @@ -9,6 +9,8 @@ aliases { serial0 = &uart0; spi0 = &dspi0; + fec0 = &fec0; + fec1 = &fec1; };
soc { @@ -44,5 +46,23 @@ spi-mode = <0>; status = "disabled"; }; + + fec0: ethernet@fc030000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc030000 0x4000>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; + + fec1: ethernet@fc034000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc034000 0x4000>; + mii-base = <1>; + max-speed = <100>; + timeout-loop = <50000>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/mcf54xx.dtsi b/arch/m68k/dts/mcf54xx.dtsi index 537bb424f3..e9cebb9f74 100644 --- a/arch/m68k/dts/mcf54xx.dtsi +++ b/arch/m68k/dts/mcf54xx.dtsi @@ -11,6 +11,8 @@ * no UARTS. */ spi0 = &dspi0; + fec0 = &fec0; + fec1 = &fec1; };
soc { @@ -35,6 +37,36 @@ spi-mode = <0>; status = "disabled"; }; + + fec0: ethernet@9000 { + compatible = "fsl,mcf-dma-fec"; + reg = <0x9000 0x800>; + mii-base = <0>; + max-speed = <100>; + timeout-loop = <50000>; + rx-task = <0>; + tx-task = <1>; + rx-piority = <6>; + tx-piority = <7>; + rx-init = <16>; + tx-init = <17>; + status = "disabled"; + }; + + fec1: ethernet@9800 { + compatible = "fsl,mcf-dma-fec"; + reg = <0x9800 0x800>; + mii-base = <1>; + max-speed = <100>; + timeout-loop = <50000>; + rx-task = <2>; + tx-task = <3>; + rx-piority = <6>; + tx-piority = <7>; + rx-init = <30>; + tx-init = <31>; + status = "disabled"; + }; }; }; };
From: Angelo Durgehello angelo.dureghello@timesys.com
Add ethernet controller overrides for all involved boards.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com --- arch/m68k/dts/M5208EVBE.dts | 3 +++ arch/m68k/dts/M5235EVB.dts | 3 +++ arch/m68k/dts/M5235EVB_Flash32.dts | 3 +++ arch/m68k/dts/M5272C3.dts | 3 +++ arch/m68k/dts/M5275EVB.dts | 7 +++++++ arch/m68k/dts/M5282EVB.dts | 3 +++ arch/m68k/dts/M53017EVB.dts | 7 +++++++ arch/m68k/dts/M5329AFEE.dts | 3 +++ arch/m68k/dts/M5329BFEE.dts | 3 +++ arch/m68k/dts/M5373EVB.dts | 3 +++ arch/m68k/dts/M54418TWR.dts | 9 +++++++++ arch/m68k/dts/M54418TWR_nand_mii.dts | 9 +++++++++ arch/m68k/dts/M54418TWR_nand_rmii.dts | 9 +++++++++ arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts | 9 +++++++++ arch/m68k/dts/M54418TWR_serial_mii.dts | 9 +++++++++ arch/m68k/dts/M54418TWR_serial_rmii.dts | 9 +++++++++ arch/m68k/dts/M54451EVB.dts | 8 ++++++++ arch/m68k/dts/M54451EVB_stmicro.dts | 8 ++++++++ arch/m68k/dts/M54455EVB.dts | 9 +++++++++ arch/m68k/dts/M54455EVB_a66.dts | 9 +++++++++ arch/m68k/dts/M54455EVB_i66.dts | 9 +++++++++ arch/m68k/dts/M54455EVB_intel.dts | 8 ++++++++ arch/m68k/dts/M54455EVB_stm33.dts | 9 +++++++++ arch/m68k/dts/M5475AFE.dts | 8 ++++++++ arch/m68k/dts/M5475BFE.dts | 8 ++++++++ arch/m68k/dts/M5475CFE.dts | 8 ++++++++ arch/m68k/dts/M5475DFE.dts | 8 ++++++++ arch/m68k/dts/M5475EFE.dts | 8 ++++++++ arch/m68k/dts/M5475FFE.dts | 8 ++++++++ arch/m68k/dts/M5475GFE.dts | 8 ++++++++ arch/m68k/dts/M5485AFE.dts | 8 ++++++++ arch/m68k/dts/M5485BFE.dts | 8 ++++++++ arch/m68k/dts/M5485CFE.dts | 8 ++++++++ arch/m68k/dts/M5485DFE.dts | 8 ++++++++ arch/m68k/dts/M5485EFE.dts | 8 ++++++++ arch/m68k/dts/M5485FFE.dts | 8 ++++++++ arch/m68k/dts/M5485GFE.dts | 8 ++++++++ arch/m68k/dts/M5485HFE.dts | 8 ++++++++ arch/m68k/dts/cobra5272.dts | 3 +++ arch/m68k/dts/eb_cpu5282.dts | 3 +++ arch/m68k/dts/eb_cpu5282_internal.dts | 3 +++ arch/m68k/dts/stmark2.dts | 9 +++++++++ 42 files changed, 290 insertions(+)
diff --git a/arch/m68k/dts/M5208EVBE.dts b/arch/m68k/dts/M5208EVBE.dts index e78513f3b8..3e5a698861 100644 --- a/arch/m68k/dts/M5208EVBE.dts +++ b/arch/m68k/dts/M5208EVBE.dts @@ -20,3 +20,6 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M5235EVB.dts b/arch/m68k/dts/M5235EVB.dts index 1a32539323..b170b7bd03 100644 --- a/arch/m68k/dts/M5235EVB.dts +++ b/arch/m68k/dts/M5235EVB.dts @@ -20,3 +20,6 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M5235EVB_Flash32.dts b/arch/m68k/dts/M5235EVB_Flash32.dts index fcbffb23f5..497d824541 100644 --- a/arch/m68k/dts/M5235EVB_Flash32.dts +++ b/arch/m68k/dts/M5235EVB_Flash32.dts @@ -20,3 +20,6 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M5272C3.dts b/arch/m68k/dts/M5272C3.dts index 6efb8a4cc5..0ecf1e7429 100644 --- a/arch/m68k/dts/M5272C3.dts +++ b/arch/m68k/dts/M5272C3.dts @@ -20,3 +20,6 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M5275EVB.dts b/arch/m68k/dts/M5275EVB.dts index cd9eb7d145..f0f573c08c 100644 --- a/arch/m68k/dts/M5275EVB.dts +++ b/arch/m68k/dts/M5275EVB.dts @@ -20,3 +20,10 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M5282EVB.dts b/arch/m68k/dts/M5282EVB.dts index 9527caafc2..9b506635b9 100644 --- a/arch/m68k/dts/M5282EVB.dts +++ b/arch/m68k/dts/M5282EVB.dts @@ -20,3 +20,6 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M53017EVB.dts b/arch/m68k/dts/M53017EVB.dts index b267488e0f..401318ddf9 100644 --- a/arch/m68k/dts/M53017EVB.dts +++ b/arch/m68k/dts/M53017EVB.dts @@ -20,3 +20,10 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M5329AFEE.dts b/arch/m68k/dts/M5329AFEE.dts index 7d121d68e7..ab009c5605 100644 --- a/arch/m68k/dts/M5329AFEE.dts +++ b/arch/m68k/dts/M5329AFEE.dts @@ -20,3 +20,6 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M5329BFEE.dts b/arch/m68k/dts/M5329BFEE.dts index cd087b6ea6..7e73ab9c66 100644 --- a/arch/m68k/dts/M5329BFEE.dts +++ b/arch/m68k/dts/M5329BFEE.dts @@ -20,3 +20,6 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M5373EVB.dts b/arch/m68k/dts/M5373EVB.dts index 930f911d4a..4e1b7aeb77 100644 --- a/arch/m68k/dts/M5373EVB.dts +++ b/arch/m68k/dts/M5373EVB.dts @@ -20,3 +20,6 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54418TWR.dts b/arch/m68k/dts/M54418TWR.dts index 7765c7abbb..058707fdf0 100644 --- a/arch/m68k/dts/M54418TWR.dts +++ b/arch/m68k/dts/M54418TWR.dts @@ -23,3 +23,12 @@ &dspi0 { status = "okay"; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M54418TWR_nand_mii.dts b/arch/m68k/dts/M54418TWR_nand_mii.dts index 9b1cb85325..8afcb0fb99 100644 --- a/arch/m68k/dts/M54418TWR_nand_mii.dts +++ b/arch/m68k/dts/M54418TWR_nand_mii.dts @@ -23,3 +23,12 @@ &dspi0 { status = "okay"; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M54418TWR_nand_rmii.dts b/arch/m68k/dts/M54418TWR_nand_rmii.dts index 824a66af48..fc2eb5b3bc 100644 --- a/arch/m68k/dts/M54418TWR_nand_rmii.dts +++ b/arch/m68k/dts/M54418TWR_nand_rmii.dts @@ -23,3 +23,12 @@ &dspi0 { status = "okay"; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts index 74fa197ea9..a39d1023b2 100644 --- a/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts +++ b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts @@ -23,3 +23,12 @@ &dspi0 { status = "okay"; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M54418TWR_serial_mii.dts b/arch/m68k/dts/M54418TWR_serial_mii.dts index 22f27b5612..edf98db003 100644 --- a/arch/m68k/dts/M54418TWR_serial_mii.dts +++ b/arch/m68k/dts/M54418TWR_serial_mii.dts @@ -23,3 +23,12 @@ &dspi0 { status = "okay"; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M54418TWR_serial_rmii.dts b/arch/m68k/dts/M54418TWR_serial_rmii.dts index 0ddefd9da2..e4639fe431 100644 --- a/arch/m68k/dts/M54418TWR_serial_rmii.dts +++ b/arch/m68k/dts/M54418TWR_serial_rmii.dts @@ -23,3 +23,12 @@ &dspi0 { status = "okay"; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M54451EVB.dts b/arch/m68k/dts/M54451EVB.dts index b57bfea2cb..b81d37a938 100644 --- a/arch/m68k/dts/M54451EVB.dts +++ b/arch/m68k/dts/M54451EVB.dts @@ -23,3 +23,11 @@ &dspi0 { status = "okay"; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54451EVB_stmicro.dts b/arch/m68k/dts/M54451EVB_stmicro.dts index 9a088e16d0..6645b58065 100644 --- a/arch/m68k/dts/M54451EVB_stmicro.dts +++ b/arch/m68k/dts/M54451EVB_stmicro.dts @@ -23,3 +23,11 @@ &dspi0 { status = "okay"; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54455EVB.dts b/arch/m68k/dts/M54455EVB.dts index dd11181033..b0ffb5144d 100644 --- a/arch/m68k/dts/M54455EVB.dts +++ b/arch/m68k/dts/M54455EVB.dts @@ -23,3 +23,12 @@ &dspi0 { status = "okay"; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M54455EVB_a66.dts b/arch/m68k/dts/M54455EVB_a66.dts index 70d544b72d..c2557bd2e6 100644 --- a/arch/m68k/dts/M54455EVB_a66.dts +++ b/arch/m68k/dts/M54455EVB_a66.dts @@ -23,3 +23,12 @@ &dspi0 { status = "okay"; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M54455EVB_i66.dts b/arch/m68k/dts/M54455EVB_i66.dts index b37a87213f..3c9161bfae 100644 --- a/arch/m68k/dts/M54455EVB_i66.dts +++ b/arch/m68k/dts/M54455EVB_i66.dts @@ -23,3 +23,12 @@ &dspi0 { status = "okay"; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M54455EVB_intel.dts b/arch/m68k/dts/M54455EVB_intel.dts index c92228fc8b..54209d25a7 100644 --- a/arch/m68k/dts/M54455EVB_intel.dts +++ b/arch/m68k/dts/M54455EVB_intel.dts @@ -24,3 +24,11 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M54455EVB_stm33.dts b/arch/m68k/dts/M54455EVB_stm33.dts index 9e467f94a1..701b9a719b 100644 --- a/arch/m68k/dts/M54455EVB_stm33.dts +++ b/arch/m68k/dts/M54455EVB_stm33.dts @@ -23,3 +23,12 @@ &dspi0 { status = "okay"; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5475AFE.dts b/arch/m68k/dts/M5475AFE.dts index 0c0a79befa..7895b520cf 100644 --- a/arch/m68k/dts/M5475AFE.dts +++ b/arch/m68k/dts/M5475AFE.dts @@ -11,3 +11,11 @@ compatible = "fsl,M5475AFE"; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5475BFE.dts b/arch/m68k/dts/M5475BFE.dts index c4d14097cd..ffbc2d6a06 100644 --- a/arch/m68k/dts/M5475BFE.dts +++ b/arch/m68k/dts/M5475BFE.dts @@ -11,3 +11,11 @@ compatible = "fsl,M5475BFE"; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5475CFE.dts b/arch/m68k/dts/M5475CFE.dts index 4c92c332ba..f1033f7efb 100644 --- a/arch/m68k/dts/M5475CFE.dts +++ b/arch/m68k/dts/M5475CFE.dts @@ -11,3 +11,11 @@ compatible = "fsl,M5475CFE"; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5475DFE.dts b/arch/m68k/dts/M5475DFE.dts index c41c1b3c12..69a8faba83 100644 --- a/arch/m68k/dts/M5475DFE.dts +++ b/arch/m68k/dts/M5475DFE.dts @@ -11,3 +11,11 @@ compatible = "fsl,M5475DFE"; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5475EFE.dts b/arch/m68k/dts/M5475EFE.dts index 5a920b241a..3c898958c8 100644 --- a/arch/m68k/dts/M5475EFE.dts +++ b/arch/m68k/dts/M5475EFE.dts @@ -11,3 +11,11 @@ compatible = "fsl,M5475EFE"; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5475FFE.dts b/arch/m68k/dts/M5475FFE.dts index d312a6ae8d..bb3c21588f 100644 --- a/arch/m68k/dts/M5475FFE.dts +++ b/arch/m68k/dts/M5475FFE.dts @@ -11,3 +11,11 @@ compatible = "fsl,M5475FFE"; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5475GFE.dts b/arch/m68k/dts/M5475GFE.dts index 9e794dafa6..75080fa737 100644 --- a/arch/m68k/dts/M5475GFE.dts +++ b/arch/m68k/dts/M5475GFE.dts @@ -11,3 +11,11 @@ compatible = "fsl,M5475GFE"; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5485AFE.dts b/arch/m68k/dts/M5485AFE.dts index 3466751174..b1f5bf0f56 100644 --- a/arch/m68k/dts/M5485AFE.dts +++ b/arch/m68k/dts/M5485AFE.dts @@ -15,3 +15,11 @@ }; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5485BFE.dts b/arch/m68k/dts/M5485BFE.dts index 6d48795a4d..10b8f5b201 100644 --- a/arch/m68k/dts/M5485BFE.dts +++ b/arch/m68k/dts/M5485BFE.dts @@ -15,3 +15,11 @@ }; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5485CFE.dts b/arch/m68k/dts/M5485CFE.dts index d1a7d9d383..a1ae64f65c 100644 --- a/arch/m68k/dts/M5485CFE.dts +++ b/arch/m68k/dts/M5485CFE.dts @@ -15,3 +15,11 @@ }; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5485DFE.dts b/arch/m68k/dts/M5485DFE.dts index 7c362e26e5..9b38d451fc 100644 --- a/arch/m68k/dts/M5485DFE.dts +++ b/arch/m68k/dts/M5485DFE.dts @@ -15,3 +15,11 @@ }; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5485EFE.dts b/arch/m68k/dts/M5485EFE.dts index 4c688dce2b..a1ac3f5a48 100644 --- a/arch/m68k/dts/M5485EFE.dts +++ b/arch/m68k/dts/M5485EFE.dts @@ -15,3 +15,11 @@ }; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5485FFE.dts b/arch/m68k/dts/M5485FFE.dts index 87ec2c543d..7f22de49f4 100644 --- a/arch/m68k/dts/M5485FFE.dts +++ b/arch/m68k/dts/M5485FFE.dts @@ -15,3 +15,11 @@ }; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5485GFE.dts b/arch/m68k/dts/M5485GFE.dts index 9f67e5516b..3430aa7279 100644 --- a/arch/m68k/dts/M5485GFE.dts +++ b/arch/m68k/dts/M5485GFE.dts @@ -15,3 +15,11 @@ }; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/M5485HFE.dts b/arch/m68k/dts/M5485HFE.dts index 2eb2213d78..57c98f1ef7 100644 --- a/arch/m68k/dts/M5485HFE.dts +++ b/arch/m68k/dts/M5485HFE.dts @@ -15,3 +15,11 @@ }; };
+&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +}; diff --git a/arch/m68k/dts/cobra5272.dts b/arch/m68k/dts/cobra5272.dts index f3b74975de..6085eee5b3 100644 --- a/arch/m68k/dts/cobra5272.dts +++ b/arch/m68k/dts/cobra5272.dts @@ -20,3 +20,6 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/eb_cpu5282.dts b/arch/m68k/dts/eb_cpu5282.dts index 4641e9cb56..655c4ecf5a 100644 --- a/arch/m68k/dts/eb_cpu5282.dts +++ b/arch/m68k/dts/eb_cpu5282.dts @@ -20,3 +20,6 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/eb_cpu5282_internal.dts b/arch/m68k/dts/eb_cpu5282_internal.dts index 0acb7935f4..f5a044d7cc 100644 --- a/arch/m68k/dts/eb_cpu5282_internal.dts +++ b/arch/m68k/dts/eb_cpu5282_internal.dts @@ -20,3 +20,6 @@ status = "okay"; };
+&fec0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/stmark2.dts b/arch/m68k/dts/stmark2.dts index fd8ce4fa35..306b56d679 100644 --- a/arch/m68k/dts/stmark2.dts +++ b/arch/m68k/dts/stmark2.dts @@ -32,3 +32,12 @@ reg = <1>; }; }; + +&fec0 { + status = "okay"; +}; + +&fec1 { + status = "okay"; + mii-base = <0>; +};
On Fri, Nov 15, 2019 at 11:54:13PM +0100, Angelo Dureghello wrote:
From: Angelo Durgehello angelo.dureghello@timesys.com
Add ethernet controller overrides for all involved boards.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com
Applied to u-boot/master, thanks!
From: Angelo Durgehello angelo.dureghello@timesys.com
Add dm eth config options for all involved ColdFire-based boards.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com --- configs/M5208EVBE_defconfig | 2 ++ configs/M5235EVB_Flash32_defconfig | 2 ++ configs/M5235EVB_defconfig | 2 ++ configs/M5272C3_defconfig | 2 ++ configs/M5275EVB_defconfig | 2 ++ configs/M5282EVB_defconfig | 2 ++ configs/M53017EVB_defconfig | 2 ++ configs/M5329AFEE_defconfig | 2 ++ configs/M5329BFEE_defconfig | 2 ++ configs/M5373EVB_defconfig | 2 ++ configs/M54418TWR_defconfig | 2 ++ configs/M54418TWR_nand_mii_defconfig | 2 ++ configs/M54418TWR_nand_rmii_defconfig | 2 ++ configs/M54418TWR_nand_rmii_lowfreq_defconfig | 2 ++ configs/M54418TWR_serial_mii_defconfig | 2 ++ configs/M54418TWR_serial_rmii_defconfig | 2 ++ configs/M54451EVB_defconfig | 2 ++ configs/M54451EVB_stmicro_defconfig | 2 ++ configs/M54455EVB_a66_defconfig | 2 ++ configs/M54455EVB_defconfig | 2 ++ configs/M54455EVB_i66_defconfig | 2 ++ configs/M54455EVB_intel_defconfig | 2 ++ configs/M54455EVB_stm33_defconfig | 2 ++ configs/M5475AFE_defconfig | 3 +++ configs/M5475BFE_defconfig | 3 +++ configs/M5475CFE_defconfig | 3 +++ configs/M5475DFE_defconfig | 3 +++ configs/M5475EFE_defconfig | 3 +++ configs/M5475FFE_defconfig | 3 +++ configs/M5475GFE_defconfig | 3 +++ configs/M5485AFE_defconfig | 3 +++ configs/M5485BFE_defconfig | 3 +++ configs/M5485CFE_defconfig | 3 +++ configs/M5485DFE_defconfig | 3 +++ configs/M5485EFE_defconfig | 3 +++ configs/M5485FFE_defconfig | 3 +++ configs/M5485GFE_defconfig | 3 +++ configs/M5485HFE_defconfig | 3 +++ configs/cobra5272_defconfig | 2 ++ configs/eb_cpu5282_defconfig | 2 ++ configs/eb_cpu5282_internal_defconfig | 2 ++ configs/stmark2_defconfig | 14 ++++++++------ 42 files changed, 105 insertions(+), 6 deletions(-)
diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index 9b5d35cd55..30091f3653 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -17,4 +17,6 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index 2e40b21d76..8aa7c9d456 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -22,4 +22,6 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index fd5dd984be..bc8f13ad07 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -22,4 +22,6 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index c39876d89c..b87676588b 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -18,4 +18,6 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index ecb3e32070..7f0f00928b 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -19,4 +19,6 @@ CONFIG_DEFAULT_DEVICE_TREE="M5275EVB" CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index 731fb1ec68..2dff7d957f 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -18,4 +18,6 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 92dfd0256d..69253a097f 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -21,4 +21,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index 20acb64b1a..88930d38b8 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -20,4 +20,6 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index 96c57ec9db..7be13ae8b6 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -20,4 +20,6 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index ef66d7ca00..97d7889cba 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -20,4 +20,6 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig index 08af6f2e45..d099aaf084 100644 --- a/configs/M54418TWR_defconfig +++ b/configs/M54418TWR_defconfig @@ -25,6 +25,8 @@ CONFIG_USE_ENV_SPI_CS=y CONFIG_ENV_SPI_CS=1 CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig index 6fa822d790..b4b95a57ad 100644 --- a/configs/M54418TWR_nand_mii_defconfig +++ b/configs/M54418TWR_nand_mii_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_CACHE=y CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_mii" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig index 1fa7b38828..0097285d06 100644 --- a/configs/M54418TWR_nand_rmii_defconfig +++ b/configs/M54418TWR_nand_rmii_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_CACHE=y CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig index 5208e598f4..cde5878d57 100644 --- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig +++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_CACHE=y CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii_lowfreq" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig index 131fd3a856..131a5b95cc 100644 --- a/configs/M54418TWR_serial_mii_defconfig +++ b/configs/M54418TWR_serial_mii_defconfig @@ -25,6 +25,8 @@ CONFIG_USE_ENV_SPI_CS=y CONFIG_ENV_SPI_CS=1 CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig index fd561f3d25..94b110db40 100644 --- a/configs/M54418TWR_serial_rmii_defconfig +++ b/configs/M54418TWR_serial_rmii_defconfig @@ -25,6 +25,8 @@ CONFIG_USE_ENV_SPI_CS=y CONFIG_ENV_SPI_CS=1 CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig index f0bd93f2d9..0da365015c 100644 --- a/configs/M54451EVB_defconfig +++ b/configs/M54451EVB_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig index 144d29b902..7130b92ad2 100644 --- a/configs/M54451EVB_stmicro_defconfig +++ b/configs/M54451EVB_stmicro_defconfig @@ -30,6 +30,8 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig index ca403083f7..0301d5210e 100644 --- a/configs/M54455EVB_a66_defconfig +++ b/configs/M54455EVB_a66_defconfig @@ -33,6 +33,8 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig index 3ca2d73797..06f1726a51 100644 --- a/configs/M54455EVB_defconfig +++ b/configs/M54455EVB_defconfig @@ -34,6 +34,8 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig index 20abcd80ab..7ffba03e6a 100644 --- a/configs/M54455EVB_i66_defconfig +++ b/configs/M54455EVB_i66_defconfig @@ -33,6 +33,8 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig index a17e4fab25..a2dee1fb8e 100644 --- a/configs/M54455EVB_intel_defconfig +++ b/configs/M54455EVB_intel_defconfig @@ -33,6 +33,8 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig index c3f04645bf..f314c322b9 100644 --- a/configs/M54455EVB_stm33_defconfig +++ b/configs/M54455EVB_stm33_defconfig @@ -35,6 +35,8 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig index 368f73e9dd..6d7ee70b1e 100644 --- a/configs/M5475AFE_defconfig +++ b/configs/M5475AFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig index d44b0b267f..7cfb342441 100644 --- a/configs/M5475BFE_defconfig +++ b/configs/M5475BFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig index 108ef978a6..cd59fe06e8 100644 --- a/configs/M5475CFE_defconfig +++ b/configs/M5475CFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig index 9325db5ba6..858b12d2df 100644 --- a/configs/M5475DFE_defconfig +++ b/configs/M5475DFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig index 6873f1500c..e7842e14c0 100644 --- a/configs/M5475EFE_defconfig +++ b/configs/M5475EFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig index a98e804c41..b558de9aa8 100644 --- a/configs/M5475FFE_defconfig +++ b/configs/M5475FFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig index ed75743801..b0dab827c8 100644 --- a/configs/M5475GFE_defconfig +++ b/configs/M5475GFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig index 8f94ac99a1..e49a2fd752 100644 --- a/configs/M5485AFE_defconfig +++ b/configs/M5485AFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig index 96bd5200da..5e1756900b 100644 --- a/configs/M5485BFE_defconfig +++ b/configs/M5485BFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig index 148be33d5a..27d6f59fce 100644 --- a/configs/M5485CFE_defconfig +++ b/configs/M5485CFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig index 5facb0733d..832c118613 100644 --- a/configs/M5485DFE_defconfig +++ b/configs/M5485DFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig index ece3e115ea..83e587fde8 100644 --- a/configs/M5485EFE_defconfig +++ b/configs/M5485EFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig index c2a2d926d6..ee31e51d39 100644 --- a/configs/M5485FFE_defconfig +++ b/configs/M5485FFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig index 9cf620242a..809ece391e 100644 --- a/configs/M5485GFE_defconfig +++ b/configs/M5485GFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig index e6c9225ea9..e3e9824f1c 100644 --- a/configs/M5485HFE_defconfig +++ b/configs/M5485HFE_defconfig @@ -20,7 +20,10 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_FSLDMAFEC=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PCI=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index 8865618999..6bec2ca7b5 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -13,5 +13,7 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_PING=y CONFIG_DEFAULT_DEVICE_TREE="cobra5272" CONFIG_MTD_NOR_FLASH=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_BAUDRATE=19200 diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index daaf83a94e..c399c31d00 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -26,6 +26,8 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_VIDEO=y # CONFIG_CFB_CONSOLE is not set diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index 7bd0d30fb6..e1e9482f92 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -25,6 +25,8 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_VIDEO=y # CONFIG_CFB_CONSOLE is not set diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig index 96c6242538..4f9fb78991 100644 --- a/configs/stmark2_defconfig +++ b/configs/stmark2_defconfig @@ -2,6 +2,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_TARGET_STMARK2=y CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000" +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 rw rootfstype=ramfs rdinit=/sbin/init devtmpfs.mount=1" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set @@ -21,24 +23,24 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y -CONFIG_DOS_PARTITION=y CONFIG_MTDIDS_DEFAULT="nor0=spi-flash.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:1m(u-boot),7m(kernel),-(rootfs)" +CONFIG_DOS_PARTITION=y CONFIG_DEFAULT_DEVICE_TREE="stmark2" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_CS=y CONFIG_ENV_SPI_CS=1 -# CONFIG_NET is not set -CONFIG_MTD_DEVICE=y CONFIG_MMC=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y +CONFIG_MTD_DEVICE=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_MCFFEC=y +CONFIG_MII=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CF_SPI=y -CONFIG_REGEX=y -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 rw rootfstype=ramfs rdinit=/sbin/init devtmpfs.mount=1"
On Fri, Nov 15, 2019 at 11:54:14PM +0100, Angelo Dureghello wrote:
From: Angelo Durgehello angelo.dureghello@timesys.com
Add dm eth config options for all involved ColdFire-based boards.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com
Applied to u-boot/master, thanks!
From: Angelo Durgehello angelo.dureghello@timesys.com
Remove unneeded fec-related defines after fec moved as dm.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com --- include/configs/M5208EVBE.h | 5 ----- include/configs/M5235EVB.h | 5 ----- include/configs/M5272C3.h | 6 ------ include/configs/M5275EVB.h | 6 ------ include/configs/M5282EVB.h | 6 ------ include/configs/M53017EVB.h | 7 ------- include/configs/M5329EVB.h | 5 ----- include/configs/M5373EVB.h | 5 ----- include/configs/M54418TWR.h | 9 --------- include/configs/M54451EVB.h | 6 ------ include/configs/M54455EVB.h | 8 -------- include/configs/M5475EVB.h | 10 ---------- include/configs/M5485EVB.h | 10 ---------- include/configs/cobra5272.h | 10 ---------- include/configs/eb_cpu5282.h | 8 ++------ include/configs/stmark2.h | 15 +++++++++++++++ 16 files changed, 17 insertions(+), 104 deletions(-)
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 0a356f483e..7515a5c55f 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -19,17 +19,12 @@ #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000
-#define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_HAS_ETH1 - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index a197c3a853..6d20b0572a 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -29,16 +29,11 @@ */ #define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 9d3bf42974..4ddc9d426c 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -49,17 +49,11 @@ /* * Command line configuration. */ - -#define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 682e2e3979..7717c774b9 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -48,17 +48,11 @@
/* Available command configuration */
-#define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC #define CONFIG_MII_INIT 1 #define CONFIG_SYS_DISCOVER_PHY #define CONFIG_SYS_RX_ETH_BUFFER 8 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_SYS_FEC0_PINMUX 0 -#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -#define CONFIG_SYS_FEC1_PINMUX 0 -#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE -#define MCFFEC_TOUT_LOOP 50000 #define CONFIG_HAS_ETH1 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ #ifndef CONFIG_SYS_DISCOVER_PHY diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index a068726681..667e81f8e0 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -41,17 +41,11 @@ /* * Command line configuration. */ - -#define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 39e2748373..b31866b3fe 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -26,7 +26,6 @@
#define CONFIG_SYS_UNIFY_CACHE
-#define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY @@ -36,12 +35,6 @@ # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_HAS_ETH1
-# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define CONFIG_SYS_FEC1_PINMUX 0 -# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE -# define MCFFEC_TOUT_LOOP 50000 - /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 7a96dd1b71..916d12fc90 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -26,16 +26,11 @@
#define CONFIG_SYS_UNIFY_CACHE
-#define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index f62fb5ac63..83468a55d2 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -26,16 +26,11 @@
#define CONFIG_SYS_UNIFY_CACHE
-#define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index e07684d820..3071f58760 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -46,7 +46,6 @@ #endif
/* Network configuration */ -#define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC #define CONFIG_MII_INIT 1 #define CONFIG_SYS_DISCOVER_PHY @@ -55,14 +54,6 @@ #define CONFIG_SYS_TX_ETH_BUFFER 2 #define CONFIG_HAS_ETH1
-#define CONFIG_SYS_FEC0_PINMUX 0 -#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -#define CONFIG_SYS_FEC1_PINMUX 0 -#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE -#define MCFFEC_TOUT_LOOP 50000 -#define CONFIG_SYS_FEC0_PHYADDR 0 -#define CONFIG_SYS_FEC1_PHYADDR 1 - #define CONFIG_ETHPRIME "FEC0" #define CONFIG_IPADDR 192.168.1.2 #define CONFIG_NETMASK 255.255.255.0 diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 2bd0e62231..baa21933e7 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -34,17 +34,11 @@ #define CONFIG_BOOTP_BOOTFILESIZE
/* Network configuration */ -#define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 - # define CONFIG_ETHPRIME "FEC0" # define CONFIG_IPADDR 192.162.1.2 # define CONFIG_NETMASK 255.255.255.0 diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index d73101f96c..92c481e982 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -34,20 +34,12 @@ #define CONFIG_BOOTP_BOOTFILESIZE
/* Network configuration */ -#define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC1_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 # define CONFIG_HAS_ETH1 - # define CONFIG_ETHPRIME "FEC0" # define CONFIG_IPADDR 192.162.1.2 # define CONFIG_NETMASK 255.255.255.0 diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index 7cc09ab7cc..69045ebd1b 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -26,23 +26,14 @@
#define CONFIG_SLTTMR
-#define CONFIG_FSLDMAFEC #ifdef CONFIG_FSLDMAFEC # define CONFIG_MII_INIT 1 # define CONFIG_HAS_ETH1 - # define CONFIG_SYS_DMA_USE_INTSRAM 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 32 # define CONFIG_SYS_TX_ETH_BUFFER 48 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define CONFIG_SYS_FEC1_PINMUX 0 -# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE - -# define MCFFEC_TOUT_LOOP 50000 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY # define FECDUPLEX FULL @@ -57,7 +48,6 @@ # define CONFIG_NETMASK 255.255.255.0 # define CONFIG_SERVERIP 192.162.1.1 # define CONFIG_GATEWAYIP 192.162.1.1 - #endif
#ifdef CONFIG_CMD_USB diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 3f5ced28ec..2c2befcfea 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -26,23 +26,14 @@
#define CONFIG_SLTTMR
-#define CONFIG_FSLDMAFEC #ifdef CONFIG_FSLDMAFEC # define CONFIG_MII_INIT 1 # define CONFIG_HAS_ETH1 - # define CONFIG_SYS_DMA_USE_INTSRAM 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 32 # define CONFIG_SYS_TX_ETH_BUFFER 48 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define CONFIG_SYS_FEC1_PINMUX 0 -# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE - -# define MCFFEC_TOUT_LOOP 50000 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY # define FECDUPLEX FULL @@ -57,7 +48,6 @@ # define CONFIG_NETMASK 255.255.255.0 # define CONFIG_SERVERIP 192.162.1.1 # define CONFIG_GATEWAYIP 192.162.1.1 - #endif
#ifdef CONFIG_CMD_USB diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 337c875655..f344baa2c0 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -32,12 +32,6 @@ #define CONFIG_SYS_CLK 66000000 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-/* --- - * Enable use of Ethernet - * --- - */ -#define CONFIG_MCFFEC - /* Enable Dma Timer */ #define CONFIG_MCFTMR
@@ -118,10 +112,6 @@ # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index e266e1f542..e32ed41909 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -76,17 +76,13 @@ * Network * *----------------------------------------------------------------------*/
-#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC #define CONFIG_MII_INIT 1 #define CONFIG_SYS_DISCOVER_PHY #define CONFIG_SYS_RX_ETH_BUFFER 8 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -#define CONFIG_SYS_FEC0_PINMUX 0 -#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -#define MCFFEC_TOUT_LOOP 50000 - #define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif
/*------------------------------------------------------------------------- * Low Level Configuration Settings diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index f02c10c59c..df48fd5f68 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -169,4 +169,19 @@ #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 12)
+#ifdef CONFIG_MCFFEC +#define CONFIG_MII_INIT 1 +#define CONFIG_SYS_DISCOVER_PHY +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +#ifndef CONFIG_SYS_DISCOVER_PHY +#define FECDUPLEX FULL +#define FECSPEED _100BASET +#else +#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#endif +#endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif #endif /* __STMARK2_CONFIG_H */
On Fri, Nov 15, 2019 at 11:54:15PM +0100, Angelo Dureghello wrote:
From: Angelo Durgehello angelo.dureghello@timesys.com
Remove unneeded fec-related defines after fec moved as dm.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com
Applied to u-boot/master, thanks!
From: Angelo Durgehello angelo.dureghello@timesys.com
Add architecture-related code for dm fec support.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com --- arch/m68k/cpu/mcf523x/cpu_init.c | 2 +- arch/m68k/cpu/mcf52x2/cpu_init.c | 19 ++++--- arch/m68k/cpu/mcf532x/cpu.c | 1 - arch/m68k/cpu/mcf532x/cpu_init.c | 21 +++++--- arch/m68k/cpu/mcf5445x/cpu_init.c | 16 +++--- arch/m68k/cpu/mcf547x_8x/cpu_init.c | 12 +++-- arch/m68k/include/asm/fec.h | 21 ++++++-- arch/m68k/include/asm/fsl_mcdmafec.h | 23 ++++---- arch/m68k/lib/Makefile | 1 + arch/m68k/lib/fec.c | 79 ++++++++++++++++++++++++++++ 10 files changed, 151 insertions(+), 44 deletions(-) create mode 100644 arch/m68k/lib/fec.c
diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c index 339fbeb429..a6eff09bf8 100644 --- a/arch/m68k/cpu/mcf523x/cpu_init.c +++ b/arch/m68k/cpu/mcf523x/cpu_init.c @@ -156,7 +156,7 @@ void uart_port_conf(int port) }
#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) +int fecpin_setclear(fec_info_t *info, int setclear) { gpio_t *gpio = (gpio_t *) MMAP_GPIO;
diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c index f4a3872667..2aac29d162 100644 --- a/arch/m68k/cpu/mcf52x2/cpu_init.c +++ b/arch/m68k/cpu/mcf52x2/cpu_init.c @@ -157,7 +157,7 @@ void uart_port_conf(int port) }
#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) +int fecpin_setclear(fec_info_t *info, int setclear) { gpio_t *gpio = (gpio_t *) MMAP_GPIO;
@@ -304,7 +304,7 @@ void uart_port_conf(int port) }
#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) +int fecpin_setclear(fec_info_t *info, int setclear) { if (setclear) { /* Enable Ethernet pins */ @@ -425,7 +425,7 @@ void uart_port_conf(int port) }
#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) +int fecpin_setclear(fec_info_t *info, int setclear) { gpio_t *gpio = (gpio_t *) MMAP_GPIO;
@@ -508,14 +508,17 @@ void uart_port_conf(int port) }
#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) +int fecpin_setclear(fec_info_t *info, int setclear) { - struct fec_info_s *info = (struct fec_info_s *) dev->priv; gpio_t *gpio = (gpio_t *)MMAP_GPIO; + u32 fec0_base; + + if (fec_get_base_addr(0, &fec0_base)) + return -1;
if (setclear) { /* Enable Ethernet pins */ - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + if (info->iobase == fec0_base) { setbits_be16(&gpio->par_feci2c, 0x0f00); setbits_8(&gpio->par_fec0hl, 0xc0); } else { @@ -523,7 +526,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear) setbits_8(&gpio->par_fec1hl, 0xc0); } } else { - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + if (info->iobase == fec0_base) { clrbits_be16(&gpio->par_feci2c, 0x0f00); clrbits_8(&gpio->par_fec0hl, 0xc0); } else { @@ -643,7 +646,7 @@ void uart_port_conf(int port) }
#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) +int fecpin_setclear(fec_info_t *info, int setclear) { if (setclear) { MCFGPIO_PASPAR |= 0x0F00; diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c index a01b5e65a7..fdc34dd16f 100644 --- a/arch/m68k/cpu/mcf532x/cpu.c +++ b/arch/m68k/cpu/mcf532x/cpu.c @@ -145,7 +145,6 @@ int watchdog_init(void) * create a board-specific function called: * int board_eth_init(bd_t *bis) */ - int cpu_eth_init(bd_t *bis) { return mcffec_initialize(bis); diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c index cbf840f76e..65882bc9d1 100644 --- a/arch/m68k/cpu/mcf532x/cpu_init.c +++ b/arch/m68k/cpu/mcf532x/cpu_init.c @@ -13,7 +13,7 @@ #include <asm/immap.h> #include <asm/io.h>
-#if defined(CONFIG_CMD_NET) +#if defined(CONFIG_MCFFEC) #include <config.h> #include <net.h> #include <asm/fec.h> @@ -93,6 +93,7 @@ void cpu_init_f(void) int cpu_init_r(void) { #ifdef CONFIG_MCFFEC + u32 fec_mii_base0, fec_mii_base1; ccm_t *ccm = (ccm_t *) MMAP_CCM; #endif #ifdef CONFIG_MCFRTC @@ -104,7 +105,10 @@ int cpu_init_r(void)
#endif #ifdef CONFIG_MCFFEC - if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE) + fec_get_mii_base(0, &fec_mii_base0); + fec_get_mii_base(1, &fec_mii_base1); + + if (fec_mii_base0 != fec_mii_base1) setbits_be16(&ccm->misccr, CCM_MISCCR_FECM); else clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM); @@ -167,13 +171,16 @@ void uart_port_conf(int port) }
#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) +int fecpin_setclear(fec_info_t *info, int setclear) { gpio_t *gpio = (gpio_t *) MMAP_GPIO; - struct fec_info_s *info = (struct fec_info_s *)dev->priv; + u32 fec0_base; + + if (fec_get_base_addr(0, &fec0_base)) + return -1;
if (setclear) { - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + if (info->iobase == fec0_base) { setbits_8(&gpio->par_fec, GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); setbits_8(&gpio->par_feci2c, @@ -185,7 +192,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear) GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1); } } else { - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + if (info->iobase == fec0_base) { clrbits_8(&gpio->par_fec, GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK); @@ -328,7 +335,7 @@ void uart_port_conf(int port) }
#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) +int fecpin_setclear(fec_info_t *info, int setclear) { gpio_t *gpio = (gpio_t *) MMAP_GPIO;
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 134510b00f..76a7a3e475 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -401,15 +401,18 @@ void uart_port_conf(int port) }
#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) +int fecpin_setclear(fec_info_t *info, int setclear) { gpio_t *gpio = (gpio_t *) MMAP_GPIO; -#ifdef CONFIG_MCF5445x - struct fec_info_s *info = (struct fec_info_s *)dev->priv; + u32 fec0_base; + + if (fec_get_base_addr(0, &fec0_base)) + return -1;
+#ifdef CONFIG_MCF5445x if (setclear) { #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) + if (info->iobase == fec0_base) setbits_be16(&gpio->par_feci2c, GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); @@ -422,7 +425,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear) GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); #endif
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) + if (info->iobase == fec0_base) setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO); else setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA); @@ -430,7 +433,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear) clrbits_be16(&gpio->par_feci2c, GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + if (info->iobase == fec0_base) { #ifdef CONFIG_SYS_FEC_FULL_MII setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII); #else @@ -462,4 +465,3 @@ int fecpin_setclear(struct eth_device *dev, int setclear) return 0; } #endif - diff --git a/arch/m68k/cpu/mcf547x_8x/cpu_init.c b/arch/m68k/cpu/mcf547x_8x/cpu_init.c index 81ffc6c094..0a83c16c27 100644 --- a/arch/m68k/cpu/mcf547x_8x/cpu_init.c +++ b/arch/m68k/cpu/mcf547x_8x/cpu_init.c @@ -16,6 +16,7 @@ #if defined(CONFIG_CMD_NET) #include <config.h> #include <net.h> +#include <asm/fec.h> #include <asm/fsl_mcdmafec.h> #endif
@@ -123,18 +124,21 @@ void uart_port_conf(int port) }
#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) +int fecpin_setclear(fec_info_t *info, int setclear) { gpio_t *gpio = (gpio_t *) MMAP_GPIO; - struct fec_info_dma *info = (struct fec_info_dma *)dev->priv; + u32 fec0_base; + + if (fec_get_base_addr(0, &fec0_base)) + return -1;
if (setclear) { - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) + if (info->iobase == fec0_base) setbits_be16(&gpio->par_feci2cirq, 0xf000); else setbits_be16(&gpio->par_feci2cirq, 0x0fc0); } else { - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) + if (info->iobase == fec0_base) clrbits_be16(&gpio->par_feci2cirq, 0xf000); else clrbits_be16(&gpio->par_feci2cirq, 0x0fc0); diff --git a/arch/m68k/include/asm/fec.h b/arch/m68k/include/asm/fec.h index 5742829c6d..cdb8119d3e 100644 --- a/arch/m68k/include/asm/fec.h +++ b/arch/m68k/include/asm/fec.h @@ -95,11 +95,12 @@ struct fec_info_s { int phyname_init; cbd_t *rxbd; /* Rx BD */ cbd_t *txbd; /* Tx BD */ - uint rxIdx; - uint txIdx; + uint rx_idx; + uint tx_idx; char *txbuf; int initialized; - struct fec_info_s *next; + int to_loop; + struct mii_dev *bus; };
#ifdef CONFIG_MCFFEC @@ -336,12 +337,22 @@ typedef struct fec { #define FEC_RESET_DELAY 100 #define FEC_RX_TOUT 100
-int fecpin_setclear(struct eth_device *dev, int setclear); +#ifdef CONFIG_MCF547x_8x +typedef struct fec_info_dma fec_info_t; +#define FEC_T fecdma_t +#else +typedef struct fec_info_s fec_info_t; +#define FEC_T fec_t +#endif + +int fecpin_setclear(fec_info_t *info, int setclear); +int mii_discover_phy(fec_info_t *info); +int fec_get_base_addr(int fec_idx, u32 *fec_iobase); +int fec_get_mii_base(int fec_idx, u32 *mii_base);
#ifdef CONFIG_SYS_DISCOVER_PHY void __mii_init(void); uint mii_send(uint mii_cmd); -int mii_discover_phy(struct eth_device *dev); int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg); int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, u16 value); diff --git a/arch/m68k/include/asm/fsl_mcdmafec.h b/arch/m68k/include/asm/fsl_mcdmafec.h index c283ad4a95..de6c548faf 100644 --- a/arch/m68k/include/asm/fsl_mcdmafec.h +++ b/arch/m68k/include/asm/fsl_mcdmafec.h @@ -72,20 +72,21 @@ struct fec_info_dma { int phyname_init; cbd_t *rxbd; /* Rx BD */ cbd_t *txbd; /* Tx BD */ - uint rxIdx; - uint txIdx; + uint rx_idx; + uint tx_idx; char *txbuf; int initialized; struct fec_info_dma *next; - - u16 rxTask; /* DMA receive Task Number */ - u16 txTask; /* DMA Transmit Task Number */ - u16 rxPri; /* DMA Receive Priority */ - u16 txPri; /* DMA Transmit Priority */ - u16 rxInit; /* DMA Receive Initiator */ - u16 txInit; /* DMA Transmit Initiator */ - u16 usedTbdIdx; /* next transmit BD to clean */ - u16 cleanTbdNum; /* the number of available transmit BDs */ + u16 rx_task; /* DMA receive Task Number */ + u16 tx_task; /* DMA Transmit Task Number */ + u16 rx_pri; /* DMA Receive Priority */ + u16 tx_pri; /* DMA Transmit Priority */ + u16 rx_init; /* DMA Receive Initiator */ + u16 tx_init; /* DMA Transmit Initiator */ + u16 used_tbd_idx; /* next transmit BD to clean */ + u16 clean_tbd_num; /* the number of available transmit BDs */ + int to_loop; + struct mii_dev *bus; };
/* Bit definitions and macros for IEVENT */ diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index 254a0a3998..a040f40eb8 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -12,3 +12,4 @@ obj-y += cache.o obj-y += interrupts.o obj-y += time.o obj-y += traps.o +obj-y += fec.o diff --git a/arch/m68k/lib/fec.c b/arch/m68k/lib/fec.c new file mode 100644 index 0000000000..dde353ad17 --- /dev/null +++ b/arch/m68k/lib/fec.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) 2019 Angelo Dureghello angelo.dureghello@timesys.com + */ + +#include <common.h> +#include <linux/libfdt.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_MCFFEC) || defined(CONFIG_FSLDMAFEC) +static int fec_get_node(int fec_idx) +{ + char fec_alias[5] = {"fec"}; + const char *path; + int node; + + if (fec_idx > 1) { + puts("Invalid MII base index"); + return -ENOENT; + } + + fec_alias[3] = fec_idx + '0'; + + path = fdt_get_alias(gd->fdt_blob, fec_alias); + if (!path) { + puts("Invalid MII path"); + return -ENOENT; + } + + node = fdt_path_offset(gd->fdt_blob, path); + if (node < 0) + return -ENOENT; + + return node; +} + +int fec_get_fdt_prop(int fec_idx, const char *prop, u32 *value) +{ + int node; + const u32 *val; + + node = fec_get_node(fec_idx); + if (node < 0) + return node; + + val = fdt_getprop(gd->fdt_blob, node, prop, NULL); + if (!val) + return -ENOENT; + + *value = fdt32_to_cpu(*val); + + return 0; +} + +int fec_get_base_addr(int fec_idx, u32 *fec_iobase) +{ + int node; + fdt_size_t size; + fdt_addr_t addr; + + node = fec_get_node(fec_idx); + if (node < 0) + return node; + + addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size); + + *fec_iobase = (u32)addr; + + return 0; +} + +int fec_get_mii_base(int fec_idx, u32 *mii_base) +{ + return fec_get_fdt_prop(fec_idx, "mii-base", mii_base); +} + +#endif //CONFIG_MCFFEC || CONFIG_FSLDMAFEC
On Fri, Nov 15, 2019 at 11:54:16PM +0100, Angelo Dureghello wrote:
From: Angelo Durgehello angelo.dureghello@timesys.com
Add architecture-related code for dm fec support.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com
Applied to u-boot/master, thanks!
From: Angelo Durgehello angelo.dureghello@timesys.com
Add ColdFire fec to Kconfig.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com --- drivers/net/Kconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 4182897d89..4efed81617 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -278,6 +278,22 @@ config FTGMAC100 applications.
+config MCFFEC + bool "ColdFire Ethernet Support" + depends on DM_ETH + select PHYLIB + help + This driver supports the network interface units in the + ColdFire family. + +config FSLDMAFEC + bool "ColdFire DMA Ethernet Support" + depends on DM_ETH + select PHYLIB + help + This driver supports the network interface units in the + ColdFire family. + config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on KIRKWOOD || ORION5X
On Fri, Nov 15, 2019 at 11:54:17PM +0100, Angelo Dureghello wrote:
From: Angelo Durgehello angelo.dureghello@timesys.com
Add ColdFire fec to Kconfig.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com
Applied to u-boot/master, thanks!
From: Angelo Durgehello angelo.dureghello@timesys.com
Full conversion to dm for all boards, legacy code removed.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com --- doc/device-tree-bindings/net/fsl,mcf-fec.txt | 22 + drivers/net/mcffec.c | 587 +++++++++---------- 2 files changed, 315 insertions(+), 294 deletions(-) create mode 100644 doc/device-tree-bindings/net/fsl,mcf-fec.txt
diff --git a/doc/device-tree-bindings/net/fsl,mcf-fec.txt b/doc/device-tree-bindings/net/fsl,mcf-fec.txt new file mode 100644 index 0000000000..39bbaa52f3 --- /dev/null +++ b/doc/device-tree-bindings/net/fsl,mcf-fec.txt @@ -0,0 +1,22 @@ +* Freescale ColdFire FEC ethernet controller + +Required properties: +- compatible: should be "fsl,mcf-fec" +- reg: address and length of the register set for the device. + +Optional properties: +- mii-base: index of FEC reg area, 0 for FEC0, 1 for FEC1 +- max-speed: max speedm Mbits/sec +- phy-addr: phy address +- timeout-loop: integer value for driver loops time out + + +Example: + +fec0: ethernet@fc030000 { + compatible = "fsl,mcf-fec"; + reg = <0xfc030000 0x400>; + mii-base = <0>; + phy-addr = <0>; + timeout-loop = <5000>; +}; diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index fb93041256..6c8123a6bb 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -5,17 +5,17 @@ * * (C) Copyright 2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * Conversion to DM + * (C) 2019 Angelo Dureghello angelo.dureghello@timesys.com */
#include <common.h> #include <env.h> #include <malloc.h> - #include <command.h> #include <net.h> -#include <netdev.h> #include <miiphy.h> - #include <asm/fec.h> #include <asm/immap.h>
@@ -26,64 +26,68 @@ #define DBUF_LENGTH 1520 #define TX_BUF_CNT 2 #define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 #define PKT_MAXBLR_SIZE 1520 #define LAST_PKTBUFSRX PKTBUFSRX - 1 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
-struct fec_info_s fec_info[] = { -#ifdef CONFIG_SYS_FEC0_IOBASE - { - 0, /* index */ - CONFIG_SYS_FEC0_IOBASE, /* io base */ - CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */ - CONFIG_SYS_FEC0_MIIBASE, /* mii base */ - -1, /* phy_addr */ - 0, /* duplex and speed */ - 0, /* phy name */ - 0, /* phyname init */ - 0, /* RX BD */ - 0, /* TX BD */ - 0, /* rx Index */ - 0, /* tx Index */ - 0, /* tx buffer */ - 0, /* initialized flag */ - (struct fec_info_s *)-1, - }, -#endif -#ifdef CONFIG_SYS_FEC1_IOBASE - { - 1, /* index */ - CONFIG_SYS_FEC1_IOBASE, /* io base */ - CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */ - CONFIG_SYS_FEC1_MIIBASE, /* mii base */ - -1, /* phy_addr */ - 0, /* duplex and speed */ - 0, /* phy name */ - 0, /* phy name init */ +DECLARE_GLOBAL_DATA_PTR; + +static void init_eth_info(struct fec_info_s *info) +{ #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM - (cbd_t *)DBUF_LENGTH, /* RX BD */ + static u32 tmp; + + if (info->index == 0) + tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; + else + info->rxbd = (cbd_t *)DBUF_LENGTH; + + /* setup Receive and Transmit buffer descriptor */ + info->rxbd = (cbd_t *)((u32)info->rxbd + tmp); + tmp = (u32)info->rxbd; + info->txbd = + (cbd_t *)((u32)info->txbd + tmp + + (PKTBUFSRX * sizeof(cbd_t))); + tmp = (u32)info->txbd; + info->txbuf = + (char *)((u32)info->txbuf + tmp + + (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + tmp = (u32)info->txbuf; #else - 0, /* RX BD */ + info->rxbd = + (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE, + (PKTBUFSRX * sizeof(cbd_t))); + info->txbd = + (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE, + (TX_BUF_CNT * sizeof(cbd_t))); + info->txbuf = + (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); #endif - 0, /* TX BD */ - 0, /* rx Index */ - 0, /* tx Index */ - 0, /* tx buffer */ - 0, /* initialized flag */ - (struct fec_info_s *)-1, - } + +#ifdef ET_DEBUG + printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd); #endif -}; + info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); +} + +static void fec_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *)(info->iobase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) + udelay(1);
-int fec_recv(struct eth_device *dev); -int fec_init(struct eth_device *dev, bd_t * bd); -void fec_halt(struct eth_device *dev); -void fec_reset(struct eth_device *dev); + if (i == FEC_RESET_DELAY) + printf("FEC_RESET_DELAY timeout\n"); +}
-void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) +static void set_fec_duplex_speed(volatile fec_t *fecp, int dup_spd) { + bd_t *bd = gd->bd; + if ((dup_spd >> 16) == FULL) { /* Set maximum frame length */ fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | @@ -115,138 +119,11 @@ void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) } }
-static int fec_send(struct eth_device *dev, void *packet, int length) -{ - struct fec_info_s *info = dev->priv; - volatile fec_t *fecp = (fec_t *) (info->iobase); - int j, rc; - u16 phyStatus; - - miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus); - - /* section 16.9.23.3 - * Wait for ready - */ - j = 0; - while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && - (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("TX not ready\n"); - } - - info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; - info->txbd[info->txIdx].cbd_datlen = length; - info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; - - /* Activate transmit Buffer Descriptor polling */ - fecp->tdar = 0x01000000; /* Descriptor polling active */ - -#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM - /* - * FEC unable to initial transmit data packet. - * A nop will ensure the descriptor polling active completed. - * CF Internal RAM has shorter cycle access than DRAM. If use - * DRAM as Buffer descriptor and data, a nop is a must. - * Affect only V2 and V3. - */ - __asm__ ("nop"); - -#endif - -#ifdef CONFIG_SYS_UNIFY_CACHE - icache_invalid(); -#endif - - j = 0; - while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && - (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("TX timeout\n"); - } - -#ifdef ET_DEBUG - printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", - __FILE__, __LINE__, __FUNCTION__, j, - info->txbd[info->txIdx].cbd_sc, - (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); -#endif - - /* return only status bits */ - rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); - info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; - - return rc; -} - -int fec_recv(struct eth_device *dev) -{ - struct fec_info_s *info = dev->priv; - volatile fec_t *fecp = (fec_t *) (info->iobase); - int length; - - for (;;) { -#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM -#endif -#ifdef CONFIG_SYS_UNIFY_CACHE - icache_invalid(); -#endif - /* section 16.9.23.2 */ - if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = info->rxbd[info->rxIdx].cbd_datlen; - - if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) { - printf("%s[%d] err: %x\n", - __FUNCTION__, __LINE__, - info->rxbd[info->rxIdx].cbd_sc); -#ifdef ET_DEBUG - printf("%s[%d] err: %x\n", - __FUNCTION__, __LINE__, - info->rxbd[info->rxIdx].cbd_sc); -#endif - } else { - - length -= 4; - /* Pass the packet up to the protocol layers. */ - net_process_received_packet(net_rx_packets[info->rxIdx], - length); - - fecp->eir |= FEC_EIR_RXF; - } - - /* Give the buffer back to the FEC. */ - info->rxbd[info->rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if (info->rxIdx == LAST_PKTBUFSRX) { - info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; - info->rxIdx = 0; - } else { - info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - info->rxIdx++; - } - - /* Try to fill Buffer Descriptors */ - fecp->rdar = 0x01000000; /* Descriptor polling active */ - } - - return length; -} - #ifdef ET_DEBUG -void dbgFecRegs(struct eth_device *dev) +static void dbg_fec_regs(struct udevice *dev) { struct fec_info_s *info = dev->priv; - volatile fec_t *fecp = (fec_t *) (info->iobase); + volatile fec_t *fecp = (fec_t *)(info->iobase);
printf("=====\n"); printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); @@ -393,28 +270,27 @@ void dbgFecRegs(struct eth_device *dev) } #endif
-int fec_init(struct eth_device *dev, bd_t * bd) +int mcffec_init(struct udevice *dev) { struct fec_info_s *info = dev->priv; volatile fec_t *fecp = (fec_t *) (info->iobase); - int i; + int rval, i; uchar ea[6];
- fecpin_setclear(dev, 1); - - fec_reset(dev); + fecpin_setclear(info, 1); + fec_reset(info);
#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ defined (CONFIG_SYS_DISCOVER_PHY)
mii_init();
- setFecDuplexSpeed(fecp, bd, info->dup_spd); + set_fec_duplex_speed(fecp, info->dup_spd); #else #ifndef CONFIG_SYS_DISCOVER_PHY - setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); -#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ -#endif /* CONFIG_CMD_MII || CONFIG_MII */ + set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED); +#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ +#endif /* CONFIG_CMD_MII || CONFIG_MII */
/* We use strictly polling mode only */ fecp->eimr = 0; @@ -423,34 +299,20 @@ int fec_init(struct eth_device *dev, bd_t * bd) fecp->eir = 0xffffffff;
/* Set station address */ - if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) { -#ifdef CONFIG_SYS_FEC1_IOBASE - volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE); - eth_env_get_enetaddr("eth1addr", ea); - fecp1->palr = - (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); - fecp1->paur = (ea[4] << 24) | (ea[5] << 16); -#endif - eth_env_get_enetaddr("ethaddr", ea); - fecp->palr = - (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); - fecp->paur = (ea[4] << 24) | (ea[5] << 16); - } else { -#ifdef CONFIG_SYS_FEC0_IOBASE - volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE); - eth_env_get_enetaddr("ethaddr", ea); - fecp0->palr = - (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); - fecp0->paur = (ea[4] << 24) | (ea[5] << 16); -#endif -#ifdef CONFIG_SYS_FEC1_IOBASE - eth_env_get_enetaddr("eth1addr", ea); - fecp->palr = - (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); - fecp->paur = (ea[4] << 24) | (ea[5] << 16); -#endif + if (info->index == 0) + rval = eth_env_get_enetaddr("ethaddr", ea); + else + rval = eth_env_get_enetaddr("eth1addr", ea); + + if (!rval) { + puts("Please set a valid MAC address\n"); + return -EINVAL; }
+ fecp->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->paur = (ea[4] << 24) | (ea[5] << 16); + /* Clear unicast address hash table */ fecp->iaur = 0; fecp->ialr = 0; @@ -465,8 +327,8 @@ int fec_init(struct eth_device *dev, bd_t * bd) /* * Setup Buffers and Buffer Descriptors */ - info->rxIdx = 0; - info->txIdx = 0; + info->rx_idx = 0; + info->tx_idx = 0;
/* * Setup Receiver Buffer Descriptors (13.14.24.18) @@ -499,119 +361,256 @@ int fec_init(struct eth_device *dev, bd_t * bd) /* Now enable the transmit and receive processing */ fecp->ecr |= FEC_ECR_ETHER_EN;
- /* And last, try to fill Rx Buffer Descriptors */ - fecp->rdar = 0x01000000; /* Descriptor polling active */ + /* And last, try to fill Rx Buffer Descriptors + * Descriptor polling active + */ + fecp->rdar = 0x01000000;
- return 1; + return 0; }
-void fec_reset(struct eth_device *dev) +static int mcffec_send(struct udevice *dev, void *packet, int length) { struct fec_info_s *info = dev->priv; - volatile fec_t *fecp = (fec_t *) (info->iobase); - int i; + volatile fec_t *fecp = (fec_t *)info->iobase; + int j, rc; + u16 phy_status;
- fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status); + + /* section 16.9.23.3 + * Wait for ready + */ + j = 0; + while ((info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_READY) && + (j < info->to_loop)) { udelay(1); + j++; } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); + if (j >= info->to_loop) + printf("TX not ready\n"); + + info->txbd[info->tx_idx].cbd_bufaddr = (uint)packet; + info->txbd[info->tx_idx].cbd_datlen = length; + info->txbd[info->tx_idx].cbd_sc |= BD_ENET_TX_RDY_LST; + + /* Activate transmit Buffer Descriptor polling */ + fecp->tdar = 0x01000000; /* Descriptor polling active */ + +#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM + /* + * FEC unable to initial transmit data packet. + * A nop will ensure the descriptor polling active completed. + * CF Internal RAM has shorter cycle access than DRAM. If use + * DRAM as Buffer descriptor and data, a nop is a must. + * Affect only V2 and V3. + */ + __asm__ ("nop"); +#endif + +#ifdef CONFIG_SYS_UNIFY_CACHE + icache_invalid(); +#endif + + j = 0; + while ((info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_READY) && + (j < info->to_loop)) { + udelay(1); + j++; + } + if (j >= info->to_loop) + printf("TX timeout\n"); + +#ifdef ET_DEBUG + printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", + __FILE__, __LINE__, __func__, j, + info->txbd[info->tx_idx].cbd_sc, + (info->txbd[info->tx_idx].cbd_sc & 0x003C) >> 2); +#endif + + /* return only status bits */ + rc = (info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS); + info->tx_idx = (info->tx_idx + 1) % TX_BUF_CNT; + + return rc; +} + +static int mcffec_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *)info->iobase; + int length = -1; + + for (;;) { +#ifdef CONFIG_SYS_UNIFY_CACHE + icache_invalid(); +#endif + /* If nothing received - leave for() loop */ + if (info->rxbd[info->rx_idx].cbd_sc & BD_ENET_RX_EMPTY) + break; + + length = info->rxbd[info->rx_idx].cbd_datlen; + + if (info->rxbd[info->rx_idx].cbd_sc & 0x003f) { + printf("%s[%d] err: %x\n", + __func__, __LINE__, + info->rxbd[info->rx_idx].cbd_sc); + } else { + length -= 4; + + /* + * Pass the buffer ptr up to the protocol layers. + */ + *packetp = net_rx_packets[info->rx_idx]; + + fecp->eir |= FEC_EIR_RXF; + } + + /* Give the buffer back to the FEC. */ + info->rxbd[info->rx_idx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if (info->rx_idx == LAST_PKTBUFSRX) { + info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; + info->rx_idx = 0; + } else { + info->rxbd[info->rx_idx].cbd_sc = BD_ENET_RX_EMPTY; + info->rx_idx++; + } + + /* Try to fill Buffer Descriptors + * Descriptor polling active + */ + fecp->rdar = 0x01000000; } + + return length; }
-void fec_halt(struct eth_device *dev) +static void mcffec_halt(struct udevice *dev) { struct fec_info_s *info = dev->priv;
- fec_reset(dev); + fec_reset(info); + fecpin_setclear(info, 0);
- fecpin_setclear(dev, 0); + info->rx_idx = 0; + info->tx_idx = 0;
- info->rxIdx = info->txIdx = 0; memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t)); memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t)); memset(info->txbuf, 0, DBUF_LENGTH); }
-int mcffec_initialize(bd_t * bis) +static const struct eth_ops mcffec_ops = { + .start = mcffec_init, + .send = mcffec_send, + .recv = mcffec_recv, + .stop = mcffec_halt, +}; + +/* + * Boot sequence, called just after mcffec_ofdata_to_platdata, + * as DM way, it replaces old mcffec_initialize. + */ +static int mcffec_probe(struct udevice *dev) { - struct eth_device *dev; - int i; -#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM - u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; -#endif + struct eth_pdata *pdata = dev_get_platdata(dev); + struct fec_info_s *info = dev->priv; + int node = dev_of_offset(dev); + int retval, fec_idx; + const u32 *val;
- for (i = 0; i < ARRAY_SIZE(fec_info); i++) { + info->index = dev->seq; + info->iobase = pdata->iobase; + info->phy_addr = -1;
- dev = - (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, - sizeof *dev); - if (dev == NULL) - hang(); + val = fdt_getprop(gd->fdt_blob, node, "mii-base", NULL); + if (val) { + u32 fec_iobase;
- memset(dev, 0, sizeof(*dev)); + fec_idx = fdt32_to_cpu(*val); + if (fec_idx == info->index) { + fec_iobase = info->iobase; + } else { + printf("mii base != base address, fec_idx %d\n", + fec_idx); + retval = fec_get_base_addr(fec_idx, &fec_iobase); + if (retval) + return retval; + } + info->miibase = fec_iobase; + }
- sprintf(dev->name, "FEC%d", fec_info[i].index); + val = fdt_getprop(gd->fdt_blob, node, "phy-addr", NULL); + if (val) + info->phy_addr = fdt32_to_cpu(*val);
- dev->priv = &fec_info[i]; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; + val = fdt_getprop(gd->fdt_blob, node, "timeout-loop", NULL); + if (val) + info->to_loop = fdt32_to_cpu(*val);
- /* setup Receive and Transmit buffer descriptor */ -#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM - fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp); - tmp = (u32)fec_info[i].rxbd; - fec_info[i].txbd = - (cbd_t *)((u32)fec_info[i].txbd + tmp + - (PKTBUFSRX * sizeof(cbd_t))); - tmp = (u32)fec_info[i].txbd; - fec_info[i].txbuf = - (char *)((u32)fec_info[i].txbuf + tmp + - (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); - tmp = (u32)fec_info[i].txbuf; -#else - fec_info[i].rxbd = - (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, - (PKTBUFSRX * sizeof(cbd_t))); - fec_info[i].txbd = - (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, - (TX_BUF_CNT * sizeof(cbd_t))); - fec_info[i].txbuf = - (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); -#endif + init_eth_info(info);
-#ifdef ET_DEBUG - printf("rxbd %x txbd %x\n", - (int)fec_info[i].rxbd, (int)fec_info[i].txbd); +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + info->bus = mdio_alloc(); + if (!info->bus) + return -ENOMEM; + strcpy(info->bus->name, dev->name); + info->bus->read = mcffec_miiphy_read; + info->bus->write = mcffec_miiphy_write; + + retval = mdio_register(info->bus); + if (retval < 0) + return retval; #endif
- fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); + return 0; +}
- eth_register(dev); +static int mcffec_remove(struct udevice *dev) +{ + struct fec_info_s *priv = dev_get_priv(dev);
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = mcffec_miiphy_read; - mdiodev->write = mcffec_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - if (i > 0) - fec_info[i - 1].next = &fec_info[i]; - } - fec_info[i - 1].next = &fec_info[0]; + mdio_unregister(priv->bus); + mdio_free(priv->bus); + + return 0; +} + +/* + * Boot sequence, called 1st + */ +static int mcffec_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + const u32 *val;
- /* default speed */ - bis->bi_ethspeed = 10; + pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); + /* Default to 10Mbit/s */ + pdata->max_speed = 10; + + val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), + "max-speed", NULL); + if (val) + pdata->max_speed = fdt32_to_cpu(*val);
return 0; } + +static const struct udevice_id mcffec_ids[] = { + { .compatible = "fsl,mcf-fec" }, + { } +}; + +U_BOOT_DRIVER(mcffec) = { + .name = "mcffec", + .id = UCLASS_ETH, + .of_match = mcffec_ids, + .ofdata_to_platdata = mcffec_ofdata_to_platdata, + .probe = mcffec_probe, + .remove = mcffec_remove, + .ops = &mcffec_ops, + .priv_auto_alloc_size = sizeof(struct fec_info_s), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +};
On Fri, Nov 15, 2019 at 11:54:18PM +0100, Angelo Dureghello wrote:
From: Angelo Durgehello angelo.dureghello@timesys.com
Full conversion to dm for all boards, legacy code removed.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com
Applied to u-boot/master, thanks!
From: Angelo Durgehello angelo.dureghello@timesys.com
Full conversion to dm for all boards, legacy code removed.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com --- .../net/fsl,mcf-dma-fec.txt | 35 + drivers/net/fsl_mcdmafec.c | 691 +++++++++--------- 2 files changed, 389 insertions(+), 337 deletions(-) create mode 100644 doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt
diff --git a/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt b/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt new file mode 100644 index 0000000000..e237825bac --- /dev/null +++ b/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt @@ -0,0 +1,35 @@ +* Freescale ColdFire DMA-FEC ethernet controller + +Required properties: +- compatible: should be "fsl,mcf-dma-fec" +- reg: address and length of the register set for the device. +- rx-task: dma channel +- tx-task: dma channel +- rx-priority: dma channel +- tx-priority: dma channel +- rx-init: dma channel +- tx-init: dma channel + +Optional properties: +- mii-base: index of FEC reg area, 0 for FEC0, 1 for FEC1 +- max-speed: max speedm Mbits/sec +- phy-addr: phy address +- timeout-loop: integer value for driver loops time out + + +Example: + +fec0: ethernet@9000 { + compatible = "fsl,mcf-dma-fec"; + reg = <0x9000 0x800>; + mii-base = <0>; + phy-addr = <0>; + timeout-loop = <5000>; + rx-task = <0>; + tx-task = <1>; + rx-piority = <6>; + tx-piority = <7>; + rx-init = <16>; + tx-init = <17>; + status = "disabled"; +}; diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index e66fb16de8..82a1bb4a2a 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -5,6 +5,9 @@ * * (C) Copyright 2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * Conversion to DM + * (C) 2019 Angelo Dureghello angelo.dureghello@timesys.com */
#include <common.h> @@ -14,6 +17,10 @@ #include <config.h> #include <net.h> #include <miiphy.h> +#include <asm/immap.h> +#include <asm/fsl_mcdmafec.h> + +#include "MCD_dma.h"
#undef ET_DEBUG #undef MII_DEBUG @@ -21,93 +28,94 @@ /* Ethernet Transmit and Receive Buffers */ #define DBUF_LENGTH 1520 #define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 -#define PKT_MAXBLR_SIZE 1536 -#define LAST_PKTBUFSRX PKTBUFSRX - 1 -#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) -#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
/* RxBD bits definitions */ #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \ BD_ENET_RX_OV | BD_ENET_RX_TR)
-#include <asm/immap.h> -#include <asm/fsl_mcdmafec.h> +DECLARE_GLOBAL_DATA_PTR;
-#include "MCD_dma.h" +static void init_eth_info(struct fec_info_dma *info) +{ + /* setup Receive and Transmit buffer descriptor */ +#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM + static u32 tmp;
-struct fec_info_dma fec_info[] = { -#ifdef CONFIG_SYS_FEC0_IOBASE - { - 0, /* index */ - CONFIG_SYS_FEC0_IOBASE, /* io base */ - CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */ - CONFIG_SYS_FEC0_MIIBASE, /* mii base */ - -1, /* phy_addr */ - 0, /* duplex and speed */ - 0, /* phy name */ - 0, /* phyname init */ - 0, /* RX BD */ - 0, /* TX BD */ - 0, /* rx Index */ - 0, /* tx Index */ - 0, /* tx buffer */ - 0, /* initialized flag */ - (struct fec_info_dma *)-1, /* next */ - FEC0_RX_TASK, /* rxTask */ - FEC0_TX_TASK, /* txTask */ - FEC0_RX_PRIORITY, /* rxPri */ - FEC0_TX_PRIORITY, /* txPri */ - FEC0_RX_INIT, /* rxInit */ - FEC0_TX_INIT, /* txInit */ - 0, /* usedTbdIndex */ - 0, /* cleanTbdNum */ - }, -#endif -#ifdef CONFIG_SYS_FEC1_IOBASE - { - 1, /* index */ - CONFIG_SYS_FEC1_IOBASE, /* io base */ - CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */ - CONFIG_SYS_FEC1_MIIBASE, /* mii base */ - -1, /* phy_addr */ - 0, /* duplex and speed */ - 0, /* phy name */ - 0, /* phy name init */ -#ifdef CONFIG_SYS_DMA_USE_INTSRAM - (cbd_t *)DBUF_LENGTH, /* RX BD */ + if (info->index == 0) + tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; + else + info->rxbd = (cbd_t *)DBUF_LENGTH; + + info->rxbd = (cbd_t *)((u32)info->rxbd + tmp); + tmp = (u32)info->rxbd; + info->txbd = + (cbd_t *)((u32)info->txbd + tmp + + (PKTBUFSRX * sizeof(cbd_t))); + tmp = (u32)info->txbd; + info->txbuf = + (char *)((u32)info->txbuf + tmp + + (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + tmp = (u32)info->txbuf; #else - 0, /* RX BD */ + info->rxbd = + (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE, + (PKTBUFSRX * sizeof(cbd_t))); + info->txbd = + (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE, + (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + info->txbuf = + (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); #endif - 0, /* TX BD */ - 0, /* rx Index */ - 0, /* tx Index */ - 0, /* tx buffer */ - 0, /* initialized flag */ - (struct fec_info_dma *)-1, /* next */ - FEC1_RX_TASK, /* rxTask */ - FEC1_TX_TASK, /* txTask */ - FEC1_RX_PRIORITY, /* rxPri */ - FEC1_TX_PRIORITY, /* txPri */ - FEC1_RX_INIT, /* rxInit */ - FEC1_TX_INIT, /* txInit */ - 0, /* usedTbdIndex */ - 0, /* cleanTbdNum */ - } + +#ifdef ET_DEBUG + printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd); #endif -}; + info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); +} + +static void fec_halt(struct udevice *dev) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *)info->iobase; + int counter = 0xffff; + + /* issue graceful stop command to the FEC transmitter if necessary */ + fecp->tcr |= FEC_TCR_GTS; + + /* wait for graceful stop to register */ + while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) + ; + + /* Disable DMA tasks */ + MCD_killDma(info->tx_task); + MCD_killDma(info->rx_task); + + /* Disable the Ethernet Controller */ + fecp->ecr &= ~FEC_ECR_ETHER_EN; + + /* Clear FIFO status registers */ + fecp->rfsr &= FIFO_ERRSTAT; + fecp->tfsr &= FIFO_ERRSTAT; + + fecp->frst = 0x01000000;
-static int fec_send(struct eth_device *dev, void *packet, int length); -static int fec_recv(struct eth_device *dev); -static int fec_init(struct eth_device *dev, bd_t * bd); -static void fec_halt(struct eth_device *dev); + /* Issue a reset command to the FEC chip */ + fecp->ecr |= FEC_ECR_RESET; + + /* wait at least 20 clock cycles */ + mdelay(10); + +#ifdef ET_DEBUG + printf("Ethernet task stopped\n"); +#endif +}
#ifdef ET_DEBUG static void dbg_fec_regs(struct eth_device *dev) { struct fec_info_dma *info = dev->priv; - volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
printf("=====\n"); printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); @@ -148,9 +156,10 @@ static void dbg_fec_regs(struct eth_device *dev) } #endif
-static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd, - int dup_spd) +static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd) { + bd_t *bd = gd->bd; + if ((dup_spd >> 16) == FULL) { /* Set maximum frame length */ fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | @@ -176,153 +185,23 @@ static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd, } }
-static int fec_send(struct eth_device *dev, void *packet, int length) -{ - struct fec_info_dma *info = dev->priv; - cbd_t *pTbd, *pUsedTbd; - u16 phyStatus; - - miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus); - - /* process all the consumed TBDs */ - while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) { - pUsedTbd = &info->txbd[info->usedTbdIdx]; - if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) { -#ifdef ET_DEBUG - printf("Cannot clean TBD %d, in use\n", - info->cleanTbdNum); -#endif - return 0; - } - - /* clean this buffer descriptor */ - if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1)) - pUsedTbd->cbd_sc = BD_ENET_TX_WRAP; - else - pUsedTbd->cbd_sc = 0; - - /* update some indeces for a correct handling of the TBD ring */ - info->cleanTbdNum++; - info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER; - } - - /* Check for valid length of data. */ - if ((length > 1500) || (length <= 0)) { - return -1; - } - - /* Check the number of vacant TxBDs. */ - if (info->cleanTbdNum < 1) { - printf("No available TxBDs ...\n"); - return -1; - } - - /* Get the first TxBD to send the mac header */ - pTbd = &info->txbd[info->txIdx]; - pTbd->cbd_datlen = length; - pTbd->cbd_bufaddr = (u32) packet; - pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; - info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER; - - /* Enable DMA transmit task */ - MCD_continDma(info->txTask); - - info->cleanTbdNum -= 1; - - /* wait until frame is sent . */ - while (pTbd->cbd_sc & BD_ENET_TX_READY) { - udelay(10); - } - - return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); -} - -static int fec_recv(struct eth_device *dev) -{ - struct fec_info_dma *info = dev->priv; - volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); - - cbd_t *prbd = &info->rxbd[info->rxIdx]; - u32 ievent; - int frame_length, len = 0; - - /* Check if any critical events have happened */ - ievent = fecp->eir; - if (ievent != 0) { - fecp->eir = ievent; - - if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) { - printf("fec_recv: error\n"); - fec_halt(dev); - fec_init(dev, NULL); - return 0; - } - - if (ievent & FEC_EIR_HBERR) { - /* Heartbeat error */ - fecp->tcr |= FEC_TCR_GTS; - } - - if (ievent & FEC_EIR_GRA) { - /* Graceful stop complete */ - if (fecp->tcr & FEC_TCR_GTS) { - printf("fec_recv: tcr_gts\n"); - fec_halt(dev); - fecp->tcr &= ~FEC_TCR_GTS; - fec_init(dev, NULL); - } - } - } - - if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) { - if ((prbd->cbd_sc & BD_ENET_RX_LAST) && - !(prbd->cbd_sc & BD_ENET_RX_ERR) && - ((prbd->cbd_datlen - 4) > 14)) { - - /* Get buffer address and size */ - frame_length = prbd->cbd_datlen - 4; - - /* Fill the buffer and pass it to upper layers */ - net_process_received_packet((uchar *)prbd->cbd_bufaddr, - frame_length); - len = frame_length; - } - - /* Reset buffer descriptor as empty */ - if ((info->rxIdx) == (PKTBUFSRX - 1)) - prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - else - prbd->cbd_sc = BD_ENET_RX_EMPTY; - - prbd->cbd_datlen = PKTSIZE_ALIGN; - - /* Now, we have an empty RxBD, restart the DMA receive task */ - MCD_continDma(info->rxTask); - - /* Increment BD count */ - info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX; - } - - return len; -} - -static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac) +static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac) { - u8 currByte; /* byte for which to compute the CRC */ + u8 curr_byte; /* byte for which to compute the CRC */ int byte; /* loop - counter */ int bit; /* loop - counter */ u32 crc = 0xffffffff; /* initial value */
for (byte = 0; byte < 6; byte++) { - currByte = mac[byte]; + curr_byte = mac[byte]; for (bit = 0; bit < 8; bit++) { - if ((currByte & 0x01) ^ (crc & 0x01)) { + if ((curr_byte & 0x01) ^ (crc & 0x01)) { crc >>= 1; crc = crc ^ 0xedb88320; } else { crc >>= 1; } - currByte >>= 1; + curr_byte >>= 1; } }
@@ -346,30 +225,28 @@ static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac) fecp->galr = 0; }
-static int fec_init(struct eth_device *dev, bd_t * bd) +static int fec_init(struct udevice *dev) { struct fec_info_dma *info = dev->priv; - volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); - int i; + volatile fecdma_t *fecp = (fecdma_t *)info->iobase; + int rval, i; uchar enetaddr[6];
#ifdef ET_DEBUG printf("fec_init: iobase 0x%08x ...\n", info->iobase); #endif
- fecpin_setclear(dev, 1); - + fecpin_setclear(info, 1); fec_halt(dev);
#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ defined (CONFIG_SYS_DISCOVER_PHY)
mii_init(); - - set_fec_duplex_speed(fecp, bd, info->dup_spd); + set_fec_duplex_speed(fecp, info->dup_spd); #else #ifndef CONFIG_SYS_DISCOVER_PHY - set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); + set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED); #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ #endif /* CONFIG_CMD_MII || CONFIG_MII */
@@ -380,18 +257,24 @@ static int fec_init(struct eth_device *dev, bd_t * bd) fecp->eir = 0xffffffff;
/* Set station address */ - if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) - eth_env_get_enetaddr("ethaddr", enetaddr); + if (info->index == 0) + rval = eth_env_get_enetaddr("ethaddr", enetaddr); else - eth_env_get_enetaddr("eth1addr", enetaddr); + rval = eth_env_get_enetaddr("eth1addr", enetaddr); + + if (!rval) { + puts("Please set a valid MAC address\n"); + return -EINVAL; + } + fec_set_hwaddr(fecp, enetaddr);
/* Set Opcode/Pause Duration Register */ fecp->opd = 0x00010020;
/* Setup Buffers and Buffer Descriptors */ - info->rxIdx = 0; - info->txIdx = 0; + info->rx_idx = 0; + info->tx_idx = 0;
/* Setup Receiver Buffer Descriptors (13.14.24.18) * Settings: Empty, Wrap */ @@ -411,8 +294,8 @@ static int fec_init(struct eth_device *dev, bd_t * bd) } info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
- info->usedTbdIdx = 0; - info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER; + info->used_tbd_idx = 0; + info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER;
/* Set Rx FIFO alarm and granularity value */ fecp->rfcr = 0x0c000000; @@ -426,154 +309,288 @@ static int fec_init(struct eth_device *dev, bd_t * bd) fecp->ctcwr = 0x03000000;
/* Enable DMA receive task */ - MCD_startDma(info->rxTask, /* Dma channel */ - (s8 *) info->rxbd, /*Source Address */ - 0, /* Source increment */ - (s8 *) (&fecp->rfdr), /* dest */ - 4, /* dest increment */ - 0, /* DMA size */ - 4, /* xfer size */ - info->rxInit, /* initiator */ - info->rxPri, /* priority */ - (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ - (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ + MCD_startDma(info->rx_task, + (s8 *)info->rxbd, + 0, + (s8 *)&fecp->rfdr, + 4, + 0, + 4, + info->rx_init, + info->rx_pri, + (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), + (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) );
/* Enable DMA tx task with no ready buffer descriptors */ - MCD_startDma(info->txTask, /* Dma channel */ - (s8 *) info->txbd, /*Source Address */ - 0, /* Source increment */ - (s8 *) (&fecp->tfdr), /* dest */ - 4, /* dest incr */ - 0, /* DMA size */ - 4, /* xfer size */ - info->txInit, /* initiator */ - info->txPri, /* priority */ - (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ - (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ + MCD_startDma(info->tx_task, + (s8 *)info->txbd, + 0, + (s8 *)&fecp->tfdr, + 4, + 0, + 4, + info->tx_init, + info->tx_pri, + (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), + (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) );
/* Now enable the transmit and receive processing */ fecp->ecr |= FEC_ECR_ETHER_EN;
- return 1; + return 0; +} + +static int mcdmafec_init(struct udevice *dev) +{ + return fec_init(dev); }
-static void fec_halt(struct eth_device *dev) +static int mcdmafec_send(struct udevice *dev, void *packet, int length) { struct fec_info_dma *info = dev->priv; - volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); - int counter = 0xffff; + cbd_t *p_tbd, *p_used_tbd; + u16 phy_status;
- /* issue graceful stop command to the FEC transmitter if necessary */ - fecp->tcr |= FEC_TCR_GTS; + miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
- /* wait for graceful stop to register */ - while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ; + /* process all the consumed TBDs */ + while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) { + p_used_tbd = &info->txbd[info->used_tbd_idx]; + if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) { +#ifdef ET_DEBUG + printf("Cannot clean TBD %d, in use\n", + info->clean_tbd_num); +#endif + return 0; + }
- /* Disable DMA tasks */ - MCD_killDma(info->txTask); - MCD_killDma(info->rxTask); + /* clean this buffer descriptor */ + if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1)) + p_used_tbd->cbd_sc = BD_ENET_TX_WRAP; + else + p_used_tbd->cbd_sc = 0;
- /* Disable the Ethernet Controller */ - fecp->ecr &= ~FEC_ECR_ETHER_EN; + /* update some indeces for a correct handling of TBD ring */ + info->clean_tbd_num++; + info->used_tbd_idx = (info->used_tbd_idx + 1) + % CONFIG_SYS_TX_ETH_BUFFER; + }
- /* Clear FIFO status registers */ - fecp->rfsr &= FIFO_ERRSTAT; - fecp->tfsr &= FIFO_ERRSTAT; + /* Check for valid length of data. */ + if (length > 1500 || length <= 0) + return -1;
- fecp->frst = 0x01000000; + /* Check the number of vacant TxBDs. */ + if (info->clean_tbd_num < 1) { + printf("No available TxBDs ...\n"); + return -1; + }
- /* Issue a reset command to the FEC chip */ - fecp->ecr |= FEC_ECR_RESET; + /* Get the first TxBD to send the mac header */ + p_tbd = &info->txbd[info->tx_idx]; + p_tbd->cbd_datlen = length; + p_tbd->cbd_bufaddr = (u32)packet; + p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; + info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
- /* wait at least 20 clock cycles */ - udelay(10000); + /* Enable DMA transmit task */ + MCD_continDma(info->tx_task);
-#ifdef ET_DEBUG - printf("Ethernet task stopped\n"); -#endif + info->clean_tbd_num -= 1; + + /* wait until frame is sent . */ + while (p_tbd->cbd_sc & BD_ENET_TX_READY) + udelay(10); + + return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS); }
-int mcdmafec_initialize(bd_t * bis) +static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp) { - struct eth_device *dev; - int i; -#ifdef CONFIG_SYS_DMA_USE_INTSRAM - u32 tmp = CONFIG_SYS_INTSRAM + 0x2000; -#endif + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
- for (i = 0; i < ARRAY_SIZE(fec_info); i++) { - - dev = - (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, - sizeof *dev); - if (dev == NULL) - hang(); - - memset(dev, 0, sizeof(*dev)); - - sprintf(dev->name, "FEC%d", fec_info[i].index); - - dev->priv = &fec_info[i]; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; - - /* setup Receive and Transmit buffer descriptor */ -#ifdef CONFIG_SYS_DMA_USE_INTSRAM - fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp); - tmp = (u32)fec_info[i].rxbd; - fec_info[i].txbd = - (cbd_t *)((u32)fec_info[i].txbd + tmp + - (PKTBUFSRX * sizeof(cbd_t))); - tmp = (u32)fec_info[i].txbd; - fec_info[i].txbuf = - (char *)((u32)fec_info[i].txbuf + tmp + - (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); - tmp = (u32)fec_info[i].txbuf; -#else - fec_info[i].rxbd = - (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, - (PKTBUFSRX * sizeof(cbd_t))); - fec_info[i].txbd = - (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, - (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); - fec_info[i].txbuf = - (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); -#endif + cbd_t *prbd = &info->rxbd[info->rx_idx]; + u32 ievent; + int frame_length, len = 0;
-#ifdef ET_DEBUG - printf("rxbd %x txbd %x\n", - (int)fec_info[i].rxbd, (int)fec_info[i].txbd); -#endif + /* Check if any critical events have happened */ + ievent = fecp->eir; + if (ievent != 0) { + fecp->eir = ievent;
- fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); + if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) { + printf("fec_recv: error\n"); + fec_halt(dev); + fec_init(dev); + return 0; + }
- eth_register(dev); + if (ievent & FEC_EIR_HBERR) { + /* Heartbeat error */ + fecp->tcr |= FEC_TCR_GTS; + } + + if (ievent & FEC_EIR_GRA) { + /* Graceful stop complete */ + if (fecp->tcr & FEC_TCR_GTS) { + printf("fec_recv: tcr_gts\n"); + fec_halt(dev); + fecp->tcr &= ~FEC_TCR_GTS; + fec_init(dev); + } + } + } + + if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) { + if ((prbd->cbd_sc & BD_ENET_RX_LAST) && + !(prbd->cbd_sc & BD_ENET_RX_ERR) && + ((prbd->cbd_datlen - 4) > 14)) { + /* Get buffer address and size */ + frame_length = prbd->cbd_datlen - 4; + + /* Fill the buffer and pass it to upper layers */ + net_process_received_packet((uchar *)prbd->cbd_bufaddr, + frame_length); + len = frame_length; + } + + /* Reset buffer descriptor as empty */ + if (info->rx_idx == (PKTBUFSRX - 1)) + prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + else + prbd->cbd_sc = BD_ENET_RX_EMPTY; + + prbd->cbd_datlen = PKTSIZE_ALIGN; + + /* Now, we have an empty RxBD, restart the DMA receive task */ + MCD_continDma(info->rx_task); + + /* Increment BD count */ + info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX; + } + + return len; +} + +static void mcdmafec_halt(struct udevice *dev) +{ + fec_halt(dev); +} + +static const struct eth_ops mcdmafec_ops = { + .start = mcdmafec_init, + .send = mcdmafec_send, + .recv = mcdmafec_recv, + .stop = mcdmafec_halt, +}; + +/* + * Boot sequence, called just after mcffec_ofdata_to_platdata, + * as DM way, it replaces old mcffec_initialize. + */ +static int mcdmafec_probe(struct udevice *dev) +{ + struct fec_info_dma *info = dev->priv; + struct eth_pdata *pdata = dev_get_platdata(dev); + int node = dev_of_offset(dev); + int retval; + const u32 *val; + + info->index = dev->seq; + info->iobase = pdata->iobase; + info->miibase = pdata->iobase; + info->phy_addr = -1; + + val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL); + if (val) + info->rx_task = fdt32_to_cpu(*val); + + val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL); + if (val) + info->tx_task = fdt32_to_cpu(*val); + + val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL); + if (val) + info->rx_pri = fdt32_to_cpu(*val); + + val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL); + if (val) + info->tx_pri = fdt32_to_cpu(*val); + + val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL); + if (val) + info->rx_init = fdt32_to_cpu(*val); + + val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL); + if (val) + info->tx_init = fdt32_to_cpu(*val); + +#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM + u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; +#endif + init_eth_info(info);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = mcffec_miiphy_read; - mdiodev->write = mcffec_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; + info->bus = mdio_alloc(); + if (!info->bus) + return -ENOMEM; + strncpy(info->bus->name, dev->name, MDIO_NAME_LEN); + info->bus->read = mcffec_miiphy_read; + info->bus->write = mcffec_miiphy_write; + + retval = mdio_register(info->bus); + if (retval < 0) + return retval; #endif
- if (i > 0) - fec_info[i - 1].next = &fec_info[i]; - } - fec_info[i - 1].next = &fec_info[0]; + return 0; +}
- /* default speed */ - bis->bi_ethspeed = 10; +static int mcdmafec_remove(struct udevice *dev) +{ + struct fec_info_dma *priv = dev_get_priv(dev); + + mdio_unregister(priv->bus); + mdio_free(priv->bus);
return 0; } + +/* + * Boot sequence, called 1st + */ +static int mcdmafec_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + const u32 *val; + + pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); + /* Default to 10Mbit/s */ + pdata->max_speed = 10; + + val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); + if (val) + pdata->max_speed = fdt32_to_cpu(*val); + + return 0; +} + +static const struct udevice_id mcdmafec_ids[] = { + { .compatible = "fsl,mcf-dma-fec" }, + { } +}; + +U_BOOT_DRIVER(mcffec) = { + .name = "mcdmafec", + .id = UCLASS_ETH, + .of_match = mcdmafec_ids, + .ofdata_to_platdata = mcdmafec_ofdata_to_platdata, + .probe = mcdmafec_probe, + .remove = mcdmafec_remove, + .ops = &mcdmafec_ops, + .priv_auto_alloc_size = sizeof(struct fec_info_dma), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +};
On Fri, Nov 15, 2019 at 11:54:19PM +0100, Angelo Dureghello wrote:
From: Angelo Durgehello angelo.dureghello@timesys.com
Full conversion to dm for all boards, legacy code removed.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com
Applied to u-boot/master, thanks!
From: Angelo Durgehello angelo.dureghello@timesys.com
Add specific dm code, but maintaining this driver as is, so more in the shape of a mii library. Can be moved to dm in a further step.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com --- drivers/net/mcfmii.c | 48 +++++++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 23 deletions(-)
diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 961618b410..27b7c5149f 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -40,14 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; # define CONFIG_SYS_UNSPEC_STRID 0 #endif
-#ifdef CONFIG_MCF547x_8x -typedef struct fec_info_dma FEC_INFO_T; -#define FEC_T fecdma_t -#else -typedef struct fec_info_s FEC_INFO_T; -#define FEC_T fec_t -#endif - typedef struct phy_info_struct { u32 phyid; char *strid; @@ -77,7 +69,7 @@ phy_info_t phyinfo[] = { * mii_init -- Initialize the MII for MII command without ethernet * This function is a subset of eth_init */ -void mii_reset(FEC_INFO_T *info) +void mii_reset(fec_info_t *info) { volatile FEC_T *fecp = (FEC_T *) (info->miibase); int i; @@ -94,9 +86,13 @@ void mii_reset(FEC_INFO_T *info) /* send command to phy using mii, wait for result */ uint mii_send(uint mii_cmd) { - FEC_INFO_T *info; - volatile FEC_T *ep; +#ifdef CONFIG_DM_ETH + struct udevice *dev; +#else struct eth_device *dev; +#endif + fec_info_t *info; + volatile FEC_T *ep; uint mii_reply; int j = 0;
@@ -109,11 +105,11 @@ uint mii_send(uint mii_cmd) ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + while (!(ep->eir & FEC_EIR_MII) && (j < info->to_loop)) { udelay(1); j++; } - if (j >= MCFFEC_TOUT_LOOP) { + if (j >= info->to_loop) { printf("MII not complete\n"); return -1; } @@ -130,10 +126,9 @@ uint mii_send(uint mii_cmd) #endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
#if defined(CONFIG_SYS_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) +int mii_discover_phy(fec_info_t *info) { #define MAX_PHY_PASSES 11 - FEC_INFO_T *info = dev->priv; int phyaddr, pass; uint phyno, phytype; int i, found = 0; @@ -156,7 +151,7 @@ int mii_discover_phy(struct eth_device *dev)
phytype = mii_send(mk_mii_read(phyno, MII_PHYSID1)); #ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); + printf("PHY type 0x%x pass %d\n", phytype, pass); #endif if (phytype == 0xffff) continue; @@ -206,9 +201,13 @@ void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void) { - FEC_INFO_T *info; - volatile FEC_T *fecp; +#ifdef CONFIG_DM_ETH + struct udevice *dev; +#else struct eth_device *dev; +#endif + fec_info_t *info; + volatile FEC_T *fecp; int miispd = 0, i = 0; u16 status = 0; u16 linkgood = 0; @@ -219,7 +218,7 @@ void __mii_init(void)
fecp = (FEC_T *) info->miibase;
- fecpin_setclear(dev, 1); + fecpin_setclear(info, 1);
mii_reset(info);
@@ -233,9 +232,13 @@ void __mii_init(void) miispd = (gd->bus_clk / 1000000) / 5; fecp->mscr = miispd << 1;
- info->phy_addr = mii_discover_phy(dev); +#ifdef CONFIG_SYS_DISCOVER_PHY + info->phy_addr = mii_discover_phy(info); +#endif + if (info->phy_addr == -1) + return;
- while (i < MCFFEC_TOUT_LOOP) { + while (i < info->to_loop) { status = 0; i++; /* Read PHY control register */ @@ -256,9 +259,8 @@ void __mii_init(void)
udelay(1); } - if (i >= MCFFEC_TOUT_LOOP) { + if (i >= info->to_loop) printf("Link UP timeout\n"); - }
/* adapt to the duplex and speed settings of the phy */ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
On Fri, Nov 15, 2019 at 11:54:20PM +0100, Angelo Dureghello wrote:
From: Angelo Durgehello angelo.dureghello@timesys.com
Add specific dm code, but maintaining this driver as is, so more in the shape of a mii library. Can be moved to dm in a further step.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com
Applied to u-boot/master, thanks!
On Fri, Nov 15, 2019 at 11:54:12PM +0100, Angelo Dureghello wrote:
From: Angelo Durgehello angelo.dureghello@timesys.com
Add basic ethernet controller devicetree nodes for all ColdFire families.
Signed-off-by: Angelo Durgehello angelo.dureghello@timesys.com
Applied to u-boot/master, thanks!
participants (2)
-
Angelo Dureghello -
Tom Rini