[U-Boot] [PATCH 00/21] ARM: uniphier: clean-ups of DRAM init code

Masahiro Yamada

26 Feb 2016 26 Feb '16

6:21 a.m.

Masahiro Yamada (21): ARM: uniphier: remove unused umc_polling() ARM: uniphier: rework struct uniphier_board_data ARM: uniphier: optimize ProXstream2 UMC init code with "for" loop ARM: uniphier: use pr_err() where possible ARM: uniphier: refactor UMC init code for ProXstream2 ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings ARM: uniphier: disable debug circuit clocks for PH1-Pro4 ARM: uniphier: add a field to specify DDR3+ ARM: uniphier: merge DDR PHY init code for 3 SoCs ARM: uniphier: remove unused argument of ph1_ld4_ddrphy_init() ARM: uniphier: refactor DDR-PHY init code ARM: uniphier: refactor UMC init code for PH1-sLD8 ARM: uniphier: support more DRAM use cases for PH1-sLD8 ARM: uniphier: refactor UMC init code for PH1-LD4 ARM: uniphier: optimize PH1-sLD8 UMC init code with "for" loop ARM: uniphier: optimize PH1-LD4 UMC init code with "for" loop ARM: uniphier: optimize PH1-Pro4 UMC init code with "for" loop ARM: uniphier: rework DRAM size handling in UMC init code ARM: uniphier: remove unused macros for UMC base addresses ARM: uniphier: deprecate umc_dram_init_{start,poll} ARM: uniphier: rename variable for DRAM controller base address

arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c | 2 +- arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c | 2 +- arch/arm/mach-uniphier/boards.c | 178 ++++++++++------ arch/arm/mach-uniphier/dram/Makefile | 4 +- arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c | 80 ++++---- arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c | 67 ------ arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c | 78 ------- arch/arm/mach-uniphier/dram/ddrphy-regs.h | 5 +- arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 225 +++++++++++---------- arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 182 +++++++++-------- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 218 +++++++++++--------- arch/arm/mach-uniphier/dram/umc-proxstream2.c | 217 ++++++++++---------- arch/arm/mach-uniphier/dram/umc-regs.h | 48 +---- arch/arm/mach-uniphier/init.h | 24 ++- arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c | 6 +- .../mach-uniphier/memconf/memconf-proxstream2.c | 6 +- arch/arm/mach-uniphier/memconf/memconf.c | 14 +- 17 files changed, 643 insertions(+), 713 deletions(-) delete mode 100644 arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c delete mode 100644 arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c

-- 1.9.1

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Masahiro Yamada

26 Feb 26 Feb

6:21 a.m.

New subject: [U-Boot] [PATCH 01/21] ARM: uniphier: remove unused umc_polling()

This function is unused.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-regs.h | 9 --------- 1 file changed, 9 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h index a6957a4..b33e2da 100644 --- a/arch/arm/mach-uniphier/dram/umc-regs.h +++ b/arch/arm/mach-uniphier/dram/umc-regs.h @@ -120,15 +120,6 @@

#include <linux/types.h>

-static inline void umc_polling(u32 address, u32 expval, u32 mask) -{ - u32 nmask = ~mask; - u32 data; - do { - data = readl(address) & nmask; - } while (data != expval); -} - static inline void umc_dram_init_start(void __iomem *dramcont) { writel(0x00000002, dramcont + UMC_INITSET);

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 02/21] ARM: uniphier: rework struct uniphier_board_data

This commit reworks "struct uniphier_board_data" with an array of DRAM channel data in it. It will allow further cleanups by means of "for" statements that iterate over the DDR channels.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c | 2 +- arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c | 2 +- arch/arm/mach-uniphier/boards.c | 176 +++++++++++++-------- arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 10 +- arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 16 +- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 10 +- arch/arm/mach-uniphier/dram/umc-proxstream2.c | 12 +- arch/arm/mach-uniphier/init.h | 21 +-- arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c | 6 +- .../mach-uniphier/memconf/memconf-proxstream2.c | 6 +- arch/arm/mach-uniphier/memconf/memconf.c | 14 +- 11 files changed, 161 insertions(+), 114 deletions(-)

diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c index f82c7d1..bbe8a74 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c @@ -22,7 +22,7 @@ int ph1_ld4_bcu_init(const struct uniphier_board_data *bd) writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */

/* Specify DDR channel */ - shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4; + shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4; writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */

shift -= 32; diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c index 75ccd15..b7497e9 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c @@ -26,7 +26,7 @@ int ph1_sld3_bcu_init(const struct uniphier_board_data *bd) writel(0x24440000, BCSCR5);

shift -= 32; diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index d70c712..05b7c76 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -14,106 +14,152 @@ DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) static const struct uniphier_board_data ph1_sld3_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x20000000, - .dram_ch0_width = 32, - .dram_ch1_base = 0xc0000000, - .dram_ch1_size = 0x20000000, - .dram_ch1_width = 16, - .dram_ch2_base = 0xc0000000, - .dram_ch2_size = 0x10000000, - .dram_ch2_width = 16, - .dram_freq = 1600, + .dram_freq = 1600, + .dram_nr_ch = 3, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x20000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xc0000000, + .size = 0x20000000, + .width = 16, + }, + .dram_ch[2] = { + .base = 0xc0000000, + .size = 0x10000000, + .width = 16, + }, }; #endif

#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) static const struct uniphier_board_data ph1_ld4_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x10000000, - .dram_ch0_width = 16, - .dram_ch1_base = 0x90000000, - .dram_ch1_size = 0x10000000, - .dram_ch1_width = 16, - .dram_freq = 1600, + .dram_freq = 1600, + .dram_nr_ch = 2, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x10000000, + .width = 16, + }, + .dram_ch[1] = { + .base = 0x90000000, + .size = 0x10000000, + .width = 16, + }, }; #endif

#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) /* 1GB RAM board */ static const struct uniphier_board_data ph1_pro4_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x20000000, - .dram_ch0_width = 32, - .dram_ch1_base = 0xa0000000, - .dram_ch1_size = 0x20000000, - .dram_ch1_width = 32, - .dram_freq = 1600, + .dram_freq = 1600, + .dram_nr_ch = 2, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x20000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xa0000000, + .size = 0x20000000, + .width = 32, + }, };

/* 2GB RAM board */ static const struct uniphier_board_data ph1_pro4_2g_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x40000000, - .dram_ch0_width = 32, - .dram_ch1_base = 0xc0000000, - .dram_ch1_size = 0x40000000, - .dram_ch1_width = 32, - .dram_freq = 1600, + .dram_freq = 1600, + .dram_nr_ch = 2, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xc0000000, + .size = 0x40000000, + .width = 32, + }, }; #endif

#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) static const struct uniphier_board_data ph1_sld8_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x10000000, - .dram_ch0_width = 16, - .dram_ch1_base = 0x90000000, - .dram_ch1_size = 0x10000000, - .dram_ch1_width = 16, - .dram_freq = 1333, + .dram_freq = 1333, + .dram_nr_ch = 2, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x10000000, + .width = 16, + }, + .dram_ch[1] = { + .base = 0x90000000, + .size = 0x10000000, + .width = 16, + }, }; #endif

#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5) static const struct uniphier_board_data ph1_pro5_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x20000000, - .dram_ch0_width = 32, - .dram_ch1_base = 0xa0000000, - .dram_ch1_size = 0x20000000, - .dram_ch1_width = 32, - .dram_freq = 1866, + .dram_freq = 1866, + .dram_nr_ch = 2, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x20000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xa0000000, + .size = 0x20000000, + .width = 32, + }, }; #endif

#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) static const struct uniphier_board_data proxstream2_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x40000000, - .dram_ch0_width = 32, - .dram_ch1_base = 0xc0000000, - .dram_ch1_size = 0x20000000, - .dram_ch1_width = 32, - .dram_ch2_base = 0xe0000000, - .dram_ch2_size = 0x20000000, - .dram_ch2_width = 16, - .dram_freq = 2133, + .dram_freq = 2133, + .dram_nr_ch = 3, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xc0000000, + .size = 0x20000000, + .width = 32, + }, + .dram_ch[2] = { + .base = 0xe0000000, + .size = 0x20000000, + .width = 16, + }, }; #endif

#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) static const struct uniphier_board_data ph1_ld6b_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x40000000, - .dram_ch0_width = 32, - .dram_ch1_base = 0xc0000000, - .dram_ch1_size = 0x20000000, - .dram_ch1_width = 32, - .dram_ch2_base = 0xe0000000, - .dram_ch2_size = 0x20000000, - .dram_ch2_width = 16, - .dram_freq = 1866, + .dram_freq = 1866, + .dram_nr_ch = 3, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xc0000000, + .size = 0x20000000, + .width = 32, + }, + .dram_ch[2] = { + .base = 0xe0000000, + .size = 0x20000000, + .width = 16, + }, }; #endif

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index ffd7aa9..f2889c0 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -162,13 +162,13 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)

int ph1_ld4_umc_init(const struct uniphier_board_data *bd) { - if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) && - (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) && + if ((bd->dram_ch[0].size == SZ_128M || bd->dram_ch[0].size == SZ_256M) && + (bd->dram_ch[1].size == SZ_128M || bd->dram_ch[1].size == SZ_256M) && (bd->dram_freq == 1333 || bd->dram_freq == 1600) && - bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) { + bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) { return umc_init_sub(bd->dram_freq, - bd->dram_ch0_size / SZ_128M, - bd->dram_ch1_size / SZ_128M); + bd->dram_ch[0].size / SZ_128M, + bd->dram_ch[1].size / SZ_128M); } else { pr_err("Unsupported DDR configuration\n"); return -EINVAL; diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 261f7cf..16c8264 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -146,39 +146,39 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd)

writel(0x00000101, dramcont0 + UMC_DIOCTLA);

- ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch0_size); + ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size);

ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0);

writel(0x00000103, dramcont0 + UMC_DIOCTLA);

- ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch0_size); + ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size);

ddrphy_prepare_training(phy0_1, 1); ddrphy_training(phy0_1);

writel(0x00000101, dramcont1 + UMC_DIOCTLA);

- ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch1_size); + ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size);

ddrphy_prepare_training(phy1_0, 0); ddrphy_training(phy1_0);

writel(0x00000103, dramcont1 + UMC_DIOCTLA);

- ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch1_size); + ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size);

ddrphy_prepare_training(phy1_1, 1); ddrphy_training(phy1_1);

- ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch0_size, - bd->dram_ch0_width); + ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch[0].size, + bd->dram_ch[0].width); if (ret) return ret;

- ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch1_size, - bd->dram_ch1_width); + ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch[1].size, + bd->dram_ch[1].width); if (ret) return ret;

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index 09f9ccf..3c2724e 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -142,13 +142,13 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)

int ph1_sld8_umc_init(const struct uniphier_board_data *bd) { - if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) && - (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) && + if ((bd->dram_ch[0].size == SZ_128M || bd->dram_ch[0].size == SZ_256M) && + (bd->dram_ch[1].size == SZ_128M || bd->dram_ch[1].size == SZ_256M) && bd->dram_freq == 1333 && - bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) { + bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) { return umc_init_sub(bd->dram_freq, - bd->dram_ch0_size / SZ_128M, - bd->dram_ch1_size / SZ_128M); + bd->dram_ch[0].size / SZ_128M, + bd->dram_ch[1].size / SZ_128M); } else { pr_err("Unsupported DDR configuration\n"); return -EINVAL; diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c index 6e7fa88..6e6fff9 100644 --- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -603,22 +603,22 @@ int proxstream2_umc_init(const struct uniphier_board_data *bd) return -EINVAL; }

- ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch0_size / SZ_256M, - bd->dram_ch0_width); + ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch[0].size / SZ_256M, + bd->dram_ch[0].width); if (ret) { printf("failed to initialize UMC ch0\n"); return ret; }

- ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch1_size / SZ_256M, - bd->dram_ch1_width); + ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch[1].size / SZ_256M, + bd->dram_ch[1].width); if (ret) { printf("failed to initialize UMC ch1\n"); return ret; }

- ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch2_size / SZ_256M, - bd->dram_ch2_width); + ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch[2].size / SZ_256M, + bd->dram_ch[2].width); if (ret) { printf("failed to initialize UMC ch2\n"); return ret; diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 0a47e70..aabd84a 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -7,17 +7,18 @@ #ifndef __MACH_INIT_H #define __MACH_INIT_H

+#define UNIPHIER_MAX_NR_DRAM_CH 3 + +struct uniphier_dram_ch { + unsigned long base; + unsigned long size; + unsigned int width; +}; + struct uniphier_board_data { - unsigned long dram_ch0_base; - unsigned long dram_ch0_size; - unsigned long dram_ch0_width; - unsigned long dram_ch1_base; - unsigned long dram_ch1_size; - unsigned long dram_ch1_width; - unsigned long dram_ch2_base; - unsigned long dram_ch2_size; - unsigned long dram_ch2_width; - unsigned int dram_freq; + unsigned int dram_freq; + unsigned int dram_nr_ch; + struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH]; };

const struct uniphier_board_data *uniphier_get_board_param(void); diff --git a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c index 9718cc5..6fdf910 100644 --- a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c +++ b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c @@ -21,14 +21,14 @@ int ph1_sld3_memconf_init(const struct uniphier_board_data *bd)

tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);

- switch (bd->dram_ch2_width) { + switch (bd->dram_ch[2].width) { case 16: tmp |= SG_MEMCONF_CH2_NUM_1; - size_per_word = bd->dram_ch2_size; + size_per_word = bd->dram_ch[2].size; break; case 32: tmp |= SG_MEMCONF_CH2_NUM_2; - size_per_word = bd->dram_ch2_size >> 1; + size_per_word = bd->dram_ch[2].size >> 1; break; default: pr_err("error: unsupported DRAM Ch2 width\n"); diff --git a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c index 9a91fb3..c47fe0a 100644 --- a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c +++ b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c @@ -21,14 +21,14 @@ int proxstream2_memconf_init(const struct uniphier_board_data *bd)

tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);

- switch (bd->dram_ch2_width) { + switch (bd->dram_ch[2].width) { case 16: tmp |= SG_MEMCONF_CH2_NUM_1; - size_per_word = bd->dram_ch2_size; + size_per_word = bd->dram_ch[2].size; break; case 32: tmp |= SG_MEMCONF_CH2_NUM_2; - size_per_word = bd->dram_ch2_size >> 1; + size_per_word = bd->dram_ch[2].size >> 1; break; default: pr_err("error: unsupported DRAM Ch2 width\n"); diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c index f2a0eaf..3d4b504 100644 --- a/arch/arm/mach-uniphier/memconf/memconf.c +++ b/arch/arm/mach-uniphier/memconf/memconf.c @@ -21,14 +21,14 @@ int memconf_init(const struct uniphier_board_data *bd)

tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);

- switch (bd->dram_ch0_width) { + switch (bd->dram_ch[0].width) { case 16: tmp |= SG_MEMCONF_CH0_NUM_1; - size_per_word = bd->dram_ch0_size; + size_per_word = bd->dram_ch[0].size; break; case 32: tmp |= SG_MEMCONF_CH0_NUM_2; - size_per_word = bd->dram_ch0_size >> 1; + size_per_word = bd->dram_ch[0].size >> 1; break; default: pr_err("error: unsupported DRAM Ch0 width\n"); @@ -59,14 +59,14 @@ int memconf_init(const struct uniphier_board_data *bd)

tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);

- switch (bd->dram_ch1_width) { + switch (bd->dram_ch[1].width) { case 16: tmp |= SG_MEMCONF_CH1_NUM_1; - size_per_word = bd->dram_ch1_size; + size_per_word = bd->dram_ch[1].size; break; case 32: tmp |= SG_MEMCONF_CH1_NUM_2; - size_per_word = bd->dram_ch1_size >> 1; + size_per_word = bd->dram_ch[1].size >> 1; break; default: pr_err("error: unsupported DRAM Ch1 width\n"); @@ -94,7 +94,7 @@ int memconf_init(const struct uniphier_board_data *bd) return -EINVAL; }

- if (bd->dram_ch0_base + bd->dram_ch0_size < bd->dram_ch1_base) + if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base) tmp |= SG_MEMCONF_SPARSEMEM; else tmp &= ~SG_MEMCONF_SPARSEMEM;

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 03/21] ARM: uniphier: optimize ProXstream2 UMC init code with "for" loop

Now this code can be re-written with a "for" statement instead of calling the same function multiple times.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-proxstream2.c | 33 +++++++++------------------ 1 file changed, 11 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c index 6e6fff9..dca34ba 100644 --- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -585,11 +585,9 @@ static void um_init(void __iomem *um_base) int proxstream2_umc_init(const struct uniphier_board_data *bd) { void __iomem *um_base = (void __iomem *)0x5b600000; - void __iomem *umc_ch0_base = (void __iomem *)0x5b800000; - void __iomem *umc_ch1_base = (void __iomem *)0x5ba00000; - void __iomem *umc_ch2_base = (void __iomem *)0x5bc00000; + void __iomem *umc_ch_base = (void __iomem *)0x5b800000; enum dram_freq freq; - int ret; + int ch, ret;

switch (bd->dram_freq) { case 1866: @@ -603,25 +601,16 @@ int proxstream2_umc_init(const struct uniphier_board_data *bd) return -EINVAL; }

- ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch[0].size / SZ_256M, - bd->dram_ch[0].width); - if (ret) { - printf("failed to initialize UMC ch0\n"); - return ret; - } - - ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch[1].size / SZ_256M, - bd->dram_ch[1].width); - if (ret) { - printf("failed to initialize UMC ch1\n"); - return ret; - } + for (ch = 0; ch < bd->dram_nr_ch; ch++) { + ret = umc_init(umc_ch_base, freq, ch, + bd->dram_ch[ch].size / SZ_256M, + bd->dram_ch[ch].width); + if (ret) { + printf("failed to initialize UMC ch%d\n", ch); + return ret; + }

- ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch[2].size / SZ_256M, - bd->dram_ch[2].width); - if (ret) { - printf("failed to initialize UMC ch2\n"); - return ret; + umc_ch_base += 0x00200000; }

um_init(um_base);

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 04/21] ARM: uniphier: use pr_err() where possible

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 2 +- arch/arm/mach-uniphier/dram/umc-proxstream2.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 16c8264..ff988e3 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -82,7 +82,7 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, dram_size = DRAM_SZ_512M; break; default: - printf("unsupported DRAM size\n"); + pr_err("unsupported DRAM size\n"); return -EINVAL; }

diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c index dca34ba..d98765b 100644 --- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -344,7 +344,7 @@ static int __ddrphy_training(void __iomem *phy_base,

do { if (--timeout < 0) { - printf("%s: error: timeout during DDR training\n", + pr_err("%s: error: timeout during DDR training\n", __func__); return -ETIMEDOUT; } @@ -354,7 +354,7 @@ static int __ddrphy_training(void __iomem *phy_base,

for (s = seq; s->description; s++) { if (pgsr0 & s->err_flag) { - printf("%s: error: %s failed\n", __func__, + pr_err("%s: error: %s failed\n", __func__, s->description); return -EIO; } @@ -597,7 +597,7 @@ int proxstream2_umc_init(const struct uniphier_board_data *bd) freq = FREQ_2133M; break; default: - printf("unsupported DRAM frequency %d MHz\n", bd->dram_freq); + pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq); return -EINVAL; }

@@ -606,7 +606,7 @@ int proxstream2_umc_init(const struct uniphier_board_data *bd) bd->dram_ch[ch].size / SZ_256M, bd->dram_ch[ch].width); if (ret) { - printf("failed to initialize UMC ch%d\n", ch); + pr_err("failed to initialize UMC ch%d\n", ch); return ret; }

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 05/21] ARM: uniphier: refactor UMC init code for ProXstream2

Currently, a dummy value is defined for the UMC_SPCCTLA register when the DRAM size is zero. This seems weird because the controller does not need setting in the first place if the size is zero.

Also, redefine enum dram_size to represent the DRAM size per 16-bit unit. This makes things simpler because the channel 0 and 1 are connected with 32-bit width DRAM, while the channel 2 is connected with 16-bit width one.

I am renaming SIZE_* into DRAM_SZ_* (and also FREQ_* to DRAM_FREQ_* for consistency) while I am here because SIZE_* might be easily mixed-up with the macros in include/linux/sizes.h.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-proxstream2.c | 109 +++++++++++++++----------- 1 file changed, 64 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c index d98765b..8690906 100644 --- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -18,46 +18,45 @@ #include "ddrmphy-regs.h" #include "umc-regs.h"

-#define CH_NR 3 +#define DRAM_CH_NR 3

enum dram_freq { - FREQ_1866M, - FREQ_2133M, - FREQ_NR, + DRAM_FREQ_1866M, + DRAM_FREQ_2133M, + DRAM_FREQ_NR, };

enum dram_size { - SIZE_0, - SIZE_512M, - SIZE_1G, - SIZE_NR, + DRAM_SZ_256M, + DRAM_SZ_512M, + DRAM_SZ_NR, };

-static u32 ddrphy_pgcr2[FREQ_NR] = {0x00FC7E5D, 0x00FC90AB}; -static u32 ddrphy_ptr0[FREQ_NR] = {0x0EA09205, 0x10C0A6C6}; -static u32 ddrphy_ptr1[FREQ_NR] = {0x0DAC041B, 0x0FA104B1}; -static u32 ddrphy_ptr3[FREQ_NR] = {0x15171e45, 0x18182357}; -static u32 ddrphy_ptr4[FREQ_NR] = {0x0e9ad8e9, 0x10b34157}; -static u32 ddrphy_dtpr0[FREQ_NR] = {0x35a00d88, 0x39e40e88}; -static u32 ddrphy_dtpr1[FREQ_NR] = {0x2288cc2c, 0x228a04d0}; -static u32 ddrphy_dtpr2[FREQ_NR] = {0x50005e00, 0x50006a00}; -static u32 ddrphy_dtpr3[FREQ_NR] = {0x0010cb49, 0x0010ec89}; -static u32 ddrphy_mr0[FREQ_NR] = {0x00000115, 0x00000125}; -static u32 ddrphy_mr2[FREQ_NR] = {0x000002a0, 0x000002a8}; +static u32 ddrphy_pgcr2[DRAM_FREQ_NR] = {0x00FC7E5D, 0x00FC90AB}; +static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0EA09205, 0x10C0A6C6}; +static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x0DAC041B, 0x0FA104B1}; +static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x15171e45, 0x18182357}; +static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x0e9ad8e9, 0x10b34157}; +static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x35a00d88, 0x39e40e88}; +static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x2288cc2c, 0x228a04d0}; +static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x50005e00, 0x50006a00}; +static u32 ddrphy_dtpr3[DRAM_FREQ_NR] = {0x0010cb49, 0x0010ec89}; +static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000115, 0x00000125}; +static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x000002a0, 0x000002a8};

/* dependent on package and board design */ -static u32 ddrphy_acbdlr0[CH_NR] = {0x0000000c, 0x0000000c, 0x00000009}; +static u32 ddrphy_acbdlr0[DRAM_CH_NR] = {0x0000000c, 0x0000000c, 0x00000009};

-static u32 umc_cmdctla[FREQ_NR] = {0x66DD131D, 0x77EE1722}; +static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722}; /* * The ch2 is a different generation UMC core. * The register spec is different, unfortunately. */ -static u32 umc_cmdctlb_ch01[FREQ_NR] = {0x13E87C44, 0x18F88C44}; -static u32 umc_cmdctlb_ch2[FREQ_NR] = {0x19E8DC44, 0x1EF8EC44}; -static u32 umc_spcctla[FREQ_NR][SIZE_NR] = { - {0x00000000, 0x004A071D, 0x0078071D}, - {0x00000000, 0x0055081E, 0x0089081E}, +static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44}; +static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44}; +static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { + {0x004A071D, 0x0078071D}, + {0x0055081E, 0x0089081E}, };

static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B}; @@ -459,18 +458,34 @@ static void umc_ud_init(void __iomem *umc_base, int ch) writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0); }

-static void umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq, - enum dram_size size, int ch, int width) +static int umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq, + unsigned long size, int width, int ch) { + enum dram_size size_e; int latency; u32 val;

+ switch (size) { + case 0: + return 0; + case SZ_256M: + size_e = DRAM_SZ_256M; + break; + case SZ_512M: + size_e = DRAM_SZ_512M; + break; + default: + pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n", + size, ch); + return -EINVAL; + } + writel(umc_cmdctla[freq], umc_dc_base + UMC_CMDCTLA);

writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq], umc_dc_base + UMC_CMDCTLB);

- writel(umc_spcctla[freq][size / (width / 16)], + writel(umc_spcctla[freq][size_e], umc_dc_base + UMC_SPCCTLA); writel(umc_spcctlb[freq], umc_dc_base + UMC_SPCCTLB);

@@ -519,13 +534,15 @@ static void umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq,

writel(0x00000000, umc_dc_base + UMC_ERRMASKA); writel(0x00000000, umc_dc_base + UMC_ERRMASKB); + + return 0; }

-static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch, - enum dram_size size, int width) +static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq, + unsigned long size, unsigned int width, int ch) { - void __iomem *umc_dc_base = umc_base + 0x00011000; - void __iomem *phy_base = umc_base + 0x00030000; + void __iomem *umc_dc_base = umc_ch_base + 0x00011000; + void __iomem *phy_base = umc_ch_base + 0x00030000; int ret;

writel(0x00000002, umc_dc_base + UMC_INITSET); @@ -546,15 +563,15 @@ static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch, if (ret) return ret;

- umc_dc_init(umc_dc_base, freq, size, ch, width); + ret = umc_dc_init(umc_dc_base, freq, size, width, ch); + if (ret) + return ret;

- umc_ud_init(umc_base, ch); + umc_ud_init(umc_ch_base, ch);

- if (size) { - ret = ddrphy_training(phy_base); - if (ret) - return ret; - } + ret = ddrphy_training(phy_base); + if (ret) + return ret;

udelay(1);

@@ -591,10 +608,10 @@ int proxstream2_umc_init(const struct uniphier_board_data *bd)

switch (bd->dram_freq) { case 1866: - freq = FREQ_1866M; + freq = DRAM_FREQ_1866M; break; case 2133: - freq = FREQ_2133M; + freq = DRAM_FREQ_2133M; break; default: pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq); @@ -602,9 +619,11 @@ int proxstream2_umc_init(const struct uniphier_board_data *bd) }

for (ch = 0; ch < bd->dram_nr_ch; ch++) { - ret = umc_init(umc_ch_base, freq, ch, - bd->dram_ch[ch].size / SZ_256M, - bd->dram_ch[ch].width); + unsigned long size = bd->dram_ch[ch].size; + unsigned int width = bd->dram_ch[ch].width; + + ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), + width, ch); if (ret) { pr_err("failed to initialize UMC ch%d\n", ch); return ret;

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 06/21] ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings

These settings were used only for the PH1-sLD3 and older SoCs. The PH1-LD4 and newer one just ignore them because their DDR-PHY take care of such timing parameters instead.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 27 --------------------------- arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 8 -------- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 18 ------------------ arch/arm/mach-uniphier/dram/umc-regs.h | 7 ------- 4 files changed, 60 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index f2889c0..638aa11 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -53,38 +53,11 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, if (freq == 1333) { writel(0x45990b11, dramcont + UMC_CMDCTLA); writel(0x16958924, dramcont + UMC_CMDCTLB); - writel(0x5101046A, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x27028B0A, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x38028B0A, dramcont + UMC_INITCTLB); - - writel(0x000FF0FF, dramcont + UMC_INITCTLC); - writel(0x00000b51, dramcont + UMC_DRMMR0); } else if (freq == 1600) { writel(0x36BB0F17, dramcont + UMC_CMDCTLA); writel(0x18C6AA24, dramcont + UMC_CMDCTLB); - writel(0x5101387F, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x2F030D3F, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x43030D3F, dramcont + UMC_INITCTLB); - - writel(0x00FF00FF, dramcont + UMC_INITCTLC); - writel(0x00000d71, dramcont + UMC_DRMMR0); }

- writel(0x00000006, dramcont + UMC_DRMMR1); - - if (freq == 1333) - writel(0x00000290, dramcont + UMC_DRMMR2); - else if (freq == 1600) - writel(0x00000298, dramcont + UMC_DRMMR2); - - writel(0x00000800, dramcont + UMC_DRMMR3); - if (freq == 1333) { if (size == 1) writel(0x00240512, dramcont + UMC_SPCCTLA); diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index ff988e3..c28492c 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -20,7 +20,6 @@ enum dram_size { DRAM_SZ_NR, };

-static u32 umc_initctlb[DRAM_SZ_NR] = {0x43030d3f, 0x43030d3f, 0x7b030d3f}; static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};

static void umc_start_ssif(void __iomem *ssif_base) @@ -88,13 +87,6 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,

writel(0x66bb0f17, dramcont + UMC_CMDCTLA); writel(0x18c6aa44, dramcont + UMC_CMDCTLB); - writel(0x5101387f, dramcont + UMC_INITCTLA); - writel(umc_initctlb[dram_size], dramcont + UMC_INITCTLB); - writel(0x00ff00ff, dramcont + UMC_INITCTLC); - writel(0x00000d71, dramcont + UMC_DRMMR0); - writel(0x00000006, dramcont + UMC_DRMMR1); - writel(0x00000298, dramcont + UMC_DRMMR2); - writel(0x00000000, dramcont + UMC_DRMMR3); writel(umc_spcctla[dram_size], dramcont + UMC_SPCCTLA); writel(0x00ff0008, dramcont + UMC_SPCCTLB); writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index 3c2724e..fa0619f 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -58,24 +58,6 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x16958924, dramcont + UMC_CMDCTLB); #endif

- writel(0x5101046A, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x27028B0A, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x38028B0A, dramcont + UMC_INITCTLB); - - writel(0x00FF00FF, dramcont + UMC_INITCTLC); - writel(0x00000b51, dramcont + UMC_DRMMR0); - writel(0x00000006, dramcont + UMC_DRMMR1); - writel(0x00000290, dramcont + UMC_DRMMR2); - -#ifdef CONFIG_DDR_STANDARD - writel(0x00000000, dramcont + UMC_DRMMR3); -#else - writel(0x00000800, dramcont + UMC_DRMMR3); -#endif - if (size == 1) writel(0x00240512, dramcont + UMC_SPCCTLA); else if (size == 2) diff --git a/arch/arm/mach-uniphier/dram/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h index b33e2da..311cf3d 100644 --- a/arch/arm/mach-uniphier/dram/umc-regs.h +++ b/arch/arm/mach-uniphier/dram/umc-regs.h @@ -56,15 +56,8 @@

#define UMC_CMDCTLA 0x00000000 #define UMC_CMDCTLB 0x00000004 -#define UMC_INITCTLA 0x00000008 -#define UMC_INITCTLB 0x0000000C -#define UMC_INITCTLC 0x00000010 #define UMC_INITSET 0x00000014 #define UMC_INITSTAT 0x00000018 -#define UMC_DRMMR0 0x0000001C -#define UMC_DRMMR1 0x00000020 -#define UMC_DRMMR2 0x00000024 -#define UMC_DRMMR3 0x00000028 #define UMC_SPCCTLA 0x00000030 #define UMC_SPCCTLB 0x00000034 #define UMC_SPCSETA 0x00000038

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 07/21] ARM: uniphier: disable debug circuit clocks for PH1-Pro4

These settings control the clocks around the memory controller. The debug ability is unneeded once it works properly.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index c28492c..f89b1da 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -24,9 +24,9 @@ static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};

static void umc_start_ssif(void __iomem *ssif_base) { - writel(0x00000001, ssif_base + 0x0000b004); + writel(0x00000000, ssif_base + 0x0000b004); writel(0xffffffff, ssif_base + 0x0000c004); - writel(0x07ffffff, ssif_base + 0x0000c008); + writel(0x000fffcf, ssif_base + 0x0000c008); writel(0x00000001, ssif_base + 0x0000b000); writel(0x00000001, ssif_base + 0x0000c000);

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 08/21] ARM: uniphier: add a field to specify DDR3+

Add a field to distinguish DDR3+ from (standard) DDR3. It also allows to delete CONFIG_DDR_STANDARD (this is not a software configuration, but a board attribute).

Default DDR3 spec for each SoC:

PH1-LD4, PH1-sLD8: DDR3+ Others: DDR3

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/boards.c | 2 ++ arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c | 5 +++-- arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c | 5 +++-- arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c | 9 +++------ arch/arm/mach-uniphier/dram/ddrphy-regs.h | 10 +++++++--- arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 9 +++++---- arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 12 ++++++++---- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 24 ++++++++++-------------- arch/arm/mach-uniphier/init.h | 3 +++ 9 files changed, 44 insertions(+), 35 deletions(-)

diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index 05b7c76..408aff0 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -38,6 +38,7 @@ static const struct uniphier_board_data ph1_sld3_data = { static const struct uniphier_board_data ph1_ld4_data = { .dram_freq = 1600, .dram_nr_ch = 2, + .dram_ddr3plus = true, .dram_ch[0] = { .base = 0x80000000, .size = 0x10000000, @@ -89,6 +90,7 @@ static const struct uniphier_board_data ph1_pro4_2g_data = { static const struct uniphier_board_data ph1_sld8_data = { .dram_freq = 1333, .dram_nr_ch = 2, + .dram_ddr3plus = true, .dram_ch[0] = { .base = 0x80000000, .size = 0x10000000, diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c index d2bc5a1..3000a28 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c @@ -9,7 +9,8 @@

#include "ddrphy-regs.h"

-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, + bool ddr3plus) { u32 tmp;

@@ -61,7 +62,7 @@ int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) else writel(0x00000298, &phy->mr2);

- writel(0x00000800, &phy->mr3); + writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);

while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) ; diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c index 9fb34f7..b4dca35 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c @@ -9,7 +9,8 @@

#include "ddrphy-regs.h"

-int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, + bool ddr3plus) { u32 tmp;

@@ -55,7 +56,7 @@ int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) else writel(0x00000298, &phy->mr2);

- writel(0x00000000, &phy->mr3); + writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);

while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) ; diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c index 6510690..0d2ae42 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c @@ -10,7 +10,8 @@

#include "ddrphy-regs.h"

-int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, + bool ddr3plus) { u32 tmp;

@@ -62,11 +63,7 @@ int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) else writel(0x00000298, &phy->mr2);

-#ifdef CONFIG_DDR_STANDARD - writel(0x00000000, &phy->mr3); -#else - writel(0x00000800, &phy->mr3); -#endif + writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);

while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) ; diff --git a/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h index 03aedc2..206fabd 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h @@ -11,6 +11,7 @@

#include <linux/bitops.h> #include <linux/compiler.h> +#include <linux/types.h>

#ifndef __ASSEMBLY__

@@ -169,9 +170,12 @@ struct ddrphy { #define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))

#ifndef __ASSEMBLY__ -int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); -int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); -int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, + bool ddr3plus); +int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, + bool ddr3plus); +int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, + bool ddr3plus); void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); int ddrphy_training(struct ddrphy __iomem *phy); #endif diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 638aa11..957a38f 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -96,7 +96,7 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x00000520, dramcont + UMC_DFICUPDCTLA); }

-static int umc_init_sub(int freq, int size_ch0, int size_ch1) +static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus) { void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); @@ -113,14 +113,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)

writel(0x00000101, dramcont0 + UMC_DIOCTLA);

- ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0); + ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);

ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0);

writel(0x00000101, dramcont1 + UMC_DIOCTLA);

- ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1); + ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);

ddrphy_prepare_training(phy1_0, 1); ddrphy_training(phy1_0); @@ -141,7 +141,8 @@ int ph1_ld4_umc_init(const struct uniphier_board_data *bd) bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) { return umc_init_sub(bd->dram_freq, bd->dram_ch[0].size / SZ_128M, - bd->dram_ch[1].size / SZ_128M); + bd->dram_ch[1].size / SZ_128M, + bd->dram_ddr3plus); } else { pr_err("Unsupported DDR configuration\n"); return -EINVAL; diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index f89b1da..38dd338 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -138,28 +138,32 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd)

writel(0x00000101, dramcont0 + UMC_DIOCTLA);

- ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size); + ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size, + bd->dram_ddr3plus);

ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0);

writel(0x00000103, dramcont0 + UMC_DIOCTLA);

- ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size); + ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size, + bd->dram_ddr3plus);

ddrphy_prepare_training(phy0_1, 1); ddrphy_training(phy0_1);

writel(0x00000101, dramcont1 + UMC_DIOCTLA);

- ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size); + ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size, + bd->dram_ddr3plus);

ddrphy_prepare_training(phy1_0, 0); ddrphy_training(phy1_0);

writel(0x00000103, dramcont1 + UMC_DIOCTLA);

- ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size); + ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size, + bd->dram_ddr3plus);

ddrphy_prepare_training(phy1_1, 1); ddrphy_training(phy1_1); diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index fa0619f..3cbb7ba 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -48,15 +48,10 @@ static void umc_start_ssif(void __iomem *ssif_base) }

static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) + int size, int freq, bool ddr3plus) { -#ifdef CONFIG_DDR_STANDARD - writel(0x55990b11, dramcont + UMC_CMDCTLA); - writel(0x16958944, dramcont + UMC_CMDCTLB); -#else - writel(0x45990b11, dramcont + UMC_CMDCTLA); - writel(0x16958924, dramcont + UMC_CMDCTLB); -#endif + writel(ddr3plus ? 0x45990b11 : 0x55990b11, dramcont + UMC_CMDCTLA); + writel(ddr3plus ? 0x16958924 : 0x16958944, dramcont + UMC_CMDCTLB);

if (size == 1) writel(0x00240512, dramcont + UMC_SPCCTLA); @@ -85,7 +80,7 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x00000520, dramcont + UMC_DFICUPDCTLA); }

-static int umc_init_sub(int freq, int size_ch0, int size_ch1) +static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus) { void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); @@ -102,20 +97,20 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)

writel(0x00000101, dramcont0 + UMC_DIOCTLA);

- ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0); + ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);

ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0);

writel(0x00000101, dramcont1 + UMC_DIOCTLA);

- ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1); + ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);

ddrphy_prepare_training(phy1_0, 1); ddrphy_training(phy1_0);

- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq, ddr3plus); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq, ddr3plus);

umc_start_ssif(ssif_base);

@@ -130,7 +125,8 @@ int ph1_sld8_umc_init(const struct uniphier_board_data *bd) bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) { return umc_init_sub(bd->dram_freq, bd->dram_ch[0].size / SZ_128M, - bd->dram_ch[1].size / SZ_128M); + bd->dram_ch[1].size / SZ_128M, + bd->dram_ddr3plus); } else { pr_err("Unsupported DDR configuration\n"); return -EINVAL; diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index aabd84a..e969fd0 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -7,6 +7,8 @@ #ifndef __MACH_INIT_H #define __MACH_INIT_H

+#include <linux/types.h> + #define UNIPHIER_MAX_NR_DRAM_CH 3

struct uniphier_dram_ch { @@ -18,6 +20,7 @@ struct uniphier_dram_ch { struct uniphier_board_data { unsigned int dram_freq; unsigned int dram_nr_ch; + bool dram_ddr3plus; struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH]; };

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 09/21] ARM: uniphier: merge DDR PHY init code for 3 SoCs

Now these three are almost the same. The only difference is the DTPR1 register dependency on the DRAM size, but it can be ignored. (It has already been ignored in PH1-sLD8 and PH1-Pro4.)

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/Makefile | 4 +- arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c | 10 +--- arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c | 68 ------------------------ arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c | 75 --------------------------- arch/arm/mach-uniphier/dram/ddrphy-regs.h | 4 -- arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 16 +++--- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 4 +- 7 files changed, 14 insertions(+), 167 deletions(-) delete mode 100644 arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c delete mode 100644 arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c

diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index a0a6003..3d1553c 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -7,9 +7,9 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o \ ddrphy-training.o ddrphy-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o \ - ddrphy-training.o ddrphy-ph1-pro4.o + ddrphy-training.o ddrphy-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \ - ddrphy-training.o ddrphy-ph1-sld8.o + ddrphy-training.o ddrphy-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += umc-proxstream2.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += umc-proxstream2.o

diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c index 3000a28..27be1cc 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c @@ -41,18 +41,12 @@ int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, writel(0x0000040B, &phy->dcr); if (freq == 1333) { writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8253c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x1a8363c0, &phy->dtpr[1]); writel(0x5002c200, &phy->dtpr[2]); writel(0x00000b51, &phy->mr0); } else { writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a82dbc0, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); + writel(0x1a878400, &phy->dtpr[1]); writel(0xa00214f8, &phy->dtpr[2]); writel(0x00000d71, &phy->mr0); } diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c deleted file mode 100644 index b4dca35..0000000 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada yamada.masahiro@socionext.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/types.h> -#include <linux/io.h> - -#include "ddrphy-regs.h" - -int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, - bool ddr3plus) -{ - u32 tmp; - - writel(0x0300c473, &phy->pgcr[1]); - if (freq == 1333) { - writel(0x0a806844, &phy->ptr[0]); - writel(0x208e0124, &phy->ptr[1]); - } else { - writel(0x0c807d04, &phy->ptr[0]); - writel(0x2710015E, &phy->ptr[1]); - } - writel(0x00083DEF, &phy->ptr[2]); - if (freq == 1333) { - writel(0x0f051616, &phy->ptr[3]); - writel(0x06ae08d6, &phy->ptr[4]); - } else { - writel(0x12061A80, &phy->ptr[3]); - writel(0x08027100, &phy->ptr[4]); - } - writel(0xF004001A, &phy->dsgcr); - - /* change the value of the on-die pull-up/pull-down registors */ - tmp = readl(&phy->dxccr); - tmp &= ~0x0ee0; - tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; - writel(tmp, &phy->dxccr); - - writel(0x0000040B, &phy->dcr); - if (freq == 1333) { - writel(0x85589955, &phy->dtpr[0]); - writel(0x1a8363c0, &phy->dtpr[1]); - writel(0x5002c200, &phy->dtpr[2]); - writel(0x00000b51, &phy->mr0); - } else { - writel(0x999cbb66, &phy->dtpr[0]); - writel(0x1a878400, &phy->dtpr[1]); - writel(0xa00214f8, &phy->dtpr[2]); - writel(0x00000d71, &phy->mr0); - } - writel(0x00000006, &phy->mr1); - if (freq == 1333) - writel(0x00000290, &phy->mr2); - else - writel(0x00000298, &phy->mr2); - - writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3); - - while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) - ; - - writel(0x0300C473, &phy->pgcr[1]); - writel(0x0000005D, &phy->zq[0].cr[1]); - - return 0; -} diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c deleted file mode 100644 index 0d2ae42..0000000 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada yamada.masahiro@socionext.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <linux/types.h> -#include <linux/io.h> - -#include "ddrphy-regs.h" - -int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, - bool ddr3plus) -{ - u32 tmp; - - writel(0x0300c473, &phy->pgcr[1]); - if (freq == 1333) { - writel(0x0a806844, &phy->ptr[0]); - writel(0x208e0124, &phy->ptr[1]); - } else { - writel(0x0c807d04, &phy->ptr[0]); - writel(0x2710015E, &phy->ptr[1]); - } - writel(0x00083DEF, &phy->ptr[2]); - if (freq == 1333) { - writel(0x0f051616, &phy->ptr[3]); - writel(0x06ae08d6, &phy->ptr[4]); - } else { - writel(0x12061A80, &phy->ptr[3]); - writel(0x08027100, &phy->ptr[4]); - } - writel(0xF004001A, &phy->dsgcr); - - /* change the value of the on-die pull-up/pull-down registors */ - tmp = readl(&phy->dxccr); - tmp &= ~0x0ee0; - tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; - writel(tmp, &phy->dxccr); - - writel(0x0000040B, &phy->dcr); - if (freq == 1333) { - writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8363c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); - writel(0x5002c200, &phy->dtpr[2]); - writel(0x00000b51, &phy->mr0); - } else { - writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a878400, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); - writel(0xa00214f8, &phy->dtpr[2]); - writel(0x00000d71, &phy->mr0); - } - writel(0x00000006, &phy->mr1); - if (freq == 1333) - writel(0x00000290, &phy->mr2); - else - writel(0x00000298, &phy->mr2); - - writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3); - - while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) - ; - - writel(0x0300C473, &phy->pgcr[1]); - writel(0x0000005D, &phy->zq[0].cr[1]); - - return 0; -} diff --git a/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h index 206fabd..a466118 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h @@ -172,10 +172,6 @@ struct ddrphy { #ifndef __ASSEMBLY__ int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, bool ddr3plus); -int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, - bool ddr3plus); -int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, - bool ddr3plus); void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); int ddrphy_training(struct ddrphy __iomem *phy); #endif diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 38dd338..877f5ef 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -138,32 +138,32 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd)

writel(0x00000101, dramcont0 + UMC_DIOCTLA);

- ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size, + bd->dram_ddr3plus);

ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0);

writel(0x00000103, dramcont0 + UMC_DIOCTLA);

- ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size, + bd->dram_ddr3plus);

ddrphy_prepare_training(phy0_1, 1); ddrphy_training(phy0_1);

writel(0x00000101, dramcont1 + UMC_DIOCTLA);

- ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size, + bd->dram_ddr3plus);

ddrphy_prepare_training(phy1_0, 0); ddrphy_training(phy1_0);

writel(0x00000103, dramcont1 + UMC_DIOCTLA);

- ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size, + bd->dram_ddr3plus);

ddrphy_prepare_training(phy1_1, 1); ddrphy_training(phy1_1); diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index 3cbb7ba..a27f91f 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -97,14 +97,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)

writel(0x00000101, dramcont0 + UMC_DIOCTLA);

- ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus); + ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);

ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0);

writel(0x00000101, dramcont1 + UMC_DIOCTLA);

- ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus); + ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);

ddrphy_prepare_training(phy1_0, 1); ddrphy_training(phy1_0);

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 10/21] ARM: uniphier: remove unused argument of ph1_ld4_ddrphy_init()

The DDR PHY settings no longer depend on the DRAM size. Drop the argument from the init function.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c | 3 +-- arch/arm/mach-uniphier/dram/ddrphy-regs.h | 3 +-- arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 4 ++-- arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 12 ++++-------- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 4 ++-- 5 files changed, 10 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c index 27be1cc..ef1941e 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c @@ -9,8 +9,7 @@

#include "ddrphy-regs.h"

-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, - bool ddr3plus) +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus) { u32 tmp;

diff --git a/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h index a466118..87f6d0d 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h @@ -170,8 +170,7 @@ struct ddrphy { #define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))

#ifndef __ASSEMBLY__ -int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, - bool ddr3plus); +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus); void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); int ddrphy_training(struct ddrphy __iomem *phy); #endif diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 957a38f..bee3ef4 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -113,14 +113,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)

writel(0x00000101, dramcont0 + UMC_DIOCTLA);

- ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus); + ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus);

ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0);

writel(0x00000101, dramcont1 + UMC_DIOCTLA);

- ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus); + ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus);

ddrphy_prepare_training(phy1_0, 1); ddrphy_training(phy1_0); diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 877f5ef..0a2485e 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -138,32 +138,28 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd)

writel(0x00000101, dramcont0 + UMC_DIOCTLA);

- ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ddr3plus);

ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0);

writel(0x00000103, dramcont0 + UMC_DIOCTLA);

- ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ddr3plus);

ddrphy_prepare_training(phy0_1, 1); ddrphy_training(phy0_1);

writel(0x00000101, dramcont1 + UMC_DIOCTLA);

- ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ddr3plus);

ddrphy_prepare_training(phy1_0, 0); ddrphy_training(phy1_0);

writel(0x00000103, dramcont1 + UMC_DIOCTLA);

- ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ddr3plus);

ddrphy_prepare_training(phy1_1, 1); ddrphy_training(phy1_1); diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index a27f91f..73ad934 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -97,14 +97,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)

writel(0x00000101, dramcont0 + UMC_DIOCTLA);

- ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus); + ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus);

ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0);

writel(0x00000101, dramcont1 + UMC_DIOCTLA);

- ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus); + ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus);

ddrphy_prepare_training(phy1_0, 1); ddrphy_training(phy1_0);

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 11/21] ARM: uniphier: refactor DDR-PHY init code

The if-else statements for the frequency-dependent register settings seem clumsy. Moving them to arrays would make it cleaner.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c | 70 ++++++++++++++++------------ 1 file changed, 40 insertions(+), 30 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c index ef1941e..eb9bf24 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c @@ -4,31 +4,52 @@ * SPDX-License-Identifier: GPL-2.0+ */

+#include <common.h> +#include <linux/err.h> #include <linux/types.h> #include <linux/io.h>

#include "ddrphy-regs.h"

+enum dram_freq { + DRAM_FREQ_1333M, + DRAM_FREQ_1600M, + DRAM_FREQ_NR, +}; + +static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04}; +static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E}; +static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80}; +static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100}; +static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66}; +static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400}; +static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8}; +static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71}; +static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298}; + int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus) { + enum dram_freq freq_e; u32 tmp;

- writel(0x0300c473, &phy->pgcr[1]); - if (freq == 1333) { - writel(0x0a806844, &phy->ptr[0]); - writel(0x208e0124, &phy->ptr[1]); - } else { - writel(0x0c807d04, &phy->ptr[0]); - writel(0x2710015E, &phy->ptr[1]); + switch (freq) { + case 1333: + freq_e = DRAM_FREQ_1333M; + break; + case 1600: + freq_e = DRAM_FREQ_1600M; + break; + default: + printf("unsupported DRAM frequency %d MHz\n", freq); + return -EINVAL; } + + writel(0x0300c473, &phy->pgcr[1]); + writel(ddrphy_ptr0[freq_e], &phy->ptr[0]); + writel(ddrphy_ptr1[freq_e], &phy->ptr[1]); writel(0x00083DEF, &phy->ptr[2]); - if (freq == 1333) { - writel(0x0f051616, &phy->ptr[3]); - writel(0x06ae08d6, &phy->ptr[4]); - } else { - writel(0x12061A80, &phy->ptr[3]); - writel(0x08027100, &phy->ptr[4]); - } + writel(ddrphy_ptr3[freq_e], &phy->ptr[3]); + writel(ddrphy_ptr4[freq_e], &phy->ptr[4]); writel(0xF004001A, &phy->dsgcr);

/* change the value of the on-die pull-up/pull-down registors */ @@ -38,23 +59,12 @@ int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus) writel(tmp, &phy->dxccr);

writel(0x0000040B, &phy->dcr); - if (freq == 1333) { - writel(0x85589955, &phy->dtpr[0]); - writel(0x1a8363c0, &phy->dtpr[1]); - writel(0x5002c200, &phy->dtpr[2]); - writel(0x00000b51, &phy->mr0); - } else { - writel(0x999cbb66, &phy->dtpr[0]); - writel(0x1a878400, &phy->dtpr[1]); - writel(0xa00214f8, &phy->dtpr[2]); - writel(0x00000d71, &phy->mr0); - } + writel(ddrphy_dtpr0[freq_e], &phy->dtpr[0]); + writel(ddrphy_dtpr1[freq_e], &phy->dtpr[1]); + writel(ddrphy_dtpr2[freq_e], &phy->dtpr[2]); + writel(ddrphy_mr0[freq_e], &phy->mr0); writel(0x00000006, &phy->mr1); - if (freq == 1333) - writel(0x00000290, &phy->mr2); - else - writel(0x00000298, &phy->mr2); - + writel(ddrphy_mr2[freq_e], &phy->mr2); writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);

while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 12/21] ARM: uniphier: refactor UMC init code for PH1-sLD8

Move frequency-dependent register settings to arrays for clean-up.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 37 +++++++++++++++++++++++------- 1 file changed, 29 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index 73ad934..5e333e0 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -13,6 +13,14 @@ #include "ddrphy-regs.h" #include "umc-regs.h"

+enum dram_size { + DRAM_SZ_128M, + DRAM_SZ_256M, + DRAM_SZ_NR, +}; + +static u32 umc_spcctla[DRAM_SZ_NR] = {0x00240512, 0x00350512}; + static void umc_start_ssif(void __iomem *ssif_base) { writel(0x00000000, ssif_base + 0x0000b004); @@ -47,17 +55,28 @@ static void umc_start_ssif(void __iomem *ssif_base) writel(0x00000001, ssif_base + UMC_DMDRST); }

-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq, bool ddr3plus) +static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq, bool ddr3plus) { + enum dram_size size_e; + + switch (size) { + case 0: + return 0; + case 1: + size_e = DRAM_SZ_128M; + break; + case 2: + size_e = DRAM_SZ_256M; + break; + default: + pr_err("unsupported DRAM size\n"); + return -EINVAL; + } + writel(ddr3plus ? 0x45990b11 : 0x55990b11, dramcont + UMC_CMDCTLA); writel(ddr3plus ? 0x16958924 : 0x16958944, dramcont + UMC_CMDCTLB); - - if (size == 1) - writel(0x00240512, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x00350512, dramcont + UMC_SPCCTLA); - + writel(umc_spcctla[size_e], dramcont + UMC_SPCCTLA); writel(0x00ff0006, dramcont + UMC_SPCCTLB); writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); writel(0x04060806, dramcont + UMC_WDATACTL_D0); @@ -78,6 +97,8 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x200a0a00, dramcont + UMC_SPCSETB); writel(0x00000000, dramcont + UMC_SPCSETD); writel(0x00000520, dramcont + UMC_DFICUPDCTLA); + + return 0; }

static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 13/21] ARM: uniphier: support more DRAM use cases for PH1-sLD8

Support DDR3-1600 / 512MB DDR size.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 46 ++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index 5e333e0..b8d729c 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -13,13 +13,29 @@ #include "ddrphy-regs.h" #include "umc-regs.h"

+enum dram_freq { + DRAM_FREQ_1333M, + DRAM_FREQ_1600M, + DRAM_FREQ_NR, +}; + enum dram_size { DRAM_SZ_128M, DRAM_SZ_256M, + DRAM_SZ_512M, DRAM_SZ_NR, };

-static u32 umc_spcctla[DRAM_SZ_NR] = {0x00240512, 0x00350512}; +static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17}; +static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17}; +static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44}; +static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24}; +static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { + {0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */ + {0x002b0617, 0x003f0617, 0x00670617}, +}; +static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008}; +static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac};

static void umc_start_ssif(void __iomem *ssif_base) { @@ -58,8 +74,21 @@ static void umc_start_ssif(void __iomem *ssif_base) static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, int size, int freq, bool ddr3plus) { + enum dram_freq freq_e; enum dram_size size_e;

+ switch (freq) { + case 1333: + freq_e = DRAM_FREQ_1333M; + break; + case 1600: + freq_e = DRAM_FREQ_1600M; + break; + default: + pr_err("unsupported DRAM frequency %d MHz\n", freq); + return -EINVAL; + } + switch (size) { case 0: return 0; @@ -69,16 +98,21 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, case 2: size_e = DRAM_SZ_256M; break; + case 4: + size_e = DRAM_SZ_512M; + break; default: pr_err("unsupported DRAM size\n"); return -EINVAL; }

- writel(ddr3plus ? 0x45990b11 : 0x55990b11, dramcont + UMC_CMDCTLA); - writel(ddr3plus ? 0x16958924 : 0x16958944, dramcont + UMC_CMDCTLB); - writel(umc_spcctla[size_e], dramcont + UMC_SPCCTLA); - writel(0x00ff0006, dramcont + UMC_SPCCTLB); - writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); + writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e], + dramcont + UMC_CMDCTLA); + writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e], + dramcont + UMC_CMDCTLB); + writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA); + writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB); + writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0); writel(0x04060806, dramcont + UMC_WDATACTL_D0); writel(0x04a02000, dramcont + UMC_DATASET); writel(0x00000000, ca_base + 0x2300);

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 14/21] ARM: uniphier: refactor UMC init code for PH1-LD4

Move frequency-dependent register settings to arrays for clean-up.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 79 +++++++++++++++++++++---------- 1 file changed, 55 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index bee3ef4..353ef69 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -13,6 +13,27 @@ #include "ddrphy-regs.h" #include "umc-regs.h"

+enum dram_freq { + DRAM_FREQ_1333M, + DRAM_FREQ_1600M, + DRAM_FREQ_NR, +}; + +enum dram_size { + DRAM_SZ_128M, + DRAM_SZ_256M, + DRAM_SZ_NR, +}; + +static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17}; +static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24}; +static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { + {0x00240512, 0x00350512}, + {0x002b0617, 0x003f0617}, +}; +static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008}; +static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae}; + static void umc_start_ssif(void __iomem *ssif_base) { writel(0x00000000, ssif_base + 0x0000b004); @@ -47,35 +68,43 @@ static void umc_start_ssif(void __iomem *ssif_base) writel(0x00000001, ssif_base + UMC_DMDRST); }

-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) +static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) { - if (freq == 1333) { - writel(0x45990b11, dramcont + UMC_CMDCTLA); - writel(0x16958924, dramcont + UMC_CMDCTLB); - } else if (freq == 1600) { - writel(0x36BB0F17, dramcont + UMC_CMDCTLA); - writel(0x18C6AA24, dramcont + UMC_CMDCTLB); + enum dram_freq freq_e; + enum dram_size size_e; + + switch (freq) { + case 1333: + freq_e = DRAM_FREQ_1333M; + break; + case 1600: + freq_e = DRAM_FREQ_1600M; + break; + default: + pr_err("unsupported DRAM frequency %d MHz\n", freq); + return -EINVAL; }

- if (freq == 1333) { - if (size == 1) - writel(0x00240512, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x00350512, dramcont + UMC_SPCCTLA); - - writel(0x00ff0006, dramcont + UMC_SPCCTLB); - writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); - } else if (freq == 1600) { - if (size == 1) - writel(0x002B0617, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x003F0617, dramcont + UMC_SPCCTLA); - - writel(0x00ff0008, dramcont + UMC_SPCCTLB); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + switch (size) { + case 0: + return 0; + case 1: + size_e = DRAM_SZ_128M; + break; + case 2: + size_e = DRAM_SZ_256M; + break; + default: + pr_err("unsupported DRAM size\n"); + return -EINVAL; }

+ writel(umc_cmdctla_plus[freq_e], dramcont + UMC_CMDCTLA); + writel(umc_cmdctlb_plus[freq_e], dramcont + UMC_CMDCTLB); + writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA); + writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB); + writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0); writel(0x04060806, dramcont + UMC_WDATACTL_D0); writel(0x04a02000, dramcont + UMC_DATASET); writel(0x00000000, ca_base + 0x2300); @@ -94,6 +123,8 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x200a0a00, dramcont + UMC_SPCSETB); writel(0x00000000, dramcont + UMC_SPCSETD); writel(0x00000520, dramcont + UMC_DFICUPDCTLA); + + return 0; }

static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 15/21] ARM: uniphier: optimize PH1-sLD8 UMC init code with "for" loop

Now this code can be re-written with a "for" statement instead of calling the same function multiple times.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 83 ++++++++++++++++-------------- 1 file changed, 43 insertions(+), 40 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index b8d729c..a2ed9ba 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -13,6 +13,8 @@ #include "ddrphy-regs.h" #include "umc-regs.h"

+#define DRAM_CH_NR 2 + enum dram_freq { DRAM_FREQ_1333M, DRAM_FREQ_1600M, @@ -37,6 +39,11 @@ static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008}; static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac};

+static int umc_get_rank(int ch) +{ + return ch; /* ch0: rank0, ch1: rank1 for this SoC */ +} + static void umc_start_ssif(void __iomem *ssif_base) { writel(0x00000000, ssif_base + 0x0000b004); @@ -135,55 +142,51 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, return 0; }

-static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus) +static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, + int freq, int size, bool ddr3plus, int ch) { - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); - - writel(0x00000101, dramcont0 + UMC_DIOCTLA); - - ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus); - - ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); + void __iomem *phy_base = dc_base + 0x00001000; + int ret;

- writel(0x00000101, dramcont1 + UMC_DIOCTLA); + umc_dram_init_start(dc_base); + umc_dram_init_poll(dc_base);

- ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus); + writel(0x00000101, dc_base + UMC_DIOCTLA);

- ddrphy_prepare_training(phy1_0, 1); - ddrphy_training(phy1_0); + ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus); + if (ret) + return ret;

- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq, ddr3plus); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq, ddr3plus); + ddrphy_prepare_training(phy_base, umc_get_rank(ch)); + ret = ddrphy_training(phy_base); + if (ret) + return ret;

- umc_start_ssif(ssif_base); - - return 0; + return umc_dramcont_init(dc_base, ca_base, size, freq, ddr3plus); }

int ph1_sld8_umc_init(const struct uniphier_board_data *bd) { - if ((bd->dram_ch[0].size == SZ_128M || bd->dram_ch[0].size == SZ_256M) && - (bd->dram_ch[1].size == SZ_128M || bd->dram_ch[1].size == SZ_256M) && - bd->dram_freq == 1333 && - bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) { - return umc_init_sub(bd->dram_freq, - bd->dram_ch[0].size / SZ_128M, - bd->dram_ch[1].size / SZ_128M, - bd->dram_ddr3plus); - } else { - pr_err("Unsupported DDR configuration\n"); - return -EINVAL; + void __iomem *umc_base = (void __iomem *)0x5b800000; + void __iomem *ca_base = umc_base + 0x00001000; + void __iomem *dc_base = umc_base + 0x00400000; + void __iomem *ssif_base = umc_base; + int ch, ret; + + for (ch = 0; ch < DRAM_CH_NR; ch++) { + ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, + bd->dram_ch[ch].size / SZ_128M, + bd->dram_ddr3plus, ch); + if (ret) { + pr_err("failed to initialize UMC ch%d\n", ch); + return ret; + } + + ca_base += 0x00001000; + dc_base += 0x00200000; } + + umc_start_ssif(ssif_base); + + return 0; }

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 16/21] ARM: uniphier: optimize PH1-LD4 UMC init code with "for" loop

Now this code can be re-written with a "for" statement instead of calling the same function multiple times.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 90 +++++++++++++++++-------------- 1 file changed, 49 insertions(+), 41 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 353ef69..92b0f18 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -13,6 +13,8 @@ #include "ddrphy-regs.h" #include "umc-regs.h"

+#define DRAM_CH_NR 2 + enum dram_freq { DRAM_FREQ_1333M, DRAM_FREQ_1600M, @@ -34,6 +36,11 @@ static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008}; static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae};

+static int umc_get_rank(int ch) +{ + return ch; /* ch0: rank0, ch1: rank1 for this SoC */ +} + static void umc_start_ssif(void __iomem *ssif_base) { writel(0x00000000, ssif_base + 0x0000b004); @@ -69,11 +76,16 @@ static void umc_start_ssif(void __iomem *ssif_base) }

static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) + int size, int freq, bool ddr3plus) { enum dram_freq freq_e; enum dram_size size_e;

+ if (!ddr3plus) { + pr_err("DDR3 standard is not supported\n"); + return -EINVAL; + } + switch (freq) { case 1333: freq_e = DRAM_FREQ_1333M; @@ -127,55 +139,51 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, return 0; }

-static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus) +static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, + int freq, int size, bool ddr3plus, int ch) { - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); - - writel(0x00000101, dramcont0 + UMC_DIOCTLA); - - ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus); + void __iomem *phy_base = dc_base + 0x00001000; + int ret;

- ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); + umc_dram_init_start(dc_base); + umc_dram_init_poll(dc_base);

- writel(0x00000101, dramcont1 + UMC_DIOCTLA); + writel(0x00000101, dc_base + UMC_DIOCTLA);

- ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus); + ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus); + if (ret) + return ret;

- ddrphy_prepare_training(phy1_0, 1); - ddrphy_training(phy1_0); + ddrphy_prepare_training(phy_base, umc_get_rank(ch)); + ret = ddrphy_training(phy_base); + if (ret) + return ret;

- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); - - umc_start_ssif(ssif_base); - - return 0; + return umc_dramcont_init(dc_base, ca_base, size, freq, ddr3plus); }

int ph1_ld4_umc_init(const struct uniphier_board_data *bd) { - if ((bd->dram_ch[0].size == SZ_128M || bd->dram_ch[0].size == SZ_256M) && - (bd->dram_ch[1].size == SZ_128M || bd->dram_ch[1].size == SZ_256M) && - (bd->dram_freq == 1333 || bd->dram_freq == 1600) && - bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) { - return umc_init_sub(bd->dram_freq, - bd->dram_ch[0].size / SZ_128M, - bd->dram_ch[1].size / SZ_128M, - bd->dram_ddr3plus); - } else { - pr_err("Unsupported DDR configuration\n"); - return -EINVAL; + void __iomem *umc_base = (void __iomem *)0x5b800000; + void __iomem *ca_base = umc_base + 0x00001000; + void __iomem *dc_base = umc_base + 0x00400000; + void __iomem *ssif_base = umc_base; + int ch, ret; + + for (ch = 0; ch < DRAM_CH_NR; ch++) { + ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, + bd->dram_ch[ch].size / SZ_128M, + bd->dram_ddr3plus, ch); + if (ret) { + pr_err("failed to initialize UMC ch%d\n", ch); + return ret; + } + + ca_base += 0x00001000; + dc_base += 0x00200000; } + + umc_start_ssif(ssif_base); + + return 0; }

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 17/21] ARM: uniphier: optimize PH1-Pro4 UMC init code with "for" loop

Now this code can be re-written with a "for" statement instead of calling the same function multiple times.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 114 +++++++++++++++-------------- 1 file changed, 59 insertions(+), 55 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 0a2485e..9569c10 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -13,6 +13,8 @@ #include "ddrphy-regs.h" #include "umc-regs.h"

+#define DRAM_CH_NR 2 + enum dram_size { DRAM_SZ_128M, DRAM_SZ_256M, @@ -66,11 +68,21 @@ static void umc_start_ssif(void __iomem *ssif_base) }

static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int width) + int freq, unsigned long size, bool ddr3plus) { enum dram_size dram_size;

- switch (size / (width / 16)) { + if (freq != 1600) { + pr_err("Unsupported DDR frequency %d MHz\n", freq); + return -EINVAL; + } + + if (ddr3plus) { + pr_err("DDR3+ is not supported\n"); + return -EINVAL; + } + + switch (size) { case SZ_128M: dram_size = DRAM_SZ_128M; break; @@ -81,7 +93,7 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, dram_size = DRAM_SZ_512M; break; default: - pr_err("unsupported DRAM size\n"); + pr_err("unsupported DRAM size 0x%08lx (per 16bit)\n", size); return -EINVAL; }

@@ -113,66 +125,58 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, return 0; }

-int ph1_pro4_umc_init(const struct uniphier_board_data *bd) +static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, + int freq, unsigned long size, unsigned int width, + bool ddr3plus) { - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1); - int ret; - - if (bd->dram_freq != 1600) { - pr_err("Unsupported DDR configuration\n"); - return -EINVAL; - } - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); - - writel(0x00000101, dramcont0 + UMC_DIOCTLA); + void __iomem *phy_base = dc_base + 0x00001000; + int nr_phy = width / 16; + int phy, ret;

- ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ddr3plus); + umc_dram_init_start(dc_base); + umc_dram_init_poll(dc_base);

- ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); + for (phy = 0; phy < nr_phy; phy++) { + writel(0x00000100 | ((1 << (phy + 1)) - 1), + dc_base + UMC_DIOCTLA);

- writel(0x00000103, dramcont0 + UMC_DIOCTLA); + ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus); + if (ret) + return ret;

- ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ddr3plus); + ddrphy_prepare_training(phy_base, phy); + ret = ddrphy_training(phy_base); + if (ret) + return ret;

- ddrphy_prepare_training(phy0_1, 1); - ddrphy_training(phy0_1); - - writel(0x00000101, dramcont1 + UMC_DIOCTLA); - - ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ddr3plus); - - ddrphy_prepare_training(phy1_0, 0); - ddrphy_training(phy1_0); - - writel(0x00000103, dramcont1 + UMC_DIOCTLA); - - ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ddr3plus); - - ddrphy_prepare_training(phy1_1, 1); - ddrphy_training(phy1_1); + phy_base += 0x00001000; + }

- ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch[0].size, - bd->dram_ch[0].width); - if (ret) - return ret; + return umc_dramcont_init(dc_base, ca_base, freq, size / (width / 16), + ddr3plus); +}

- ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch[1].size, - bd->dram_ch[1].width); - if (ret) - return ret; +int ph1_pro4_umc_init(const struct uniphier_board_data *bd) +{ + void __iomem *umc_base = (void __iomem *)0x5b800000; + void __iomem *ca_base = umc_base + 0x00001000; + void __iomem *dc_base = umc_base + 0x00400000; + void __iomem *ssif_base = umc_base; + int ch, ret; + + for (ch = 0; ch < DRAM_CH_NR; ch++) { + ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, + bd->dram_ch[ch].size, + bd->dram_ch[ch].width, + bd->dram_ddr3plus); + if (ret) { + pr_err("failed to initialize UMC ch%d\n", ch); + return ret; + } + + ca_base += 0x00001000; + dc_base += 0x00200000; + }

umc_start_ssif(ssif_base);

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 18/21] ARM: uniphier: rework DRAM size handling in UMC init code

Currently, DRAM size is converted twice: size in byte -> size in Gbit -> enum

Optimize the code by converting the "size in byte" into enum directly.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 14 +++++++------- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 16 ++++++++-------- 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 92b0f18..0eb47d7 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -76,7 +76,7 @@ static void umc_start_ssif(void __iomem *ssif_base) }

static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq, bool ddr3plus) + int freq, unsigned long size, bool ddr3plus) { enum dram_freq freq_e; enum dram_size size_e; @@ -101,14 +101,14 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, switch (size) { case 0: return 0; - case 1: + case SZ_128M: size_e = DRAM_SZ_128M; break; - case 2: + case SZ_256M: size_e = DRAM_SZ_256M; break; default: - pr_err("unsupported DRAM size\n"); + pr_err("unsupported DRAM size 0x%08lx\n", size); return -EINVAL; }

@@ -140,7 +140,7 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, }

static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, - int freq, int size, bool ddr3plus, int ch) + int freq, unsigned long size, bool ddr3plus, int ch) { void __iomem *phy_base = dc_base + 0x00001000; int ret; @@ -159,7 +159,7 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, if (ret) return ret;

- return umc_dramcont_init(dc_base, ca_base, size, freq, ddr3plus); + return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus); }

int ph1_ld4_umc_init(const struct uniphier_board_data *bd) @@ -172,7 +172,7 @@ int ph1_ld4_umc_init(const struct uniphier_board_data *bd)

for (ch = 0; ch < DRAM_CH_NR; ch++) { ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, - bd->dram_ch[ch].size / SZ_128M, + bd->dram_ch[ch].size, bd->dram_ddr3plus, ch); if (ret) { pr_err("failed to initialize UMC ch%d\n", ch); diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index a2ed9ba..43e53fd 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -79,7 +79,7 @@ static void umc_start_ssif(void __iomem *ssif_base) }

static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq, bool ddr3plus) + int freq, unsigned long size, bool ddr3plus) { enum dram_freq freq_e; enum dram_size size_e; @@ -99,17 +99,17 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, switch (size) { case 0: return 0; - case 1: + case SZ_128M: size_e = DRAM_SZ_128M; break; - case 2: + case SZ_256M: size_e = DRAM_SZ_256M; break; - case 4: + case SZ_512M: size_e = DRAM_SZ_512M; break; default: - pr_err("unsupported DRAM size\n"); + pr_err("unsupported DRAM size 0x%08lx\n", size); return -EINVAL; }

@@ -143,7 +143,7 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, }

static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, - int freq, int size, bool ddr3plus, int ch) + int freq, unsigned long size, bool ddr3plus, int ch) { void __iomem *phy_base = dc_base + 0x00001000; int ret; @@ -162,7 +162,7 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, if (ret) return ret;

- return umc_dramcont_init(dc_base, ca_base, size, freq, ddr3plus); + return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus); }

int ph1_sld8_umc_init(const struct uniphier_board_data *bd) @@ -175,7 +175,7 @@ int ph1_sld8_umc_init(const struct uniphier_board_data *bd)

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 19/21] ARM: uniphier: remove unused macros for UMC base addresses

These macros are no longer used. These base addresses are SoC-dependent, so they should not be placed in the header.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-regs.h | 11 ----------- 1 file changed, 11 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h index 311cf3d..c65dd82 100644 --- a/arch/arm/mach-uniphier/dram/umc-regs.h +++ b/arch/arm/mach-uniphier/dram/umc-regs.h @@ -9,11 +9,6 @@ #ifndef ARCH_UMC_REGS_H #define ARCH_UMC_REGS_H

-#define UMC_BASE 0x5b800000 - -/* SSIF registers */ -#define UMC_SSIF_BASE UMC_BASE - #define UMC_CPURST 0x00000700 #define UMC_IDSRST 0x0000070C #define UMC_IXMRST 0x00000714 @@ -48,12 +43,6 @@ #define UMC_CLKEN_SSIF_RC 0x0000C080 #define UMC_CLKEN_SSIF_DST 0x0000C084

-/* CA registers */ -#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch)) - -/* DRAM controller registers */ -#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch)) - #define UMC_CMDCTLA 0x00000000 #define UMC_CMDCTLB 0x00000004 #define UMC_INITSET 0x00000014

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 20/21] ARM: uniphier: deprecate umc_dram_init_{start, poll}

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 6 ++++-- arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 6 ++++-- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 6 ++++-- arch/arm/mach-uniphier/dram/umc-regs.h | 23 ++++++----------------- 4 files changed, 18 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 0eb47d7..09b2c1c 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -8,6 +8,7 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> +#include <asm/processor.h>

#include "../init.h" #include "ddrphy-regs.h" @@ -145,8 +146,9 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, void __iomem *phy_base = dc_base + 0x00001000; int ret;

- umc_dram_init_start(dc_base); - umc_dram_init_poll(dc_base); + writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET); + while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST) + cpu_relax();

writel(0x00000101, dc_base + UMC_DIOCTLA);

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 9569c10..93d2e2c 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -8,6 +8,7 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> +#include <asm/processor.h>

#include "../init.h" #include "ddrphy-regs.h" @@ -133,8 +134,9 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, int nr_phy = width / 16; int phy, ret;

- umc_dram_init_start(dc_base); - umc_dram_init_poll(dc_base); + writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET); + while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST) + cpu_relax();

for (phy = 0; phy < nr_phy; phy++) { writel(0x00000100 | ((1 << (phy + 1)) - 1), diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index 43e53fd..d873130 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -8,6 +8,7 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> +#include <asm/processor.h>

#include "../init.h" #include "ddrphy-regs.h" @@ -148,8 +149,9 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, void __iomem *phy_base = dc_base + 0x00001000; int ret;

- umc_dram_init_start(dc_base); - umc_dram_init_poll(dc_base); + writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET); + while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST) + cpu_relax();

writel(0x00000101, dc_base + UMC_DIOCTLA);

diff --git a/arch/arm/mach-uniphier/dram/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h index c65dd82..cc2dd27 100644 --- a/arch/arm/mach-uniphier/dram/umc-regs.h +++ b/arch/arm/mach-uniphier/dram/umc-regs.h @@ -9,6 +9,8 @@ #ifndef ARCH_UMC_REGS_H #define ARCH_UMC_REGS_H

+#include <linux/bitops.h> + #define UMC_CPURST 0x00000700 #define UMC_IDSRST 0x0000070C #define UMC_IXMRST 0x00000714 @@ -46,7 +48,11 @@ #define UMC_CMDCTLA 0x00000000 #define UMC_CMDCTLB 0x00000004 #define UMC_INITSET 0x00000014 +#define UMC_INITSET_INIT1EN BIT(1) /* init without power-on wait */ +#define UMC_INITSET_INIT0EN BIT(0) /* init with power-on wait */ #define UMC_INITSTAT 0x00000018 +#define UMC_INITSTAT_INIT1ST BIT(1) /* init without power-on wait */ +#define UMC_INITSTAT_INIT0ST BIT(0) /* init with power-on wait */ #define UMC_SPCCTLA 0x00000030 #define UMC_SPCCTLB 0x00000034 #define UMC_SPCSETA 0x00000038 @@ -98,21 +104,4 @@ #define UMC_BITPERPIXELMODE_D0 0x010 #define UMC_PAIR1DOFF_D0 0x054

-#ifndef __ASSEMBLY__ - -#include <linux/types.h> - -static inline void umc_dram_init_start(void __iomem *dramcont) -{ - writel(0x00000002, dramcont + UMC_INITSET); -} - -static inline void umc_dram_init_poll(void __iomem *dramcont) -{ - while ((readl(dramcont + UMC_INITSTAT) & 0x00000002)) - ; -} - -#endif - #endif

-- 1.9.1

Masahiro Yamada

6:21 a.m.

New subject: [U-Boot] [PATCH 21/21] ARM: uniphier: rename variable for DRAM controller base address

Rename the variable that contains the base address for consistency.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 44 +++++++------- arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 54 ++++++++--------- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 44 +++++++------- arch/arm/mach-uniphier/dram/umc-proxstream2.c | 85 +++++++++++++-------------- 4 files changed, 113 insertions(+), 114 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 09b2c1c..72447cc 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -76,7 +76,7 @@ static void umc_start_ssif(void __iomem *ssif_base) writel(0x00000001, ssif_base + UMC_DMDRST); }

-static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, +static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base, int freq, unsigned long size, bool ddr3plus) { enum dram_freq freq_e; @@ -113,29 +113,29 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, return -EINVAL; }

- writel(umc_cmdctla_plus[freq_e], dramcont + UMC_CMDCTLA); - writel(umc_cmdctlb_plus[freq_e], dramcont + UMC_CMDCTLB); - writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA); - writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB); - writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0); - writel(0x04060806, dramcont + UMC_WDATACTL_D0); - writel(0x04a02000, dramcont + UMC_DATASET); + writel(umc_cmdctla_plus[freq_e], dc_base + UMC_CMDCTLA); + writel(umc_cmdctlb_plus[freq_e], dc_base + UMC_CMDCTLB); + writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA); + writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB); + writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0); + writel(0x04060806, dc_base + UMC_WDATACTL_D0); + writel(0x04a02000, dc_base + UMC_DATASET); writel(0x00000000, ca_base + 0x2300); - writel(0x00400020, dramcont + UMC_DCCGCTL); - writel(0x00000003, dramcont + 0x7000); - writel(0x0000000f, dramcont + 0x8000); - writel(0x000000c3, dramcont + 0x8004); - writel(0x00000071, dramcont + 0x8008); - writel(0x0000003b, dramcont + UMC_DICGCTLA); - writel(0x020a0808, dramcont + UMC_DICGCTLB); - writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x00400020, dc_base + UMC_DCCGCTL); + writel(0x00000003, dc_base + 0x7000); + writel(0x0000000f, dc_base + 0x8000); + writel(0x000000c3, dc_base + 0x8004); + writel(0x00000071, dc_base + 0x8008); + writel(0x0000003b, dc_base + UMC_DICGCTLA); + writel(0x020a0808, dc_base + UMC_DICGCTLB); + writel(0x00000004, dc_base + UMC_FLOWCTLG); writel(0x80000201, ca_base + 0xc20); - writel(0x0801e01e, dramcont + UMC_FLOWCTLA); - writel(0x00200000, dramcont + UMC_FLOWCTLB); - writel(0x00004444, dramcont + UMC_FLOWCTLC); - writel(0x200a0a00, dramcont + UMC_SPCSETB); - writel(0x00000000, dramcont + UMC_SPCSETD); - writel(0x00000520, dramcont + UMC_DFICUPDCTLA); + writel(0x0801e01e, dc_base + UMC_FLOWCTLA); + writel(0x00200000, dc_base + UMC_FLOWCTLB); + writel(0x00004444, dc_base + UMC_FLOWCTLC); + writel(0x200a0a00, dc_base + UMC_SPCSETB); + writel(0x00000000, dc_base + UMC_SPCSETD); + writel(0x00000520, dc_base + UMC_DFICUPDCTLA);

return 0; } diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 93d2e2c..23fb7b9 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -68,10 +68,10 @@ static void umc_start_ssif(void __iomem *ssif_base) writel(0x00000001, ssif_base + UMC_DMDRST); }

-static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, +static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base, int freq, unsigned long size, bool ddr3plus) { - enum dram_size dram_size; + enum dram_size size_e;

if (freq != 1600) { pr_err("Unsupported DDR frequency %d MHz\n", freq); @@ -85,43 +85,43 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,

switch (size) { case SZ_128M: - dram_size = DRAM_SZ_128M; + size_e = DRAM_SZ_128M; break; case SZ_256M: - dram_size = DRAM_SZ_256M; + size_e = DRAM_SZ_256M; break; case SZ_512M: - dram_size = DRAM_SZ_512M; + size_e = DRAM_SZ_512M; break; default: pr_err("unsupported DRAM size 0x%08lx (per 16bit)\n", size); return -EINVAL; }

- writel(0x66bb0f17, dramcont + UMC_CMDCTLA); - writel(0x18c6aa44, dramcont + UMC_CMDCTLB); - writel(umc_spcctla[dram_size], dramcont + UMC_SPCCTLA); - writel(0x00ff0008, dramcont + UMC_SPCCTLB); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D1); - writel(0x04060802, dramcont + UMC_WDATACTL_D0); - writel(0x04060802, dramcont + UMC_WDATACTL_D1); - writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x66bb0f17, dc_base + UMC_CMDCTLA); + writel(0x18c6aa44, dc_base + UMC_CMDCTLB); + writel(umc_spcctla[size_e], dc_base + UMC_SPCCTLA); + writel(0x00ff0008, dc_base + UMC_SPCCTLB); + writel(0x000c00ae, dc_base + UMC_RDATACTL_D0); + writel(0x000c00ae, dc_base + UMC_RDATACTL_D1); + writel(0x04060802, dc_base + UMC_WDATACTL_D0); + writel(0x04060802, dc_base + UMC_WDATACTL_D1); + writel(0x04a02000, dc_base + UMC_DATASET); writel(0x00000000, ca_base + 0x2300); - writel(0x00400020, dramcont + UMC_DCCGCTL); - writel(0x0000000f, dramcont + 0x7000); - writel(0x0000000f, dramcont + 0x8000); - writel(0x000000c3, dramcont + 0x8004); - writel(0x00000071, dramcont + 0x8008); - writel(0x00000004, dramcont + UMC_FLOWCTLG); - writel(0x00000000, dramcont + 0x0060); + writel(0x00400020, dc_base + UMC_DCCGCTL); + writel(0x0000000f, dc_base + 0x7000); + writel(0x0000000f, dc_base + 0x8000); + writel(0x000000c3, dc_base + 0x8004); + writel(0x00000071, dc_base + 0x8008); + writel(0x00000004, dc_base + UMC_FLOWCTLG); + writel(0x00000000, dc_base + 0x0060); writel(0x80000201, ca_base + 0xc20); - writel(0x0801e01e, dramcont + UMC_FLOWCTLA); - writel(0x00200000, dramcont + UMC_FLOWCTLB); - writel(0x00004444, dramcont + UMC_FLOWCTLC); - writel(0x200a0a00, dramcont + UMC_SPCSETB); - writel(0x00010000, dramcont + UMC_SPCSETD); - writel(0x80000020, dramcont + UMC_DFICUPDCTLA); + writel(0x0801e01e, dc_base + UMC_FLOWCTLA); + writel(0x00200000, dc_base + UMC_FLOWCTLB); + writel(0x00004444, dc_base + UMC_FLOWCTLC); + writel(0x200a0a00, dc_base + UMC_SPCSETB); + writel(0x00010000, dc_base + UMC_SPCSETD); + writel(0x80000020, dc_base + UMC_DFICUPDCTLA);

return 0; } diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index d873130..6cacd25 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -79,7 +79,7 @@ static void umc_start_ssif(void __iomem *ssif_base) writel(0x00000001, ssif_base + UMC_DMDRST); }

-static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, +static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base, int freq, unsigned long size, bool ddr3plus) { enum dram_freq freq_e; @@ -115,30 +115,30 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, }

writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e], - dramcont + UMC_CMDCTLA); + dc_base + UMC_CMDCTLA); writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e], - dramcont + UMC_CMDCTLB); - writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA); - writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB); - writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0); - writel(0x04060806, dramcont + UMC_WDATACTL_D0); - writel(0x04a02000, dramcont + UMC_DATASET); + dc_base + UMC_CMDCTLB); + writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA); + writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB); + writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0); + writel(0x04060806, dc_base + UMC_WDATACTL_D0); + writel(0x04a02000, dc_base + UMC_DATASET); writel(0x00000000, ca_base + 0x2300); - writel(0x00400020, dramcont + UMC_DCCGCTL); - writel(0x00000003, dramcont + 0x7000); - writel(0x0000004f, dramcont + 0x8000); - writel(0x000000c3, dramcont + 0x8004); - writel(0x00000077, dramcont + 0x8008); - writel(0x0000003b, dramcont + UMC_DICGCTLA); - writel(0x020a0808, dramcont + UMC_DICGCTLB); - writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x00400020, dc_base + UMC_DCCGCTL); + writel(0x00000003, dc_base + 0x7000); + writel(0x0000004f, dc_base + 0x8000); + writel(0x000000c3, dc_base + 0x8004); + writel(0x00000077, dc_base + 0x8008); + writel(0x0000003b, dc_base + UMC_DICGCTLA); + writel(0x020a0808, dc_base + UMC_DICGCTLB); + writel(0x00000004, dc_base + UMC_FLOWCTLG); writel(0x80000201, ca_base + 0xc20); - writel(0x0801e01e, dramcont + UMC_FLOWCTLA); - writel(0x00200000, dramcont + UMC_FLOWCTLB); - writel(0x00004444, dramcont + UMC_FLOWCTLC); - writel(0x200a0a00, dramcont + UMC_SPCSETB); - writel(0x00000000, dramcont + UMC_SPCSETD); - writel(0x00000520, dramcont + UMC_DFICUPDCTLA); + writel(0x0801e01e, dc_base + UMC_FLOWCTLA); + writel(0x00200000, dc_base + UMC_FLOWCTLB); + writel(0x00004444, dc_base + UMC_FLOWCTLC); + writel(0x200a0a00, dc_base + UMC_SPCSETB); + writel(0x00000000, dc_base + UMC_SPCSETD); + writel(0x00000520, dc_base + UMC_DFICUPDCTLA);

return 0; } diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c index 8690906..50c0238 100644 --- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -404,12 +404,12 @@ static int ddrphy_training(void __iomem *phy_base) }

/* UMC */ -static void umc_set_system_latency(void __iomem *umc_dc_base, int phy_latency) +static void umc_set_system_latency(void __iomem *dc_base, int phy_latency) { u32 val; int latency;

- val = readl(umc_dc_base + UMC_RDATACTL_D0); + val = readl(dc_base + UMC_RDATACTL_D0); latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT; latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >> UMC_RDATACTL_RAD2LTY_SHIFT; @@ -427,18 +427,18 @@ static void umc_set_system_latency(void __iomem *umc_dc_base, int phy_latency) val |= latency << UMC_RDATACTL_RADLTY_SHIFT; }

- writel(val, umc_dc_base + UMC_RDATACTL_D0); - writel(val, umc_dc_base + UMC_RDATACTL_D1); + writel(val, dc_base + UMC_RDATACTL_D0); + writel(val, dc_base + UMC_RDATACTL_D1);

- readl(umc_dc_base + UMC_RDATACTL_D1); /* relax */ + readl(dc_base + UMC_RDATACTL_D1); /* relax */ }

/* enable/disable auto refresh */ -void umc_refresh_ctrl(void __iomem *umc_dc_base, int enable) +void umc_refresh_ctrl(void __iomem *dc_base, int enable) { u32 tmp;

- tmp = readl(umc_dc_base + UMC_SPCSETB); + tmp = readl(dc_base + UMC_SPCSETB); tmp &= ~UMC_SPCSETB_AREFMD_MASK;

if (enable) @@ -446,7 +446,7 @@ void umc_refresh_ctrl(void __iomem *umc_dc_base, int enable) else tmp |= UMC_SPCSETB_AREFMD_REG;

- writel(tmp, umc_dc_base + UMC_SPCSETB); + writel(tmp, dc_base + UMC_SPCSETB); udelay(1); }

@@ -458,7 +458,7 @@ static void umc_ud_init(void __iomem *umc_base, int ch) writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0); }

-static int umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq, +static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, unsigned long size, int width, int ch) { enum dram_size size_e; @@ -480,14 +480,13 @@ static int umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq, return -EINVAL; }

- writel(umc_cmdctla[freq], umc_dc_base + UMC_CMDCTLA); + writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);

writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq], - umc_dc_base + UMC_CMDCTLB); + dc_base + UMC_CMDCTLB);

- writel(umc_spcctla[freq][size_e], - umc_dc_base + UMC_SPCCTLA); - writel(umc_spcctlb[freq], umc_dc_base + UMC_SPCCTLB); + writel(umc_spcctla[freq][size_e], dc_base + UMC_SPCCTLA); + writel(umc_spcctlb[freq], dc_base + UMC_SPCCTLB);

val = 0x000e000e; latency = 12; @@ -502,38 +501,38 @@ static int umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq, val |= latency << UMC_RDATACTL_RADLTY_SHIFT; }

- writel(val, umc_dc_base + UMC_RDATACTL_D0); + writel(val, dc_base + UMC_RDATACTL_D0); if (width >= 32) - writel(val, umc_dc_base + UMC_RDATACTL_D1); + writel(val, dc_base + UMC_RDATACTL_D1);

- writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D0); + writel(0x04060A02, dc_base + UMC_WDATACTL_D0); if (width >= 32) - writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D1); - writel(0x04000000, umc_dc_base + UMC_DATASET); - writel(0x00400020, umc_dc_base + UMC_DCCGCTL); - writel(0x00000084, umc_dc_base + UMC_FLOWCTLG); - writel(0x00000000, umc_dc_base + UMC_ACSSETA); + writel(0x04060A02, dc_base + UMC_WDATACTL_D1); + writel(0x04000000, dc_base + UMC_DATASET); + writel(0x00400020, dc_base + UMC_DCCGCTL); + writel(0x00000084, dc_base + UMC_FLOWCTLG); + writel(0x00000000, dc_base + UMC_ACSSETA);

writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq], - umc_dc_base + UMC_FLOWCTLA); + dc_base + UMC_FLOWCTLA);

- writel(0x00004400, umc_dc_base + UMC_FLOWCTLC); - writel(0x200A0A00, umc_dc_base + UMC_SPCSETB); - writel(0x00000520, umc_dc_base + UMC_DFICUPDCTLA); - writel(0x0000000D, umc_dc_base + UMC_RESPCTL); + writel(0x00004400, dc_base + UMC_FLOWCTLC); + writel(0x200A0A00, dc_base + UMC_SPCSETB); + writel(0x00000520, dc_base + UMC_DFICUPDCTLA); + writel(0x0000000D, dc_base + UMC_RESPCTL);

if (ch != 2) { - writel(0x00202000, umc_dc_base + UMC_FLOWCTLB); - writel(0xFDBFFFFF, umc_dc_base + UMC_FLOWCTLOB0); - writel(0xFFFFFFFF, umc_dc_base + UMC_FLOWCTLOB1); - writel(0x00080700, umc_dc_base + UMC_BSICMAPSET); + writel(0x00202000, dc_base + UMC_FLOWCTLB); + writel(0xFDBFFFFF, dc_base + UMC_FLOWCTLOB0); + writel(0xFFFFFFFF, dc_base + UMC_FLOWCTLOB1); + writel(0x00080700, dc_base + UMC_BSICMAPSET); } else { - writel(0x00200000, umc_dc_base + UMC_FLOWCTLB); - writel(0x00000000, umc_dc_base + UMC_BSICMAPSET); + writel(0x00200000, dc_base + UMC_FLOWCTLB); + writel(0x00000000, dc_base + UMC_BSICMAPSET); }

- writel(0x00000000, umc_dc_base + UMC_ERRMASKA); - writel(0x00000000, umc_dc_base + UMC_ERRMASKB); + writel(0x00000000, dc_base + UMC_ERRMASKA); + writel(0x00000000, dc_base + UMC_ERRMASKB);

return 0; } @@ -541,17 +540,17 @@ static int umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq, static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq, unsigned long size, unsigned int width, int ch) { - void __iomem *umc_dc_base = umc_ch_base + 0x00011000; + void __iomem *dc_base = umc_ch_base + 0x00011000; void __iomem *phy_base = umc_ch_base + 0x00030000; int ret;

- writel(0x00000002, umc_dc_base + UMC_INITSET); - while (readl(umc_dc_base + UMC_INITSTAT) & BIT(2)) + writel(0x00000002, dc_base + UMC_INITSET); + while (readl(dc_base + UMC_INITSTAT) & BIT(2)) cpu_relax();

/* deassert PHY reset signals */ writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, - umc_dc_base + UMC_DIOCTLA); + dc_base + UMC_DIOCTLA);

ddrphy_init(phy_base, freq, width, ch);

@@ -563,7 +562,7 @@ static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq, if (ret) return ret;

- ret = umc_dc_init(umc_dc_base, freq, size, width, ch); + ret = umc_dc_init(dc_base, freq, size, width, ch); if (ret) return ret;

@@ -576,15 +575,15 @@ static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq, udelay(1);

/* match the system latency between UMC and PHY */ - umc_set_system_latency(umc_dc_base, + umc_set_system_latency(dc_base, ddrphy_get_system_latency(phy_base, width));

udelay(1);

/* stop auto refresh before clearing FIFO in PHY */ - umc_refresh_ctrl(umc_dc_base, 0); + umc_refresh_ctrl(dc_base, 0); ddrphy_fifo_reset(phy_base); - umc_refresh_ctrl(umc_dc_base, 1); + umc_refresh_ctrl(dc_base, 1);

udelay(10);

-- 1.9.1

Masahiro Yamada

28 Feb 28 Feb

7:55 p.m.

New subject: [U-Boot] [PATCH 00/21] ARM: uniphier: clean-ups of DRAM init code

2016-02-26 14:21 GMT+09:00 Masahiro Yamada yamada.masahiro@socionext.com:

...

Masahiro Yamada (21): ARM: uniphier: remove unused umc_polling() ARM: uniphier: rework struct uniphier_board_data ARM: uniphier: optimize ProXstream2 UMC init code with "for" loop ARM: uniphier: use pr_err() where possible ARM: uniphier: refactor UMC init code for ProXstream2 ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings ARM: uniphier: disable debug circuit clocks for PH1-Pro4 ARM: uniphier: add a field to specify DDR3+ ARM: uniphier: merge DDR PHY init code for 3 SoCs ARM: uniphier: remove unused argument of ph1_ld4_ddrphy_init() ARM: uniphier: refactor DDR-PHY init code ARM: uniphier: refactor UMC init code for PH1-sLD8 ARM: uniphier: support more DRAM use cases for PH1-sLD8 ARM: uniphier: refactor UMC init code for PH1-LD4 ARM: uniphier: optimize PH1-sLD8 UMC init code with "for" loop ARM: uniphier: optimize PH1-LD4 UMC init code with "for" loop ARM: uniphier: optimize PH1-Pro4 UMC init code with "for" loop ARM: uniphier: rework DRAM size handling in UMC init code ARM: uniphier: remove unused macros for UMC base addresses ARM: uniphier: deprecate umc_dram_init_{start,poll} ARM: uniphier: rename variable for DRAM controller base address

Series, applied to u-boot-uniphier/master

-- Best Regards Masahiro Yamada

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Masahiro Yamada