[U-Boot-Users] Debugging U-boot with BDI-2000 on MPC8349

newer
Re: [U-Boot-Users] Codesourcery...

Ben Warren

14 Sep 2006 14 Sep '06

8:52 p.m.

Hello,

Has anybody been able to successfully single step through U-boot code on an MPC8349 CPU using a BDI-2000? I've been working with an FAE at the company that represents Abatron in the US, and he seems to think it's a GDB problem. Of course, I'd prefer it to be something else... I'm using the ppc_6xx-gdb version 6.3 that's part of ELDK 4.0. I've also built the latest gdb 6.5, but no dice there either.

Here's a snippet:

(gdb) target remote 10.69.69.200:2001 Remote debugging using 10.69.69.200:2001 0x00000100 in ?? () (gdb) b board_init_f Breakpoint 1 at 0xfe0044a4: file board.c, line 374. (gdb) c Continuing.

Breakpoint 1, board_init_f (bootflag=1) at board.c:374 374 { (gdb) list 369 * 370 ************************************************************************ 371 */ 372 373 void board_init_f (ulong bootflag) 374 { 375 bd_t *bd; 376 ulong len, addr, addr_sp; 377 ulong *s; 378 gd_t *id; (gdb) next Cannot access memory at address 0xfd000efc /****** This isn't an address in Flash! The BDI-2000 shows the PC incrementing, so 'next' did advance things ******/

(gdb) del 1 (gdb) b relocate_code Breakpoint 2 at 0xfe0035a0: file /bld_home/bwarren/fpga/u-boot/cpu/mpc83xx/start.S, line 888. (gdb) c Continuing.

Breakpoint 2, relocate_code () at /bld_home/bwarren/fpga/u-boot/cpu/mpc83xx/start.S:889 889 mr r9, r4 /* Save copy of Global Data pointer */ (gdb) next 890 mr r10, r5 /* Save copy of Destination Address */

/****** We can single step through this code for some reason ******/

If anybody's seen this behavior and has any clues, please let me know. I apologize if this is a bit off-topic.

regards, Ben

Show replies by date

Timur Tabi

14 Sep 14 Sep

8:57 p.m.

Ben Warren wrote:

...

Hello,

Has anybody been able to successfully single step through U-boot code on an MPC8349 CPU using a BDI-2000?

I've attached two config files. One can be used to flash the 9349E-mITX, and the other can be used to debug it.

The flash-enabled one programs a bunch of registers that wake up the flash chip. Unfortunately, when using this config, U-boot hangs somewhere in start.S. I'm probably programming the board just differently enough to confuse U-Boot.

The other config programs nothing, which gives U-Boot a clean slate to program.

I presume it should be possible to create a "unified" config that works in both situations, but I haven't had the time to try it.

I've never used GDB with the BDI.

-- Timur Tabi Linux Kernel Developer @ Freescale [INIT] ; Machine check enable, exception vectors at 0x0000_0000 ; 0 0000 00000 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 ;WREG MSR 0x00001002 ;MSR : ME,RI ; WINDOW 0 - configuration space - Initially mapped by RCWHR[BMS], relocated to 0xff400000 WM32 0xff400020 0xff400000 ; LBLAWBAR0 - begining at 0xff400000 ; WINDOW 1 - FLASH and LED & Board ID WM32 0xff400028 0xf8000000 ; LBLAWBAR1 - begining at 0xf8000000 WM32 0xff40002c 0x8000001a ; LBLAWAR1 - enable, size = 128MB ; PCI Local Access Windows ; WINDOW 0 WM32 0xff400060 0x80000000 ; PCILAWBAR0 - begining at 0x80000000 WM32 0xff400064 0x8000001c ; PCILAWAR0 - enable, size = 512MB ; WINDOW 1 WM32 0xff400068 0xa0000000 ; PCILAWBAR1 - begining at 0xa0000000 WM32 0xff40006c 0x8000001c ; PCILAWAR1 - enable, size = 512MB ; DDR Local Access Windows ; WINDOW 0 - 1st DDR SODIMM WM32 0xff4000a0 0x00000000 ; DDRLAWBAR0 - begining at 0x00000000 WM32 0xff4000a4 0x8000001b ; DDRLAWAR0 - enable, size = 256MB ; WINDOW 1 - 2nd DDR SODIMM WM32 0xff4000a8 0x10000000 ; DDRLAWBAR1 - begining at 0x10000000 WM32 0xff4000ac 0x8000001b ; DDRLAWAR1 - enable, size = 256MB ; DDR Controller Configuration ; CS0_BNDS ; bit 8-15 - starting address ; bit 24-31 - ending address ; 8347PC, 128M WM32 0xff402000 0x00000007 ; 0x00000000 - 0x07FFFFFF ; CS0_CONFIG ; bit 0 = 1 - CS_0_EN CS0 enable ; bit 21 - 23 = 0 - ROW_BITS_CS_0 13 rows ; bit 29 - 31 = 2 - COL_BITS_CS_0 10 columns WM32 0xff402080 0x80000102 ; CS1_BNDS ; bit 8-15 - starting address ; bit 24-31 - ending address ; 8347PC ;;WM32 0xff402008 0x0018001f ; 0x18000000 - 0x1FFFFFFF ; CS1_CONFIG ; bit 0 = 1 - CS_1_EN CS1 enable ; bit 21 - 23 = 1 - ROW_BITS_CS_1 13 rows ; bit 29 - 31 = 1 - COL_BITS_CS_1 9 columns ; 8347PC ;;WM32 0xff402084 0x80000101 ; CS2_BNDS ; bit 8-15 - starting address ; bit 24-31 - ending address ; 8347PC ;;WM32 0xff402010 0x00000007 ; 0x00000000 - 0x07FFFFFF ; CS2_CONFIG ; bit 0 = 1 - CS_2_EN CS2 enable ; bit 21 - 23 = 1 - ROW_BITS_CS_2 13 rows ; bit 29 - 31 = 1 - COL_BITS_CS_2 9 columns ; 8347PC ;;WM32 0xff402088 0x80000101 ; CS3_BNDS ; bit 8-15 - starting address ; bit 24-31 - ending address ; 8347PC ;;WM32 0xff402018 0x0008000f ; 0x08000000 - 0x09FFFFFF ; CS3_CONFIG ; bit 0 = 1 - CS_3_EN CS3 enable ; bit 21 - 23 = 1 - ROW_BITS_CS_3 13 rows ; bit 29 - 31 = 1 - COL_BITS_CS_3 9 columns ; 8347PC ;;WM32 0xff40208C 0x80000101 ; TIMING_CONFIG_1 ; bit 1-3 = 3 - PRETOACT precharge activate interval 3 clock cycles ; bit 4-7 = 7 - ACTTOPRE activate to precharge interval 7 clock cycles ; bit 9-11 = 3 = ACTTORW activate to r/w interval 3 clock cycles ; bit 13 - 15 = 3 - CASLAT CAS latency 2.5 clock cycles ; bit 16 - 19 = 3 - REFREC refresh recovery time 11 clock cycles ; bit 21 - 23 = 3 - WRREC data to precharge interval 3 clock cycles ; bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles ; bit 29 - 31 = 1 - WRTORD write data to read command interval 1 clock cycle ;;;WM32 0xff402108 0x37343321 ; For 266(133)MHz ; bit 13 - 15 = 3 - CASLAT CAS latency 2 clock cycles ; CASLAT = 1.5 WM32 0xff402108 0x37324321 ; CASLAT = 2.5 ;WM32 0xff402108 0x37344321 ; TIMING_CONFIG_2 ; bit 19-21 = b010 - WR_DATA_DELAY - 1/2 DRAM clock delay WM32 0xff40210C 0x00000800 ; temporary disable the memory interface for reconfiguration ; DDR_SDRAM_CFG ; bit 0 = 0 - MEM_EN SDRAM interface logic is disabled ; bit 1 = 1 - SREN enable self refresh during sleep ; bit 2 = 0 - ECC_EN disable ECC interrupt generation ; bit 3 = 0 - RD_EN unbuffered DIMMs ; bit 6 - 7 = 2 - SDRAM_TYPE DDR SDRAM ; bit 10 = 0 - DYN_PWR power management disabled WM32 0xff402110 0x42000000 ; DDR_SDRAM_MODE ; bit 0 - 15 = 0x2000 - ESDMODE ; bit 16 - 31 = 0x0162 - SDMODE ;;;;;WM32 0xff402118 0x20000162 ;CASLAT = 2 WM32 0xff402118 0x00000022 ;CASLAT = 2.5 ;WM32 0xff402118 0x00000062 ; DDR_SDRAM_INTERVAL ; bit 2 - 15 = 0x45b0 - REFINT ; bit 18 - 31 = 0x0100 - BSTOPRE auto precharge r/w commands used ;;;;WM32 0xff402124 0x045b0100 ;;;;;WM32 0xff402124 0x03a30100 WM32 0xff402124 0x04060100 ; 8347PC : sdram_clk_cntl : Source Sync mode enable SS_EN=1, CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM clock cycle after address/command WM32 0xff402130 0x82000000 ; debug register, ddr6 errata ;WM32 0xff402f00 0x202c0000 DELAY 300 ; enable the DDR memory controller ; DDR_SDRAM_CFG ; bit 0 = 1 - MEM_EN SDRAM interface logic enabled WM32 0xff402110 0xc2000000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Local Bus Interface (LBIU) Configuration ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; CS0 - 16MB FLASH WM32 0xff405000 0xfe001001 ; BR0 base address at 0xFe000000, port size 16 bit, GPCM, valid WM32 0xff405004 0xff006ff7 ; OR0 16MB flash size (two 8M), 15 w.s., timing relaxed ; CS1 - board VSC7385 WM32 0xff405008 0xf8000801 ; BR1 base address at 0xFE400000, port size 8 bit, GPCM, valid WM32 0xff40500c 0xfffe09ff ; OR1 128KB size, 15 w.s., timing relaxed, external TA ; CS2 - LED & Board ID WM32 0xff405014 0xffe0ef97 ; OR2 128KB size WM32 0xff405010 0xf8000801 ; BR2 base address at 0xF8000000, port size 8 bit, GPCM, valid ; LBCR - local bus enable WM32 0xff4050d0 0x00000000 ; LCRR ; bit 14 - 15 = 0b11 - EADC - 3 external address delay cycles ; bit 28 - 31 = 0x0100 - CLKDIV - system clock:memory bus clock = 4 WM32 0xff4050d4 0x00030004 ; Unlock flash in BCSR1 WM32 0xff400800 0x00000000 ; ACR ;MMAP 0 0xFFFFFFF ; DDR ;MMAP 0xFE000000 0xFEFFFFFF ; Flash ;MMAP 0xFF400000 0xFF4FFFFF ; IMMR [TARGET] CPUTYPE 8349 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock STARTUP RESET ;halt immediately at the boot vector BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;TRACE or HWBP, HWBP uses a hardware breakpoint ;If flash has been corrupted, you may need to uncomment this line to prevent ;the BDI from continuously resetting the board. ;RCW 0xbf60a000 0x04040000 VECTOR CATCH [HOST] IP 192.168.1.1 FILE $u-boot.bin FORMAT BIN 0x10000 LOAD MANUAL PROMPT 8349E-mITX> DUMP itx-dump.bin [FLASH] CHIPTYPE AM29BX16 CHIPSIZE 0x800000 ;The size of one flash chip in bytes BUSWIDTH 16 ERASE 0xfe000000 0x10000 128 ; Erase the lower 8MB, each sector is 64KB ;ERASE 0xfe800000 0x10000 128 ; Erase the upper 8MB, each sector is 64KB ;Uncomment this to use RAM for flashing. Although it will flash much faster, ;it may not work, and it may not report an error either, so manually verify ;after flashing. ;WORKSPACE 0x1000 ;flash_image.bin is an image file of an entire 8MB flash region. ;Flash this file at 0xfe0000000 and 0xfe800000 to restore all of flash. FILE $flash_image.bin FORMAT BIN 0xfe000000 ; Write image to lower 8MB ;FORMAT BIN 0xfe800000 ; Write image to upper 8MB [REGS] FILE $reg8349e.def [TARGET] CPUTYPE 8349 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock STARTUP RESET ;halt immediately at the boot vector BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;TRACE or HWBP, HWBP uses a hardware breakpoint ;RCW 0xbf60a000 0x04040000 ;VECTOR CATCH ;QACK LOW ;POWERUP 2000 ;start delay after power-up detected in ms ;WAKEUP 2000 ;give reset time to complete [HOST] IP 192.168.1.1 FILE $u-boot.bin FORMAT BIN 0x10000 LOAD MANUAL ;load code MANUAL or AUTO after reset PROMPT 8349ITX> DUMP itx-dump.bin [FLASH] CHIPTYPE AM29BX16 CHIPSIZE 0x800000 ;The size of one flash chip in bytes ;WORKSPACE 200000 BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64) FILE $flash_image.bin FORMAT BIN 0xfe000000 ERASE 0xfe000000 0x10000 128 ; Erase 8MB, each sector is 64KB [REGS] FILE $reg8349e.def

Ben Warren

9:20 p.m.

Thanks Timur,

On Thu, 2006-09-14 at 13:57 -0500, Timur Tabi wrote:

...

Ben Warren wrote:

...
Hello,

Has anybody been able to successfully single step through U-boot code on an MPC8349 CPU using a BDI-2000?

I've attached two config files. One can be used to flash the 9349E-mITX, and the other can be used to debug it.

The flash-enabled one programs a bunch of registers that wake up the flash chip. Unfortunately, when using this config, U-boot hangs somewhere in start.S. I'm probably programming the board just differently enough to confuse U-Boot.

The other config programs nothing, which gives U-Boot a clean slate to program.

The config I use to debug is much like your second one. In general, less is more.

...

I presume it should be possible to create a "unified" config that works in both situations, but I haven't had the time to try it.

I've never used GDB with the BDI.

I've used it with Linux drivers and it's really very slick. I imagine it would be excellent with U-boot too, if I could get it to work in code other than start.S.

regards, Ben

Jerry Van Baren

9:39 p.m.

Ben Warren wrote:

...

Thanks Timur,

On Thu, 2006-09-14 at 13:57 -0500, Timur Tabi wrote:

...
Ben Warren wrote:

...
Hello,

Has anybody been able to successfully single step through U-boot code on an MPC8349 CPU using a BDI-2000?

I've attached two config files. One can be used to flash the 9349E-mITX, and the other can be used to debug it.

The flash-enabled one programs a bunch of registers that wake up the flash chip. Unfortunately, when using this config, U-boot hangs somewhere in start.S. I'm probably programming the board just differently enough to confuse U-Boot.

The other config programs nothing, which gives U-Boot a clean slate to program.

The config I use to debug is much like your second one. In general, less is more.

...
I presume it should be possible to create a "unified" config that works in both situations, but I haven't had the time to try it.

I've never used GDB with the BDI.

I've used it with Linux drivers and it's really very slick. I imagine it would be excellent with U-boot too, if I could get it to work in code other than start.S.

regards, Ben

Have you tried the FAQ "10.1.2. Debugging of U-Boot After Relocation"? http://www.denx.de/wiki/view/DULG/DebuggingUBoot

gvb

Ben Warren

9:53 p.m.

Hi Jerry,

On Thu, 2006-09-14 at 15:39 -0400, Jerry Van Baren wrote:

...

Have you tried the FAQ "10.1.2. Debugging of U-Boot After Relocation"? http://www.denx.de/wiki/view/DULG/DebuggingUBoot

My problem arises when I try to do exactly what's shown in the FAQ (before relocation, in this case).

Instead of:

Breakpoint 1, cpu_init_f () at cpu_init.c:136 136 asm volatile(" bl 0f" ::: "lr"); (gdb) s 137 asm volatile("0: mflr 3" ::: "r3"); (gdb)

I get:

Breakpoint 1, cpu_init_f (im=0xe0000000) at cpu_init.c:42 42 { (gdb) s Cannot access memory at address 0xfd000ed8 (gdb) print im $1 = (volatile immap_t *) 0xe0000000 (gdb) print *im Cannot access memory at address 0xe0000000 (gdb)

Uncool.

regards, Ben

6815

Age (days ago)

6815

Last active (days ago)

List overview

Download

4 comments

3 participants

tags (0)

participants (3)

Ben Warren
Jerry Van Baren
Timur Tabi