[U-Boot] [PATCH 0/2] ARM: k2g: Add support for dynamic programming of PLL
As k2g supports various sysclk frequencies, this series support PLL configuration for all supported sysclk frequencies.
This series depends on Franklin's K2G ICE support series[1]
[1] https://lists.denx.de/pipermail/u-boot/2017-March/282913.html
Lokesh Vutla (2): ARM: k2g: Add support for dynamic programming of PLL based on SYSCLK ARM: keystone2: Add support for getting external clock dynamically
arch/arm/mach-keystone/clock.c | 12 +- arch/arm/mach-keystone/include/mach/clock-k2g.h | 4 +- arch/arm/mach-keystone/include/mach/clock.h | 2 +- arch/arm/mach-keystone/include/mach/hardware-k2g.h | 21 +++ board/ti/ks2_evm/board_k2e.c | 30 ++++- board/ti/ks2_evm/board_k2g.c | 150 +++++++++++++++++---- board/ti/ks2_evm/board_k2hk.c | 31 +++++ board/ti/ks2_evm/board_k2l.c | 34 ++++- include/configs/ti_armv7_keystone2.h | 2 +- 9 files changed, 235 insertions(+), 51 deletions(-)
K2G supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configured based on this sysclock frequency. Add PLL configurations for all supported sysclk frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-keystone/include/mach/clock-k2g.h | 4 +- arch/arm/mach-keystone/include/mach/hardware-k2g.h | 21 ++++ board/ti/ks2_evm/board_k2g.c | 116 +++++++++++++++++---- 3 files changed, 118 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2g.h b/arch/arm/mach-keystone/include/mach/clock-k2g.h index 74de6202fe..374f0d92af 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2g.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2g.h @@ -12,8 +12,8 @@
#define PLLSET_CMD_LIST "<pa|arm|ddr3>"
-#define DEV_SUPPORTED_SPEEDS 0x1ff -#define ARM_SUPPORTED_SPEEDS 0xff +#define DEV_SUPPORTED_SPEEDS 0xff +#define ARM_SUPPORTED_SPEEDS 0x3ff
#define KS2_CLK1_6 sys_clk0_6_clk
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h index 0f6bf61867..90ca1208d4 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h @@ -86,4 +86,25 @@ #define RSTMUX_OMODE8_INT 0x3 #define RSTMUX_OMODE8_INT_AND_DEV_RESET 0x4
+/* DEVSTAT register definition */ +#define KS2_DEVSTAT_REFCLK_SHIFT 7 +#define KS2_DEVSTAT_REFCLK_MASK (0x7 << 7) + +/* GPMC */ +#define KS2_GPMC_BASE 0x21818000 + +/* SYSCLK indexes */ +#define SYSCLK_19MHz 0 +#define SYSCLK_24MHz 1 +#define SYSCLK_25MHz 2 +#define SYSCLK_26MHz 3 +#define MAX_SYSCLK 4 + +#ifndef __ASSEMBLY__ +static inline u8 get_sysclk_index(void) +{ + u32 dev_stat = __raw_readl(KS2_DEVSTAT); + return (dev_stat & KS2_DEVSTAT_REFCLK_MASK) >> KS2_DEVSTAT_REFCLK_SHIFT; +} +#endif #endif /* __ASM_ARCH_HARDWARE_K2G_H */ diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index de881596d4..6c590b4ff9 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -20,6 +20,13 @@ #define SYS_CLK 24000000 #define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
+const unsigned int sysclk_array[MAX_SYSCLK] = { + 19200000, + 24000000, + 25000000, + 26000000, +}; + unsigned int external_clk[ext_clk_count] = { [sys_clk] = SYS_CLK, [pa_clk] = SYS_CLK, @@ -52,49 +59,116 @@ static int dev_speeds[DEVSPEED_NUMSPDS] = { SPD400, };
-static struct pll_init_data main_pll_config[NUM_SPDS] = { - [SPD400] = {MAIN_PLL, 100, 3, 2}, - [SPD600] = {MAIN_PLL, 300, 6, 2}, - [SPD800] = {MAIN_PLL, 200, 3, 2}, - [SPD900] = {TETRIS_PLL, 75, 1, 2}, - [SPD1000] = {TETRIS_PLL, 250, 3, 2}, +static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = { + [SYSCLK_19MHz] = { + [SPD400] = {MAIN_PLL, 125, 3, 2}, + [SPD600] = {MAIN_PLL, 125, 2, 2}, + [SPD800] = {MAIN_PLL, 250, 3, 2}, + [SPD900] = {TETRIS_PLL, 187, 2, 2}, + [SPD1000] = {TETRIS_PLL, 104, 1, 2}, + }, + [SYSCLK_24MHz] = { + [SPD400] = {MAIN_PLL, 100, 3, 2}, + [SPD600] = {MAIN_PLL, 300, 6, 2}, + [SPD800] = {MAIN_PLL, 200, 3, 2}, + [SPD900] = {TETRIS_PLL, 75, 1, 2}, + [SPD1000] = {TETRIS_PLL, 250, 3, 2}, + }, + [SYSCLK_25MHz] = { + [SPD400] = {MAIN_PLL, 32, 1, 2}, + [SPD600] = {MAIN_PLL, 48, 1, 2}, + [SPD800] = {MAIN_PLL, 64, 1, 2}, + [SPD900] = {TETRIS_PLL, 72, 1, 2}, + [SPD1000] = {TETRIS_PLL, 80, 1, 2}, + }, + [SYSCLK_26MHz] = { + [SPD400] = {MAIN_PLL, 400, 13, 2}, + [SPD600] = {MAIN_PLL, 230, 5, 2}, + [SPD800] = {MAIN_PLL, 123, 2, 2}, + [SPD900] = {TETRIS_PLL, 69, 1, 2}, + [SPD1000] = {TETRIS_PLL, 384, 5, 2}, + }, };
-static struct pll_init_data tetris_pll_config[NUM_SPDS] = { - [SPD200] = {TETRIS_PLL, 250, 3, 10}, - [SPD400] = {TETRIS_PLL, 100, 1, 6}, - [SPD600] = {TETRIS_PLL, 100, 1, 4}, - [SPD800] = {TETRIS_PLL, 400, 3, 4}, - [SPD900] = {TETRIS_PLL, 75, 1, 2}, - [SPD1000] = {TETRIS_PLL, 250, 3, 2}, +static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = { + [SYSCLK_19MHz] = { + [SPD200] = {TETRIS_PLL, 625, 6, 10}, + [SPD400] = {TETRIS_PLL, 125, 1, 6}, + [SPD600] = {TETRIS_PLL, 125, 1, 4}, + [SPD800] = {TETRIS_PLL, 333, 2, 4}, + [SPD900] = {TETRIS_PLL, 187, 2, 2}, + [SPD1000] = {TETRIS_PLL, 104, 1, 2}, + }, + [SYSCLK_24MHz] = { + [SPD200] = {TETRIS_PLL, 250, 3, 10}, + [SPD400] = {TETRIS_PLL, 100, 1, 6}, + [SPD600] = {TETRIS_PLL, 100, 1, 4}, + [SPD800] = {TETRIS_PLL, 400, 3, 4}, + [SPD900] = {TETRIS_PLL, 75, 1, 2}, + [SPD1000] = {TETRIS_PLL, 250, 3, 2}, + }, + [SYSCLK_25MHz] = { + [SPD200] = {TETRIS_PLL, 80, 1, 10}, + [SPD400] = {TETRIS_PLL, 96, 1, 6}, + [SPD600] = {TETRIS_PLL, 96, 1, 4}, + [SPD800] = {TETRIS_PLL, 128, 1, 4}, + [SPD900] = {TETRIS_PLL, 72, 1, 2}, + [SPD1000] = {TETRIS_PLL, 80, 1, 2}, + }, + [SYSCLK_26MHz] = { + [SPD200] = {TETRIS_PLL, 307, 4, 10}, + [SPD400] = {TETRIS_PLL, 369, 4, 6}, + [SPD600] = {TETRIS_PLL, 369, 4, 4}, + [SPD800] = {TETRIS_PLL, 123, 1, 4}, + [SPD900] = {TETRIS_PLL, 69, 1, 2}, + [SPD1000] = {TETRIS_PLL, 384, 5, 2}, + }, +}; + +static struct pll_init_data uart_pll_config[MAX_SYSCLK] = { + [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8}, + [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8}, + [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10}, + [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2}, };
-static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; -static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; -static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 133, 1, 16}; +static struct pll_init_data nss_pll_config[MAX_SYSCLK] = { + [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2}, + [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2}, + [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2}, + [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2}, +}; + +static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = { + [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16}, + [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16}, + [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16}, + [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16}, +};
struct pll_init_data *get_pll_init_data(int pll) { int speed; struct pll_init_data *data = NULL; + u8 sysclk_index = get_sysclk_index();
switch (pll) { case MAIN_PLL: speed = get_max_dev_speed(dev_speeds); - data = &main_pll_config[speed]; + data = &main_pll_config[sysclk_index][speed]; break; case TETRIS_PLL: speed = get_max_arm_speed(arm_speeds); - data = &tetris_pll_config[speed]; + data = &tetris_pll_config[sysclk_index][speed]; break; case NSS_PLL: - data = &nss_pll_config; + data = &nss_pll_config[sysclk_index]; break; case UART_PLL: - data = &uart_pll_config; + data = &uart_pll_config[sysclk_index]; break; case DDR3_PLL: - data = &ddr3_pll_config; + data = &ddr3_pll_config[sysclk_index]; break; default: data = NULL;
On Wed, May 03, 2017 at 04:58:25PM +0530, Lokesh Vutla wrote:
K2G supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configured based on this sysclock frequency. Add PLL configurations for all supported sysclk frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, May 03, 2017 at 04:58:25PM +0530, Lokesh Vutla wrote:
K2G supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configured based on this sysclock frequency. Add PLL configurations for all supported sysclk frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
One some keystone2 platforms like K2G ICE, there is an option to switch between 24MHz or 25MHz as sysclk. But the existing driver assumes it is always 24MHz. Add support for getting all reference clocks dynamically by reading boot pins.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-keystone/clock.c | 12 +++++----- arch/arm/mach-keystone/include/mach/clock.h | 2 +- board/ti/ks2_evm/board_k2e.c | 30 +++++++++++++++++++----- board/ti/ks2_evm/board_k2g.c | 36 ++++++++++++++++++++++------- board/ti/ks2_evm/board_k2hk.c | 31 +++++++++++++++++++++++++ board/ti/ks2_evm/board_k2l.c | 34 +++++++++++++++++++++------ include/configs/ti_armv7_keystone2.h | 2 +- 7 files changed, 118 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index 68f898036f..645bd9629e 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -284,7 +284,7 @@ static unsigned long pll_freq_get(int pll) u32 tmp, reg;
if (pll == MAIN_PLL) { - ret = external_clk[sys_clk]; + ret = get_external_clk(sys_clk); if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) { /* PLL mode */ tmp = __raw_readl(KS2_MAINPLLCTL0); @@ -302,23 +302,23 @@ static unsigned long pll_freq_get(int pll) } else { switch (pll) { case PASS_PLL: - ret = external_clk[pa_clk]; + ret = get_external_clk(pa_clk); reg = KS2_PASSPLLCTL0; break; case TETRIS_PLL: - ret = external_clk[tetris_clk]; + ret = get_external_clk(tetris_clk); reg = KS2_ARMPLLCTL0; break; case DDR3A_PLL: - ret = external_clk[ddr3a_clk]; + ret = get_external_clk(ddr3a_clk); reg = KS2_DDR3APLLCTL0; break; case DDR3B_PLL: - ret = external_clk[ddr3b_clk]; + ret = get_external_clk(ddr3b_clk); reg = KS2_DDR3BPLLCTL0; break; case UART_PLL: - ret = external_clk[uart_clk]; + ret = get_external_clk(uart_clk); reg = KS2_UARTPLLCTL0; break; default: diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index 0d8a9444de..006d0744d1 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -117,7 +117,6 @@ struct pll_init_data { int pll_od; /* PLL output divider */ };
-extern unsigned int external_clk[ext_clk_count]; extern const struct keystone_pll_regs keystone_pll_regs[]; extern s16 divn_val[]; extern int speeds[]; @@ -129,6 +128,7 @@ unsigned long ks_clk_get_rate(unsigned int clk); int get_max_dev_speed(int *spds); int get_max_arm_speed(int *spds); void pll_pa_clk_sel(void); +unsigned int get_external_clk(u32 clk);
#endif #endif diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index 4bbcf2df4e..266a66b678 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -14,12 +14,30 @@
DECLARE_GLOBAL_DATA_PTR;
-unsigned int external_clk[ext_clk_count] = { - [sys_clk] = 100000000, - [alt_core_clk] = 100000000, - [pa_clk] = 100000000, - [ddr3a_clk] = 100000000, -}; +unsigned int get_external_clk(u32 clk) +{ + unsigned int clk_freq; + + switch (clk) { + case sys_clk: + clk_freq = 100000000; + break; + case alt_core_clk: + clk_freq = 100000000; + break; + case pa_clk: + clk_freq = 100000000; + break; + case ddr3a_clk: + clk_freq = 100000000; + break; + default: + clk_freq = 0; + break; + } + + return clk_freq; +}
static struct pll_init_data core_pll_config[NUM_SPDS] = { [SPD800] = CORE_PLL_800, diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 6c590b4ff9..da21fd6f73 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -17,7 +17,6 @@ #include "mux-k2g.h" #include "../common/board_detect.h"
-#define SYS_CLK 24000000 #define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
const unsigned int sysclk_array[MAX_SYSCLK] = { @@ -27,13 +26,34 @@ const unsigned int sysclk_array[MAX_SYSCLK] = { 26000000, };
-unsigned int external_clk[ext_clk_count] = { - [sys_clk] = SYS_CLK, - [pa_clk] = SYS_CLK, - [tetris_clk] = SYS_CLK, - [ddr3a_clk] = SYS_CLK, - [uart_clk] = SYS_CLK, -}; +unsigned int get_external_clk(u32 clk) +{ + unsigned int clk_freq; + u8 sysclk_index = get_sysclk_index(); + + switch (clk) { + case sys_clk: + clk_freq = sysclk_array[sysclk_index]; + break; + case pa_clk: + clk_freq = sysclk_array[sysclk_index]; + break; + case tetris_clk: + clk_freq = sysclk_array[sysclk_index]; + break; + case ddr3a_clk: + clk_freq = sysclk_array[sysclk_index]; + break; + case uart_clk: + clk_freq = sysclk_array[sysclk_index]; + break; + default: + clk_freq = 0; + break; + } + + return clk_freq; +}
static int arm_speeds[DEVSPEED_NUMSPDS] = { SPD400, diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index 6f2246f39e..c7330996d1 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -23,6 +23,37 @@ unsigned int external_clk[ext_clk_count] = { [ddr3b_clk] = 100000000, };
+unsigned int get_external_clk(u32 clk) +{ + unsigned int clk_freq; + + switch (clk) { + case sys_clk: + clk_freq = 122880000; + break; + case alt_core_clk: + clk_freq = 125000000; + break; + case pa_clk: + clk_freq = 122880000; + break; + case tetris_clk: + clk_freq = 125000000; + break; + case ddr3a_clk: + clk_freq = 100000000; + break; + case ddr3b_clk: + clk_freq = 100000000; + break; + default: + clk_freq = 0; + break; + } + + return clk_freq; +} + static struct pll_init_data core_pll_config[NUM_SPDS] = { [SPD800] = CORE_PLL_799, [SPD1000] = CORE_PLL_999, diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index dfd82165f8..166367bfb9 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -14,13 +14,33 @@
DECLARE_GLOBAL_DATA_PTR;
-unsigned int external_clk[ext_clk_count] = { - [sys_clk] = 122880000, - [alt_core_clk] = 100000000, - [pa_clk] = 122880000, - [tetris_clk] = 122880000, - [ddr3a_clk] = 100000000, -}; +unsigned int get_external_clk(u32 clk) +{ + unsigned int clk_freq; + + switch (clk) { + case sys_clk: + clk_freq = 122880000; + break; + case alt_core_clk: + clk_freq = 100000000; + break; + case pa_clk: + clk_freq = 122880000; + break; + case tetris_clk: + clk_freq = 122880000; + break; + case ddr3a_clk: + clk_freq = 100000000; + break; + default: + clk_freq = 0; + break; + } + + return clk_freq; +}
static struct pll_init_data core_pll_config[NUM_SPDS] = { [SPD800] = CORE_PLL_799, diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 5d2a7ab509..868464cd32 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -318,7 +318,7 @@ #ifndef CONFIG_SOC_K2G #define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) #else -#define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk] +#define CONFIG_SYS_HZ_CLOCK get_external_clk(sys_clk) #endif
#endif /* __CONFIG_KS2_EVM_H */
On Wed, May 03, 2017 at 04:58:26PM +0530, Lokesh Vutla wrote:
One some keystone2 platforms like K2G ICE, there is an option to switch between 24MHz or 25MHz as sysclk. But the existing driver assumes it is always 24MHz. Add support for getting all reference clocks dynamically by reading boot pins.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, May 03, 2017 at 04:58:26PM +0530, Lokesh Vutla wrote:
One some keystone2 platforms like K2G ICE, there is an option to switch between 24MHz or 25MHz as sysclk. But the existing driver assumes it is always 24MHz. Add support for getting all reference clocks dynamically by reading boot pins.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
participants (2)
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Lokesh Vutla -
Tom Rini