[U-Boot] [PATCH 0/2] sunxi: Fix SRAM C corruption issue on Allwinner A64
The full SPL support is not quite ready for Allwinner A64 yet, but these fixes are likely to be necessary. Of course, unless the problem is actually caused by wrong voltages and the AXP803 PMIC support magically fixes it.
PS. Discovered when developing a sunxi-fel based SPI flash programmer tool and trying to use the SRAM C on A64 as a temporary buffer (after loading the U-Boot SPL with the hope to gain more speed from the higher CPU and AHB clock speeds).
Siarhei Siamashka (2): sunxi: Downclock AHB1 to 100MHz on Allwinner A64 sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +++++ include/configs/sunxi-common.h | 5 ++--- 2 files changed, 7 insertions(+), 3 deletions(-)
Currently the AHB1 clock speed is configured as 200MHz by the SPL, but this causes a subtle and hard to reproduce data corruption in SRAM C (for example, this can't be easily detected with a trivial memset/memcmp test).
For what it's worth, the Allwinner's BSP configures AHB1 as 200MHz, as can be verified by running the devmem2 tool in the system running the Allwinner's kernel 3.10.x:
0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3180 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x1
However the FEL mode uses more conservative settings (100MHz for AHB1):
0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3180 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x0
It is yet to be confirmed whether faster AHB1/AHB2 clock settings can be used safely if we initialize the AXP803 PMIC instead of using reset defaults. But in order to resolve the data corruption problem right now, it's best to downclock AHB1 to a safe level.
Note that this issue only affects the SPL, which is not fully supported on Allwinner A64 yet and it should not affect the boot0 usage (unless somebody can confirm SRAM C corruption with the boot0 too).
Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index f2990db..c2e72f5 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -222,7 +222,12 @@ struct sunxi_ccm_reg { #define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_EN (0x1 << 31)
+#if defined(CONFIG_MACH_SUN50I) +/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */ +#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */ +#else #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ +#endif
#define AXI_GATE_OFFSET_DRAM 0
On Tue, 31 May 2016 01:48:05 +0300 Siarhei Siamashka siarhei.siamashka@gmail.com wrote:
Currently the AHB1 clock speed is configured as 200MHz by the SPL, but this causes a subtle and hard to reproduce data corruption in SRAM C (for example, this can't be easily detected with a trivial memset/memcmp test).
For what it's worth, the Allwinner's BSP configures AHB1 as 200MHz, as can be verified by running the devmem2 tool in the system running the Allwinner's kernel 3.10.x:
0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3180 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x1
However the FEL mode uses more conservative settings (100MHz for AHB1):
0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3180
Oops, a copy-paste issue when editing the commit message, this should be 0x3190
0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x0
It is yet to be confirmed whether faster AHB1/AHB2 clock settings can be used safely if we initialize the AXP803 PMIC instead of using reset defaults. But in order to resolve the data corruption problem right now, it's best to downclock AHB1 to a safe level.
Note that this issue only affects the SPL, which is not fully supported on Allwinner A64 yet and it should not affect the boot0 usage (unless somebody can confirm SRAM C corruption with the boot0 too).
Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index f2990db..c2e72f5 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -222,7 +222,12 @@ struct sunxi_ccm_reg { #define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_EN (0x1 << 31)
+#if defined(CONFIG_MACH_SUN50I) +/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */ +#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */ +#else #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ +#endif
#define AXI_GATE_OFFSET_DRAM 0
Hi,
On 31-05-16 00:55, Siarhei Siamashka wrote:
On Tue, 31 May 2016 01:48:05 +0300 Siarhei Siamashka siarhei.siamashka@gmail.com wrote:
Currently the AHB1 clock speed is configured as 200MHz by the SPL, but this causes a subtle and hard to reproduce data corruption in SRAM C (for example, this can't be easily detected with a trivial memset/memcmp test).
For what it's worth, the Allwinner's BSP configures AHB1 as 200MHz, as can be verified by running the devmem2 tool in the system running the Allwinner's kernel 3.10.x:
0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3180 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x1
However the FEL mode uses more conservative settings (100MHz for AHB1):
0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3180
Oops, a copy-paste issue when editing the commit message, this should be 0x3190
Thanks I've added both patches to u-boot-sunxi, with the commit msg fixed-up. I'll send out a pull-req to get these into v2016.07 soon after this mail.
Regards,
Hans
0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x0
It is yet to be confirmed whether faster AHB1/AHB2 clock settings can be used safely if we initialize the AXP803 PMIC instead of using reset defaults. But in order to resolve the data corruption problem right now, it's best to downclock AHB1 to a safe level.
Note that this issue only affects the SPL, which is not fully supported on Allwinner A64 yet and it should not affect the boot0 usage (unless somebody can confirm SRAM C corruption with the boot0 too).
Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index f2990db..c2e72f5 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -222,7 +222,12 @@ struct sunxi_ccm_reg { #define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_EN (0x1 << 31)
+#if defined(CONFIG_MACH_SUN50I) +/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */ +#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */ +#else #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ +#endif
#define AXI_GATE_OFFSET_DRAM 0
Since the SRAM C corruption issue is now resolved on Allwinner A64, it is possible to move the stack top to the address 0x1A000 on both A64 and A80. The boot ROM can load SPL binaries with up to 32 KiB size on A64 (the 24 KiB SPL size limitation only affects A10/A20), and this patch also ensures the availability of 8 KiB stack.
Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com --- include/configs/sunxi-common.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b33cfb8..94275a7 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -100,7 +100,7 @@ * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. */ #define CONFIG_SYS_INIT_RAM_ADDR 0x10000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */ +#define CONFIG_SYS_INIT_RAM_SIZE 0xA000 /* 40 KiB */ #else #define CONFIG_SYS_INIT_RAM_ADDR 0x0 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ @@ -213,8 +213,7 @@ #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I) -/* FIXME: 40 KiB instead of 32 KiB ? */ -#define LOW_LEVEL_SRAM_STACK 0x00018000 +#define LOW_LEVEL_SRAM_STACK 0x0001A000 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #else /* end of 32 KiB in sram */
participants (2)
-
Hans de Goede -
Siarhei Siamashka