Provide a page describing the usage of U-Boot on the LicheeRV Nano and a description of the board.

Signed-off-by: Thomas Bonnefille thomas.bonnefille@bootlin.com --- doc/board/sophgo/licheerv_nano.rst | 72 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+)

diff --git a/doc/board/sophgo/licheerv_nano.rst b/doc/board/sophgo/licheerv_nano.rst new file mode 100644 index 0000000000000000000000000000000000000000..70401e295c4a56845353c3a92ab4ec98678a1180 --- /dev/null +++ b/doc/board/sophgo/licheerv_nano.rst @@ -0,0 +1,72 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +LicheeRV Nano +========== + +SG2002 RISC-V SoC +------------------ +The SG2002 is a high-performance, low-power 64-bit RISC-V/ARM SoC from Sophgo. + +Mainline support +---------------- +The support for following drivers are already enabled: +1. ns16550 UART Driver. +2. Synopsys Designware MSHC Driver + +Building +~~~~~~~~ +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: console + + export CROSS_COMPILE=<riscv64 toolchain prefix> + cd <U-Boot-dir> + make licheerv_nano_defconfig + make + +This will generate u-boot.bin + +Booting +~~~~~~~ +Currently, we rely on vendor FSBL (First Stage Boot Loader) to initialize the +clock and load the u-boot image, then bootup from it. + +To run u-boot.bin on top of FSBL, follow these steps: + +1. Use mainline OpenSBI with a newer version than 1.5 to generate fw_dynamic. + +2. Generate a compatible u-boot.bin using U-Boot with the LicheeRV Nano default + configuration. + +3. Use the vendor-provided tool [1] to create a unified fip.bin file containing + FSBL, OpenSBI, and U-Boot. + Note that you will have to use the file cv181x.bin as the FSBL. + +2. Place the generated fip.bin file into the FAT partition of the SD card. + +3. Insert the SD card into the board and power it on. + +The board will automatically execute the FSBL from the fip.bin file. +Subsequently, it will transition to OpenSBI, and finally, OpenSBI will invoke +U-Boot. + +[1]: https://github.com/sophgo/fiptool + + +Sample boot log from LicheeRV Nano board +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none + + U-Boot 2024.10 (Oct 24 2024 - 15:00:20 +0200)licheerv_nano + + DRAM: 256 MiB + Core: 19 devices, 11 uclasses, devicetree: separate + MMC: mmc@4310000: 0 + Loading Environment from nowhere... OK + In: serial@4140000 + Out: serial@4140000 + Err: serial@4140000 + Net: No ethernet found. + Hit any key to stop autoboot: 0 + licheerv_nano#

Import a slightly modified version of the LicheeRV Nano and SG2002 device trees from the Linux Kernel. The current supported IPs are UART, MMC, Timer, PLIC and CLINT.

Signed-off-by: Thomas Bonnefille thomas.bonnefille@bootlin.com --- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/sg2002-licheerv-nano-b.dts | 45 +++++++++++++++++++++++++++++++ arch/riscv/dts/sg2002.dtsi | 34 +++++++++++++++++++++++ 3 files changed, 80 insertions(+)

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 17cda483e128996bb944f5a2b9b7676d32e45ae5..0848cded398d45955dcc17b339dc1869829c6467 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb +dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb diff --git a/arch/riscv/dts/sg2002-licheerv-nano-b.dts b/arch/riscv/dts/sg2002-licheerv-nano-b.dts new file mode 100644 index 0000000000000000000000000000000000000000..9871a75836c04a0b0943dc44c6a1090c90752dbd --- /dev/null +++ b/arch/riscv/dts/sg2002-licheerv-nano-b.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Thomas Bonnefille thomas.bonnefille@bootlin.com + */ + +/dts-v1/; + +#include "sg2002.dtsi" + +/ { + model = "LicheeRV Nano B"; + compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", "sophgo,sg2002"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&sdhci0 { + status = "okay"; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/dts/sg2002.dtsi b/arch/riscv/dts/sg2002.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..0f97000fa8beaaa10a08d03211f7c4a0c2f6e001 --- /dev/null +++ b/arch/riscv/dts/sg2002.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Thomas Bonnefille thomas.bonnefille@bootlin.com + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include "cv18xx.dtsi" + +/ { + compatible = "sophgo,sg2002"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&plic { + compatible = "sophgo,sg2002-plic", "sophgo,cv1800b-plic", "thead,c900-plic"; +}; + +&clint { + compatible = "sophgo,sg2002-plic", "sophgo,cv1800b-clint", "thead,c900-clint"; +}; + +&clk { + compatible = "sophgo,sg2002-clk", "sophgo,cv1800-clk"; +}; + +&sdhci0 { + compatible = "sophgo,sg2002-dwcmshc", "sophgo,cv1800b-dwcmshc"; +};