[U-Boot] [PATCH v4 0/9] arm: socfpga: implement proper peripheral reset handling
This series implements peripheral reset handling for socfpga gen5.
It moves from enabling all peripherals during SPL startup to using the socfpga reset driver from all peripherals and enabling peripherals when they are used.
As Linux cannot even handle this in 4.20, the reset driver implements a compatibility mode where it takes all peripherals out of reset before jumping to the OS if an environment variable "socfpga_legacy_reset_compat=1" is found. This is enabled by default for socfpga gen5 boards, but should be moved to default off in the near future once a Linux kernel supports reset handling for all drivers.
Changes in v4: - added patch that renames 'membase' to 'modrst_base'
Changes in v3: - centralize u-boot,dem-pre-reloc for soc, rst and sdr into one common file - rename env var to socfpga_legacy_reset_compat - add env var to CONFIG_EXTRA_ENV_SETTINGS without further ifdefs - changed the order of patches to keep things bisectable - fix falcon mode in SPL should work, too - change env var name "socfpga_permodrst_ungate" to "socfpga_legacy_reset_compat" - in compat mode, don't reset peripherals once they are enabled - add DM_FLAG_OS_PREPARE flag - add DM_FLAG_OS_PREPARE flag - keep the call to enable fpga bridges in SPL
Changes in v2: - cleanly merged Linux dts (moved change of SDR controller base address to a separate patch) - this patch is new in v2 - moved from Kernel option "OLD_SOCFPGA_KERNEL_COMPAT" to environment variable "socfpga_permodrst_ungate" - port DDR driver to DM UCLASS_RAM - don't change DDR calibration training driver (code got too big) - use reset.h code instead of socfpga_per_reset() - fix copy/paste issues - add .remove callback to release the resets - add .remove callback to release the resets - removed Kconfig option OLD_SOCFPGA_KERNEL_COMPAT since compatibility now uses an environment variable
Simon Goldschmidt (9): arm: socfpga: gen5: sync devicetrees to Linux arm: socfpga: gen5: add reset & sdr node to SPL devicetrees reset: socfpga: rename membase ptr to modrst_base arm: socfpga: gen5: deassert peripheral reset by default reset: socfpga: add reset handling for old kernels arm: socfpga: move gen5 SDR driver to DM mtd: rawnand: denali: add reset handling spi: cadence_qspi: add reset handling arm: socfpga: implement proper peripheral reset
arch/arm/Kconfig | 2 + arch/arm/dts/socfpga-common-u-boot.dtsi | 19 +++ arch/arm/dts/socfpga.dtsi | 23 ++- arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 6 +- arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 5 +- .../socfpga_cyclone5_de0_nano_soc-u-boot.dtsi | 6 +- arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 5 +- arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 5 +- arch/arm/dts/socfpga_cyclone5_is1.dts | 5 +- .../dts/socfpga_cyclone5_socdk-u-boot.dtsi | 6 +- .../dts/socfpga_cyclone5_sockit-u-boot.dtsi | 6 +- .../dts/socfpga_cyclone5_socrates-u-boot.dtsi | 6 +- arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 - arch/arm/dts/socfpga_cyclone5_sr1500.dts | 5 +- .../socfpga_cyclone5_vining_fpga-u-boot.dtsi | 6 +- .../mach-socfpga/include/mach/sdram_gen5.h | 4 - arch/arm/mach-socfpga/misc_gen5.c | 10 -- arch/arm/mach-socfpga/spl_gen5.c | 38 ++--- drivers/ddr/altera/Kconfig | 1 + drivers/ddr/altera/sdram_gen5.c | 143 ++++++++++++++++-- drivers/ddr/altera/sequencer.c | 9 +- drivers/ddr/altera/sequencer.h | 35 +++++ drivers/mtd/nand/raw/denali.h | 2 + drivers/mtd/nand/raw/denali_dt.c | 15 ++ drivers/reset/reset-socfpga.c | 55 ++++++- drivers/spi/cadence_qspi.c | 17 +++ drivers/spi/cadence_qspi.h | 4 + include/configs/socfpga_common.h | 1 + 28 files changed, 328 insertions(+), 113 deletions(-) create mode 100644 arch/arm/dts/socfpga-common-u-boot.dtsi
This is again a sync to linux-next + pending patches in Dinh's tree at commit 1c909b2dfe6a ("ARM: dts: socfpga: update more missing reset properties")'
It adds missing peripheral reset properties to socfpga.dtsi and removes U-Boot specific leftovers from socfpga_cyclone5_socrates.dts.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: None Changes in v3: None Changes in v2: - cleanly merged Linux dts (moved change of SDR controller base address to a separate patch)
arch/arm/dts/socfpga.dtsi | 19 +++++++++++++++++-- arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 -- 2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 2458d6707d..ec1966480f 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -84,6 +84,7 @@ #dma-requests = <32>; clocks = <&l4_main_clk>; clock-names = "apb_pclk"; + resets = <&rst DMA_RESET>; }; };
@@ -100,6 +101,7 @@ reg = <0xffc00000 0x1000>; interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; clocks = <&can0_clk>; + resets = <&rst CAN0_RESET>; status = "disabled"; };
@@ -108,6 +110,7 @@ reg = <0xffc01000 0x1000>; interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; clocks = <&can1_clk>; + resets = <&rst CAN1_RESET>; status = "disabled"; };
@@ -585,6 +588,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff708000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO0_RESET>; status = "disabled";
porta: gpio-controller@0 { @@ -605,6 +609,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff709000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO1_RESET>; status = "disabled";
portb: gpio-controller@0 { @@ -625,6 +630,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff70a000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO2_RESET>; status = "disabled";
portc: gpio-controller@0 { @@ -735,6 +741,7 @@ #size-cells = <0>; clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; + resets = <&rst SDMMC_RESET>; status = "disabled"; };
@@ -746,9 +753,9 @@ <0xffb80000 0x10000>; reg-names = "nand_data", "denali_reg"; interrupts = <0x0 0x90 0x4>; - dma-mask = <0xffffffff>; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; + resets = <&rst NAND_RESET>; status = "disabled"; };
@@ -759,7 +766,7 @@
qspi: spi@ff705000 { compatible = "cdns,qspi-nor"; - #address-cells = <1>; + #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, <0xffa00000 0x1000>; @@ -768,6 +775,7 @@ cdns,fifo-width = <4>; cdns,trigger-address = <0x00000000>; clocks = <&qspi_clk>; + resets = <&rst QSPI_RESET>; status = "disabled"; };
@@ -786,6 +794,7 @@ sdr: sdr@ffc25000 { compatible = "altr,sdr-ctl", "syscon"; reg = <0xffc25000 0x1000>; + resets = <&rst SDR_RESET>; };
sdramedac { @@ -802,6 +811,7 @@ interrupts = <0 154 4>; num-cs = <4>; clocks = <&spi_m_clk>; + resets = <&rst SPIM0_RESET>; status = "disabled"; };
@@ -813,6 +823,7 @@ interrupts = <0 155 4>; num-cs = <4>; clocks = <&spi_m_clk>; + resets = <&rst SPIM1_RESET>; status = "disabled"; };
@@ -879,6 +890,7 @@ dmas = <&pdma 28>, <&pdma 29>; dma-names = "tx", "rx"; + resets = <&rst UART0_RESET>; };
uart1: serial1@ffc03000 { @@ -891,6 +903,7 @@ dmas = <&pdma 30>, <&pdma 31>; dma-names = "tx", "rx"; + resets = <&rst UART1_RESET>; };
usbphy0: usbphy { @@ -930,6 +943,7 @@ reg = <0xffd02000 0x1000>; interrupts = <0 171 4>; clocks = <&osc1>; + resets = <&rst L4WD0_RESET>; status = "disabled"; };
@@ -938,6 +952,7 @@ reg = <0xffd03000 0x1000>; interrupts = <0 172 4>; clocks = <&osc1>; + resets = <&rst L4WD1_RESET>; status = "disabled"; }; }; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 93c3fa4a48..8d5d3996f6 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -76,7 +76,6 @@
&qspi { status = "okay"; - u-boot,dm-pre-reloc;
flash: flash@0 { #address-cells = <1>; @@ -91,6 +90,5 @@ cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; status = "okay"; - u-boot,dm-pre-reloc; }; };
The SPL for socfpga gen5 currently takes all peripherals out of reset unconditionally. To implement proper reset handling for peripherals, the reset node has to be provided with the SPL dts.
In preparation to move the DDR driver to DM, the sdr node is required in SPL, too.
This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon files so that the reset manager and SDR driver correctly probe in SPL. It centralizes these settings into a common file since in contrast to boot-type specific nodes, "soc", "rst" and "sdr" are always needed.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: None Changes in v3: - centralize u-boot,dem-pre-reloc for soc, rst and sdr into one common file
Changes in v2: None
arch/arm/dts/socfpga-common-u-boot.dtsi | 19 +++++++++++++++++++ arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 6 ++---- arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 5 +---- .../socfpga_cyclone5_de0_nano_soc-u-boot.dtsi | 6 ++---- arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 5 +---- arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 5 +---- arch/arm/dts/socfpga_cyclone5_is1.dts | 5 +---- .../dts/socfpga_cyclone5_socdk-u-boot.dtsi | 6 ++---- .../dts/socfpga_cyclone5_sockit-u-boot.dtsi | 6 ++---- .../dts/socfpga_cyclone5_socrates-u-boot.dtsi | 6 ++---- arch/arm/dts/socfpga_cyclone5_sr1500.dts | 5 +---- .../socfpga_cyclone5_vining_fpga-u-boot.dtsi | 6 ++---- 12 files changed, 36 insertions(+), 44 deletions(-) create mode 100644 arch/arm/dts/socfpga-common-u-boot.dtsi
diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi new file mode 100644 index 0000000000..322c858c4b --- /dev/null +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (c) 2019 Simon Goldschmidt + */ +/{ + soc { + u-boot,dm-pre-reloc; + }; +}; + +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi index c44d1ee2fa..e059831a08 100644 --- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */
+#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts index a387071674..6439daa525 100644 --- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts +++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts @@ -4,6 +4,7 @@ */
#include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi"
/ { model = "Devboards.de DBM-SoC1"; @@ -24,10 +25,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; };
&gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi index 08d81da169..0219c6948d 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi @@ -6,14 +6,12 @@ * Copyright (c) 2018 Simon Goldschmidt */
+#include "socfpga-common-u-boot.dtsi" + /{ aliases { udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index e9105743ea..b620dd8dda 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -6,6 +6,7 @@ */
#include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi"
/ { model = "Terasic DE10-Nano"; @@ -26,10 +27,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; };
&gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts index 4f076bce93..ff1e61e0cb 100644 --- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts @@ -4,6 +4,7 @@ */
#include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi"
/ { model = "Terasic DE1-SoC"; @@ -24,10 +25,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; };
&gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index b7054bfd5a..1788e4dfa3 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -4,6 +4,7 @@ */
#include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi"
/ { model = "SoCFPGA Cyclone V IS1"; @@ -31,10 +32,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi index 9436e0fa8b..3b6887fb84 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */
+#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&can0 { diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi index 648f1bd01d..7c569488e6 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */
+#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi index 31bd1dba0f..ad88d3ff7b 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */
+#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts index 6a6c29be79..26efe04de0 100644 --- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -4,6 +4,7 @@ */
#include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi"
/ { model = "SoCFPGA Cyclone V SR1500"; @@ -27,10 +28,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; };
&gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 360b946ba2..743ad3a5c0 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */
+#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb0; }; - - soc { - u-boot,dm-pre-reloc; - }; };
&watchdog0 {
The only member of this driver's priv struct is a pointer, which is called 'membase'. However, since this driver handles multiple sub- architectures, this is not the base address from dts but the base address of some common registers of those sub-arches.
Reflect this better in sourcecode by renaming 'membase' to 'modrst_base'.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: - added patch that renames 'membase' to 'modrst_base'
Changes in v3: None Changes in v2: None
drivers/reset/reset-socfpga.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index b2acfcd2ec..244db51d85 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -24,7 +24,7 @@ #define NR_BANKS 8
struct socfpga_reset_data { - void __iomem *membase; + void __iomem *modrst_base; };
static int socfpga_reset_assert(struct reset_ctl *reset_ctl) @@ -35,7 +35,7 @@ static int socfpga_reset_assert(struct reset_ctl *reset_ctl) int bank = id / (reg_width * BITS_PER_BYTE); int offset = id % (reg_width * BITS_PER_BYTE);
- setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); + setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset)); return 0; }
@@ -47,7 +47,7 @@ static int socfpga_reset_deassert(struct reset_ctl *reset_ctl) int bank = id / (reg_width * BITS_PER_BYTE); int offset = id % (reg_width * BITS_PER_BYTE);
- clrbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); + clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset)); return 0; }
@@ -80,11 +80,12 @@ static int socfpga_reset_probe(struct udevice *dev) const void *blob = gd->fdt_blob; int node = dev_of_offset(dev); u32 modrst_offset; + void __iomem *membase;
- data->membase = devfdt_get_addr_ptr(dev); + membase = devfdt_get_addr_ptr(dev);
modrst_offset = fdtdec_get_int(blob, node, "altr,modrst-offset", 0x10); - data->membase += modrst_offset; + data->modrst_base = membase + modrst_offset;
return 0; }
To keep the current behaviour of taking all peripherals out of reset before booting the OS before removing that code from socfpga gen5 SPL, this enables the new behaviour by default for all gen5 boards by adding the environment variable "socfpga_legacy_reset_compat=1" to the default environment.
This can be overridden in board config files or by saving an environment without this variable enabled.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: None Changes in v3: - rename env var to socfpga_legacy_reset_compat - add env var to CONFIG_EXTRA_ENV_SETTINGS without further ifdefs - changed the order of patches to keep things bisectable
Changes in v2: - this patch is new in v2
include/configs/socfpga_common.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c9cbf8f5e3..f7e2c6b240 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -330,6 +330,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "scriptaddr=0x02100000\0" \ "pxefile_addr_r=0x02200000\0" \ "ramdisk_addr_r=0x02300000\0" \ + "socfpga_legacy_reset_compat=1\0" \ BOOTENV
#endif
This adds code to take peripherals out of reset based on an environment variable. This is in preparation for removing the code that does this from SPL.
However, some drivers even in current Linux cannot handle peripheral reset, so until this works, we need a compatibility workaround.
This workaround is implemented in the 'assert' and 'remove' callbacks of this reset driver: the 'assert' callback does not disable peripherals that were already taken out of reset, while the 'remove' callback, which is called on OS_PREPARE, deasserts all peripheral resets if the environment variable "socfpga_legacy_reset_compat" is set to 1, which is what the gen5 SPL did up to now.
This is in preparation to clean up the SPL and implementing proper reset handling for U-Boot.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: None Changes in v3: - fix falcon mode in SPL should work, too - change env var name "socfpga_permodrst_ungate" to "socfpga_legacy_reset_compat" - in compat mode, don't reset peripherals once they are enabled
Changes in v2: - moved from Kernel option "OLD_SOCFPGA_KERNEL_COMPAT" to environment variable "socfpga_permodrst_ungate"
drivers/reset/reset-socfpga.c | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+)
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 244db51d85..cb8312619f 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -27,6 +27,36 @@ struct socfpga_reset_data { void __iomem *modrst_base; };
+/* + * For compatibility with Kernels that don't support peripheral reset, this + * driver can keep the old behaviour of not asserting peripheral reset before + * starting the OS and deasserting all peripheral resets (enabling all + * peripherals). + * + * For that, the reset driver checks the environment variable + * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not + * reset again once taken out of reset and all peripherals in 'permodrst' are + * taken out of reset before booting into the OS. + * Note that this should be required for gen5 systems only that are running + * Linux kernels without proper peripheral reset support for all drivers used. + */ +static bool socfpga_reset_keep_enabled(void) +{ +#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT) + const char *env_str; + long val; + + env_str = env_get("socfpga_legacy_reset_compat"); + if (env_str) { + val = simple_strtol(env_str, NULL, 0); + if (val == 1) + return true; + } +#endif + + return false; +} + static int socfpga_reset_assert(struct reset_ctl *reset_ctl) { struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); @@ -90,6 +120,18 @@ static int socfpga_reset_probe(struct udevice *dev) return 0; }
+static int socfpga_reset_remove(struct udevice *dev) +{ + struct socfpga_reset_data *data = dev_get_priv(dev); + + if (socfpga_reset_keep_enabled()) { + puts("Deasserting all peripheral resets\n"); + writel(0, data->modrst_base + 4); + } + + return 0; +} + static const struct udevice_id socfpga_reset_match[] = { { .compatible = "altr,rst-mgr" }, { /* sentinel */ }, @@ -102,4 +144,6 @@ U_BOOT_DRIVER(socfpga_reset) = { .probe = socfpga_reset_probe, .priv_auto_alloc_size = sizeof(struct socfpga_reset_data), .ops = &socfpga_reset_ops, + .remove = socfpga_reset_remove, + .flags = DM_FLAG_OS_PREPARE, };
To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling.
This gets us rid of one ad-hoc call to socfpga_per_reset().
The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise.
SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: None Changes in v3: None Changes in v2: - port DDR driver to DM UCLASS_RAM - don't change DDR calibration training driver (code got too big) - use reset.h code instead of socfpga_per_reset()
arch/arm/Kconfig | 2 + arch/arm/dts/socfpga.dtsi | 4 +- .../mach-socfpga/include/mach/sdram_gen5.h | 4 - arch/arm/mach-socfpga/spl_gen5.c | 29 ++-- drivers/ddr/altera/Kconfig | 1 + drivers/ddr/altera/sdram_gen5.c | 143 ++++++++++++++++-- drivers/ddr/altera/sequencer.c | 9 +- drivers/ddr/altera/sequencer.h | 35 +++++ 8 files changed, 185 insertions(+), 42 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ded7c11a4c..3b77d731a7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -821,12 +821,14 @@ config ARCH_SOCFPGA select DM_SERIAL select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select OF_CONTROL + select RAM if TARGET_SOCFPGA_GEN5 select SPL_DM_RESET if DM_RESET select SPL_DM_SERIAL select SPL_LIBCOMMON_SUPPORT select SPL_LIBGENERIC_SUPPORT select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL + select SPL_RAM if TARGET_SOCFPGA_GEN5 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 select SPL_SERIAL_SUPPORT select SPL_WATCHDOG_SUPPORT diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index ec1966480f..51a6a51b53 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -791,9 +791,9 @@ reg = <0xfffec000 0x100>; };
- sdr: sdr@ffc25000 { + sdr: sdr@ffc20000 { compatible = "altr,sdr-ctl", "syscon"; - reg = <0xffc25000 0x1000>; + reg = <0xffc20000 0x6000>; resets = <&rst SDR_RESET>; };
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h index a238d5d17f..c41208591a 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h @@ -7,10 +7,6 @@
#ifndef __ASSEMBLY__
-unsigned long sdram_calculate_size(void); -int sdram_mmr_init_full(unsigned int sdr_phy_reg); -int sdram_calibration_full(void); - const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 142b60f887..c5399bb697 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -21,6 +21,7 @@ #include <debug_uart.h> #include <fdtdec.h> #include <watchdog.h> +#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -123,9 +124,9 @@ static void socfpga_pl310_clear(void) void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); - unsigned long sdram_size; unsigned long reg; int ret; + struct udevice *dev;
/* * First C code to run. Clear fake OCRAM ECC first as SBE @@ -156,7 +157,6 @@ void board_init_f(ulong dummy) socfpga_bridges_reset(1); }
- socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
@@ -200,27 +200,16 @@ void board_init_f(ulong dummy) hang(); }
+ ret = uclass_get_device(UCLASS_RESET, 0, &dev); + if (ret) + debug("Reset init failed: %d\n", ret); + /* enable console uart printing */ preloader_console_init();
- if (sdram_mmr_init_full(0xffffffff) != 0) { - puts("SDRAM init failed.\n"); - hang(); - } - - debug("SDRAM: Calibrating PHY\n"); - /* SDRAM calibration */ - if (sdram_calibration_full() == 0) { - puts("SDRAM calibration failed.\n"); - hang(); - } - - sdram_size = sdram_calculate_size(); - debug("SDRAM: %ld MiB\n", sdram_size >> 20); - - /* Sanity check ensure correct SDRAM size specified */ - if (get_ram_size(0, sdram_size) != sdram_size) { - puts("SDRAM size check failed!\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); hang(); }
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 2b28a97f6e..7370d4133a 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,5 +1,6 @@ config ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver" + depends on RAM depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 821060459c..fcd89b619d 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -3,14 +3,30 @@ * Copyright Altera Corporation (C) 2014-2015 */ #include <common.h> +#include <dm.h> #include <errno.h> #include <div64.h> +#include <ram.h> +#include <reset.h> #include <watchdog.h> #include <asm/arch/fpga_manager.h> +#include <asm/arch/reset_manager.h> #include <asm/arch/sdram.h> #include <asm/arch/system_manager.h> #include <asm/io.h>
+#include "sequencer.h" + +#ifdef CONFIG_SPL_BUILD + +struct altera_gen5_sdram_priv { + struct ram_info info; +}; + +struct altera_gen5_sdram_platdata { + struct socfpga_sdr *sdr; +}; + struct sdram_prot_rule { u32 sdram_start; /* SDRAM start address */ u32 sdram_end; /* SDRAM end address */ @@ -26,8 +42,8 @@ struct sdram_prot_rule {
static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -static struct socfpga_sdr_ctrl *sdr_ctrl = - (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; + +static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
/** * get_errata_rows() - Up the number of DRAM rows to cover entire address space @@ -104,7 +120,8 @@ static int get_errata_rows(const struct socfpga_sdram_config *cfg) }
/* SDRAM protection rules vary from 0-19, a total of 20 rules. */ -static void sdram_set_rule(struct sdram_prot_rule *prule) +static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl, + struct sdram_prot_rule *prule) { u32 lo_addr_bits; u32 hi_addr_bits; @@ -141,7 +158,8 @@ static void sdram_set_rule(struct sdram_prot_rule *prule) writel(0, &sdr_ctrl->prot_rule_rdwr); }
-static void sdram_get_rule(struct sdram_prot_rule *prule) +static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl, + struct sdram_prot_rule *prule) { u32 addr; u32 id; @@ -172,7 +190,8 @@ static void sdram_get_rule(struct sdram_prot_rule *prule) }
static void -sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) +sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl, + const u32 sdram_start, const u32 sdram_end) { struct sdram_prot_rule rule; int rules; @@ -185,7 +204,7 @@ sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
for (rules = 0; rules < 20; rules++) { rule.rule = rules; - sdram_set_rule(&rule); + sdram_set_rule(sdr_ctrl, &rule); }
/* new rule: accept SDRAM */ @@ -200,13 +219,13 @@ sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) rule.rule = 0;
/* set new rule */ - sdram_set_rule(&rule); + sdram_set_rule(sdr_ctrl, &rule);
/* default rule: reject everything */ writel(0x3ff, &sdr_ctrl->protport_default); }
-static void sdram_dump_protection_config(void) +static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl) { struct sdram_prot_rule rule; int rules; @@ -216,7 +235,7 @@ static void sdram_dump_protection_config(void)
for (rules = 0; rules < 20; rules++) { rule.rule = rules; - sdram_get_rule(&rule); + sdram_get_rule(sdr_ctrl, &rule); debug("Rule %d, rules ...\n", rules); debug(" sdram start %x\n", rule.sdram_start); debug(" sdram end %x\n", rule.sdram_end); @@ -322,7 +341,8 @@ static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) * * This function loads the register values into the SDRAM controller block. */ -static void sdr_load_regs(const struct socfpga_sdram_config *cfg) +static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl, + const struct socfpga_sdram_config *cfg) { const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); const u32 dram_addrw = sdr_get_addr_rw(cfg); @@ -426,7 +446,8 @@ static void sdr_load_regs(const struct socfpga_sdram_config *cfg) * * Initialize the SDRAM MMR. */ -int sdram_mmr_init_full(unsigned int sdr_phy_reg) +int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl, + unsigned int sdr_phy_reg) { const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); const unsigned int rows = @@ -436,7 +457,7 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg)
writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
- sdr_load_regs(cfg); + sdr_load_regs(sdr_ctrl, cfg);
/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); @@ -459,9 +480,10 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
- sdram_set_protection_config(0, sdram_calculate_size() - 1); + sdram_set_protection_config(sdr_ctrl, 0, + sdram_calculate_size(sdr_ctrl) - 1);
- sdram_dump_protection_config(); + sdram_dump_protection_config(sdr_ctrl);
return 0; } @@ -472,7 +494,7 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) * Calculate SDRAM device size based on SDRAM controller parameters. * Size is specified in bytes. */ -unsigned long sdram_calculate_size(void) +static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl) { unsigned long temp; unsigned long row, bank, col, cs, width; @@ -534,3 +556,94 @@ unsigned long sdram_calculate_size(void)
return temp; } + +static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev) +{ + struct altera_gen5_sdram_platdata *plat = dev->platdata; + + plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0); + if (!plat->sdr) + return -ENODEV; + + return 0; +} + +static int altera_gen5_sdram_probe(struct udevice *dev) +{ + int ret; + unsigned long sdram_size; + struct altera_gen5_sdram_platdata *plat = dev->platdata; + struct altera_gen5_sdram_priv *priv = dev_get_priv(dev); + struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl; + struct reset_ctl_bulk resets; + + ret = reset_get_bulk(dev, &resets); + if (ret) { + dev_err(dev, "Can't get reset: %d\n", ret); + return -ENODEV; + } + reset_deassert_bulk(&resets); + + if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) { + puts("SDRAM init failed.\n"); + goto failed; + } + + debug("SDRAM: Calibrating PHY\n"); + /* SDRAM calibration */ + if (sdram_calibration_full(plat->sdr) == 0) { + puts("SDRAM calibration failed.\n"); + goto failed; + } + + sdram_size = sdram_calculate_size(sdr_ctrl); + debug("SDRAM: %ld MiB\n", sdram_size >> 20); + + /* Sanity check ensure correct SDRAM size specified */ + if (get_ram_size(0, sdram_size) != sdram_size) { + puts("SDRAM size check failed!\n"); + goto failed; + } + + priv->info.base = 0; + priv->info.size = sdram_size; + + return 0; + +failed: + reset_release_bulk(&resets); + return -ENODEV; +} + +static int altera_gen5_sdram_get_info(struct udevice *dev, + struct ram_info *info) +{ + struct altera_gen5_sdram_priv *priv = dev_get_priv(dev); + + info->base = priv->info.base; + info->size = priv->info.size; + + return 0; +} + +static struct ram_ops altera_gen5_sdram_ops = { + .get_info = altera_gen5_sdram_get_info, +}; + +static const struct udevice_id altera_gen5_sdram_ids[] = { + { .compatible = "altr,sdr-ctl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(altera_gen5_sdram) = { + .name = "altr_sdr_ctl", + .id = UCLASS_RAM, + .of_match = altera_gen5_sdram_ids, + .ops = &altera_gen5_sdram_ops, + .ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct altera_gen5_sdram_platdata), + .probe = altera_gen5_sdram_probe, + .priv_auto_alloc_size = sizeof(struct altera_gen5_sdram_priv), +}; + +#endif /* CONFIG_SPL_BUILD */ diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 5e7a943b68..0e4526288e 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3705,12 +3705,19 @@ static void initialize_tracking(void) &sdr_reg_file->trk_rfsh); }
-int sdram_calibration_full(void) +int sdram_calibration_full(struct socfpga_sdr *sdr) { struct param_type my_param; struct gbl_type my_gbl; u32 pass;
+ /* + * For size reasons, this file uses hard coded addresses. + * Check if we are called with the correct address. + */ + if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS) + return -ENODEV; + memset(&my_param, 0, sizeof(my_param)); memset(&my_gbl, 0, sizeof(my_gbl));
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index a5760b03a5..d7f6935201 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -223,4 +223,39 @@ struct socfpga_data_mgr { u32 mem_t_add; u32 t_rl_add; }; + +/* This struct describes the controller @ SOCFPGA_SDR_ADDRESS */ +struct socfpga_sdr { + /* SDR_PHYGRP_SCCGRP_ADDRESS */ + u8 _align1[0xe00]; + /* SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00 */ + struct socfpga_sdr_scc_mgr sdr_scc_mgr; + u8 _align2[0x1bc]; + /* SDR_PHYGRP_PHYMGRGRP_ADDRESS */ + struct socfpga_phy_mgr_cmd phy_mgr_cmd; + u8 _align3[0x2c]; + /* SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40 */ + struct socfpga_phy_mgr_cfg phy_mgr_cfg; + u8 _align4[0xfa0]; + /* SDR_PHYGRP_RWMGRGRP_ADDRESS */ + u8 rwmgr_grp[0x800]; + /* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800 */ + struct socfpga_sdr_rw_load_manager sdr_rw_load_mgr_regs; + u8 _align5[0x3f0]; + /* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00 */ + struct socfpga_sdr_rw_load_jump_manager sdr_rw_load_jump_mgr_regs; + u8 _align6[0x13f0]; + /* SDR_PHYGRP_DATAMGRGRP_ADDRESS */ + struct socfpga_data_mgr data_mgr; + u8 _align7[0x7f0]; + /* SDR_PHYGRP_REGFILEGRP_ADDRESS */ + struct socfpga_sdr_reg_file sdr_reg_file; + u8 _align8[0x7c8]; + /* SDR_CTRLGRP_ADDRESS */ + struct socfpga_sdr_ctrl sdr_ctrl; + u8 _align9[0xea4]; +}; + +int sdram_calibration_full(struct socfpga_sdr *sdr); + #endif /* _SEQUENCER_H_ */
This adds reset handling to the devicetree-enabled Denali NAND driver.
For backwards compatibility, only a warning is printed when failing to get reset handles.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: None Changes in v3: - add DM_FLAG_OS_PREPARE flag
Changes in v2: - fix copy/paste issues - add .remove callback to release the resets
drivers/mtd/nand/raw/denali.h | 2 ++ drivers/mtd/nand/raw/denali_dt.c | 15 +++++++++++++++ 2 files changed, 17 insertions(+)
diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index 019deda094..63ae828768 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -10,6 +10,7 @@ #include <linux/bitops.h> #include <linux/mtd/rawnand.h> #include <linux/types.h> +#include <reset.h>
#define DEVICE_RESET 0x0 #define DEVICE_RESET__BANK(bank) BIT(bank) @@ -315,6 +316,7 @@ struct denali_nand_info { void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data); void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr, int page, int write); + struct reset_ctl_bulk resets; };
#define DENALI_CAP_HW_ECC_FIXUP BIT(0) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index d384b974df..0ce81324b9 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -131,15 +131,30 @@ static int denali_dt_probe(struct udevice *dev) denali->clk_x_rate = 200000000; }
+ ret = reset_get_bulk(dev, &denali->resets); + if (ret) + dev_warn(dev, "Can't get reset: %d\n", ret); + else + reset_deassert_bulk(&denali->resets); + return denali_init(denali); }
+static int denali_dt_remove(struct udevice *dev) +{ + struct denali_nand_info *denali = dev_get_priv(dev); + + return reset_release_bulk(&denali->resets); +} + U_BOOT_DRIVER(denali_nand_dt) = { .name = "denali-nand-dt", .id = UCLASS_MISC, .of_match = denali_nand_dt_ids, .probe = denali_dt_probe, .priv_auto_alloc_size = sizeof(struct denali_nand_info), + .remove = denali_dt_remove, + .flags = DM_FLAG_OS_PREPARE, };
void board_nand_init(void)
This adds reset handling to the cadence qspi driver.
For backwards compatibility, only a warning is printed when failing to get reset handles.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: None Changes in v3: - add DM_FLAG_OS_PREPARE flag
Changes in v2: - add .remove callback to release the resets
drivers/spi/cadence_qspi.c | 17 +++++++++++++++++ drivers/spi/cadence_qspi.h | 4 ++++ 2 files changed, 21 insertions(+)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 11fce9c4fe..c0735d6ef4 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -8,6 +8,7 @@ #include <dm.h> #include <fdtdec.h> #include <malloc.h> +#include <reset.h> #include <spi.h> #include <linux/errno.h> #include "cadence_qspi.h" @@ -154,10 +155,17 @@ static int cadence_spi_probe(struct udevice *bus) { struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); + int ret;
priv->regbase = plat->regbase; priv->ahbbase = plat->ahbbase;
+ ret = reset_get_bulk(bus, &priv->resets); + if (ret) + dev_warn(bus, "Can't get reset: %d\n", ret); + else + reset_deassert_bulk(&priv->resets); + if (!priv->qspi_is_init) { cadence_qspi_apb_controller_init(plat); priv->qspi_is_init = 1; @@ -166,6 +174,13 @@ static int cadence_spi_probe(struct udevice *bus) return 0; }
+static int cadence_spi_remove(struct udevice *dev) +{ + struct cadence_spi_priv *priv = dev_get_priv(dev); + + return reset_release_bulk(&priv->resets); +} + static int cadence_spi_set_mode(struct udevice *bus, uint mode) { struct cadence_spi_priv *priv = dev_get_priv(bus); @@ -342,4 +357,6 @@ U_BOOT_DRIVER(cadence_spi) = { .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata), .priv_auto_alloc_size = sizeof(struct cadence_spi_priv), .probe = cadence_spi_probe, + .remove = cadence_spi_remove, + .flags = DM_FLAG_OS_PREPARE, }; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 055900def0..d4ede6e15e 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -7,6 +7,8 @@ #ifndef __CADENCE_QSPI_H__ #define __CADENCE_QSPI_H__
+#include <reset.h> + #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
#define CQSPI_NO_DECODER_MAX_CS 4 @@ -42,6 +44,8 @@ struct cadence_spi_priv { unsigned int qspi_calibrated_hz; unsigned int qspi_calibrated_cs; unsigned int previous_hz; + + struct reset_ctl_bulk resets; };
/* Functions call declaration */
This commit removes ad-hoc reset handling for peripheral resets from SPL for socfpga gen5.
This is done because as U-Boot drivers support reset handling by now.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
Changes in v4: None Changes in v3: - keep the call to enable fpga bridges in SPL
Changes in v2: - removed Kconfig option OLD_SOCFPGA_KERNEL_COMPAT since compatibility now uses an environment variable
arch/arm/mach-socfpga/misc_gen5.c | 10 ---------- arch/arm/mach-socfpga/spl_gen5.c | 9 +-------- 2 files changed, 1 insertion(+), 18 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 6e11ba6cb2..9865f5b5b1 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -201,16 +201,6 @@ int arch_early_init_r(void) /* Add device descriptor to FPGA device table */ socfpga_fpga_add(&altera_fpga[0]);
-#ifdef CONFIG_DESIGNWARE_SPI - /* Get Designware SPI controller out of reset */ - socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); - socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); -#endif - -#ifdef CONFIG_NAND_DENALI - socfpga_per_reset(SOCFPGA_RESET(NAND), 0); -#endif - return 0; }
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index c5399bb697..9dd0afb4bc 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -39,16 +39,12 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ case 0x3: /* NAND Flash (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(NAND), 0); return BOOT_DEVICE_NAND; case 0x4: /* SD/MMC External Transceiver (1.8V) */ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); - socfpga_per_reset(SOCFPGA_RESET(DMA), 0); return BOOT_DEVICE_MMC1; case 0x6: /* QSPI Flash (1.8V) */ case 0x7: /* QSPI Flash (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); return BOOT_DEVICE_SPI; default: printf("Invalid boot device (bsel=%08x)!\n", bsel); @@ -157,9 +153,7 @@ void board_init_f(ulong dummy) socfpga_bridges_reset(1); }
- socfpga_per_reset(SOCFPGA_RESET(UART0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); - timer_init();
debug("Reconfigure Clock Manager\n"); @@ -181,8 +175,7 @@ void board_init_f(ulong dummy) sysmgr_pinmux_init(); sysmgr_config_warmrstcfgio(0);
- /* De-assert reset for peripherals and bridges based on handoff */ - reset_deassert_peripherals_handoff(); + /* De-assert reset for bridges based on handoff */ socfpga_bridges_reset(0);
debug("Unfreezing/Thaw all I/O banks\n");
On 3/1/19 8:12 PM, Simon Goldschmidt wrote:
This series implements peripheral reset handling for socfpga gen5.
It moves from enabling all peripherals during SPL startup to using the socfpga reset driver from all peripherals and enabling peripherals when they are used.
As Linux cannot even handle this in 4.20, the reset driver implements a compatibility mode where it takes all peripherals out of reset before jumping to the OS if an environment variable "socfpga_legacy_reset_compat=1" is found. This is enabled by default for socfpga gen5 boards, but should be moved to default off in the near future once a Linux kernel supports reset handling for all drivers.
Changes in v4:
- added patch that renames 'membase' to 'modrst_base'
Changes in v3:
- centralize u-boot,dem-pre-reloc for soc, rst and sdr into one common file
- rename env var to socfpga_legacy_reset_compat
- add env var to CONFIG_EXTRA_ENV_SETTINGS without further ifdefs
- changed the order of patches to keep things bisectable
- fix falcon mode in SPL should work, too
- change env var name "socfpga_permodrst_ungate" to "socfpga_legacy_reset_compat"
- in compat mode, don't reset peripherals once they are enabled
- add DM_FLAG_OS_PREPARE flag
- add DM_FLAG_OS_PREPARE flag
- keep the call to enable fpga bridges in SPL
Changes in v2:
- cleanly merged Linux dts (moved change of SDR controller base address to a separate patch)
- this patch is new in v2
- moved from Kernel option "OLD_SOCFPGA_KERNEL_COMPAT" to environment variable "socfpga_permodrst_ungate"
- port DDR driver to DM UCLASS_RAM
- don't change DDR calibration training driver (code got too big)
- use reset.h code instead of socfpga_per_reset()
- fix copy/paste issues
- add .remove callback to release the resets
- add .remove callback to release the resets
- removed Kconfig option OLD_SOCFPGA_KERNEL_COMPAT since compatibility now uses an environment variable
Simon Goldschmidt (9): arm: socfpga: gen5: sync devicetrees to Linux arm: socfpga: gen5: add reset & sdr node to SPL devicetrees reset: socfpga: rename membase ptr to modrst_base arm: socfpga: gen5: deassert peripheral reset by default reset: socfpga: add reset handling for old kernels arm: socfpga: move gen5 SDR driver to DM mtd: rawnand: denali: add reset handling spi: cadence_qspi: add reset handling arm: socfpga: implement proper peripheral reset
arch/arm/Kconfig | 2 + arch/arm/dts/socfpga-common-u-boot.dtsi | 19 +++ arch/arm/dts/socfpga.dtsi | 23 ++- arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 6 +- arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 5 +- .../socfpga_cyclone5_de0_nano_soc-u-boot.dtsi | 6 +- arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 5 +- arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 5 +- arch/arm/dts/socfpga_cyclone5_is1.dts | 5 +- .../dts/socfpga_cyclone5_socdk-u-boot.dtsi | 6 +- .../dts/socfpga_cyclone5_sockit-u-boot.dtsi | 6 +- .../dts/socfpga_cyclone5_socrates-u-boot.dtsi | 6 +- arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 - arch/arm/dts/socfpga_cyclone5_sr1500.dts | 5 +- .../socfpga_cyclone5_vining_fpga-u-boot.dtsi | 6 +- .../mach-socfpga/include/mach/sdram_gen5.h | 4 - arch/arm/mach-socfpga/misc_gen5.c | 10 -- arch/arm/mach-socfpga/spl_gen5.c | 38 ++--- drivers/ddr/altera/Kconfig | 1 + drivers/ddr/altera/sdram_gen5.c | 143 ++++++++++++++++-- drivers/ddr/altera/sequencer.c | 9 +- drivers/ddr/altera/sequencer.h | 35 +++++ drivers/mtd/nand/raw/denali.h | 2 + drivers/mtd/nand/raw/denali_dt.c | 15 ++ drivers/reset/reset-socfpga.c | 55 ++++++- drivers/spi/cadence_qspi.c | 17 +++ drivers/spi/cadence_qspi.h | 4 + include/configs/socfpga_common.h | 1 + 28 files changed, 328 insertions(+), 113 deletions(-) create mode 100644 arch/arm/dts/socfpga-common-u-boot.dtsi
Applied all to socfpga/next, thanks !
participants (2)
-
Marek Vasut -
Simon Goldschmidt