[U-Boot] [PATCH 0/2] Add workaround for Cortex-A9 errata
From: Nitin Garg nitin.garg@freescale.com
These patches implement workaround for 2 Cortex-A9 erratas.
Nitin Garg (2): ARM: Add workaround for Cortex-A9 errata 794072 ARM: Add workaround for Cortex-A9 errata 761320
README | 2 ++ arch/arm/cpu/armv7/start.S | 10 ++++++++++ 2 files changed, 12 insertions(+), 0 deletions(-)
From: Nitin Garg nitin.garg@freescale.com
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions.
Signed-off-by: Nitin Garg nitin.garg@freescale.com --- README | 1 + arch/arm/cpu/armv7/start.S | 5 +++++ 2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/README b/README index 7cb7c4f..a496c65 100644 --- a/README +++ b/README @@ -566,6 +566,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 + CONFIG_ARM_ERRATA_794072
If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index ac1e55a..b87a378 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 11 @ set bit #11 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_794072 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 4 @ set bit #4 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif
mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15)
On 02.04.2014 05:33, nitin.garg@freescale.com wrote:
From: Nitin Garg nitin.garg@freescale.com
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions.
Signed-off-by: Nitin Garg nitin.garg@freescale.com
README | 1 + arch/arm/cpu/armv7/start.S | 5 +++++ 2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/README b/README index 7cb7c4f..a496c65 100644 --- a/README +++ b/README @@ -566,6 +566,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472
CONFIG_ARM_ERRATA_794072If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index ac1e55a..b87a378 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 11 @ set bit #11 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_794072
- mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
- orr r0, r0, #1 << 4 @ set bit #4
- mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
Where is the difference between the errata code for above new CONFIG_ARM_ERRATA_794072 and the existing
#ifdef CONFIG_ARM_ERRATA_742230 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif
?
Maybe we should just do a
#if (defined(CONFIG_ARM_ERRATA_794072) || defined(CONFIG_ARM_ERRATA_742230))
?
Best regards
Dirk
Good point! I will do that.
Regards, Nitin Garg
-----Original Message----- From: Dirk Behme [mailto:dirk.behme@de.bosch.com] Sent: Wednesday, April 02, 2014 1:42 AM To: Garg Nitin-B37173 Cc: trini@ti.com; Estevam Fabio-R49496; u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH 1/2] ARM: Add workaround for Cortex-A9 errata 794072
On 02.04.2014 05:33, nitin.garg@freescale.com wrote:
From: Nitin Garg nitin.garg@freescale.com
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions.
Signed-off-by: Nitin Garg nitin.garg@freescale.com
README | 1 + arch/arm/cpu/armv7/start.S | 5 +++++ 2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/README b/README index 7cb7c4f..a496c65 100644 --- a/README +++ b/README @@ -566,6 +566,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472
CONFIG_ARM_ERRATA_794072If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the diff
--git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index ac1e55a..b87a378 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 11 @ set bit #11 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_794072
- mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
- orr r0, r0, #1 << 4 @ set bit #4
- mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
Where is the difference between the errata code for above new CONFIG_ARM_ERRATA_794072 and the existing
#ifdef CONFIG_ARM_ERRATA_742230 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif
?
Maybe we should just do a
#if (defined(CONFIG_ARM_ERRATA_794072) || defined(CONFIG_ARM_ERRATA_742230))
?
Best regards
Dirk
From: Nitin Garg nitin.garg@freescale.com
Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions.
Signed-off-by: Nitin Garg nitin.garg@freescale.com --- README | 1 + arch/arm/cpu/armv7/start.S | 5 +++++ 2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/README b/README index a496c65..b7c0f68 100644 --- a/README +++ b/README @@ -567,6 +567,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 CONFIG_ARM_ERRATA_794072 + CONFIG_ARM_ERRATA_761320
If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index b87a378..1229476 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -227,6 +227,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_761320 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 21 @ set bit #21 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif
mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15)
On 02.04.2014 05:33, nitin.garg@freescale.com wrote:
From: Nitin Garg nitin.garg@freescale.com
Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions.
Signed-off-by: Nitin Garg nitin.garg@freescale.com
README | 1 + arch/arm/cpu/armv7/start.S | 5 +++++ 2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/README b/README index a496c65..b7c0f68 100644 --- a/README +++ b/README @@ -567,6 +567,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 CONFIG_ARM_ERRATA_794072
CONFIG_ARM_ERRATA_761320If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index b87a378..1229476 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -227,6 +227,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_761320
- mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
- orr r0, r0, #1 << 21 @ set bit #21
- mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
Is there any reason why you dropped the check for r4p0
cmp r6, #0x40 @ present prior to r4p0
which you still had in
http://www.spinics.net/lists/arm-kernel/msg319223.html
?
Best regards
Dirk
Hi Dirk,
There is no revision and variant in this cpu_init_cp15 function. I think this function is common unlike kernel code which was cortex specific.
Regards, Nitin Garg
-----Original Message----- From: Dirk Behme [mailto:dirk.behme@de.bosch.com] Sent: Wednesday, April 02, 2014 1:46 AM To: Garg Nitin-B37173 Cc: trini@ti.com; Estevam Fabio-R49496; u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH 2/2] ARM: Add workaround for Cortex-A9 errata 761320
On 02.04.2014 05:33, nitin.garg@freescale.com wrote:
From: Nitin Garg nitin.garg@freescale.com
Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions.
Signed-off-by: Nitin Garg nitin.garg@freescale.com
README | 1 + arch/arm/cpu/armv7/start.S | 5 +++++ 2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/README b/README index a496c65..b7c0f68 100644 --- a/README +++ b/README @@ -567,6 +567,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 CONFIG_ARM_ERRATA_794072
CONFIG_ARM_ERRATA_761320If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the diff
--git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index b87a378..1229476 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -227,6 +227,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_761320
- mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
- orr r0, r0, #1 << 21 @ set bit #21
- mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
Is there any reason why you dropped the check for r4p0
cmp r6, #0x40 @ present prior to r4p0
which you still had in
http://www.spinics.net/lists/arm-kernel/msg319223.html
?
Best regards
Dirk
Hi Nitin,
On Wed, Apr 2, 2014 at 12:33 AM, nitin.garg@freescale.com wrote:
From: Nitin Garg nitin.garg@freescale.com
These patches implement workaround for 2 Cortex-A9 erratas.
Nitin Garg (2): ARM: Add workaround for Cortex-A9 errata 794072 ARM: Add workaround for Cortex-A9 errata 761320
README | 2 ++ arch/arm/cpu/armv7/start.S | 10 ++++++++++ 2 files changed, 12 insertions(+), 0 deletions(-)
I would expect a third patch in this series that would actually define the new errata configuration (like include/configs/mx6_common.h, for example), otherwise this series just adds dead code.
Regards,
Fabio Estevam
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