--- board/xilinx/fx12mm/Makefile | 64 +++++++++++ board/xilinx/fx12mm/config.mk | 28 +++++ board/xilinx/fx12mm/fx12mm.c | 118 +++++++++++++++++++ board/xilinx/fx12mm/init.S | 48 ++++++++ board/xilinx/fx12mm/serial.c | 154 +++++++++++++++++++++++++ board/xilinx/fx12mm/u-boot.lds | 149 ++++++++++++++++++++++++ board/xilinx/fx12mm/xparameters.h | 225 +++++++++++++++++++++++++++++++++++++ include/configs/FX12MM.h | 103 +++++++++++++++++ 8 files changed, 889 insertions(+), 0 deletions(-)

diff --git a/board/xilinx/fx12mm/Makefile b/board/xilinx/fx12mm/Makefile new file mode 100644 index 0000000..61aba24 --- /dev/null +++ b/board/xilinx/fx12mm/Makefile @@ -0,0 +1,64 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +$(shell mkdir -p $(obj)../xilinx_iic) +endif + +INCS := -I../common -I../xilinx_iic +CFLAGS += $(INCS) +HOST_CFLAGS += $(INCS) + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o \ + ../common/xbasic_types.o ../common/xdma_channel.o \ + ../common/xdma_channel_sg.o \ + ../common/xversion.o \ + serial.o \ + +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xilinx/fx12mm/config.mk b/board/xilinx/fx12mm/config.mk new file mode 100644 index 0000000..69490fb --- /dev/null +++ b/board/xilinx/fx12mm/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Memec/Avnet Virtex4FX12 MiniModul +# Standard EDK 10.1 Flash Address +# +TEXT_BASE = 0xFF800000 diff --git a/board/xilinx/fx12mm/fx12mm.c b/board/xilinx/fx12mm/fx12mm.c new file mode 100644 index 0000000..0f2dd76 --- /dev/null +++ b/board/xilinx/fx12mm/fx12mm.c @@ -0,0 +1,118 @@ +/* + * fx12mm.c: U-Boot platform support for Avnet/Memec FX12 MiniModul + * + * Author: Xilinx, Inc. + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, + * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE + * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING + * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY + * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM + * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * + * Xilinx hardware products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * + * (c) Copyright 2002-2004 Xilinx Inc. + * All rights reserved. + * + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <config.h> +#include <common.h> +#include <asm/processor.h> + +#ifdef CFG_ENV_IS_IN_EEPROM +extern void convert_env(void); +#endif + +int +board_pre_init(void) +{ + return 0; +} + +int +checkboard(void) +{ + char tmp[64]; /* long enough for environment variables */ + char *s, *e; + int i = getenv_r("L", tmp, sizeof(tmp)); + + if (i < 0) { + printf("### No HW ID - assuming FX12MM"); + } else { + for (e = tmp; *e; ++e) { + if (*e == ' ') + break; + } + + printf("### Board Serial# is "); + + for (s = tmp; s < e; ++s) { + putc(*s); + } + + } + putc('\n'); + + return 0; +} + +phys_size_t +initdram(int board_type) +{ + return 64 * 1024 * 1024; +} + +int +testdram(void) +{ + printf("test: xxx MB - ok\n"); + + return 0; +} + +/* implement functions originally in cpu/ppc4xx/speed.c */ +void +get_sys_info(sys_info_t *sysInfo) +{ + sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + + /* only correct if the PLB and OPB run at the same frequency */ + + sysInfo->freqPLB = XPAR_UARTNS550_0_CLOCK_FREQ_HZ; + sysInfo->freqPCI = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 3; +} + +#ifdef CONFIG_MISC_INIT_R + +int +misc_init_r() +{ + /* convert env name and value to u-boot standard */ + convert_env(); + return 0; +} + +#endif diff --git a/board/xilinx/fx12mm/init.S b/board/xilinx/fx12mm/init.S new file mode 100644 index 0000000..f753df8 --- /dev/null +++ b/board/xilinx/fx12mm/init.S @@ -0,0 +1,48 @@ +/* + * init.S: Stubs for U-Boot initialization + * + * Author: Xilinx, Inc. + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, + * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE + * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING + * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY + * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM + * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * + * Xilinx hardware products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * + * (c) Copyright 2002-2004 Xilinx Inc. + * All rights reserved. + * + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + */ + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + blr + + .globl sdram_init +sdram_init: + blr diff --git a/board/xilinx/fx12mm/serial.c b/board/xilinx/fx12mm/serial.c new file mode 100644 index 0000000..0c3e868 --- /dev/null +++ b/board/xilinx/fx12mm/serial.c @@ -0,0 +1,154 @@ +/* + * Author: Xilinx, Inc. + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, + * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE + * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING + * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY + * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM + * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * + * Xilinx hardware products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * + * (c) Copyright 2002-2004 Xilinx Inc. + * All rights reserved. + * + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <asm/u-boot.h> +#include <asm/processor.h> +#include <common.h> +#include <command.h> +#include <config.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define USE_CHAN1 \ + ((defined XPAR_UARTNS550_0_BASEADDR) && (defined CFG_INIT_CHAN1)) +#define USE_CHAN2 \ + ((defined XPAR_UARTNS550_1_BASEADDR) && (defined CFG_INIT_CHAN2)) + +#if USE_CHAN1 +#include <ns16550.h> +#endif + +#if USE_CHAN1 +const NS16550_t COM_PORTS[] = { (NS16550_t) (XPAR_UARTNS550_0_BASEADDR + 3) +#if USE_CHAN2 + , (NS16550_t) (XPAR_UARTNS550_1_BASEADDR + 3) +#endif +}; +#endif + +int +serial_init(void) +{ +#if USE_CHAN1 + int clock_divisor; + + clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate; + (void) NS16550_init(COM_PORTS[0], clock_divisor); +#if USE_CHAN2 + clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate; + (void) NS16550_init(COM_PORTS[1], clock_divisor); +#endif +#endif + return 0; + +} + +void +serial_putc(const char c) +{ + if (c == '\n') + NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r'); + + NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c); +} + +int +serial_getc(void) +{ + return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]); +} + +int +serial_tstc(void) +{ + return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]); +} + +void +serial_setbrg(void) +{ +#if USE_CHAN1 + int clock_divisor; + + clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate; + NS16550_reinit(COM_PORTS[0], clock_divisor); +#if USE_CHAN2 + clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate; + NS16550_reinit(COM_PORTS[1], clock_divisor); +#endif +#endif +} + +void +serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); + +} + +#if defined(CONFIG_CMD_KGDB) +void +kgdb_serial_init(void) +{ +} + +void +putDebugChar(int c) +{ + serial_putc(c); +} + +void +putDebugStr(const char *str) +{ + serial_puts(str); +} + +int +getDebugChar(void) +{ + return serial_getc(); +} + +void +kgdb_interruptible(int yes) +{ + return; +} +#endif diff --git a/board/xilinx/fx12mm/u-boot.lds b/board/xilinx/fx12mm/u-boot.lds new file mode 100644 index 0000000..31af107 --- /dev/null +++ b/board/xilinx/fx12mm/u-boot.lds @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +ENTRY(_start) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ +/* + cpu/ppc4xx/start.o (.text) + board/xilinx/fx12mm/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) +*/ +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xilinx/fx12mm/xparameters.h b/board/xilinx/fx12mm/xparameters.h new file mode 100644 index 0000000..c197186 --- /dev/null +++ b/board/xilinx/fx12mm/xparameters.h @@ -0,0 +1,225 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by libgen. +* Version: Xilinx EDK 10.1.02 EDK_K_SP2.5 +* DO NOT EDIT. +* +* Copyright (c) 2005 Xilinx, Inc. All rights reserved. +* +* Description: Driver parameters +* +*******************************************************************/ + + +/* Definitions for peripheral XPS_BRAM_IF_CNTLR_1 */ +#define XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR 0xFFFFE000 +#define XPAR_XPS_BRAM_IF_CNTLR_1_HIGHADDR 0xFFFFFFFF + + +/******************************************************************/ + +/* Definitions for driver UARTNS550 */ +#define XPAR_XUARTNS550_NUM_INSTANCES 1 +#define XPAR_XUARTNS550_CLOCK_HZ 100000000 + +/* Definitions for peripheral RS232 */ +#define XPAR_RS232_DEVICE_ID 0 +#define XPAR_RS232_BASEADDR 0x83E00000 +#define XPAR_RS232_HIGHADDR 0x83E0FFFF + + +/******************************************************************/ + + +/* Canonical definitions for peripheral RS232 */ +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 +#define XPAR_UARTNS550_0_DEVICE_ID XPAR_RS232_DEVICE_ID +#define XPAR_UARTNS550_0_BASEADDR 0x83E00000 +#define XPAR_UARTNS550_0_HIGHADDR 0x83E0FFFF +#define XPAR_UARTNS550_0_SIO_CHAN 1 + + +/******************************************************************/ + +/* Definitions for driver EMACLITE */ +#define XPAR_XEMACLITE_NUM_INSTANCES 1 + +/* Definitions for peripheral ETHERNET_MAC */ +#define XPAR_ETHERNET_MAC_DEVICE_ID 0 +#define XPAR_ETHERNET_MAC_BASEADDR 0x81000000 +#define XPAR_ETHERNET_MAC_HIGHADDR 0x8100FFFF +#define XPAR_ETHERNET_MAC_TX_PING_PONG 0 +#define XPAR_ETHERNET_MAC_RX_PING_PONG 0 + + +/******************************************************************/ + + +/* Canonical definitions for peripheral ETHERNET_MAC */ +#define XPAR_EMACLITE_0_DEVICE_ID XPAR_ETHERNET_MAC_DEVICE_ID +#define XPAR_EMACLITE_0_BASEADDR 0x81000000 +#define XPAR_EMACLITE_0_HIGHADDR 0x8100FFFF +#define XPAR_EMACLITE_0_TX_PING_PONG 0 +#define XPAR_EMACLITE_0_RX_PING_PONG 0 + + +/******************************************************************/ + + +/* Definitions for peripheral FLASH_2MX16 */ +#define XPAR_FLASH_2MX16_NUM_BANKS_MEM 1 + + +/******************************************************************/ + +/* Definitions for peripheral FLASH_2MX16 */ +#define XPAR_FLASH_2MX16_MEM0_BASEADDR 0xFF800000 +#define XPAR_FLASH_2MX16_MEM0_HIGHADDR 0xFFBFFFFF + +/******************************************************************/ + +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2 +#define XPAR_XINTC_HAS_IPR 1 +#define XPAR_XINTC_USE_DCR 0 +/* Definitions for driver INTC */ +#define XPAR_XINTC_NUM_INSTANCES 1 + +/* Definitions for peripheral XPS_INTC_0 */ +#define XPAR_XPS_INTC_0_DEVICE_ID 0 +#define XPAR_XPS_INTC_0_BASEADDR 0x81800000 +#define XPAR_XPS_INTC_0_HIGHADDR 0x8180FFFF +#define XPAR_XPS_INTC_0_KIND_OF_INTR 0x00000001 + + +/******************************************************************/ + +#define XPAR_INTC_SINGLE_BASEADDR 0x81800000 +#define XPAR_INTC_SINGLE_HIGHADDR 0x8180FFFF +#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_XPS_INTC_0_DEVICE_ID +#define XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK 0X000001 +#define XPAR_XPS_INTC_0_ETHERNET_MAC_IP2INTC_IRPT_INTR 0 +#define XPAR_RS232_IP2INTC_IRPT_MASK 0X000002 +#define XPAR_XPS_INTC_0_RS232_IP2INTC_IRPT_INTR 1 + +/******************************************************************/ + + +/* Canonical definitions for peripheral XPS_INTC_0 */ +#define XPAR_INTC_0_DEVICE_ID XPAR_XPS_INTC_0_DEVICE_ID +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_INTC_0_HIGHADDR 0x8180FFFF +#define XPAR_INTC_0_KIND_OF_INTR 0x00000001 + +#define XPAR_INTC_0_EMACLITE_0_VEC_ID XPAR_XPS_INTC_0_ETHERNET_MAC_IP2INTC_IRPT_INTR +#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_XPS_INTC_0_RS232_IP2INTC_IRPT_INTR + +/******************************************************************/ + +/* Definitions for driver MPMC */ +#define XPAR_XMPMC_NUM_INSTANCES 1 + +/* Definitions for peripheral DDR_SDRAM_32MX16 */ +#define XPAR_DDR_SDRAM_32MX16_DEVICE_ID 0 +#define XPAR_DDR_SDRAM_32MX16_MPMC_BASEADDR 0x00000000 +#define XPAR_DDR_SDRAM_32MX16_MPMC_CTRL_BASEADDR 0xFFFFFFFF +#define XPAR_DDR_SDRAM_32MX16_INCLUDE_ECC_SUPPORT 0 +#define XPAR_DDR_SDRAM_32MX16_USE_STATIC_PHY 0 +#define XPAR_DDR_SDRAM_32MX16_PM_ENABLE 0 +#define XPAR_DDR_SDRAM_32MX16_NUM_PORTS 2 + + +/******************************************************************/ + + +/* Definitions for peripheral DDR_SDRAM_32MX16 */ +#define XPAR_DDR_SDRAM_32MX16_MPMC_BASEADDR 0x00000000 +#define XPAR_DDR_SDRAM_32MX16_MPMC_HIGHADDR 0x03FFFFFF + + +/******************************************************************/ + + +/* Canonical definitions for peripheral DDR_SDRAM_32MX16 */ +#define XPAR_MPMC_0_DEVICE_ID XPAR_DDR_SDRAM_32MX16_DEVICE_ID +#define XPAR_MPMC_0_MPMC_BASEADDR 0x00000000 +#define XPAR_MPMC_0_MPMC_CTRL_BASEADDR 0xFFFFFFFF +#define XPAR_MPMC_0_INCLUDE_ECC_SUPPORT 0 +#define XPAR_MPMC_0_USE_STATIC_PHY 0 +#define XPAR_MPMC_0_PM_ENABLE 0 +#define XPAR_MPMC_0_NUM_PORTS 2 + + +/******************************************************************/ + +#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 + +/******************************************************************/ + +#define XPAR_CPU_ID 0 +#define XPAR_PPC405_VIRTEX4_ID 0 +#define XPAR_PPC405_VIRTEX4_CORE_CLOCK_FREQ_HZ 300000000 +#define XPAR_PPC405_VIRTEX4_DPLB0_DWIDTH 64 +#define XPAR_PPC405_VIRTEX4_DPLB0_NATIVE_DWIDTH 64 +#define XPAR_PPC405_VIRTEX4_IPLB0_DWIDTH 64 +#define XPAR_PPC405_VIRTEX4_IPLB0_NATIVE_DWIDTH 64 +#define XPAR_PPC405_VIRTEX4_DPLB1_DWIDTH 64 +#define XPAR_PPC405_VIRTEX4_DPLB1_NATIVE_DWIDTH 64 +#define XPAR_PPC405_VIRTEX4_IPLB1_DWIDTH 64 +#define XPAR_PPC405_VIRTEX4_IPLB1_NATIVE_DWIDTH 64 +#define XPAR_PPC405_VIRTEX4_DPLB1_ADDR_BASE 0x00000000 +#define XPAR_PPC405_VIRTEX4_DPLB1_ADDR_HIGH 0x03ffffff +#define XPAR_PPC405_VIRTEX4_IPLB1_ADDR_BASE 0x00000000 +#define XPAR_PPC405_VIRTEX4_IPLB1_ADDR_HIGH 0x03ffffff +#define XPAR_PPC405_VIRTEX4_FASTEST_PLB_CLOCK DPLB0 +#define XPAR_PPC405_VIRTEX4_GENERATE_PLB_TIMESPECS 1 +#define XPAR_PPC405_VIRTEX4_DPLB0_P2P 0 +#define XPAR_PPC405_VIRTEX4_DPLB1_P2P 1 +#define XPAR_PPC405_VIRTEX4_IPLB0_P2P 0 +#define XPAR_PPC405_VIRTEX4_IPLB1_P2P 1 +#define XPAR_PPC405_VIRTEX4_IDCR_BASEADDR 0x00000100 +#define XPAR_PPC405_VIRTEX4_IDCR_HIGHADDR 0x000001FF +#define XPAR_PPC405_VIRTEX4_DISABLE_OPERAND_FORWARDING 1 +#define XPAR_PPC405_VIRTEX4_MMU_ENABLE 1 +#define XPAR_PPC405_VIRTEX4_DETERMINISTIC_MULT 0 +#define XPAR_PPC405_VIRTEX4_PLBSYNCBYPASS 1 +#define XPAR_PPC405_VIRTEX4_APU_CONTROL 0b1101111000000000 +#define XPAR_PPC405_VIRTEX4_APU_UDI_1 0b101000011000100110000011 +#define XPAR_PPC405_VIRTEX4_APU_UDI_2 0b101000111000100110000011 +#define XPAR_PPC405_VIRTEX4_APU_UDI_3 0b101001011000100111000011 +#define XPAR_PPC405_VIRTEX4_APU_UDI_4 0b101001111000100111000011 +#define XPAR_PPC405_VIRTEX4_APU_UDI_5 0b101010011000110000000011 +#define XPAR_PPC405_VIRTEX4_APU_UDI_6 0b101010111000110000000011 +#define XPAR_PPC405_VIRTEX4_APU_UDI_7 0b101011011000110001000011 +#define XPAR_PPC405_VIRTEX4_APU_UDI_8 0b101011111000110001000011 +#define XPAR_PPC405_VIRTEX4_PVR_HIGH 0b0000 +#define XPAR_PPC405_VIRTEX4_PVR_LOW 0b0000 +#define XPAR_PPC405_VIRTEX4_HW_VER "2.01.a" + +/******************************************************************/ + + +/******************************************************************/ + +/* Cannonical Constant Names */ + +/******************************************************************/ + +#undef XPAR_UARTNS550_0_BASEADDR +#define XPAR_UARTNS550_0_BASEADDR (XPAR_RS232_BASEADDR+0x1000) + +/******************************************************************/ + + +/******************************************************************/ + +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ +#define XPAR_DDR_0_SIZE 0x04000000 + +/******************************************************************/ + +#define XPAR_PCI_0_CLOCK_FREQ_HZ 0 + +/******************************************************************/ + diff --git a/include/configs/FX12MM.h b/include/configs/FX12MM.h new file mode 100644 index 0000000..b47e403 --- /dev/null +++ b/include/configs/FX12MM.h @@ -0,0 +1,103 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + + +#include "../board/xilinx/fx12mm/xparameters.h" + +#define CONFIG_4xx 1 /* PPC4xx family */ +#define CONFIG_405 1 +#define CONFIG_XILINX_405 1 /* Xilinx On Chip */ + +#define CONFIG_SYS_CLK_FREQ 100000000 + +#ifdef XPAR_SYSACE_0_DEVICE_ID +#define CONFIG_SYSTEMACE 1 +#define CONFIG_DOS_PARTITION 1 +#define CFG_SYSTEMACE_BASE XPAR_SYSACE_0_BASEADDR +#define CFG_SYSTEMACE_WIDTH XPAR_SYSACE_0_MEM_WIDTH +#define ADD_SYSTEMACE_CMDS (| CFG_CMD_FAT) +#define RM_SYSTEMACE_CMDS +#else +#define ADD_SYSTEMACE_CMDS +#define RM_SYSTEMACE_CMDS | CFG_CMD_FAT +#endif + + +#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ +#define ADD_FLASH_CMDS | CFG_CMD_FLASH +#define RM_FLASH_CMDS + + +#ifdef XPAR_IIC_0_DEVICE_ID +#if ! defined(CFG_ENV_IS_IN_FLASH) +#define CFG_ENV_IS_IN_EEPROM 1 /* environment is in IIC EEPROM */ +#endif +#define ADD_IIC_CMDS | CFG_CMD_I2C +#define RM_IIC_CMDS +#else +#define ADD_IIC_CMDS +#define RM_IIC_CMDS | CFG_CMD_I2C +#endif + + +#define CFG_FLASH_BASE 0xff800000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 150000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CFG_ENV_OFFSET 0x003fe000 +#define CFG_ENV_SIZE 0x00002000 +#define CONFIG_ENV_OVERWRITE 1 /* writable ethaddr and serial# */ +#define CFG_MONITOR_BASE 0xff800000 + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#include <config_cmd_default.h> +#undef CONFIG_CMD_NET +#define CONFIG_CMD_JFFS2 + + +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0800000 /* 4 ... 12 MB in DRAM */ + +#define CFG_DUART_CHAN 0 +#define CFG_NS16550_REG_SIZE -4 +#define CFG_NS16550 1 +#define CFG_INIT_CHAN1 1 + +#define CFG_LOAD_ADDR 0x01000000 /* default load address */ + +#define CFG_HZ 2000 /* decrementer freq: 1 ms ticks */ + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 128 kB for malloc() */ + +#define CFG_CACHELINE_SIZE 32 /* ... */ +#define CFG_CACHELINE_SHIFT 2 + +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ +