[U-Boot] [PATCH 1/6] ppc4xx: Handle other board variant in PMC440 FPGA code
From: Matthias Fuchs matthias.fuchs@esd-electronics.com
Signed-off-by: Matthias Fuchs matthias.fuchs@esd-electronics.com --- board/esd/pmc440/fpga.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index a35f42b..a2eda32 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -220,8 +220,9 @@ int fpga_post_config_fn(int cookie)
FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
- /* NGCC only: enable ledlink */ - if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) + /* NGCC/CANDES only: enable ledlink */ + if ((s = getenv("bd_type")) && + ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
return rc;
From: Matthias Fuchs matthias.fuchs@esd-electronics.com
-Codingstyle cleanup -Remove unused GPIO define
Signed-off-by: Matthias Fuchs matthias.fuchs@esd-electronics.com --- board/esd/pmc440/pmc440.h | 17 +++++++---------- 1 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h index 7e70fd1..207780f 100644 --- a/board/esd/pmc440/pmc440.h +++ b/board/esd/pmc440/pmc440.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. * * See file CREDITS for list of people who contributed to this @@ -24,8 +24,7 @@ #ifndef __PMC440_H__ #define __PMC440_H__
- -/*----------------------------------------------------------------------- +/* * GPIOs */ #define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */ @@ -41,9 +40,10 @@ #define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */ #define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */ #define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */ -#define GPIO0_SELF_RST (0x80000000 >> 6) /* GPIO6 OD */
-/* FPGA programming pin configuration */ +/* + * FPGA programming pin configuration + */ #define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */ #define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */ #define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */ @@ -51,7 +51,7 @@ #define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */ #define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */
-/*----------------------------------------------------------------------- +/* * FPGA interface */ #define FPGA_BA CFG_FPGA_BASE0 @@ -103,7 +103,6 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; #define RESET_OUT (1 << 19) #define IRIGB_R_OUT (1 << 14)
- /* status register */ #define STATUS_VERSION_SHIFT 24 #define STATUS_VERSION_MASK 0xff000000 @@ -115,13 +114,11 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; #define STATUS_FIFO_ISF (1 << 9) #define STATUS_HOST_ISF (1 << 8)
- /* inputs */ #define RESET_IN (1 << 0) #define CLOCK_IN (1 << 1) #define IRIGB_R_IN (1 << 5)
- /* hostctrl register */ #define HOSTCTRL_PMCRSTOUT_GATE (1 << 17) #define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16) @@ -137,7 +134,7 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; #define NGCC_CTRL_BASE (CFG_FPGA_BASE0 + 0x80000) #define NGCC_CTRL_FPGARST_N (1 << 2)
-/*----------------------------------------------------------------------- +/* * FPGA to PPC interrupt */ #define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */
From: Matthias Fuchs matthias.fuchs@esd-electronics.com
This patch fixes esd's loadpci command when not all memory on adapter boards is accessable via PCI.
Signed-off-by: Matthias Fuchs matthias.fuchs@esd-electronics.com --- board/esd/common/cmd_loadpci.c | 18 ++++++++++-------- 1 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c index d88b387..5db0678 100644 --- a/board/esd/common/cmd_loadpci.c +++ b/board/esd/common/cmd_loadpci.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2008 * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -36,18 +36,21 @@ extern int do_autoscript (cmd_tbl_t *, int, int, char *[]); */ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - unsigned int *ptr = 0; + u32 *ptr = 0; int count = 0; int count2 = 0; char addr[16]; char str[] = "\|/-"; char *local_args[2]; + u32 la, ptm1la; + + ptm1la = in32r(PCIX0_PTM1LA);
while(1) { /* * Mark sync address */ - ptr = 0; + ptr = (u32 *)ptm1la; memset(ptr, 0, 0x20);
*ptr = 0xffffffff; @@ -74,7 +77,8 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) }
printf("\nGot bootcode %08x: ", *ptr); - sprintf(addr, "%08x", *ptr & ADDRMASK); + la = ptm1la + (*ptr & ADDRMASK); + sprintf(addr, "%08x", la);
switch (*ptr & ~ADDRMASK) { case 0: @@ -83,8 +87,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ printf("booting image at addr 0x%s ...\n", addr); setenv("loadaddr", addr); - - do_bootm (cmdtp, 0, 0, NULL); + do_bootm(cmdtp, 0, 0, NULL); break;
case 1: @@ -92,7 +95,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Boot image via autoscr */ printf("executing script at addr 0x%s ...\n", addr); - local_args[0] = addr; local_args[1] = NULL; do_autoscript(cmdtp, 0, 1, local_args); @@ -103,7 +105,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Call run_cmd */ printf("running command at addr 0x%s ...\n", addr); - run_command ((char*)(*ptr & ADDRMASK), 0); + run_command((char*)la, 0); break;
default:
From: Matthias Fuchs matthias.fuchs@esd-electronics.com
Signed-off-by: Matthias Fuchs matthias.fuchs@esd-electronics.com --- include/configs/PMC440.h | 62 +++++++++++++++++++++++++++++----------------- 1 files changed, 39 insertions(+), 23 deletions(-)
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 467a11c..9c75f0a 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. * Based on the sequoia configuration file. * @@ -46,6 +46,7 @@ #endif
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_F 1 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ #define CONFIG_BOARD_TYPES 1 /* support board types */ /*----------------------------------------------------------------------- @@ -79,6 +80,7 @@ #define CFG_USB_HOST 0xe0000400 #define CFG_FPGA_BASE0 0xef000000 /* 32 bit */ #define CFG_FPGA_BASE1 0xef100000 /* 16 bit */ +#define CFG_RESET_BASE 0xef200000
/*----------------------------------------------------------------------- * Initial RAM & stack pointer @@ -217,13 +219,15 @@ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */
/*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F
#define CONFIG_I2C_CMD_TREE 1 @@ -261,38 +265,50 @@ #define CONFIG_DTT_ADM1021 #define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
-#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_PREBOOT "echo Add \"run fpga\" and " \ + "\"painit\" to preboot command"
#undef CONFIG_BOOTARGS
/* Setup some board specific values for the default environment variables */ #define CONFIG_HOSTNAME pmc440 #define CFG_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk_410/ppc_4xx\0" +#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
#define CONFIG_EXTRA_ENV_SETTINGS \ CFG_BOOTFILE \ CFG_ROOTPATH \ + "fdt_file=/tftpboot/pmc440/pmc440.dtb\0" \ "netdev=eth0\0" \ "ethrotate=no\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "kernel_addr=FC000000\0" \ - "ramdisk_addr=FC180000\0" \ + "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \ + "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \ + "nand_boot=run nandargs addip addtty addmisc;bootm ${kernel_addr}\0" \ + "nand_boot_fdt=run nandargs addip addtty addmisc;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmisc;" \ + "bootm\0" \ + "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdt_file};" \ + "run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "kernel_addr=ffc00000\0" \ + "kernel_addr_r=200000\0" \ + "fpga_addr=fff00000\0" \ + "fdt_addr=fff80000\0" \ + "fdt_addr_r=800000\0" \ + "fpga=fpga loadb 0 ${fpga_addr}\0" \ "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \ - "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ - "cp.b 200000 FFFA0000 60000\0" \ + "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ + "cp.b 200000 fffa0000 60000\0" \ ""
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ @@ -367,14 +383,8 @@ CFG_POST_SPR)
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) - -/* esd expects pram at end of physical memory. - * So no logbuffer at the moment. - */ -#if 0 #define CONFIG_LOGBUFFER -#endif -#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ +#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
@@ -479,6 +489,10 @@ #define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) #endif
+/* Memory Bank 1 (RESET) initialization */ +#define CFG_EBC_PB1AP 0x7f817200 //0x03017200 +#define CFG_EBC_PB1CR (CFG_RESET_BASE | 0x1c000) + /* Memory Bank 4 (FPGA / 32Bit) initialization */ #define CFG_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */ #define CFG_EBC_PB4CR (CFG_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */ @@ -513,4 +527,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_API 1 + #endif /* __CONFIG_H */
From: Matthias Fuchs matthias.fuchs@esd-electronics.com
This patch fixes the PMC440 BSP commands painit and selfreset
Signed-off-by: Matthias Fuchs matthias.fuchs@esd-electronics.com --- board/esd/pmc440/cmd_pmc440.c | 70 +++++++++++++++++++++------------------- 1 files changed, 37 insertions(+), 33 deletions(-)
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 74cf4c3..78fbf8c 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -26,6 +26,9 @@ #include <asm/io.h> #include <asm/cache.h> #include <asm/processor.h> +#if defined(CONFIG_LOGBUFFER) +#include <logbuff.h> +#endif
#include "pmc440.h"
@@ -343,14 +346,11 @@ extern env_t *env_ptr;
int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - u32 memsize; - u32 pram, env_base; + u32 pram, nextbase, base; char *v; u32 param; ulong *lptr;
- memsize = gd->bd->bi_memsize; - v = getenv("pram"); if (v) pram = simple_strtoul(v, NULL, 10); @@ -359,21 +359,42 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; }
- param = memsize - (pram << 10); + base = gd->bd->bi_memsize; +#if defined(CONFIG_LOGBUFFER) + base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD; +#endif + /* + * gd->bd->bi_memsize == physical ram size - CFG_MEM_TOP_HIDE + */ + param = base - (pram << 10); printf("PARAM: @%08x\n", param); + debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base);
+ /* clear entire PA ram */ memset((void*)param, 0, (pram << 10)); - env_base = memsize - 4096 - ((CONFIG_ENV_SIZE + 4096) & ~(4096-1)); - memcpy((void*)env_base, env_ptr, CONFIG_ENV_SIZE);
- lptr = (ulong*)memsize; - *(--lptr) = CONFIG_ENV_SIZE; - *(--lptr) = memsize - env_base; - *(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08); - *(--lptr) = 0; + /* reserve 4k for pointer field */ + nextbase = base - 4096; + lptr = (ulong*)(base); + + /* + * *(--lptr) = item_size; + * *(--lptr) = base - item_base = distance from field top; + */ + + /* env is first (4k aligned) */ + nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1)); + memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE); + *(--lptr) = CONFIG_ENV_SIZE; /* size */ + *(--lptr) = base - nextbase; /* offset | type=0 */ + + /* free section */ + *(--lptr) = nextbase - param; /* size */ + *(--lptr) = (base - param) | 126; /* offset | type=126 */
- /* make sure data can be accessed through PCI */ - flush_dcache_range(param, param + (pram << 10) - 1); + /* terminate pointer field */ + *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10); + *(--lptr) = 0; /* offset=0 -> terminator */ return 0; } U_BOOT_CMD( @@ -385,28 +406,11 @@ U_BOOT_CMD(
int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - if (argc > 1) { - if (argv[1][0] == '0') { - /* assert */ - printf("self-reset# asserted\n"); - out_be32((void*)GPIO0_TCR, - in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST); - } else { - /* deassert */ - printf("self-reset# deasserted\n"); - out_be32((void*)GPIO0_TCR, - in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST); - } - } else { - printf("self-reset# is %s\n", - in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ? - "active" : "inactive"); - } - + in_be32((void*)CFG_RESET_BASE); return 0; } U_BOOT_CMD( - selfreset, 2, 1, do_selfreset, + selfreset, 1, 1, do_selfreset, "selfreset- assert self-reset# signal\n", NULL );
From: Matthias Fuchs matthias.fuchs@esd-electronics.com
This patch brings PMC440 board support up to date:
- fix GPIO configuration - add misc_init_f() - use better values for usbact variable - fix USB 2.0 phy reset sequence - shrink BAR2 to save PCI address space - add FDT support
Signed-off-by: Matthias Fuchs matthias.fuchs@esd-electronics.com --- board/esd/pmc440/pmc440.c | 129 +++++++++++++++++++++++++++++++++++++-------- 1 files changed, 106 insertions(+), 23 deletions(-)
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 85ef26f..ca1aab0 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -45,9 +45,11 @@ DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern void __ft_board_setup(void *blob, bd_t *bd);
ulong flash_get_size(ulong base, int banknum); int pci_is_66mhz(void); +int is_monarch(void); int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
@@ -107,9 +109,9 @@ int board_early_init_f(void) */ out32(GPIO0_OR, 0x40000002); out32(GPIO0_TCR, 0x4c90011f); - out32(GPIO0_OSRL, 0x28011400); + out32(GPIO0_OSRL, 0x28051400); out32(GPIO0_OSRH, 0x55005000); - out32(GPIO0_TSRL, 0x08011400); + out32(GPIO0_TSRL, 0x08051400); out32(GPIO0_TSRH, 0x55005000); out32(GPIO0_ISR1L, 0x54000000); out32(GPIO0_ISR1H, 0x00000000); @@ -196,6 +198,23 @@ int board_early_init_f(void) return 0; }
+#if defined(CONFIG_MISC_INIT_F) +int misc_init_f(void) +{ + struct pci_controller hose; + hose.first_busno = 0; + hose.last_busno = 0; + hose.region_count = 0; + + if (getenv("pciearly") && (!is_monarch())) { + printf("PCI: early target init\n"); + pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA); + pci_target_init(&hose); + } + return 0; +} +#endif + /* * misc_init_r. */ @@ -207,6 +226,7 @@ int misc_init_r(void) unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; + unsigned long sdr0_srst0, sdr0_srst1; char *act = getenv("usbact");
/* @@ -256,7 +276,7 @@ int misc_init_r(void) /* * USB suff... */ - if ((act == NULL || strcmp(act, "hostdev") == 0) && + if ((act == NULL || strcmp(act, "host") == 0) && !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){ /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); @@ -290,12 +310,46 @@ int misc_init_r(void) mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr);
- /* clear resets */ + /* + * Take USB out of reset: + * -Initial status = all cores are in reset + * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores + * -wait 1 ms + * -deassert reset to PHY + * -wait 1 ms + * -deassert reset to HOST + * -wait 4 ms + * -deassert all other resets + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \ + SDR0_SRST1_P4OPB0 | \ + SDR0_SRST1_OPBA2 | \ + SDR0_SRST1_PLB42OPB1 | \ + SDR0_SRST1_OPB2PLB40); + mtsdr(SDR0_SRST1, sdr0_srst1); udelay(1000); - mtsdr(SDR0_SRST1, 0x00000000); + + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_USB20PHY; + mtsdr(SDR0_SRST1, sdr0_srst1); udelay(1000); + + mfsdr(SDR0_SRST0, sdr0_srst0); + sdr0_srst0 &= ~SDR0_SRST0_USB2H; + mtsdr(SDR0_SRST0, sdr0_srst0); + udelay(4000); + + /* finally all the other resets */ + mtsdr(SDR0_SRST1, 0x00000000); mtsdr(SDR0_SRST0, 0x00000000);
+ if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { + /* enable power on USB socket */ + out_be32((void*)GPIO1_OR, + in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); + } + printf("USB: Host\n");
} else if ((strcmp(act, "dev") == 0) || @@ -547,14 +601,14 @@ void pci_target_init(struct pci_controller *hose) out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16)); out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16)); } else { - /* BAR2: default: 16 MB FPGA + registers */ - out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */ + /* BAR2: default: 4MB FPGA */ + out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */ out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */ }
if (is_monarch()) { /* BAR2: map FPGA registers behind system memory at 1GB */ - pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008); + pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008); }
/* @@ -562,8 +616,8 @@ void pci_target_init(struct pci_controller *hose) */
/* Program the board's vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); + pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID);
/* disabled for PMC405 backward compatibility */ /* Configure command register as bus master */ @@ -571,19 +625,17 @@ void pci_target_init(struct pci_controller *hose)
/* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
/* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
if (!is_monarch()) { /* Program the board's subsystem id/classcode */ - pci_write_config_word(0, PCI_SUBSYSTEM_ID, - CFG_PCI_SUBSYS_ID_NONMONARCH); - pci_write_config_word(0, PCI_CLASS_SUB_CODE, - CFG_PCI_CLASSCODE_NONMONARCH); + pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, + CFG_PCI_SUBSYS_ID_NONMONARCH); + pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE, + CFG_PCI_CLASSCODE_NONMONARCH);
/* PCI configuration done: release ERREADY */ out_be32((void*)GPIO1_OR, @@ -592,11 +644,14 @@ void pci_target_init(struct pci_controller *hose) in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY); } else { /* Program the board's subsystem id/classcode */ - pci_write_config_word(0, PCI_SUBSYSTEM_ID, - CFG_PCI_SUBSYS_ID_MONARCH); - pci_write_config_word(0, PCI_CLASS_SUB_CODE, - CFG_PCI_CLASSCODE_MONARCH); + pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, + CFG_PCI_SUBSYS_ID_MONARCH); + pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE, + CFG_PCI_CLASSCODE_MONARCH); } + + /* enable host configuration */ + pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101); } #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
@@ -626,6 +681,12 @@ static void wait_for_pci_ready(void) { int i; char *s = getenv("pcidelay"); + /* + * We have our own handling of the pcidelay variable. + * Using CONFIG_PCI_BOOTDELAY enables pausing for host + * and adapter devices. For adapter devices we do not + * want this. + */ if (s) { int ms = simple_strtoul(s, NULL, 10); printf("PCI: Waiting for %d ms\n", ms); @@ -851,7 +912,7 @@ int usb_board_init(void) char *act = getenv("usbact"); int i;
- if ((act == NULL || strcmp(act, "hostdev") == 0) && + if ((act == NULL || strcmp(act, "host") == 0) && !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) /* enable power on USB socket */ out_be32((void*)GPIO1_OR, @@ -876,3 +937,25 @@ int usb_board_init_fail(void) return 0; } #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */ + + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + int rc; + + __ft_board_setup(blob, bd); + + /* + * Disable PCI in non-monarch mode. + */ + if (!is_monarch()) { + rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status", + "disabled", sizeof("disabled"), 1); + if (rc) { + printf("Unable to update property status in PCI node, err=%s\n", + fdt_strerror(rc)); + } + } +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Matthias,
On Wednesday 08 October 2008, matthias.fuchs@esd-electronics.com wrote:
From: Matthias Fuchs matthias.fuchs@esd-electronics.com
I know you're on vacation now, but nevertheless here a short report. After applying those 6 patches I get the following errors:
Configuring for CPCI2DP board... ../common/cmd_loadpci.c: In function 'do_loadpci': ../common/cmd_loadpci.c:47: error: 'PCIX0_PTM1LA' undeclared (first use in this function) ../common/cmd_loadpci.c:47: error: (Each undeclared identifier is reported only once ../common/cmd_loadpci.c:47: error: for each function it appears in.) make[1]: *** [../common/cmd_loadpci.o] Error 1
Configuring for PMC405 board... ../common/cmd_loadpci.c: In function 'do_loadpci': ../common/cmd_loadpci.c:47: error: 'PCIX0_PTM1LA' undeclared (first use in this function) ../common/cmd_loadpci.c:47: error: (Each undeclared identifier is reported only once ../common/cmd_loadpci.c:47: error: for each function it appears in.) make[1]: *** [../common/cmd_loadpci.o] Error 1
Configuring for PMC440 board... api_storage.c: In function 'dev_stor_init': api_storage.c:94: error: 'USB_MAX_STOR_DEV' undeclared (first use in this function) api_storage.c:94: error: (Each undeclared identifier is reported only once api_storage.c:94: error: for each function it appears in.) make[1]: *** [api_storage.o] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [api/libapi.a] Error 2
Sorry, but with this status I can't add those patches to my 4xx/master branch. Please fix those problem and resubmit.
Thanks.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
Stefan,
On Friday 10 October 2008 17:30, Stefan Roese wrote:
Matthias,
On Wednesday 08 October 2008, matthias.fuchs@esd-electronics.com wrote:
From: Matthias Fuchs matthias.fuchs@esd-electronics.com
I know you're on vacation now, but nevertheless here a short report. After applying those 6 patches I get the following errors:
Configuring for CPCI2DP board... ../common/cmd_loadpci.c: In function 'do_loadpci': ../common/cmd_loadpci.c:47: error: 'PCIX0_PTM1LA' undeclared (first use in this function) ../common/cmd_loadpci.c:47: error: (Each undeclared identifier is reported only once ../common/cmd_loadpci.c:47: error: for each function it appears in.) make[1]: *** [../common/cmd_loadpci.o] Error 1
Oops.
Configuring for PMC405 board... ../common/cmd_loadpci.c: In function 'do_loadpci': ../common/cmd_loadpci.c:47: error: 'PCIX0_PTM1LA' undeclared (first use in this function) ../common/cmd_loadpci.c:47: error: (Each undeclared identifier is reported only once ../common/cmd_loadpci.c:47: error: for each function it appears in.) make[1]: *** [../common/cmd_loadpci.o] Error 1
Oops. Must be PTM1LA on 405 platforms.
Configuring for PMC440 board... api_storage.c: In function 'dev_stor_init': api_storage.c:94: error: 'USB_MAX_STOR_DEV' undeclared (first use in this function) api_storage.c:94: error: (Each undeclared identifier is reported only once api_storage.c:94: error: for each function it appears in.) make[1]: *** [api_storage.o] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [api/libapi.a] Error 2
I posted a patch to fix the CONFIG_API support. This patch has been applied by Wolfgang so it should work now.
Sorry, but with this status I can't add those patches to my 4xx/master branch. Please fix those problem and resubmit.
I will resend my patch series rebased to top of git in a couple of minutes.
Matthias
Hi Matthias,
On Tuesday 28 October 2008, Matthias Fuchs wrote:
Sorry, but with this status I can't add those patches to my 4xx/master branch. Please fix those problem and resubmit.
I will resend my patch series rebased to top of git in a couple of minutes.
Applied all 6 patches to 4xx/master. Thanks.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
participants (3)
-
Matthias Fuchs -
matthias.fuchs＠esd-electronics.com
-
Stefan Roese