It is not good practice to raise an exception in a constructor. In this case the 'text' entry may not actually be used, if -i is used to filter out the images that get built.

Move the exception to where the data is actually used.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

tools/binman/etype/text.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/binman/etype/text.py b/tools/binman/etype/text.py index 6e99819487f..c4aa510a87b 100644 --- a/tools/binman/etype/text.py +++ b/tools/binman/etype/text.py @@ -51,10 +51,10 @@ class Entry_text(Entry): self.text_label, = self.GetEntryArgsOrProps( [EntryArg('text-label', str)]) self.value, = self.GetEntryArgsOrProps([EntryArg(self.text_label, str)]) + + def ObtainContents(self): if not self.value: self.Raise("No value provided for text label '%s'" % self.text_label) - - def ObtainContents(self): self.SetContents(self.value) return True

This message is not very important since it is simply indicating that the user's instructions are being followed. Only show it when the verbosity level is above the default.

Also drop the unnecessary extra newline on this message, which causes two line breaks.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Update commit message to mention dropping the \n - Update testSelectImage() to test in normal and verbose modes

tools/binman/control.py | 4 ++-- tools/binman/ftest.py | 26 +++++++++++++++++++------- 2 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/tools/binman/control.py b/tools/binman/control.py index 3446e2e79c5..b32e4e1996f 100644 --- a/tools/binman/control.py +++ b/tools/binman/control.py @@ -133,8 +133,8 @@ def Binman(options, args): if name not in options.image: del images[name] skip.append(name) - if skip: - print 'Skipping images: %s\n' % ', '.join(skip) + if skip and options.verbosity >= 2: + print 'Skipping images: %s' % ', '.join(skip)

state.Prepare(images, dtb)

diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index e77fce5a26f..75658c9a366 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -187,7 +187,8 @@ class TestFunctional(unittest.TestCase): return control.Binman(options, args)

def _DoTestFile(self, fname, debug=False, map=False, update_dtb=False, - entry_args=None, images=None, use_real_dtb=False): + entry_args=None, images=None, use_real_dtb=False, + verbosity=None): """Run binman with a given test file

Args: @@ -210,6 +211,8 @@ class TestFunctional(unittest.TestCase): args.append('-up') if not use_real_dtb: args.append('--fake-dtb') + if verbosity is not None: + args.append('-v%d' % verbosity) if entry_args: for arg, value in entry_args.iteritems(): args.append('-a%s=%s' % (arg, value)) @@ -1459,13 +1462,22 @@ class TestFunctional(unittest.TestCase):

def testSelectImage(self): """Test that we can select which images to build""" - with test_util.capture_sys_output() as (stdout, stderr): - retcode = self._DoTestFile('006_dual_image.dts', images=['image2']) - self.assertEqual(0, retcode) - self.assertIn('Skipping images: image1', stdout.getvalue()) + expected = 'Skipping images: image1' + + # We should only get the expected message in verbose mode + for verbosity in (None, 2): + with test_util.capture_sys_output() as (stdout, stderr): + retcode = self._DoTestFile('006_dual_image.dts', + verbosity=verbosity, + images=['image2']) + self.assertEqual(0, retcode) + if verbosity: + self.assertIn(expected, stdout.getvalue()) + else: + self.assertNotIn(expected, stdout.getvalue())

- self.assertFalse(os.path.exists(tools.GetOutputFilename('image1.bin'))) - self.assertTrue(os.path.exists(tools.GetOutputFilename('image2.bin'))) + self.assertFalse(os.path.exists(tools.GetOutputFilename('image1.bin'))) + self.assertTrue(os.path.exists(tools.GetOutputFilename('image2.bin')))

def testUpdateFdtAll(self): """Test that all device trees are updated with offset/size info"""

At present only OF_SEPARATE is considered valid for building a device-tree file in SPL. However sandbox uses OF_HOSTFILE instead. Update the logic to handle this and make it easier to understand.

Note that the new logic is not quite the same as the old logic. It was previously assumed that checking for:

$(CONFIG_$(SPL_TPL_)OF_CONTROL) $(CONFIG_OF_SEPARATE) $(CONFIG_$(SPL_TPL_)OF_PLATDATA)

producing 'yy' meant that the first two were 'y' and the last was empty. Strictly speaking it would be possible for any two of the three to be 'y' and still yield the same result. However, that was not the intention of the new logic, since OF_PLATDATA always ensures that no device-tree file is included. So in effect the new logic is the same, with the addition of OF_HOSTFILE as an option for OP_SEPARATE.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Add a better explanation of the logic change, in the commit message

scripts/Makefile.spl | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 56dbbe127ba..8d76a2d4007 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -253,8 +253,20 @@ else FINAL_DTB_CONTAINER = $(obj)/$(SPL_BIN).multidtb.fit endif

+# Build the .dtb file if: +# - we are not using OF_PLATDATA +# - we are using OF_CONTROL +# - we have either OF_SEPARATE or OF_HOSTFILE +build_dtb := +ifeq ($(CONFIG_$(SPL_TPL_)OF_PLATDATA),) +ifneq ($(CONFIG_$(SPL_TPL_)OF_CONTROL),) +ifeq ($(CONFIG_OF_SEPARATE)$(CONFIG_OF_HOSTFILE),y) +build_dtb := y +endif +endif +endif

-ifeq ($(CONFIG_$(SPL_TPL_)OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy) +ifneq ($(build_dtb),) $(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \ $(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \ $(FINAL_DTB_CONTAINER) FORCE

There is a typo in this header. Fix it.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/cpu/start64.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/cpu/start64.S b/arch/x86/cpu/start64.S index a78a3316b6d..7be834788b9 100644 --- a/arch/x86/cpu/start64.S +++ b/arch/x86/cpu/start64.S @@ -2,7 +2,7 @@ /* * 64-bit x86 Startup Code * - * (C) Copyright 216 Google, Inc + * Copyright 2019 Google, Inc * Written by Simon Glass sjg@chromium.org */

At present many of the functions in this file return -1 as an error number. which is -EPERM. Update the code to use real error numbers.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/cpu/mp_init.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index ea64c2ee57e..fefbf8f7282 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -322,7 +322,7 @@ static int start_aps(int ap_count, atomic_t *num_aps) if (sipi_vector > max_vector_loc) { printf("SIPI vector too large! 0x%08x\n", sipi_vector); - return -1; + return -ENOSPC; }

debug("Attempting to start %d APs\n", ap_count); @@ -364,7 +364,7 @@ static int start_aps(int ap_count, atomic_t *num_aps) if (wait_for_aps(num_aps, ap_count, 10000, 50)) { debug("Not all APs checked in: %d/%d\n", atomic_read(num_aps), ap_count); - return -1; + return -EIO; }

return 0; @@ -387,7 +387,7 @@ static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params) if (wait_for_aps(&rec->cpus_entered, num_aps, timeout_us, step_us)) { debug("MP record %d timeout\n", i); - ret = -1; + ret = -ETIMEDOUT; } }

@@ -508,7 +508,7 @@ int mp_init(struct mp_params *p)

if (p == NULL || p->flight_plan == NULL || p->num_records < 1) { printf("Invalid MP parameters\n"); - return -1; + return -EINVAL; }

num_cpus = cpu_get_count(cpu); @@ -531,7 +531,7 @@ int mp_init(struct mp_params *p) /* Load the SIPI vector */ ret = load_sipi_vector(&ap_count, num_cpus); if (ap_count == NULL) - return -1; + return -ENOENT;

/* * Make sure SIPI data hits RAM so the APs that come up will see

We cannot init the CPU fully both than once during a boot. Add a new function which can be called to figure out the CPU identity, but which does not change anything. For x86_64, this is empty for now.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/cpu/i386/cpu.c | 113 ++++++++++++++++++------------ arch/x86/cpu/x86_64/cpu.c | 5 ++ arch/x86/include/asm/u-boot-x86.h | 20 ++++++ 3 files changed, 94 insertions(+), 44 deletions(-)

diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 3bde44ebf53..90b546e7410 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -309,21 +309,22 @@ u32 cpu_get_stepping(void) return gd->arch.x86_mask; }

-int x86_cpu_init_f(void) +/* initialise FPU, reset EM, set MP and NE */ +static void setup_cpu_features(void) { const u32 em_rst = ~X86_CR0_EM; const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;

- if (ll_boot_init()) { - /* initialize FPU, reset EM, set MP and NE */ - asm ("fninit\n" \ - "movl %%cr0, %%eax\n" \ - "andl %0, %%eax\n" \ - "orl %1, %%eax\n" \ - "movl %%eax, %%cr0\n" \ - : : "i" (em_rst), "i" (mp_ne_set) : "eax"); - } + asm ("fninit\n" \ + "movl %%cr0, %%eax\n" \ + "andl %0, %%eax\n" \ + "orl %1, %%eax\n" \ + "movl %%eax, %%cr0\n" \ + : : "i" (em_rst), "i" (mp_ne_set) : "eax"); +}

+static void setup_identity(void) +{ /* identify CPU via cpuid and store the decoded info into gd->arch */ if (has_cpuid()) { struct cpu_device_id cpu; @@ -339,46 +340,70 @@ int x86_cpu_init_f(void)

gd->arch.has_mtrr = has_mtrr(); } - /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ +} + +/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ +static void setup_pci_ram_top(void) +{ gd->pci_ram_top = 0x80000000U; +} + +static void setup_mtrr(void) +{ + u64 mtrr_cap;

/* Configure fixed range MTRRs for some legacy regions */ - if (gd->arch.has_mtrr) { - u64 mtrr_cap; - - mtrr_cap = native_read_msr(MTRR_CAP_MSR); - if (mtrr_cap & MTRR_CAP_FIX) { - /* Mark the VGA RAM area as uncacheable */ - native_write_msr(MTRR_FIX_16K_A0000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), - MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); - - /* - * Mark the PCI ROM area as cacheable to improve ROM - * execution performance. - */ - native_write_msr(MTRR_FIX_4K_C0000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); - native_write_msr(MTRR_FIX_4K_C8000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); - native_write_msr(MTRR_FIX_4K_D0000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); - native_write_msr(MTRR_FIX_4K_D8000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); - - /* Enable the fixed range MTRRs */ - msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); - } + if (!gd->arch.has_mtrr) + return; + + mtrr_cap = native_read_msr(MTRR_CAP_MSR); + if (mtrr_cap & MTRR_CAP_FIX) { + /* Mark the VGA RAM area as uncacheable */ + native_write_msr(MTRR_FIX_16K_A0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); + + /* + * Mark the PCI ROM area as cacheable to improve ROM + * execution performance. + */ + native_write_msr(MTRR_FIX_4K_C0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_C8000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_D0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_D8000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + + /* Enable the fixed range MTRRs */ + msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); } +} + +int x86_cpu_init_f(void) +{ + if (ll_boot_init()) + setup_cpu_features(); + setup_identity(); + setup_mtrr(); + setup_pci_ram_top();

-#ifdef CONFIG_I8254_TIMER /* Set up the i8254 timer if required */ - i8254_init(); -#endif + if (IS_ENABLED(CONFIG_I8254_TIMER)) + i8254_init(); + + return 0; +} + +int x86_cpu_reinit_f(void) +{ + setup_identity(); + setup_pci_ram_top();

return 0; } diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 6c063e82009..42abb23a9ed 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -61,3 +61,8 @@ int print_cpuinfo(void) { return 0; } + +int x86_cpu_reinit_f(void) +{ + return 0; +} diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 670fcdc0093..c252192bf41 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -13,7 +13,27 @@ extern char gdt_rom[];

/* cpu/.../cpu.c */ int arch_cpu_init(void); + +/** + * x86_cpu_init_f() - Set up basic features of the x86 CPU + * + * 0 on success, -ve on error + */ int x86_cpu_init_f(void); + +/** + * x86_cpu_reinit_f() - Set up the CPU a second time + * + * Once cpu_init_f() has been called (e.g. in SPL) we should not call it + * again (e.g. in U-Boot proper) since it sets up the state from scratch. + * Call this function in later phases of U-Boot instead. It reads the CPU + * identify so that CPU functions can be used correctly, but does not change + * anything. + * + * @return 0 (indicating success, to mimic cpu_init_f()) + */ +int x86_cpu_reinit_f(void); + int cpu_init_f(void); void setup_gdt(struct global_data *id, u64 *gdt_addr); /*

Add labels for these nodes so that board DT files can reference them.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/dts/reset.dtsi | 2 +- arch/x86/dts/rtc.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/dts/reset.dtsi b/arch/x86/dts/reset.dtsi index f979d83757c..555d0dd9608 100644 --- a/arch/x86/dts/reset.dtsi +++ b/arch/x86/dts/reset.dtsi @@ -1,5 +1,5 @@ / { - reset { + reset: reset { compatible = "x86,reset"; u-boot,dm-pre-reloc; }; diff --git a/arch/x86/dts/rtc.dtsi b/arch/x86/dts/rtc.dtsi index 1797e042daf..d0bbd84e509 100644 --- a/arch/x86/dts/rtc.dtsi +++ b/arch/x86/dts/rtc.dtsi @@ -1,5 +1,5 @@ / { - rtc { + rtc: rtc { compatible = "motorola,mc146818"; u-boot,dm-pre-reloc; reg = <0x70 2>;

We use binman to build the x86 image now. Update a comment which still refers to ifdtool.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: - Update the comment in fsp_cap.S too

arch/x86/cpu/intel_common/car.S | 2 +- arch/x86/lib/fsp/fsp_car.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/intel_common/car.S b/arch/x86/cpu/intel_common/car.S index 52a77bb2d18..00308dbdef9 100644 --- a/arch/x86/cpu/intel_common/car.S +++ b/arch/x86/cpu/intel_common/car.S @@ -235,7 +235,7 @@ mtrr_table_end:

.align 4 _dt_ucode_base_size: - /* These next two fields are filled in by ifdtool */ + /* These next two fields are filled in by binman */ .globl ucode_base ucode_base: /* Declared in microcode.h */ .long 0 /* microcode base */ diff --git a/arch/x86/lib/fsp/fsp_car.S b/arch/x86/lib/fsp/fsp_car.S index 48edc8362a7..8c54cea3db4 100644 --- a/arch/x86/lib/fsp/fsp_car.S +++ b/arch/x86/lib/fsp/fsp_car.S @@ -100,7 +100,7 @@ temp_ram_init_romstack: .long temp_ram_init_params temp_ram_init_params: _dt_ucode_base_size: - /* These next two fields are filled in by ifdtool */ + /* These next two fields are filled in by binman */ .globl ucode_base ucode_base: /* Declared in microcode.h */ .long 0 /* microcode base */

At present only chromebook_link64 supports SPL. It is useful to eb able to support both TPL and SPL to implement verified boot on x86.

Enable the options for both along with some suitable default options needed to boot through these phases.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/Kconfig | 31 +++++++++++++++++++++++++++++++ arch/x86/Kconfig | 1 - 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/arch/Kconfig b/arch/Kconfig index 2f3d07c13a1..a1d1ac301d6 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -126,6 +126,8 @@ config SH

config X86 bool "x86 architecture" + select SUPPORT_SPL + select SUPPORT_TPL select CREATE_ARCH_SYMLINK select DM select DM_PCI @@ -164,6 +166,35 @@ config X86 imply USB_HOST_ETHER imply PCH

+ # Thing to enable for when SPL/TPL are enabled: SPL + imply SPL_DM + imply SPL_OF_LIBFDT + imply SPL_DRIVERS_MISC_SUPPORT + imply SPL_GPIO_SUPPORT + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_SERIAL_SUPPORT + imply SPL_SPI_FLASH_SUPPORT + imply SPL_SPI_SUPPORT + imply SPL_OF_CONTROL + imply SPL_TIMER + imply SPL_REGMAP + imply SPL_SYSCON + # TPL + imply TPL_DM + imply TPL_OF_LIBFDT + imply TPL_DRIVERS_MISC_SUPPORT + imply TPL_GPIO_SUPPORT + imply TPL_LIBCOMMON_SUPPORT + imply TPL_LIBGENERIC_SUPPORT + imply TPL_SERIAL_SUPPORT + imply TPL_SPI_FLASH_SUPPORT + imply TPL_SPI_SUPPORT + imply TPL_OF_CONTROL + imply TPL_TIMER + imply TPL_REGMAP + imply TPL_SYSCON + config XTENSA bool "Xtensa architecture" select CREATE_ARCH_SYMLINK diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e0520937751..185f0ef8c40 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -32,7 +32,6 @@ config X86_RUN_32BIT config X86_RUN_64BIT bool "64-bit" select X86_64 - select SUPPORT_SPL select SPL select SPL_SEPARATE_BSS help

Some boards want to use TPL as the first phase of U-Boot. This allows selection of A or B SPL phases, thus allowing the memory init to be upgraded in the field.

Add a new Kconfig option for this.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/Kconfig | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 185f0ef8c40..45a533625a6 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -176,10 +176,17 @@ config X86_16BIT_INIT config SPL_X86_16BIT_INIT bool depends on X86_RESET_VECTOR - default y if X86_RESET_VECTOR && SPL + default y if X86_RESET_VECTOR && SPL && !TPL help This is enabled when 16-bit init is in SPL

+config TPL_X86_16BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && TPL + help + This is enabled when 16-bit init is in TPL + config X86_32BIT_INIT bool depends on X86_RESET_VECTOR

Add an arch-specific handoff header so that we can use the HANDOFF feature on x86 devices.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/include/asm/handoff.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 arch/x86/include/asm/handoff.h

diff --git a/arch/x86/include/asm/handoff.h b/arch/x86/include/asm/handoff.h new file mode 100644 index 00000000000..4d18d59efed --- /dev/null +++ b/arch/x86/include/asm/handoff.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Architecture-specific SPL handoff information for x86 + * + * Copyright 2018 Google, Inc + * Written by Simon Glass sjg@chromium.org + */ + +#ifndef __x86_asm_handoff_h +#define __x86_asm_handoff_h + +struct arch_spl_handoff { +}; + +#endif

Add debugging during SDRAM init so that problems are easier to diagnose.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/cpu/broadwell/sdram.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-)

diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c index 03a35bcf73f..1b9f9840c6f 100644 --- a/arch/x86/cpu/broadwell/sdram.c +++ b/arch/x86/cpu/broadwell/sdram.c @@ -204,16 +204,18 @@ int dram_init(void)

/* Print ME state before MRC */ ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev); - if (ret) + if (ret) { + debug("Cannot get ME (err=%d)\n", ret); return ret; + } intel_me_status(me_dev);

/* Save ME HSIO version */ - ret = uclass_first_device(UCLASS_PCH, &pch_dev); - if (ret) + ret = uclass_first_device_err(UCLASS_PCH, &pch_dev); + if (ret) { + debug("Cannot get PCH (err=%d)\n", ret); return ret; - if (!pch_dev) - return -ENODEV; + } power_state_get(pch_dev, &ps);

intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum); @@ -221,15 +223,17 @@ int dram_init(void) broadwell_fill_pei_data(pei_data); mainboard_fill_pei_data(pei_data);

- ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); - if (ret) + ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev); + if (ret) { + debug("Cannot get Northbridge (err=%d)\n", ret); return ret; - if (!dev) - return -ENODEV; + } size = 256; ret = mrc_locate_spd(dev, size, &spd_data); - if (ret) + if (ret) { + debug("Cannot locate SPD (err=%d)\n", ret); return ret; + } memcpy(pei_data->spd_data[0][0], spd_data, size); memcpy(pei_data->spd_data[1][0], spd_data, size);

@@ -239,13 +243,17 @@ int dram_init(void)

debug("PEI version %#x\n", pei_data->pei_version); ret = mrc_common_init(dev, pei_data, true); - if (ret) + if (ret) { + debug("mrc_common_init() failed(err=%d)\n", ret); return ret; + } debug("Memory init done\n");

ret = sdram_find(dev); - if (ret) + if (ret) { + debug("sdram_find() failed (err=%d)\n", ret); return ret; + } gd->ram_size = gd->arch.meminfo.total_32bit_memory; debug("RAM size %llx\n", (unsigned long long)gd->ram_size);

At present, for broadwell, SDRAM is always set up in U-Boot proper since the 64-bit mode (which uses SDRAM init in SPL) is not supported.

Update the code to allow SDRAM init in SPL instead so that U-Boot proper can be loaded into SDRAM and run from there. This allows U-Boot to be compressed to reduce space, since it is not necessary to run it directly from flash. It could later allow us to support 64-bit U-Boot on broadwell.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Update commit message to make it clear this patch is just for broadwell - Bring in sdram_console_tx_byte() to allow debugging

arch/x86/cpu/broadwell/Makefile | 2 +- arch/x86/cpu/broadwell/northbridge.c | 100 +++++++++++++++++++++++++++ arch/x86/cpu/broadwell/sdram.c | 93 ------------------------- 3 files changed, 101 insertions(+), 94 deletions(-)

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile index d3785aabdf2..d464507e6c0 100644 --- a/arch/x86/cpu/broadwell/Makefile +++ b/arch/x86/cpu/broadwell/Makefile @@ -13,4 +13,4 @@ obj-y += pinctrl_broadwell.o obj-y += power_state.o obj-y += refcode.o obj-y += sata.o -obj-y += sdram.o +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += sdram.o diff --git a/arch/x86/cpu/broadwell/northbridge.c b/arch/x86/cpu/broadwell/northbridge.c index 3055880bb77..4bcab785560 100644 --- a/arch/x86/cpu/broadwell/northbridge.c +++ b/arch/x86/cpu/broadwell/northbridge.c @@ -6,8 +6,108 @@ #include <common.h> #include <dm.h> #include <asm/io.h> +#include <asm/mrc_common.h> #include <asm/arch/iomap.h> #include <asm/arch/pch.h> +#include <asm/arch/pei_data.h> + +__weak asmlinkage void sdram_console_tx_byte(unsigned char byte) +{ +#ifdef DEBUG + putc(byte); +#endif +} + +void broadwell_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->pei_version = PEI_VERSION; + pei_data->board_type = BOARD_TYPE_ULT; + pei_data->pciexbar = MCFG_BASE_ADDRESS; + pei_data->smbusbar = SMBUS_BASE_ADDRESS; + pei_data->ehcibar = EARLY_EHCI_BAR; + pei_data->xhcibar = EARLY_XHCI_BAR; + pei_data->gttbar = EARLY_GTT_BAR; + pei_data->pmbase = ACPI_BASE_ADDRESS; + pei_data->gpiobase = GPIO_BASE_ADDRESS; + pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; + pei_data->temp_mmio_base = EARLY_TEMP_MMIO; + pei_data->tx_byte = sdram_console_tx_byte; + pei_data->ddr_refresh_2x = 1; +} + +static void pei_data_usb2_port(struct pei_data *pei_data, int port, uint length, + uint enable, uint oc_pin, uint location) +{ + pei_data->usb2_ports[port].length = length; + pei_data->usb2_ports[port].enable = enable; + pei_data->usb2_ports[port].oc_pin = oc_pin; + pei_data->usb2_ports[port].location = location; +} + +static void pei_data_usb3_port(struct pei_data *pei_data, int port, uint enable, + uint oc_pin, uint fixed_eq) +{ + pei_data->usb3_ports[port].enable = enable; + pei_data->usb3_ports[port].oc_pin = oc_pin; + pei_data->usb3_ports[port].fixed_eq = fixed_eq; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + /* DQ byte map for Samus board */ + const u8 dq_map[2][6][2] = { + { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, + { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } }, + { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, + { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } }; + /* DQS CPU<>DRAM map for Samus board */ + const u8 dqs_map[2][8] = { + { 2, 0, 1, 3, 6, 4, 7, 5 }, + { 2, 1, 0, 3, 6, 5, 4, 7 } }; + + pei_data->ec_present = 1; + + /* One installed DIMM per channel */ + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + + memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); + memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); + + /* P0: HOST PORT */ + pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0, + USB_PORT_BACK_PANEL); + /* P1: HOST PORT */ + pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, + USB_PORT_BACK_PANEL); + /* P2: RAIDEN */ + pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + /* P3: SD CARD */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P4: RAIDEN */ + pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + /* P5: WWAN (Disabled) */ + pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, + USB_PORT_SKIP); + /* P6: CAMERA */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P7: BT */ + pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + + /* P1: HOST PORT */ + pei_data_usb3_port(pei_data, 0, 1, 0, 0); + /* P2: HOST PORT */ + pei_data_usb3_port(pei_data, 1, 1, 1, 0); + /* P3: RAIDEN */ + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + /* P4: RAIDEN */ + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); +}

static int broadwell_northbridge_early_init(struct udevice *dev) { diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c index 1b9f9840c6f..b8450cc9d29 100644 --- a/arch/x86/cpu/broadwell/sdram.c +++ b/arch/x86/cpu/broadwell/sdram.c @@ -34,99 +34,6 @@ int dram_init_banksize(void) return 0; }

-void broadwell_fill_pei_data(struct pei_data *pei_data) -{ - pei_data->pei_version = PEI_VERSION; - pei_data->board_type = BOARD_TYPE_ULT; - pei_data->pciexbar = MCFG_BASE_ADDRESS; - pei_data->smbusbar = SMBUS_BASE_ADDRESS; - pei_data->ehcibar = EARLY_EHCI_BAR; - pei_data->xhcibar = EARLY_XHCI_BAR; - pei_data->gttbar = EARLY_GTT_BAR; - pei_data->pmbase = ACPI_BASE_ADDRESS; - pei_data->gpiobase = GPIO_BASE_ADDRESS; - pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; - pei_data->temp_mmio_base = EARLY_TEMP_MMIO; - pei_data->tx_byte = sdram_console_tx_byte; - pei_data->ddr_refresh_2x = 1; -} - -static inline void pei_data_usb2_port(struct pei_data *pei_data, int port, - uint16_t length, uint8_t enable, - uint8_t oc_pin, uint8_t location) -{ - pei_data->usb2_ports[port].length = length; - pei_data->usb2_ports[port].enable = enable; - pei_data->usb2_ports[port].oc_pin = oc_pin; - pei_data->usb2_ports[port].location = location; -} - -static inline void pei_data_usb3_port(struct pei_data *pei_data, int port, - uint8_t enable, uint8_t oc_pin, - uint8_t fixed_eq) -{ - pei_data->usb3_ports[port].enable = enable; - pei_data->usb3_ports[port].oc_pin = oc_pin; - pei_data->usb3_ports[port].fixed_eq = fixed_eq; -} - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - /* DQ byte map for Samus board */ - const u8 dq_map[2][6][2] = { - { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, - { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } }, - { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, - { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } }; - /* DQS CPU<>DRAM map for Samus board */ - const u8 dqs_map[2][8] = { - { 2, 0, 1, 3, 6, 4, 7, 5 }, - { 2, 1, 0, 3, 6, 5, 4, 7 } }; - - pei_data->ec_present = 1; - - /* One installed DIMM per channel */ - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; - - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - - /* P0: HOST PORT */ - pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0, - USB_PORT_BACK_PANEL); - /* P1: HOST PORT */ - pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, - USB_PORT_BACK_PANEL); - /* P2: RAIDEN */ - pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, - USB_PORT_BACK_PANEL); - /* P3: SD CARD */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_INTERNAL); - /* P4: RAIDEN */ - pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, - USB_PORT_BACK_PANEL); - /* P5: WWAN (Disabled) */ - pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, - USB_PORT_SKIP); - /* P6: CAMERA */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_INTERNAL); - /* P7: BT */ - pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_INTERNAL); - - /* P1: HOST PORT */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); - /* P2: HOST PORT */ - pei_data_usb3_port(pei_data, 1, 1, 1, 0); - /* P3: RAIDEN */ - pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); - /* P4: RAIDEN */ - pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); -} - static unsigned long get_top_of_ram(struct udevice *dev) { /*

At present we support having 16-bit init be in SPL or U-Boot proper, but not TPL. Add support for this so that TPL can boot.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

Makefile | 1 + arch/x86/Makefile | 4 ++-- arch/x86/cpu/intel_common/Makefile | 2 +- arch/x86/cpu/u-boot-spl.lds | 2 +- scripts/Makefile.spl | 10 +++++++++- 5 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/Makefile b/Makefile index f2c7bb6041a..56497e4afe5 100644 --- a/Makefile +++ b/Makefile @@ -1380,6 +1380,7 @@ cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \

u-boot.rom: u-boot-x86-16bit.bin u-boot.bin \ $(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \ + $(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin) \ $(if $(CONFIG_HAVE_REFCODE),refcode.bin) FORCE $(call if_changed,binman)

diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 9fd6cf2d3bb..f1afc74fff8 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -20,8 +20,8 @@ endif endif endif # EFI

-head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o -head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o +head-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o +head-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o

libs-y += arch/x86/cpu/ libs-y += arch/x86/lib/ diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index bf798c287f3..80fbc7ab661 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -3,7 +3,7 @@ # Copyright (c) 2016 Google, Inc

ifdef CONFIG_HAVE_MRC -obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += car.o +obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += me_status.o obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += report_platform.o obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds index 4e656dc4e5a..f20c0b810d3 100644 --- a/arch/x86/cpu/u-boot-spl.lds +++ b/arch/x86/cpu/u-boot-spl.lds @@ -54,7 +54,7 @@ SECTIONS /DISCARD/ : { *(.interp*) } /DISCARD/ : { *(.gnu*) }

-#ifdef CONFIG_SPL_X86_16BIT_INIT +#if defined(CONFIG_SPL_X86_16BIT_INIT) || defined(CONFIG_TPL_X86_16BIT_INIT) /* * The following expressions place the 16-bit Real-Mode code and * Reset Vector at the end of the Flash ROM diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 8d76a2d4007..7af6b120b6c 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -228,7 +228,11 @@ ifeq ($(CONFIG_SYS_SOC),"at91") ALL-y += $(obj)/boot.bin endif

+ifdef CONFIG_TPL_BUILD +ALL-$(CONFIG_TPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-tpl.bin +else ALL-$(CONFIG_SPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-spl.bin +endif

ALL-$(CONFIG_ARCH_ZYNQ) += $(obj)/boot.bin ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin @@ -328,7 +332,7 @@ quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@

OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary \ - $(if $(CONFIG_SPL_X86_16BIT_INIT),-R .start16 -R .resetvec) + $(if $(CONFIG_$(SPL_TPL_)X86_16BIT_INIT),-R .start16 -R .resetvec)

$(obj)/$(SPL_BIN)-nodtb.bin: $(obj)/$(SPL_BIN) FORCE $(call if_changed,objcopy) @@ -337,6 +341,10 @@ OBJCOPYFLAGS_u-boot-x86-16bit-spl.bin := -O binary -j .start16 -j .resetvec $(obj)/u-boot-x86-16bit-spl.bin: $(obj)/u-boot-spl FORCE $(call if_changed,objcopy)

+OBJCOPYFLAGS_u-boot-x86-16bit-tpl.bin := -O binary -j .start16 -j .resetvec +$(obj)/u-boot-x86-16bit-tpl.bin: $(obj)/u-boot-tpl FORCE + $(call if_changed,objcopy) + LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)

# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.

At present broadwell only supports booting straight into U-Boot proper. Add a separate init file to boot from SPL into U-Boot proper, and select it when SPL is in use.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/cpu/broadwell/Makefile | 15 +++++++ arch/x86/cpu/broadwell/cpu_from_spl.c | 63 +++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) create mode 100644 arch/x86/cpu/broadwell/cpu_from_spl.c

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile index 8553615f67b..fbc778cda5f 100644 --- a/arch/x86/cpu/broadwell/Makefile +++ b/arch/x86/cpu/broadwell/Makefile @@ -5,6 +5,21 @@ obj-y += adsp.o obj-y += cpu.o obj-y += cpu_full.o + +ifdef CONFIG_SPL +ifndef CONFIG_SPL_BUILD +obj-y += cpu_from_spl.o +obj-y += cpu_full.o +endif +ifndef CONFIG_SPL_BUILD +# obj-y += cpu_from_spl.o +endif +endif + +ifeq ($(CONFIG_$(SPL_TPL_)X86_32BIT_INIT),) +#obj-y += cpu_from_spl.o +endif + obj-y += iobp.o obj-y += lpc.o obj-y += me.o diff --git a/arch/x86/cpu/broadwell/cpu_from_spl.c b/arch/x86/cpu/broadwell/cpu_from_spl.c new file mode 100644 index 00000000000..c3d4a8d5477 --- /dev/null +++ b/arch/x86/cpu/broadwell/cpu_from_spl.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Google, Inc + * Written by Simon Glass sjg@chromium.org + */ + +#include <common.h> +#include <bloblist.h> +#include <debug_uart.h> +#include <handoff.h> +#include <asm/mtrr.h> + +int misc_init_r(void) +{ + return 0; +} + +int dram_init(void) +{ + struct spl_handoff *ho; + + ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho)); + if (!ho) + return log_msg_ret("Missing SPL hand-off info", -ENOENT); + handoff_load_dram_size(ho); +#ifdef CONFIG_TPL + /* TODO(sjg@chromium.org): MTRR cannot be adjusted without a hang */ + mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30); +#else + mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); + mtrr_commit(true); +#endif + + return 0; +} + +int checkcpu(void) +{ + return 0; +} + +int print_cpuinfo(void) +{ + return 0; +} + +void board_debug_uart_init(void) +{ +} + +int dram_init_banksize(void) +{ +#ifdef CONFIG_NR_DRAM_BANKS + struct spl_handoff *ho; + + ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho)); + if (!ho) + return log_msg_ret("Missing SPL hand-off info", -ENOENT); + handoff_load_dram_banks(ho); +#endif + + return 0; +}

Allow broadwell to build for SPL and include the reference code.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/cpu/broadwell/Makefile | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile index fbc778cda5f..52d56c65be8 100644 --- a/arch/x86/cpu/broadwell/Makefile +++ b/arch/x86/cpu/broadwell/Makefile @@ -3,13 +3,14 @@ # Copyright (c) 2016 Google, Inc

obj-y += adsp.o -obj-y += cpu.o -obj-y += cpu_full.o +obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += cpu.o +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += cpu_full.o

ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD obj-y += cpu_from_spl.o obj-y += cpu_full.o +obj-y += refcode.o endif ifndef CONFIG_SPL_BUILD # obj-y += cpu_from_spl.o @@ -27,6 +28,6 @@ obj-y += northbridge.o obj-y += pch.o obj-y += pinctrl_broadwell.o obj-y += power_state.o -obj-y += refcode.o +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += refcode.o obj-y += sata.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += sdram.o

Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/cpu/intel_common/Makefile | 6 ++++++ arch/x86/cpu/intel_common/cpu_from_spl.c | 27 ++++++++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 arch/x86/cpu/intel_common/cpu_from_spl.c

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 80fbc7ab661..57cca0b930c 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -14,3 +14,9 @@ ifndef CONFIG_TARGET_EFI_APP obj-y += microcode.o endif obj-y += pch.o + +ifdef CONFIG_SPL +ifndef CONFIG_SPL_BUILD +obj-y += cpu_from_spl.o +endif +endif diff --git a/arch/x86/cpu/intel_common/cpu_from_spl.c b/arch/x86/cpu/intel_common/cpu_from_spl.c new file mode 100644 index 00000000000..a6233c75ce2 --- /dev/null +++ b/arch/x86/cpu/intel_common/cpu_from_spl.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2016 Google, Inc + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <asm/cpu_common.h> +#include <asm/intel_regs.h> +#include <asm/lapic.h> +#include <asm/lpc_common.h> +#include <asm/msr.h> +#include <asm/mtrr.h> +#include <asm/post.h> +#include <asm/microcode.h> + +DECLARE_GLOBAL_DATA_PTR; + +int arch_cpu_init(void) +{ + int ret; + + ret = x86_cpu_reinit_f(); + + return ret; +}

When SPL is used to set up the memory controller we want to save the MRC data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a function to handle that.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/include/asm/mrccache.h | 11 ++++++++++ arch/x86/lib/mrccache.c | 36 ++++++++++++++++++++++++--------- 2 files changed, 38 insertions(+), 9 deletions(-)

diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index 04783cd3292..40fda856ff4 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -103,4 +103,15 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry); */ int mrccache_save(void);

+/** + * mrccache_spl_save() - Save to the MRC region from SPL + * + * When SPL is used to set up the memory controller we want to save the MRC + * data in SPL to avoid needing to pass it up to U-Boot proper to save. This + * function handles that. + * + * @return 0 if saved to SPI flash successfully, other error if failed + */ +int mrccache_spl_save(void); + #endif /* _ASM_MRCCACHE_H */ diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 2a8919885b7..f37a732a45c 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -159,18 +159,11 @@ int mrccache_update(struct udevice *sf, struct mrc_region *entry, return 0; }

-int mrccache_reserve(void) +static void mrccache_setup(void *data) { - struct mrc_data_container *cache; + struct mrc_data_container *cache = data; u16 checksum;

- if (!gd->arch.mrc_output_len) - return 0; - - /* adjust stack pointer to store pure cache data plus the header */ - gd->start_addr_sp -= (gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE); - cache = (struct mrc_data_container *)gd->start_addr_sp; - cache->signature = MRC_DATA_SIGNATURE; cache->data_size = gd->arch.mrc_output_len; checksum = compute_ip_checksum(gd->arch.mrc_output, cache->data_size); @@ -182,6 +175,16 @@ int mrccache_reserve(void)

/* gd->arch.mrc_output now points to the container */ gd->arch.mrc_output = (char *)cache; +} + +int mrccache_reserve(void) +{ + if (!gd->arch.mrc_output_len) + return 0; + + /* adjust stack pointer to store pure cache data plus the header */ + gd->start_addr_sp -= (gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE); + mrccache_setup((void *)gd->start_addr_sp);

gd->start_addr_sp &= ~0xf;

@@ -256,3 +259,18 @@ err_entry: debug("%s: Failed: %d\n", __func__, ret); return ret; } + +int mrccache_spl_save(void) +{ + void *data; + int size; + + size = gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE; + data = malloc(size); + if (!data) + return log_msg_ret("Allocate MRC cache block", -ENOMEM); + mrccache_setup(data); + gd->arch.mrc_output = data; + + return mrccache_save(); +}

Add the required CPU code so that TPL builds correctly. Also update the SPL code to deal with being booted from TPL.

Reviewed-by: Bin Meng bmeng.cn@gmail.com Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/include/asm/spl.h | 17 ++++- arch/x86/lib/Makefile | 9 ++- arch/x86/lib/spl.c | 44 ++++++++++- arch/x86/lib/tpl.c | 118 ++++++++++++++++++++++++++++++ include/configs/chromebook_link.h | 3 - include/configs/qemu-x86.h | 3 - 6 files changed, 183 insertions(+), 11 deletions(-) create mode 100644 arch/x86/lib/tpl.c

diff --git a/arch/x86/include/asm/spl.h b/arch/x86/include/asm/spl.h index 8cf59d14e7c..27432b28979 100644 --- a/arch/x86/include/asm/spl.h +++ b/arch/x86/include/asm/spl.h @@ -2,6 +2,19 @@ /* * Copyright (C) 2017 Google, Inc * Written by Simon Glass sjg@chromium.org - * - * This file is required for SPL to build, but is empty. */ + +#ifndef __asm_spl_h +#define __asm_spl_h + +#define CONFIG_SPL_BOARD_LOAD_IMAGE + +enum { + BOOT_DEVICE_SPI = 10, + BOOT_DEVICE_BOARD, + BOOT_DEVICE_CROS_VBOOT, +}; + +void jump_to_spl(ulong entry); + +#endif diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 56fd680033b..436252dd831 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -43,7 +43,14 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_ZBOOT) += zimage.o endif obj-$(CONFIG_HAVE_FSP) += fsp/ -obj-$(CONFIG_SPL_BUILD) += spl.o + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_TPL_BUILD +obj-y += tpl.o +else +obj-y += spl.o +endif +endif

lib-$(CONFIG_USE_PRIVATE_LIBGCC) += div64.o

diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 7d290740bfa..5d5d1a9ca74 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -5,8 +5,10 @@

#include <common.h> #include <debug_uart.h> +#include <malloc.h> #include <spl.h> #include <asm/cpu.h> +#include <asm/mrccache.h> #include <asm/mtrr.h> #include <asm/processor.h> #include <asm-generic/sections.h> @@ -20,6 +22,7 @@ __weak int arch_cpu_init_dm(void)

static int x86_spl_init(void) { +#ifndef CONFIG_TPL /* * TODO(sjg@chromium.org): We use this area of RAM for the stack * and global_data in SPL. Once U-Boot starts up and releocates it @@ -27,6 +30,7 @@ static int x86_spl_init(void) * place it immediately below CONFIG_SYS_TEXT_BASE. */ char *ptr = (char *)0x110000; +#endif int ret;

debug("%s starting\n", __func__); @@ -35,27 +39,44 @@ static int x86_spl_init(void) debug("%s: spl_init() failed\n", __func__); return ret; } +#ifdef CONFIG_TPL + /* Do a mini-init if TPL has already done the full init */ + ret = x86_cpu_reinit_f(); +#else ret = arch_cpu_init(); +#endif if (ret) { debug("%s: arch_cpu_init() failed\n", __func__); return ret; } +#ifndef CONFIG_TPL ret = arch_cpu_init_dm(); if (ret) { debug("%s: arch_cpu_init_dm() failed\n", __func__); return ret; } +#endif preloader_console_init(); +#ifndef CONFIG_TPL ret = print_cpuinfo(); if (ret) { debug("%s: print_cpuinfo() failed\n", __func__); return ret; } +#endif ret = dram_init(); if (ret) { debug("%s: dram_init() failed\n", __func__); return ret; } + if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) { + ret = mrccache_spl_save(); + if (ret) + debug("%s: Failed to write to mrccache (err=%d)\n", + __func__, ret); + } + +#ifndef CONFIG_TPL memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);

/* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */ @@ -80,9 +101,11 @@ static int x86_spl_init(void) (1ULL << 32) - CONFIG_XIP_ROM_SIZE, CONFIG_XIP_ROM_SIZE); if (ret) { - debug("%s: SPI cache setup failed\n", __func__); + debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret); return ret; } + mtrr_commit(true); +#endif

return 0; } @@ -96,9 +119,17 @@ void board_init_f(ulong flags) debug("Error %d\n", ret); hang(); } - +#ifdef CONFIG_TPL + gd->bd = malloc(sizeof(*gd->bd)); + if (!gd->bd) { + printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd)); + hang(); + } + board_init_r(gd, 0); +#else /* Uninit CAR and jump to board_init_f_r() */ board_init_f_r_trampoline(gd->start_addr_sp); +#endif }

void board_init_f_r(void) @@ -144,6 +175,7 @@ int spl_spi_load_image(void) return -EPERM; }

+#ifdef CONFIG_X86_RUN_64BIT void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { int ret; @@ -154,3 +186,11 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) while (1) ; } +#endif + +void spl_board_init(void) +{ +#ifndef CONFIG_TPL + preloader_console_init(); +#endif +} diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c new file mode 100644 index 00000000000..492a2d65216 --- /dev/null +++ b/arch/x86/lib/tpl.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Google, Inc + */ + +#include <common.h> +#include <debug_uart.h> +#include <spl.h> +#include <asm/cpu.h> +#include <asm/mtrr.h> +#include <asm/processor.h> +#include <asm-generic/sections.h> + +DECLARE_GLOBAL_DATA_PTR; + +__weak int arch_cpu_init_dm(void) +{ + return 0; +} + +static int x86_tpl_init(void) +{ + int ret; + + debug("%s starting\n", __func__); + ret = spl_init(); + if (ret) { + debug("%s: spl_init() failed\n", __func__); + return ret; + } + ret = arch_cpu_init(); + if (ret) { + debug("%s: arch_cpu_init() failed\n", __func__); + return ret; + } + ret = arch_cpu_init_dm(); + if (ret) { + debug("%s: arch_cpu_init_dm() failed\n", __func__); + return ret; + } + preloader_console_init(); + ret = print_cpuinfo(); + if (ret) { + debug("%s: print_cpuinfo() failed\n", __func__); + return ret; + } + + return 0; +} + +void board_init_f(ulong flags) +{ + int ret; + + ret = x86_tpl_init(); + if (ret) { + debug("Error %d\n", ret); + hang(); + } + + /* Uninit CAR and jump to board_init_f_r() */ + board_init_r(gd, 0); +} + +void board_init_f_r(void) +{ + /* Not used since we never call board_init_f_r_trampoline() */ + while (1); +} + +u32 spl_boot_device(void) +{ + return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT : + BOOT_DEVICE_BOARD; +} + +int spl_start_uboot(void) +{ + return 0; +} + +void spl_board_announce_boot_device(void) +{ + printf("SPI flash"); +} + +static int spl_board_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */ + spl_image->entry_point = CONFIG_SPL_TEXT_BASE; + spl_image->load_addr = CONFIG_SPL_TEXT_BASE; + spl_image->os = IH_OS_U_BOOT; + spl_image->name = "U-Boot"; + + debug("Loading to %lx\n", spl_image->load_addr); + + return 0; +} +SPL_LOAD_IMAGE_METHOD("SPI", 0, BOOT_DEVICE_BOARD, spl_board_load_image); + +int spl_spi_load_image(void) +{ + return -EPERM; +} + +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + printf("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point); + jump_to_spl(spl_image->entry_point); + while (1) + ; +} + +void spl_board_init(void) +{ + preloader_console_init(); +} diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index ee546d8f893..f59ed8e28b1 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -20,9 +20,6 @@

#define CONFIG_SPL_TEXT_BASE 0xfffd0000

-#define BOOT_DEVICE_SPI 10 - #define CONFIG_SPL_BOARD_LOAD_IMAGE -#define BOOT_DEVICE_BOARD 11

#endif /* __CONFIG_H */ diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index 4b9ddd6f258..59206fb24b1 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -37,9 +37,6 @@

#define CONFIG_SPL_TEXT_BASE 0xfffd0000

-#define BOOT_DEVICE_SPI 10 - #define CONFIG_SPL_BOARD_LOAD_IMAGE -#define BOOT_DEVICE_BOARD 11

#endif /* __CONFIG_H */

When the MRC cache fails to save it is useful to have some debugging info to indicate what when wrong. Add some more debug() calls.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/lib/mrccache.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index f37a732a45c..be107627b80 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -113,8 +113,10 @@ int mrccache_update(struct udevice *sf, struct mrc_region *entry, ulong base_addr; int ret;

- if (!is_mrc_cache(cur)) + if (!is_mrc_cache(cur)) { + debug("%s: Cache data not valid\n", __func__); return -EINVAL; + }

/* Find the last used block */ base_addr = entry->base + entry->offset; @@ -205,17 +207,23 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) return -ENOENT; }

- if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2)) + if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2)) { + debug("%s: Cannot find memory map\n", __func__); return -EINVAL; + } entry->base = reg[0];

/* Find the place where we put the MRC cache */ mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache"); - if (mrc_node < 0) + if (mrc_node < 0) { + debug("%s: Cannot find node\n", __func__); return -EPERM; + }

- if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2)) + if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2)) { + debug("%s: Cannot find address\n", __func__); return -EINVAL; + } entry->offset = reg[0]; entry->length = reg[1];

The EFI implementation of reset sits inside the driver and is called directly from outside the driver, breaking the normal driver-model conventions. Worse, it passed NULL as the device pointer, hoping that the called function won't use it, which breaks as soon as code is added to use it.

Separate out the implementation to improve the situation enough to allow a future patch to add new sysreset features.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Add new patch to separate out the EFI code in sysreset

drivers/sysreset/sysreset_x86.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c index 009f3766027..d484ec5de49 100644 --- a/drivers/sysreset/sysreset_x86.c +++ b/drivers/sysreset/sysreset_x86.c @@ -12,8 +12,7 @@ #include <asm/processor.h> #include <efi_loader.h>

-static __efi_runtime int x86_sysreset_request(struct udevice *dev, - enum sysreset_t type) +static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type) { int value;

@@ -39,11 +38,18 @@ void __efi_runtime EFIAPI efi_reset_system( efi_status_t reset_status, unsigned long data_size, void *reset_data) { + int value; + + /* + * inline this code since we are not caused in the context of a + * udevice and passing NULL to x86_sysreset_request() is too horrible. + */ if (reset_type == EFI_RESET_COLD || reset_type == EFI_RESET_PLATFORM_SPECIFIC) - x86_sysreset_request(NULL, SYSRESET_COLD); - else if (reset_type == EFI_RESET_WARM) - x86_sysreset_request(NULL, SYSRESET_WARM); + value = SYS_RST | RST_CPU | FULL_RST; + else /* assume EFI_RESET_WARM since we cannot return an error */ + value = SYS_RST | RST_CPU; + outb(value, IO_PORT_RESET);

/* TODO EFI_RESET_SHUTDOWN */

Implement this ioctl() to support power off.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Add new patch to implement PCH_REQ_PMBASE_INFO on ivybridge

arch/x86/cpu/ivybridge/bd82x6x.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index ed9bce64168..1cb6cecda9e 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -229,6 +229,21 @@ static int bd82x6x_ioctl(struct udevice *dev, enum pch_req_t req, void *data, return -ENOENT;

return val & RCBA_AUDIO_CONFIG_MASK; + case PCH_REQ_PMBASE_INFO: { + struct pch_pmbase_info *pm = data; + int ret; + + /* Find the base address of the powermanagement registers */ + ret = dm_pci_read_config16(dev, 0x40, &pm->base); + if (ret) + return ret; + pm->base &= 0xfffe; + pm->gpio0_en_ofs = GPE0_EN; + pm->pm1_sts_ofs = PM1_STS; + pm->pm1_cnt_ofs = PM1_CNT; + + return 0; + } default: return -ENOSYS; }

On modern x86 devices we can power the system off using the power- management features of the PCH. Add an implementation for this.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Add new patch to implement power-off if available

drivers/sysreset/sysreset_x86.c | 82 +++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+)

diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c index d484ec5de49..bd759aa8bf4 100644 --- a/drivers/sysreset/sysreset_x86.c +++ b/drivers/sysreset/sysreset_x86.c @@ -7,14 +7,80 @@

#include <common.h> #include <dm.h> +#include <pch.h> #include <sysreset.h> #include <asm/io.h> #include <asm/processor.h> #include <efi_loader.h>

+struct x86_sysreset_platdata { + struct udevice *pch; +}; + +#define PWRBTN_STS (1 << 8) + +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S5 7 + +/* + * Power down the machine by using the power management sleep control + * of the chipset. This will currently only work on Intel chipsets. + * However, adapting it to new chipsets is fairly simple. You will + * have to find the IO address of the power management register block + * in your southbridge, and look up the appropriate SLP_TYP_S5 value + * from your southbridge's data sheet. + * + * This function never returns. + */ +int pch_sysreset_power_off(struct udevice *dev) +{ + struct x86_sysreset_platdata *plat = dev_get_platdata(dev); + struct pch_pmbase_info pm; + u32 reg32; + int ret; + + if (!plat->pch) + return -ENOENT; + ret = pch_ioctl(plat->pch, PCH_REQ_PMBASE_INFO, &pm, sizeof(pm)); + if (ret) + return ret; + + + /* Mask interrupts or system might stay in a coma + * (not executing code anymore, but not powered off either) + */ + asm("cli"); + + /* + * Avoid any GPI waking the system from S5* or the system might stay in + * a coma + */ + outl(0x00000000, pm.base + pm.gpio0_en_ofs); + + /* Clear Power Button Status */ + outw(PWRBTN_STS, pm.base + pm.pm1_sts_ofs); + + /* PMBASE + 4, Bit 10-12, Sleeping Type, * set to 111 -> S5, soft_off */ + reg32 = inl(pm.base + pm.pm1_cnt_ofs); + + /* Set Sleeping Type to S5 (poweroff) */ + reg32 &= ~(SLP_EN | SLP_TYP); + reg32 |= SLP_TYP_S5; + outl(reg32, pm.base + pm.pm1_cnt_ofs); + + /* Now set the Sleep Enable bit */ + reg32 |= SLP_EN; + outl(reg32, pm.base + pm.pm1_cnt_ofs); + + for (;;) + asm("hlt"); +} + static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type) { int value; + int ret;

switch (type) { case SYSRESET_WARM: @@ -23,6 +89,11 @@ static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type) case SYSRESET_COLD: value = SYS_RST | RST_CPU | FULL_RST; break; + case SYSRESET_POWER_OFF: + ret = pch_sysreset_power_off(dev); + if (ret) + return ret; + return -EINPROGRESS; default: return -ENOSYS; } @@ -57,6 +128,15 @@ void __efi_runtime EFIAPI efi_reset_system( } #endif

+static int x86_sysreset_probe(struct udevice *dev) +{ + struct x86_sysreset_platdata *plat = dev_get_platdata(dev); + + /* Locate the PCH if there is one. It isn't essential */ + uclass_first_device(UCLASS_PCH, &plat->pch); + + return 0; +}

static const struct udevice_id x86_sysreset_ids[] = { { .compatible = "x86,reset" }, @@ -72,4 +152,6 @@ U_BOOT_DRIVER(x86_sysreset) = { .id = UCLASS_SYSRESET, .of_match = x86_sysreset_ids, .ops = &x86_sysreset_ops, + .probe = x86_sysreset_probe, + .platdata_auto_alloc_size = sizeof(struct x86_sysreset_platdata), };

Update the Makefie rules to ensure that the correct files are built when TPL is being used.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/cpu/intel_common/Makefile | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 57cca0b930c..07f27c29ec7 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -4,15 +4,18 @@

ifdef CONFIG_HAVE_MRC obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o -obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += me_status.o -obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += report_platform.o -obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o endif obj-y += cpu.o obj-y += lpc.o ifndef CONFIG_TARGET_EFI_APP +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o +ifndef CONFIG_$(SPL_)X86_64 obj-y += microcode.o endif +endif obj-y += pch.o

ifdef CONFIG_SPL

The MTRRs are normally set up in U-Boot proper, so avoid setting them up in SPL as well.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/lib/init_helpers.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 0481f453ca6..ac85278cdf0 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -18,7 +18,10 @@ __weak ulong board_get_usable_ram_top(ulong total_size)

int init_cache_f_r(void) { -#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) +#if (CONFIG_IS_ENABLED(X86_32BIT_INIT) || \ + (!defined(CONFIG_SPL_BUILD) && \ + !CONFIG_IS_ENABLED(CONFIG_X86_RUN_64BIT))) && \ + !defined(CONFIG_HAVE_FSP) int ret;

ret = mtrr_commit(false);

This report is normally generated by U-Boot proper. Correct the condition here so that it respects the Kconfig options for bootstage.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/lib/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 832b1f901c6..5443a862ab5 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -35,7 +35,7 @@ void bootm_announce_and_cleanup(void) timestamp_add_now(TS_U_BOOT_START_KERNEL); #endif bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); -#ifdef CONFIG_BOOTSTAGE_REPORT +#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT) bootstage_report(); #endif

When TPL is in use, U-Boot proper should support initing the VGA ROM even though the 32-bit init portion is in SPL. Update the condition to handle this.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

drivers/pci/pci_rom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 7d9b75c2c45..2cede1211bb 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -306,7 +306,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), goto err; #endif } else { -#if defined(CONFIG_X86) && CONFIG_IS_ENABLED(X86_32BIT_INIT) +#if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL) bios_set_interrupt_handler(0x15, int15_handler);

bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,

Add a default implementation of this method which always indicates that the last reset was a power-on reset. This is the most likely type of reset and without a PCH-specific driver we cannot determine any other type.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

drivers/sysreset/sysreset_x86.c | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c index bd759aa8bf4..b8876dc51e7 100644 --- a/drivers/sysreset/sysreset_x86.c +++ b/drivers/sysreset/sysreset_x86.c @@ -103,6 +103,11 @@ static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type) return -EINPROGRESS; }

+static int x86_sysreset_get_last(struct udevice *dev) +{ + return SYSRESET_POWER; +} + #ifdef CONFIG_EFI_LOADER void __efi_runtime EFIAPI efi_reset_system( enum efi_reset_type reset_type, @@ -145,6 +150,7 @@ static const struct udevice_id x86_sysreset_ids[] = {

static struct sysreset_ops x86_sysreset_ops = { .request = x86_sysreset_request, + .get_last = x86_sysreset_get_last, };

U_BOOT_DRIVER(x86_sysreset) = {

There are quite a few variables which control where things appear in the final ROM image. Add a flashmap in the documentation to make this easier to figure out.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

doc/README.x86 | 14 ++++++++++++++ 1 file changed, 14 insertions(+)

diff --git a/doc/README.x86 b/doc/README.x86 index fa49cb8b8a2..d5224b75367 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -185,6 +185,20 @@ If you are using em100, then this command will flash write -Boot:

em100 -s -d filename.rom -c W25Q64CV -r

+Flash map for samus / broadwell: + + fffff800 SYS_X86_START16 + ffff0000 RESET_SEG_START + fffd8000 TPL_TEXT_BASE + fffa0000 X86_MRC_ADDR + fff90000 VGA_BIOS_ADDR + ffed0000 SYS_TEXT_BASE + ffea0000 X86_REFCODE_ADDR + ffe70000 SPL_TEXT_BASE + ffa00000 <spare> + ff801000 intel-me (address set by descriptor.bin) + ff800000 intel-descriptor + ---

Intel Crown Bay specific instructions for bare mode:

Add TPL binaries to the device x86 binman desciption. When enabled, TPL will start first, doing the 16-bit init, then jump to SPL and finally U-Boot proper.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/dts/u-boot.dtsi | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 1050236330a..70e9c8f7acd 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -22,7 +22,21 @@ filename = CONFIG_INTEL_ME_FILE; }; #endif -#ifdef CONFIG_SPL +#ifdef CONFIG_TPL + u-boot-spl { + offset = <CONFIG_SPL_TEXT_BASE>; + }; + u-boot-spl-dtb { + }; + u-boot-tpl-with-ucode-ptr { + offset = <CONFIG_TPL_TEXT_BASE>; + }; + u-boot-tpl-dtb { + }; + u-boot { + offset = <CONFIG_SYS_TEXT_BASE>; + }; +#elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { offset = <CONFIG_SPL_TEXT_BASE>; }; @@ -31,7 +45,11 @@ type = "u-boot-dtb-with-ucode"; }; u-boot { +#if CONFIG_SYS_TEXT_BASE == 0x1110000 offset = <0xfff00000>; +#else + offset = <CONFIG_SYS_TEXT_BASE>; +#endif }; #else u-boot-with-ucode-ptr { @@ -77,7 +95,11 @@ offset = <CONFIG_X86_REFCODE_ADDR>; }; #endif -#ifdef CONFIG_SPL +#ifdef CONFIG_TPL + x86-start16-tpl { + offset = <CONFIG_SYS_X86_START16>; + }; +#elif defined(CONFIG_SPL) x86-start16-spl { offset = <CONFIG_SYS_X86_START16>; };

The standard image generated by U-Boot on x86 is u-boot.rom. Add a separate image called image.bin for verified boot. This supports verification in TPL of which SPL/U-Boot to start, then jumping to the correct one, with SPL setting up the SDRAM and U-Boot proper providing the user interface if needed.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

arch/x86/dts/u-boot.dtsi | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 70e9c8f7acd..5943619b863 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -6,9 +6,23 @@

#include <config.h>

-#ifdef CONFIG_ROM_SIZE +#ifdef CONFIG_CHROMEOS / { binman { + multiple-images; + rom: rom { + }; + }; +}; +#else +/ { + rom: binman { + }; +}; +#endif + +#ifdef CONFIG_ROM_SIZE +&rom { filename = "u-boot.rom"; end-at-4gb; sort-by-offset; @@ -108,6 +122,5 @@ offset = <CONFIG_SYS_X86_START16>; }; #endif - }; }; #endif

This is again too small, so increase it slightly.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

configs/chromebook_samus_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 7e2453f2440..5f5db07b5a5 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -1,6 +1,6 @@ CONFIG_X86=y CONFIG_SYS_TEXT_BASE=0xFFE00000 -CONFIG_SYS_MALLOC_F_LEN=0x1c00 +CONFIG_SYS_MALLOC_F_LEN=0x1d00 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200

Add a version of samus which supports booting from TPL to SPL and then to U-Boot. This allows TPL to select from an A or B SPL to support verified boot with field upgrade.

Reviewed-by: Bin Meng bmeng.cn@gmail.com Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: - Sort defconfig and adjust it to build after rebase on maste

board/google/Kconfig | 8 +++ board/google/chromebook_samus/Kconfig | 14 +++- board/google/chromebook_samus/MAINTAINERS | 7 ++ configs/chromebook_samus_tpl_defconfig | 81 +++++++++++++++++++++++ include/configs/chromebook_samus.h | 3 + 5 files changed, 111 insertions(+), 2 deletions(-) create mode 100644 configs/chromebook_samus_tpl_defconfig

diff --git a/board/google/Kconfig b/board/google/Kconfig index d98a5e818fc..679a0f10239 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -52,6 +52,14 @@ config TARGET_CHROMEBOOK_SAMUS Chrome OS EC connected on LPC, and it provides a 2560x1700 high resolution touch-enabled LCD display.

+config TARGET_CHROMEBOOK_SAMUS_TPL + bool "Chromebook samus booting from TPL" + help + This is a version of Samus which boots into TPL, then to SPL and + U-Boot proper. This is useful where verified boot must select + between different A/B versions of SPL/U-Boot, to allow upgrading of + almost all U-Boot code in the field. + endchoice

source "board/google/chromebook_link/Kconfig" diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig index afbfe53deb4..90c23cba1be 100644 --- a/board/google/chromebook_samus/Kconfig +++ b/board/google/chromebook_samus/Kconfig @@ -1,4 +1,4 @@ -if TARGET_CHROMEBOOK_SAMUS +if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL

config SYS_BOARD default "chromebook_samus" @@ -10,7 +10,8 @@ config SYS_SOC default "broadwell"

config SYS_CONFIG_NAME - default "chromebook_samus" + default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS + default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL

config SYS_TEXT_BASE default 0xffe00000 @@ -39,3 +40,12 @@ config SYS_CAR_SIZE default 0x40000

endif + +if TARGET_CHROMEBOOK_SAMUS_TPL + +config BOARD_SPECIFIC_OPTIONS_TPL # dummy + def_bool y + select SPL + select TPL + +endif diff --git a/board/google/chromebook_samus/MAINTAINERS b/board/google/chromebook_samus/MAINTAINERS index 5500e46b408..ca4b16500af 100644 --- a/board/google/chromebook_samus/MAINTAINERS +++ b/board/google/chromebook_samus/MAINTAINERS @@ -4,3 +4,10 @@ S: Maintained F: board/google/chromebook_samus/ F: include/configs/chromebook_samus.h F: configs/chromebook_samus_defconfig + +CHROMEBOOK SAMUS TPL BOARD +M: Simon Glass sjg@chromium.org +S: Maintained +F: board/google/chromebook_samus/ +F: include/configs/chromebook_samus.h +F: configs/chromebook_samus_tpl_defconfig diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig new file mode 100644 index 00000000000..c586804e705 --- /dev/null +++ b/configs/chromebook_samus_tpl_defconfig @@ -0,0 +1,81 @@ +CONFIG_X86=y +CONFIG_SYS_TEXT_BASE=0xffed0000 +CONFIG_SYS_MALLOC_F_LEN=0x1a00 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_VENDOR_GOOGLE=y +CONFIG_TARGET_CHROMEBOOK_SAMUS_TPL=y +CONFIG_DEBUG_UART=y +CONFIG_HAVE_MRC=y +CONFIG_HAVE_REFCODE=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_MISC_INIT_R=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_SIZE=0x1000 +CONFIG_BLOBLIST_ADDR=0xff7c0000 +CONFIG_HANDOFF=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_PCI=y +CONFIG_SPL_PCH_SUPPORT=y +CONFIG_TPL_PCI=y +CONFIG_TPL_PCH_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_PART=y +CONFIG_CMD_SATA=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_TPM=y +CONFIG_CMD_TPM_TEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +# CONFIG_SPL_MAC_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus" +# CONFIG_NET is not set +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_TPL_MISC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_LPC=y +CONFIG_SYS_NS16550=y +CONFIG_SOUND=y +CONFIG_SOUND_I8254=y +CONFIG_SOUND_RT5677=y +CONFIG_SPI=y +CONFIG_TPM_TIS_LPC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_KEYBOARD=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_CONSOLE_SCROLL_LINES=5 +CONFIG_TPM=y diff --git a/include/configs/chromebook_samus.h b/include/configs/chromebook_samus.h index ccb2fe8caad..610be1e7b5e 100644 --- a/include/configs/chromebook_samus.h +++ b/include/configs/chromebook_samus.h @@ -23,4 +23,7 @@ #define CONFIG_ENV_SECT_SIZE 0x1000 #define CONFIG_ENV_OFFSET 0x003f8000

+#define CONFIG_SPL_TEXT_BASE 0xffe70000 +#define CONFIG_TPL_TEXT_BASE 0xfffd8000 + #endif /* __CONFIG_H */