There was for long time no activity in the 8xx area. We need to go further and convert to Kconfig, but it turned out, nobody is interested anymore in 8xx, so remove it (with a heavy heart, knowing that I remove here the root of U-Boot).

Signed-off-by: Heiko Schocher hs@denx.de ---

.travis.yml | 2 - README | 88 +- api/api_platform-powerpc.c | 2 +- arch/powerpc/Kconfig | 4 - arch/powerpc/cpu/mpc8xx/Kconfig | 51 - arch/powerpc/cpu/mpc8xx/Makefile | 25 - arch/powerpc/cpu/mpc8xx/bedbug_860.c | 314 ------- arch/powerpc/cpu/mpc8xx/config.mk | 8 - arch/powerpc/cpu/mpc8xx/cpu.c | 580 ------------ arch/powerpc/cpu/mpc8xx/cpu_init.c | 218 ----- arch/powerpc/cpu/mpc8xx/fdt.c | 27 - arch/powerpc/cpu/mpc8xx/fec.c | 933 ------------------- arch/powerpc/cpu/mpc8xx/fec.h | 12 - arch/powerpc/cpu/mpc8xx/interrupts.c | 278 ------ arch/powerpc/cpu/mpc8xx/kgdb.S | 54 -- arch/powerpc/cpu/mpc8xx/plprcr_write.S | 119 --- arch/powerpc/cpu/mpc8xx/scc.c | 472 ---------- arch/powerpc/cpu/mpc8xx/serial.c | 676 -------------- arch/powerpc/cpu/mpc8xx/speed.c | 403 -------- arch/powerpc/cpu/mpc8xx/spi.c | 533 ----------- arch/powerpc/cpu/mpc8xx/start.S | 650 ------------- arch/powerpc/cpu/mpc8xx/traps.c | 216 ----- arch/powerpc/cpu/mpc8xx/upatch.c | 194 ---- arch/powerpc/cpu/mpc8xx/video.c | 1123 ---------------------- arch/powerpc/cpu/ppc4xx/4xx_uart.c | 1 - arch/powerpc/cpu/ppc4xx/interrupts.c | 1 - arch/powerpc/cpu/ppc4xx/miiphy.c | 1 - arch/powerpc/cpu/ppc4xx/uic.c | 1 - arch/powerpc/cpu/ppc4xx/xilinx_irq.c | 1 - arch/powerpc/include/asm/8xx_immap.h | 515 ----------- arch/powerpc/include/asm/cache.h | 41 +- arch/powerpc/include/asm/global_data.h | 3 - arch/powerpc/include/asm/iopin_8xx.h | 379 -------- arch/powerpc/include/asm/ppc.h | 38 +- arch/powerpc/include/asm/processor.h | 5 +- arch/powerpc/include/asm/status_led.h | 4 +- arch/powerpc/lib/Makefile | 1 - arch/powerpc/lib/ide.c | 184 ---- arch/powerpc/lib/ide.h | 15 - arch/powerpc/lib/immap.c | 106 +-- arch/powerpc/lib/time.c | 4 +- board/tqc/tqm8xx/Kconfig | 155 ---- board/tqc/tqm8xx/MAINTAINERS | 31 - board/tqc/tqm8xx/Makefile | 8 - board/tqc/tqm8xx/load_sernum_ethaddr.c | 89 -- board/tqc/tqm8xx/tqm8xx.c | 677 -------------- board/tqc/tqm8xx/u-boot.lds | 94 -- cmd/bdinfo.c | 2 +- cmd/bedbug.c | 4 - cmd/ide.c | 9 +- cmd/pcmcia.c | 4 - cmd/reginfo.c | 59 +- cmd/source.c | 3 - common/board_f.c | 4 +- common/board_r.c | 14 - common/bootm_os.c | 14 +- common/lcd.c | 4 - configs/TQM823L_LCD_defconfig | 24 - configs/TQM823L_defconfig | 27 - configs/TQM823M_defconfig | 27 - configs/TQM850L_defconfig | 27 - configs/TQM850M_defconfig | 27 - configs/TQM855L_defconfig | 27 - configs/TQM855M_defconfig | 28 - configs/TQM860L_defconfig | 27 - configs/TQM860M_defconfig | 27 - configs/TQM862L_defconfig | 27 - configs/TQM862M_defconfig | 27 - configs/TQM866M_defconfig | 27 - configs/TQM885D_defconfig | 30 - configs/TTTech_defconfig | 24 - configs/wtk_defconfig | 24 - doc/README.LED | 1 - doc/README.MPC866 | 24 - doc/README.fsl-clk | 6 - doc/README.scrapyard | 1 - drivers/block/ide.c | 11 - drivers/block/sil680.c | 1 - drivers/bootcount/bootcount.c | 5 - drivers/i2c/i2c_core.c | 11 - drivers/i2c/soft_i2c.c | 3 - drivers/net/4xx_enet.c | 1 - drivers/pcmcia/Makefile | 2 - drivers/pcmcia/mpc8xx_pcmcia.c | 258 ------ drivers/pcmcia/tqm8xx_pcmcia.c | 254 ----- drivers/rtc/Makefile | 1 - drivers/rtc/mpc8xx.c | 60 -- drivers/usb/gadget/Makefile | 1 - drivers/usb/gadget/mpc8xx_udc.c | 1386 ---------------------------- drivers/video/Makefile | 1 - drivers/video/mpc8xx_lcd.c | 400 -------- examples/standalone/Makefile | 2 - examples/standalone/test_burst.c | 284 ------ examples/standalone/test_burst.h | 22 - examples/standalone/test_burst_lib.S | 154 ---- examples/standalone/timer.c | 333 ------- include/asm-generic/u-boot.h | 2 +- include/commproc.h | 849 ----------------- include/configs/CPCI4052.h | 1 - include/configs/MIP405.h | 1 - include/configs/PIP405.h | 1 - include/configs/PLU405.h | 1 - include/configs/TQM5200.h | 3 - include/configs/TQM823L.h | 435 --------- include/configs/TQM823M.h | 434 --------- include/configs/TQM850L.h | 428 --------- include/configs/TQM850M.h | 429 --------- include/configs/TQM855L.h | 434 --------- include/configs/TQM855M.h | 464 ---------- include/configs/TQM860L.h | 434 --------- include/configs/TQM860M.h | 438 --------- include/configs/TQM862L.h | 438 --------- include/configs/TQM862M.h | 439 --------- include/configs/TQM866M.h | 457 --------- include/configs/TQM885D.h | 451 --------- include/configs/a4m072.h | 4 - include/configs/aria.h | 2 - include/configs/inka4x0.h | 4 - include/configs/manroland/mpc5200-common.h | 3 - include/configs/mpc5121ads.h | 3 - include/configs/pcm030.h | 2 - include/configs/v38b.h | 2 - include/i2c.h | 22 - include/lcd.h | 4 +- include/mpc823_lcd.h | 44 - include/net.h | 4 - include/pcmcia.h | 30 +- include/post.h | 5 - include/ppc_asm.tmpl | 46 +- include/status_led.h | 11 +- include/usb/mpc8xx_udc.h | 178 ---- include/watchdog.h | 5 - post/Makefile | 1 - post/cpu/mpc8xx/Makefile | 9 - post/cpu/mpc8xx/cache.c | 62 -- post/cpu/mpc8xx/cache_8xx.S | 477 ---------- post/cpu/mpc8xx/ether.c | 532 ----------- post/cpu/mpc8xx/spr.c | 132 --- post/cpu/mpc8xx/uart.c | 510 ---------- post/cpu/mpc8xx/usb.c | 249 ----- post/cpu/mpc8xx/watchdog.c | 59 -- post/tests.c | 12 - scripts/config_whitelist.txt | 50 - 143 files changed, 45 insertions(+), 21631 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc8xx/Kconfig delete mode 100644 arch/powerpc/cpu/mpc8xx/Makefile delete mode 100644 arch/powerpc/cpu/mpc8xx/bedbug_860.c delete mode 100644 arch/powerpc/cpu/mpc8xx/config.mk delete mode 100644 arch/powerpc/cpu/mpc8xx/cpu.c delete mode 100644 arch/powerpc/cpu/mpc8xx/cpu_init.c delete mode 100644 arch/powerpc/cpu/mpc8xx/fdt.c delete mode 100644 arch/powerpc/cpu/mpc8xx/fec.c delete mode 100644 arch/powerpc/cpu/mpc8xx/fec.h delete mode 100644 arch/powerpc/cpu/mpc8xx/interrupts.c delete mode 100644 arch/powerpc/cpu/mpc8xx/kgdb.S delete mode 100644 arch/powerpc/cpu/mpc8xx/plprcr_write.S delete mode 100644 arch/powerpc/cpu/mpc8xx/scc.c delete mode 100644 arch/powerpc/cpu/mpc8xx/serial.c delete mode 100644 arch/powerpc/cpu/mpc8xx/speed.c delete mode 100644 arch/powerpc/cpu/mpc8xx/spi.c delete mode 100644 arch/powerpc/cpu/mpc8xx/start.S delete mode 100644 arch/powerpc/cpu/mpc8xx/traps.c delete mode 100644 arch/powerpc/cpu/mpc8xx/upatch.c delete mode 100644 arch/powerpc/cpu/mpc8xx/video.c delete mode 100644 arch/powerpc/include/asm/8xx_immap.h delete mode 100644 arch/powerpc/include/asm/iopin_8xx.h delete mode 100644 arch/powerpc/lib/ide.c delete mode 100644 arch/powerpc/lib/ide.h delete mode 100644 board/tqc/tqm8xx/Kconfig delete mode 100644 board/tqc/tqm8xx/MAINTAINERS delete mode 100644 board/tqc/tqm8xx/Makefile delete mode 100644 board/tqc/tqm8xx/load_sernum_ethaddr.c delete mode 100644 board/tqc/tqm8xx/tqm8xx.c delete mode 100644 board/tqc/tqm8xx/u-boot.lds delete mode 100644 configs/TQM823L_LCD_defconfig delete mode 100644 configs/TQM823L_defconfig delete mode 100644 configs/TQM823M_defconfig delete mode 100644 configs/TQM850L_defconfig delete mode 100644 configs/TQM850M_defconfig delete mode 100644 configs/TQM855L_defconfig delete mode 100644 configs/TQM855M_defconfig delete mode 100644 configs/TQM860L_defconfig delete mode 100644 configs/TQM860M_defconfig delete mode 100644 configs/TQM862L_defconfig delete mode 100644 configs/TQM862M_defconfig delete mode 100644 configs/TQM866M_defconfig delete mode 100644 configs/TQM885D_defconfig delete mode 100644 configs/TTTech_defconfig delete mode 100644 configs/wtk_defconfig delete mode 100644 doc/README.MPC866 delete mode 100644 doc/README.fsl-clk delete mode 100644 drivers/pcmcia/mpc8xx_pcmcia.c delete mode 100644 drivers/pcmcia/tqm8xx_pcmcia.c delete mode 100644 drivers/rtc/mpc8xx.c delete mode 100644 drivers/usb/gadget/mpc8xx_udc.c delete mode 100644 drivers/video/mpc8xx_lcd.c delete mode 100644 examples/standalone/test_burst.c delete mode 100644 examples/standalone/test_burst.h delete mode 100644 examples/standalone/test_burst_lib.S delete mode 100644 examples/standalone/timer.c delete mode 100644 include/commproc.h delete mode 100644 include/configs/TQM823L.h delete mode 100644 include/configs/TQM823M.h delete mode 100644 include/configs/TQM850L.h delete mode 100644 include/configs/TQM850M.h delete mode 100644 include/configs/TQM855L.h delete mode 100644 include/configs/TQM855M.h delete mode 100644 include/configs/TQM860L.h delete mode 100644 include/configs/TQM860M.h delete mode 100644 include/configs/TQM862L.h delete mode 100644 include/configs/TQM862M.h delete mode 100644 include/configs/TQM866M.h delete mode 100644 include/configs/TQM885D.h delete mode 100644 include/mpc823_lcd.h delete mode 100644 include/usb/mpc8xx_udc.h delete mode 100644 post/cpu/mpc8xx/Makefile delete mode 100644 post/cpu/mpc8xx/cache.c delete mode 100644 post/cpu/mpc8xx/cache_8xx.S delete mode 100644 post/cpu/mpc8xx/ether.c delete mode 100644 post/cpu/mpc8xx/spr.c delete mode 100644 post/cpu/mpc8xx/uart.c delete mode 100644 post/cpu/mpc8xx/usb.c delete mode 100644 post/cpu/mpc8xx/watchdog.c

diff --git a/.travis.yml b/.travis.yml index d7094e3..8915284 100644 --- a/.travis.yml +++ b/.travis.yml @@ -218,8 +218,6 @@ matrix: - env: - BUILDMAN="mpc86xx" - env: - - BUILDMAN="mpc8xx" - - env: - BUILDMAN="siemens" - env: - BUILDMAN="tegra" diff --git a/README b/README index 075d919..6355c79 100644 --- a/README +++ b/README @@ -328,34 +328,6 @@ The following options need to be configured: multiple fs option at one time for marvell soc family

-- 8xx CPU Options: (if using an MPC8xx CPU) - CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if - get_gclk_freq() cannot work - e.g. if there is no 32KHz - reference PIT/RTC clock - CONFIG_8xx_OSCLK - PLL input clock (either EXTCLK - or XTAL/EXTAL) - -- 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU): - CONFIG_SYS_8xx_CPUCLK_MIN - CONFIG_SYS_8xx_CPUCLK_MAX - CONFIG_8xx_CPUCLK_DEFAULT - See doc/README.MPC866 - - CONFIG_SYS_MEASURE_CPUCLK - - Define this to measure the actual CPU clock instead - of relying on the correctness of the configured - values. Mostly useful for board bringup to make sure - the PLL is locked at the intended frequency. Note - that this requires a (stable) reference clock (32 kHz - RTC clock or CONFIG_SYS_8XX_XIN) - - CONFIG_SYS_DELAYED_ICACHE - - Define this option if you want to enable the - ICache only when Code runs from RAM. - - 85xx CPU Options: CONFIG_SYS_PPC64

@@ -723,26 +695,15 @@ The following options need to be configured: Define this variable to enable hw flow control in serial driver. Current user of this option is drivers/serial/nsl16550.c driver

-- Console Interface: - Depending on board, define exactly one serial port - (like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2, - CONFIG_8xx_CONS_SCC1, ...), or switch off the serial - console by defining CONFIG_8xx_CONS_NONE - - Note: if CONFIG_8xx_CONS_NONE is defined, the serial - port routines must be defined elsewhere - (i.e. serial_init(), serial_getc(), ...) - - Console Baudrate: CONFIG_BAUDRATE - in bps Select one of the baudrates listed in CONFIG_SYS_BAUDRATE_TABLE, see below. - CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale

- Console Rx buffer length With CONFIG_SYS_SMC_RXBUFLEN it is possible to define the maximum receive buffer length for the SMC. - This option is actual only for 82xx and 8xx possible. + This option is actual only for 82xx possible. If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE must be defined, to setup the maximum idle timeout for the SMC. @@ -912,7 +873,7 @@ The following options need to be configured: Note: Don't enable the "icache" and "dcache" commands (configuration option CONFIG_CMD_CACHE) unless you know what you (and your U-Boot users) are doing. Data - cache cannot be enabled on systems like the 8xx or + cache cannot be enabled on systems like the 8260 (where accesses to the IMMR region must be uncached), and it cannot be disabled on all other systems where we (mis-) use the data cache to hold an @@ -976,7 +937,7 @@ The following options need to be configured: CONFIG_WATCHDOG If this variable is defined, it enables watchdog support for the SoC. There must be support in the SoC - specific code for a watchdog. For the 8xx and 8260 + specific code for a watchdog. For the 8260 CPUs, the SIU Watchdog feature is enabled in the SYPCR register. When supported for a specific SoC is available, then no further board specific code should @@ -1004,7 +965,6 @@ The following options need to be configured: has to be selected, too. Define exactly one of the following options:

- CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC CONFIG_RTC_MC146818 - use MC146818 RTC @@ -1345,11 +1305,6 @@ The following options need to be configured: Define this if you want stdin, stdout &/or stderr to be set to usbtty.

- mpc8xx: - CONFIG_SYS_USB_EXTC_CLK 0xBLAH - Derive USB clock from external clock "blah" - - CONFIG_SYS_USB_EXTC_CLK 0x02 - If you have a USB-IF assigned VendorID then you may wish to define your own vendor specific values either in BoardName.h or directly in usbd_vendor_info.h. If you don't define @@ -1953,7 +1908,7 @@ The following options need to be configured:

Defining CONFIG_CAN_DRIVER enables CAN driver support on those systems that support this (optional) - feature, like the TQM8xxL modules. + feature.

- I2C Support: CONFIG_SYS_I2C

@@ -2445,7 +2400,7 @@ The following options need to be configured: following board configurations are known to be "pRAM-clean":

- IVMS8, IVML24, SPD8xx, TQM8xxL, + IVMS8, IVML24, SPD8xx, HERMES, IP860, RPXlite, LWMON, FLAGADM, TQM8260

@@ -4048,7 +4003,7 @@ Low Level (hardware related) configuration options:

- CONFIG_SYS_IMMR: Physical address of the Internal Memory. DO NOT CHANGE unless you know exactly what you're - doing! (11-4) [MPC8xx/82xx systems only] + doing! (11-4) [82xx systems only]

- CONFIG_SYS_INIT_RAM_ADDR:

@@ -4061,7 +4016,7 @@ Low Level (hardware related) configuration options: sequences.

U-Boot uses the following memory types: - - MPC8xx and MPC8260: IMMR (internal memory of the CPU) + - MPC8260: IMMR (internal memory of the CPU) - MPC824X: data cache - PPC4xx: data cache

@@ -4119,19 +4074,7 @@ Low Level (hardware related) configuration options: Machine Mode Register and Memory Periodic Timer Prescaler definitions (SDRAM timing)

-- CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]: - enable I2C microcode relocation patch (MPC8xx); - define relocation offset in DPRAM [DSP2] - -- CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]: - enable SMC microcode relocation patch (MPC8xx); - define relocation offset in DPRAM [SMC1] - -- CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]: - enable SPI microcode relocation patch (MPC8xx); - define relocation offset in DPRAM [SCC4] - -- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only) +- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8260 only) Offset of the bootmode word in DPRAM used by post (Power On Self Tests). This definition overrides #define'd default value in commproc.h resp. @@ -4225,21 +4168,6 @@ Low Level (hardware related) configuration options: Only for 83xx systems. If specified, then DDR should be configured using CS0 and CS1 instead of CS2 and CS3.

-- CONFIG_ETHER_ON_FEC[12] - Define to enable FEC[12] on a 8xx series processor. - -- CONFIG_FEC[12]_PHY - Define to the hardcoded PHY address which corresponds - to the given FEC; i. e. - #define CONFIG_FEC1_PHY 4 - means that the PHY with address 4 is connected to FEC1 - - When set to -1, means to probe for first available. - -- CONFIG_FEC[12]_PHY_NORXERR - The PHY does not have a RXERR line (RMII only). - (so program the FEC to ignore it). - - CONFIG_RMII Enable RMII mode for all FECs. Note that this is a global option, we can't diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c index f23f175..71fea5a 100644 --- a/api/api_platform-powerpc.c +++ b/api/api_platform-powerpc.c @@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si) si->clk_bus = gd->bus_clk; si->clk_cpu = gd->cpu_clk;

-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || \ +#if defined(CONFIG_5xx) || defined(CONFIG_MPC8260) || \ defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define bi_bar bi_immr_base #elif defined(CONFIG_MPC5xxx) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index f37a9cb..671d2cc 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -41,9 +41,6 @@ config MPC86xx select SYS_FSL_DDR select SYS_FSL_DDR_BE

-config 8xx - bool "MPC8xx" - config 4xx bool "PPC4xx" select CREATE_ARCH_SYMLINK @@ -60,7 +57,6 @@ source "arch/powerpc/cpu/mpc8260/Kconfig" source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc86xx/Kconfig" -source "arch/powerpc/cpu/mpc8xx/Kconfig" source "arch/powerpc/cpu/ppc4xx/Kconfig"

endmenu diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig deleted file mode 100644 index 79cee35..0000000 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ /dev/null @@ -1,51 +0,0 @@ -menu "mpc8xx CPU" - depends on 8xx - -config SYS_CPU - default "mpc8xx" - -choice - prompt "Target select" - optional - -config TARGET_TQM823L - bool "Support TQM823L" - -config TARGET_TQM823M - bool "Support TQM823M" - -config TARGET_TQM850L - bool "Support TQM850L" - -config TARGET_TQM850M - bool "Support TQM850M" - -config TARGET_TQM855L - bool "Support TQM855L" - -config TARGET_TQM855M - bool "Support TQM855M" - -config TARGET_TQM860L - bool "Support TQM860L" - -config TARGET_TQM860M - bool "Support TQM860M" - -config TARGET_TQM862L - bool "Support TQM862L" - -config TARGET_TQM862M - bool "Support TQM862M" - -config TARGET_TQM866M - bool "Support TQM866M" - -config TARGET_TQM885D - bool "Support TQM885D" - -endchoice - -source "board/tqc/tqm8xx/Kconfig" - -endmenu diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile deleted file mode 100644 index fc91a05..0000000 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# ccflags-y += -DET_DEBUG - -extra-y += start.o -extra-y += traps.o -obj-y += bedbug_860.o -obj-y += cpu.o -obj-y += cpu_init.o -obj-y += fec.o -obj-$(CONFIG_OF_LIBFDT) += fdt.o -obj-y += interrupts.o -obj-y += scc.o -obj-y += serial.o -obj-y += speed.o -obj-y += spi.o -obj-y += upatch.o -obj-y += video.o -obj-y += kgdb.o -obj-y += plprcr_write.o diff --git a/arch/powerpc/cpu/mpc8xx/bedbug_860.c b/arch/powerpc/cpu/mpc8xx/bedbug_860.c deleted file mode 100644 index c0016f7..0000000 --- a/arch/powerpc/cpu/mpc8xx/bedbug_860.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * Bedbug Functions specific to the MPC860 chip - */ - -#include <common.h> -#include <command.h> -#include <linux/ctype.h> -#include <bedbug/bedbug.h> -#include <bedbug/regs.h> -#include <bedbug/ppc.h> -#include <bedbug/type.h> - -#if defined(CONFIG_CMD_BEDBUG) && defined(CONFIG_8xx) - -#define MAX_BREAK_POINTS 2 - -extern CPU_DEBUG_CTX bug_ctx; - -void bedbug860_init __P((void)); -void bedbug860_do_break __P((cmd_tbl_t*,int,int,char*const[])); -void bedbug860_break_isr __P((struct pt_regs*)); -int bedbug860_find_empty __P((void)); -int bedbug860_set __P((int,unsigned long)); -int bedbug860_clear __P((int)); - - -/* ====================================================================== - * Initialize the global bug_ctx structure for the MPC860. Clear all - * of the breakpoints. - * ====================================================================== */ - -void bedbug860_init( void ) -{ - int i; - /* -------------------------------------------------- */ - - bug_ctx.hw_debug_enabled = 0; - bug_ctx.stopped = 0; - bug_ctx.current_bp = 0; - bug_ctx.regs = NULL; - - bug_ctx.do_break = bedbug860_do_break; - bug_ctx.break_isr = bedbug860_break_isr; - bug_ctx.find_empty = bedbug860_find_empty; - bug_ctx.set = bedbug860_set; - bug_ctx.clear = bedbug860_clear; - - for( i = 1; i <= MAX_BREAK_POINTS; ++i ) - (*bug_ctx.clear)( i ); - - puts ("BEDBUG:ready\n"); - return; -} /* bedbug_init_breakpoints */ - - - -/* ====================================================================== - * Set/clear/show one of the hardware breakpoints for the 860. The "off" - * string will disable a specific breakpoint. The "show" string will - * display the current breakpoints. Otherwise an address will set a - * breakpoint at that address. Setting a breakpoint uses the CPU-specific - * set routine which will assign a breakpoint number. - * ====================================================================== */ - -void bedbug860_do_break (cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - long addr = 0; /* Address to break at */ - int which_bp; /* Breakpoint number */ - /* -------------------------------------------------- */ - - if (argc < 2) { - cmd_usage(cmdtp); - return; - } - - /* Turn off a breakpoint */ - - if( strcmp( argv[ 1 ], "off" ) == 0 ) - { - if( bug_ctx.hw_debug_enabled == 0 ) - { - printf( "No breakpoints enabled\n" ); - return; - } - - which_bp = simple_strtoul( argv[ 2 ], NULL, 10 ); - - if( bug_ctx.clear ) - (*bug_ctx.clear)( which_bp ); - - printf( "Breakpoint %d removed\n", which_bp ); - return; - } - - /* Show a list of breakpoints */ - - if( strcmp( argv[ 1 ], "show" ) == 0 ) - { - for( which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp ) - { - - switch( which_bp ) - { - case 1: addr = GET_CMPA(); break; - case 2: addr = GET_CMPB(); break; - case 3: addr = GET_CMPC(); break; - case 4: addr = GET_CMPD(); break; - } - - printf( "Breakpoint [%d]: ", which_bp ); - if( addr == 0 ) - printf( "NOT SET\n" ); - else - disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); - } - return; - } - - /* Set a breakpoint at the address */ - - if( !isdigit( argv[ 1 ][ 0 ])) { - cmd_usage(cmdtp); - return; - } - - addr = simple_strtoul( argv[ 1 ], NULL, 16 ) & 0xfffffffc; - - if(( bug_ctx.set ) && ( which_bp = (*bug_ctx.set)( 0, addr )) > 0 ) - { - printf( "Breakpoint [%d]: ", which_bp ); - disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); - } - - return; -} /* bedbug860_do_break */ - - - -/* ====================================================================== - * Handle a breakpoint. First determine which breakpoint was hit by - * looking at the DeBug Status Register (DBSR), clear the breakpoint - * and enter a mini main loop. Stay in the loop until the stopped flag - * in the debug context is cleared. - * ====================================================================== */ - -void bedbug860_break_isr( struct pt_regs *regs ) -{ - unsigned long addr; /* Address stopped at */ - unsigned long cause; /* Address stopped at */ - /* -------------------------------------------------- */ - - cause = GET_ICR(); - - if( !(cause & 0x00000004)) { - printf( "Not an instruction breakpoint (ICR 0x%08lx)\n", cause ); - return; - } - - addr = regs->nip; - - if( addr == GET_CMPA() ) - { - bug_ctx.current_bp = 1; - } - else if( addr == GET_CMPB() ) - { - bug_ctx.current_bp = 2; - } - else if( addr == GET_CMPC() ) - { - bug_ctx.current_bp = 3; - } - else if( addr == GET_CMPD() ) - { - bug_ctx.current_bp = 4; - } - - bedbug_main_loop( addr, regs ); - return; -} /* bedbug860_break_isr */ - - - -/* ====================================================================== - * Look through all of the hardware breakpoints available to see if one - * is unused. - * ====================================================================== */ - -int bedbug860_find_empty( void ) -{ - /* -------------------------------------------------- */ - - if( GET_CMPA() == 0 ) - return 1; - - if( GET_CMPB() == 0 ) - return 2; - - if( GET_CMPC() == 0 ) - return 3; - - if( GET_CMPD() == 0 ) - return 4; - - return 0; -} /* bedbug860_find_empty */ - - - -/* ====================================================================== - * Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint - * number, otherwise reassign the given breakpoint. If hardware debugging - * is not enabled, then turn it on via the MSR and DBCR0. Set the break - * address in the appropriate IACx register and enable proper address - * beakpoint in DBCR0. - * ====================================================================== */ - -int bedbug860_set( int which_bp, unsigned long addr ) -{ - /* -------------------------------------------------- */ - - /* Only look if which_bp == 0, else use which_bp */ - if(( bug_ctx.find_empty ) && ( !which_bp ) && - ( which_bp = (*bug_ctx.find_empty)()) == 0 ) - { - printf( "All breakpoints in use\n" ); - return 0; - } - - if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) - { - printf( "Invalid break point # %d\n", which_bp ); - return 0; - } - - if( ! bug_ctx.hw_debug_enabled ) - { - bug_ctx.hw_debug_enabled = 1; - SET_DER( GET_DER() | 0x00000004 ); - } - - switch( which_bp ) - { - case 1: - SET_CMPA( addr ); - SET_ICTRL( GET_ICTRL() | 0x80080800 ); /* CTA=Equal,IW0=Match A,SIW0EN */ - break; - - case 2: - SET_CMPB( addr ); - SET_ICTRL( GET_ICTRL() | 0x10020400 ); /* CTB=Equal,IW1=Match B,SIW1EN */ - break; - - case 3: - SET_CMPC( addr ); - SET_ICTRL( GET_ICTRL() | 0x02008200 ); /* CTC=Equal,IW2=Match C,SIW2EN */ - break; - - case 4: - SET_CMPD( addr ); - SET_ICTRL( GET_ICTRL() | 0x00404100 ); /* CTD=Equal,IW3=Match D,SIW3EN */ - break; - } - - return which_bp; -} /* bedbug860_set */ - - - -/* ====================================================================== - * Disable a specific breakoint by setting the appropriate IACx register - * to zero and claring the instruction address breakpoint in DBCR0. - * ====================================================================== */ - -int bedbug860_clear( int which_bp ) -{ - /* -------------------------------------------------- */ - - if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) - { - printf( "Invalid break point # (%d)\n", which_bp ); - return -1; - } - - switch( which_bp ) - { - case 1: - SET_CMPA( 0 ); - SET_ICTRL( GET_ICTRL() & ~0x80080800 ); /* CTA=Equal,IW0=Match A,SIW0EN */ - break; - - case 2: - SET_CMPB( 0 ); - SET_ICTRL( GET_ICTRL() & ~0x10020400 ); /* CTB=Equal,IW1=Match B,SIW1EN */ - break; - - case 3: - SET_CMPC( 0 ); - SET_ICTRL( GET_ICTRL() & ~0x02008200 ); /* CTC=Equal,IW2=Match C,SIW2EN */ - break; - - case 4: - SET_CMPD( 0 ); - SET_ICTRL( GET_ICTRL() & ~0x00404100 ); /* CTD=Equal,IW3=Match D,SIW3EN */ - break; - } - - return 0; -} /* bedbug860_clear */ - - -/* ====================================================================== */ -#endif diff --git a/arch/powerpc/cpu/mpc8xx/config.mk b/arch/powerpc/cpu/mpc8xx/config.mk deleted file mode 100644 index 485e43d..0000000 --- a/arch/powerpc/cpu/mpc8xx/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mstring -mcpu=860 -msoft-float diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c deleted file mode 100644 index 105be9c..0000000 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ /dev/null @@ -1,580 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * m8xx.c - * - * CPU specific code - * - * written or collected and sometimes rewritten by - * Magnus Damm damm@bitsmart.com - * - * minor modifications by - * Wolfgang Denk wd@denx.de - */ - -#include <common.h> -#include <watchdog.h> -#include <command.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <netdev.h> -#include <asm/cache.h> -#include <linux/compiler.h> -#include <asm/io.h> - -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static char *cpu_warning = "\n " \ - "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***"; - -#if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \ - !defined(CONFIG_MPC862)) - -static int check_CPU (long clock, uint pvr, uint immr) -{ - char *id_str = -# if defined(CONFIG_MPC855) - "PC855"; -# elif defined(CONFIG_MPC860P) - "PC860P"; -# else - NULL; -# endif - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint k, m; - char buf[32]; - char pre = 'X'; - char *mid = "xx"; - char *suf; - - /* the highest 16 bits should be 0x0050 for a 860 */ - - if ((pvr >> 16) != 0x0050) - return -1; - - k = (immr << 16) | - immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]; - m = 0; - suf = ""; - - /* - * Some boards use sockets so different CPUs can be used. - * We have to check chip version in run time. - */ - switch (k) { - case 0x00020001: pre = 'P'; break; - case 0x00030001: break; - case 0x00120003: suf = "A"; break; - case 0x00130003: suf = "A3"; break; - - case 0x00200004: suf = "B"; break; - - case 0x00300004: suf = "C"; break; - case 0x00310004: suf = "C1"; m = 1; break; - - case 0x00200064: mid = "SR"; suf = "B"; break; - case 0x00300065: mid = "SR"; suf = "C"; break; - case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break; - case 0x05010000: suf = "D3"; m = 1; break; - case 0x05020000: suf = "D4"; m = 1; break; - /* this value is not documented anywhere */ - case 0x40000000: pre = 'P'; suf = "D"; m = 1; break; - /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */ - case 0x08010004: /* Rev. A.0 */ - suf = "A"; - /* fall through */ - case 0x08000003: /* Rev. 0.3 */ - pre = 'M'; m = 1; - if (id_str == NULL) - id_str = -# if defined(CONFIG_MPC859T) - "PC859T"; -# else - "PC866x"; /* Unknown chip from MPC866 family */ -# endif - break; - case 0x09000000: pre = 'M'; mid = suf = ""; m = 1; - if (id_str == NULL) - id_str = "PC885"; /* 870/875/880/885 */ - break; - - default: suf = NULL; break; - } - - if (id_str == NULL) - id_str = "PC86x"; /* Unknown 86x chip */ - if (suf) - printf ("%c%s%sZPnn%s", pre, id_str, mid, suf); - else - printf ("unknown M%s (0x%08x)", id_str, k); - - -#if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX) - printf (" at %s MHz [%d.%d...%d.%d MHz]\n ", - strmhz (buf, clock), - CONFIG_SYS_8xx_CPUCLK_MIN / 1000000, - ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000, - CONFIG_SYS_8xx_CPUCLK_MAX / 1000000, - ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000 - ); -#else - printf (" at %s MHz: ", strmhz (buf, clock)); -#endif - print_size(checkicache(), " I-Cache "); - print_size(checkdcache(), " D-Cache"); - - /* do we have a FEC (860T/P or 852/859/866/885)? */ - - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { - printf (" FEC present"); - } - - if (!m) { - puts (cpu_warning); - } - - putc ('\n'); - -#ifdef DEBUG - if(clock != measure_gclk()) { - printf ("clock %ldHz != %dHz\n", clock, measure_gclk()); - } -#endif - - return 0; -} - -#elif defined(CONFIG_MPC862) - -static int check_CPU (long clock, uint pvr, uint immr) -{ - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint k, m; - char buf[32]; - char pre = 'X'; - __maybe_unused char *mid = "xx"; - char *suf; - - /* the highest 16 bits should be 0x0050 for a 8xx */ - - if ((pvr >> 16) != 0x0050) - return -1; - - k = (immr << 16) | - immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]; - m = 0; - - switch (k) { - - /* this value is not documented anywhere */ - case 0x06000000: mid = "P"; suf = "0"; break; - case 0x06010001: mid = "P"; suf = "A"; m = 1; break; - case 0x07000003: mid = "P"; suf = "B"; m = 1; break; - default: suf = NULL; break; - } - -#ifndef CONFIG_MPC857 - if (suf) - printf ("%cPC862%sZPnn%s", pre, mid, suf); - else - printf ("unknown MPC862 (0x%08x)", k); -#else - if (suf) - printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */ - else - printf ("unknown MPC857 (0x%08x)", k); -#endif - - printf(" at %s MHz: ", strmhz(buf, clock)); - - print_size(checkicache(), " I-Cache "); - print_size(checkdcache(), " D-Cache"); - - /* lets check and see if we're running on a 862T (or P?) */ - - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { - printf (" FEC present"); - } - - if (!m) { - puts (cpu_warning); - } - - putc ('\n'); - - return 0; -} - -#elif defined(CONFIG_MPC823) - -static int check_CPU (long clock, uint pvr, uint immr) -{ - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint k, m; - char buf[32]; - char *suf; - - /* the highest 16 bits should be 0x0050 for a 8xx */ - - if ((pvr >> 16) != 0x0050) - return -1; - - k = (immr << 16) | - in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]); - m = 0; - - switch (k) { - /* MPC823 */ - case 0x20000000: suf = "0"; break; - case 0x20010000: suf = "0.1"; break; - case 0x20020000: suf = "Z2/3"; break; - case 0x20020001: suf = "Z3"; break; - case 0x21000000: suf = "A"; break; - case 0x21010000: suf = "B"; m = 1; break; - case 0x21010001: suf = "B2"; m = 1; break; - /* MPC823E */ - case 0x24010000: suf = NULL; - puts ("PPC823EZTnnB2"); - m = 1; - break; - default: - suf = NULL; - printf ("unknown MPC823 (0x%08x)", k); - break; - } - if (suf) - printf ("PPC823ZTnn%s", suf); - - printf(" at %s MHz: ", strmhz(buf, clock)); - - print_size(checkicache(), " I-Cache "); - print_size(checkdcache(), " D-Cache"); - - /* lets check and see if we're running on a 860T (or P?) */ - - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { - puts (" FEC present"); - } - - if (!m) { - puts (cpu_warning); - } - - putc ('\n'); - - return 0; -} - -#elif defined(CONFIG_MPC850) - -static int check_CPU (long clock, uint pvr, uint immr) -{ - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint k, m; - char buf[32]; - - /* the highest 16 bits should be 0x0050 for a 8xx */ - - if ((pvr >> 16) != 0x0050) - return -1; - - k = (immr << 16) | - immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]; - m = 0; - - switch (k) { - case 0x20020001: - printf ("XPC850xxZT"); - break; - case 0x21000065: - printf ("XPC850xxZTA"); - break; - case 0x21010067: - printf ("XPC850xxZTB"); - m = 1; - break; - case 0x21020068: - printf ("XPC850xxZTC"); - m = 1; - break; - default: - printf ("unknown MPC850 (0x%08x)", k); - } - printf(" at %s MHz: ", strmhz(buf, clock)); - - print_size(checkicache(), " I-Cache "); - print_size(checkdcache(), " D-Cache"); - - /* lets check and see if we're running on a 850T (or P?) */ - - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { - printf (" FEC present"); - } - - if (!m) { - puts (cpu_warning); - } - - putc ('\n'); - - return 0; -} -#else -#error CPU undefined -#endif -/* ------------------------------------------------------------------------- */ - -int checkcpu (void) -{ - ulong clock = gd->cpu_clk; - uint immr = get_immr (0); /* Return full IMMR contents */ - uint pvr = get_pvr (); - - puts ("CPU: "); - - /* 850 has PARTNUM 20 */ - /* 801 has PARTNUM 10 */ - return check_CPU (clock, pvr, immr); -} - -/* ------------------------------------------------------------------------- */ -/* L1 i-cache */ -/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ -/* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */ - -int checkicache (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - u32 cacheon = rd_ic_cst () & IDC_ENABLED; - -#ifdef CONFIG_IP86x - u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ -#else - u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ -#endif - u32 m; - u32 lines = -1; - - wr_ic_cst (IDC_UNALL); - wr_ic_cst (IDC_INVALL); - wr_ic_cst (IDC_DISABLE); - __asm__ volatile ("isync"); - - while (!((m = rd_ic_cst ()) & IDC_CERR2)) { - wr_ic_adr (k); - wr_ic_cst (IDC_LDLCK); - __asm__ volatile ("isync"); - - lines++; - k += 0x10; /* the number of bytes in a cacheline */ - } - - wr_ic_cst (IDC_UNALL); - wr_ic_cst (IDC_INVALL); - - if (cacheon) - wr_ic_cst (IDC_ENABLE); - else - wr_ic_cst (IDC_DISABLE); - - __asm__ volatile ("isync"); - - return lines << 4; -}; - -/* ------------------------------------------------------------------------- */ -/* L1 d-cache */ -/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ -/* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */ -/* call with cache disabled */ - -int checkdcache (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - u32 cacheon = rd_dc_cst () & IDC_ENABLED; - -#ifdef CONFIG_IP86x - u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ -#else - u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ -#endif - u32 m; - u32 lines = -1; - - wr_dc_cst (IDC_UNALL); - wr_dc_cst (IDC_INVALL); - wr_dc_cst (IDC_DISABLE); - - while (!((m = rd_dc_cst ()) & IDC_CERR2)) { - wr_dc_adr (k); - wr_dc_cst (IDC_LDLCK); - lines++; - k += 0x10; /* the number of bytes in a cacheline */ - } - - wr_dc_cst (IDC_UNALL); - wr_dc_cst (IDC_INVALL); - - if (cacheon) - wr_dc_cst (IDC_ENABLE); - else - wr_dc_cst (IDC_DISABLE); - - return lines << 4; -}; - -/* ------------------------------------------------------------------------- */ - -void upmconfig (uint upm, uint * table, uint size) -{ - uint i; - uint addr = 0; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - for (i = 0; i < size; i++) { - memctl->memc_mdr = table[i]; /* (16-15) */ - memctl->memc_mcr = addr | upm; /* (16-16) */ - addr++; - } -} - -/* ------------------------------------------------------------------------- */ - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong msr, addr; - - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */ - - /* Interrupts and MMU off */ - __asm__ volatile ("mtspr 81, 0"); - __asm__ volatile ("mfmsr %0":"=r" (msr)); - - msr &= ~0x1030; - __asm__ volatile ("mtmsr %0"::"r" (msr)); - - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE - * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. - * "(ulong)-1" used to be a good choice for many systems... - */ - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*)(void)) addr) (); - return 1; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * - * See sections 14.2 and 14.6 of the User's Manual - */ -unsigned long get_tbclk (void) -{ - uint immr = get_immr (0); /* Return full IMMR contents */ - volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000); - ulong oscclk, factor, pll; - - if (immap->im_clkrst.car_sccr & SCCR_TBS) { - return (gd->cpu_clk / 16); - } - - pll = immap->im_clkrst.car_plprcr; - -#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) - - /* - * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication - * factor is calculated as follows: - * - * MFN - * MFI + ------- - * MFD + 1 - * factor = ----------------- - * (PDF + 1) * 2^S - * - * For older chips, it's just MF field of PLPRCR plus one. - */ - if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ - factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/ - (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S)); - } else { - factor = PLPRCR_val(MF)+1; - } - - oscclk = gd->cpu_clk / factor; - - if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { - return (oscclk / 4); - } - return (oscclk / 16); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) -{ - int re_enable = disable_interrupts (); - - reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); - if (re_enable) - enable_interrupts (); -} -#endif /* CONFIG_WATCHDOG */ - -#if defined(CONFIG_WATCHDOG) - -void reset_8xx_watchdog (volatile immap_t * immr) -{ - /* - * All other boards use the MPC8xx Internal Watchdog - */ - immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */ - immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ -} -#endif /* CONFIG_WATCHDOG */ - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(bd_t *bis) -{ -#if defined(SCC_ENET) && defined(CONFIG_CMD_NET) - scc_initialize(bis); -#endif -#if defined(FEC_ENET) - fec_initialize(bis); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c deleted file mode 100644 index f621d62..0000000 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <watchdog.h> - -#include <mpc8xx.h> -#include <commproc.h> - -#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS) -DECLARE_GLOBAL_DATA_PTR; -#endif - -#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ - defined(CONFIG_SYS_SMC_UCODE_PATCH) -void cpm_load_patch (volatile immap_t * immr); -#endif - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f (volatile immap_t * immr) -{ - volatile memctl8xx_t *memctl = &immr->im_memctl; -# ifdef CONFIG_SYS_PLPRCR - ulong mfmask; -# endif - ulong reg; - - /* SYPCR - contains watchdog control (11-9) */ - - immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR; - -#if defined(CONFIG_WATCHDOG) - reset_8xx_watchdog (immr); -#endif /* CONFIG_WATCHDOG */ - - /* SIUMCR - contains debug pin configuration (11-6) */ - immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; - /* initialize timebase status and control register (11-26) */ - /* unlock TBSCRK */ - - immr->im_sitk.sitk_tbscrk = KAPWR_KEY; - immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR; - - /* initialize the PIT (11-31) */ - - immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; - - /* System integration timers. Don't change EBDF! (15-27) */ - - immr->im_clkrstk.cark_sccrk = KAPWR_KEY; - reg = immr->im_clkrst.car_sccr; - reg &= SCCR_MASK; - reg |= CONFIG_SYS_SCCR; - immr->im_clkrst.car_sccr = reg; - - /* PLL (CPU clock) settings (15-30) */ - - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - - /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to - * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, - * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF - * field value. - * - * For newer (starting MPC866) chips PLPRCR layout is different. - */ -#ifdef CONFIG_SYS_PLPRCR - if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK) - mfmask = PLPRCR_MFACT_MSK; - else - mfmask = PLPRCR_MF_MSK; - - if ((CONFIG_SYS_PLPRCR & mfmask) != 0) - reg = CONFIG_SYS_PLPRCR; /* reset control bits */ - else { - reg = immr->im_clkrst.car_plprcr; - reg &= mfmask; /* isolate MF-related fields */ - reg |= CONFIG_SYS_PLPRCR; /* reset control bits */ - } - immr->im_clkrst.car_plprcr = reg; -#endif - - /* - * Memory Controller: - */ - - /* perform BR0 reset that MPC850 Rev. A can't guarantee */ - reg = memctl->memc_br0; - reg &= BR_PS_MSK; /* Clear everything except Port Size bits */ - reg |= BR_V; /* then add just the "Bank Valid" bit */ - memctl->memc_br0 = reg; - - /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at - * preliminary addresses - these have to be modified later - * when FLASH size has been determined - * - * Depending on the size of the memory region defined by - * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the - * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't - * map CONFIG_SYS_MONITOR_BASE. - * - * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is - * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000. - * - * If BR0 wasn't loaded with address base 0xff000000, then BR0's - * base address remains as 0x00000000. However, the address mask - * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped - * into the Bank0. - * - * This is why CONFIG_IVMS8 and similar boards must load BR0 with - * CONFIG_SYS_BR0_PRELIM in advance. - * - * [Thanks to Michael Liao for this explanation. - * I owe him a free beer. - wd] - */ - -#if defined(CONFIG_SYS_OR0_REMAP) - memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; -#endif -#if defined(CONFIG_SYS_OR1_REMAP) - memctl->memc_or1 = CONFIG_SYS_OR1_REMAP; -#endif -#if defined(CONFIG_SYS_OR5_REMAP) - memctl->memc_or5 = CONFIG_SYS_OR5_REMAP; -#endif - - /* now restrict to preliminary range */ - memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; - memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; - -#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) - memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; - memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) - memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM; - memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) - memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM; - memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; -#endif - - /* - * Reset CPM - */ - immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG; - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - -#ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */ - /* write config value */ - immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; -#endif - -#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ - defined(CONFIG_SYS_SMC_UCODE_PATCH) - cpm_load_patch (immr); /* load mpc8xx microcode patch */ -#endif -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r (void) -{ -#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS) - bd_t *bd = gd->bd; - volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base); -#endif - -#ifdef CONFIG_SYS_RTCSC - /* Unlock RTSC register */ - immr->im_sitk.sitk_rtcsck = KAPWR_KEY; - /* write config value */ - immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC; -#endif - -#ifdef CONFIG_SYS_RMDS - /* write config value */ - immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS; -#endif - return (0); -} diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c deleted file mode 100644 index 34d3647..0000000 --- a/arch/powerpc/cpu/mpc8xx/fdt.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2008 (C) Bryan O'Donoghue - * - * Code copied & edited from Freescale mpc85xx stuff. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <libfdt.h> -#include <fdt_support.h> - -DECLARE_GLOBAL_DATA_PTR; - -void ft_cpu_setup(void *blob, bd_t *bd) -{ - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", get_tbclk(), 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); - do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", - gd->arch.brg_clk, 1); - - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -} diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c deleted file mode 100644 index b27310f..0000000 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ /dev/null @@ -1,933 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <commproc.h> -#include <malloc.h> -#include <net.h> - -#include <phy.h> - -DECLARE_GLOBAL_DATA_PTR; - -#undef ET_DEBUG - -#if defined(CONFIG_CMD_NET) && \ - (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)) - -/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */ -#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2) -#define CONFIG_ETHER_ON_FEC1 1 -#endif - -/* define WANT_MII when MII support is required */ -#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY) -#define WANT_MII -#else -#undef WANT_MII -#endif - -#if defined(WANT_MII) -#include <miiphy.h> - -#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) -#error "CONFIG_MII has to be defined!" -#endif - -#endif - -#if defined(CONFIG_RMII) && !defined(WANT_MII) -#error RMII support is unusable without a working PHY. -#endif - -#ifdef CONFIG_SYS_DISCOVER_PHY -static int mii_discover_phy(struct eth_device *dev); -#endif - -int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg); -int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, - u16 value); - -static struct ether_fcc_info_s -{ - int ether_index; - int fecp_offset; - int phy_addr; - int actual_phy_addr; - int initialized; -} - ether_fcc_info[] = { -#if defined(CONFIG_ETHER_ON_FEC1) - { - 0, - offsetof(immap_t, im_cpm.cp_fec1), -#if defined(CONFIG_FEC1_PHY) - CONFIG_FEC1_PHY, -#else - -1, /* discover */ -#endif - -1, - 0, - - }, -#endif -#if defined(CONFIG_ETHER_ON_FEC2) - { - 1, - offsetof(immap_t, im_cpm.cp_fec2), -#if defined(CONFIG_FEC2_PHY) - CONFIG_FEC2_PHY, -#else - -1, -#endif - -1, - 0, - }, -#endif -}; - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 100 - -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 -#define PKT_MAXBLR_SIZE 1520 - -#ifdef __GNUC__ -static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8))); -#else -#error txbuf must be aligned. -#endif - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FEC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx = NULL; - -static int fec_send(struct eth_device *dev, void *packet, int length); -static int fec_recv(struct eth_device* dev); -static int fec_init(struct eth_device* dev, bd_t * bd); -static void fec_halt(struct eth_device* dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -static void __mii_init(void); -#endif - -int fec_initialize(bd_t *bis) -{ - struct eth_device* dev; - struct ether_fcc_info_s *efis; - int i; - - for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) { - - dev = malloc(sizeof(*dev)); - if (dev == NULL) - hang(); - - memset(dev, 0, sizeof(*dev)); - - /* for FEC1 make sure that the name of the interface is the same - as the old one for compatibility reasons */ - if (i == 0) { - strcpy(dev->name, "FEC"); - } else { - sprintf (dev->name, "FEC%d", - ether_fcc_info[i].ether_index + 1); - } - - efis = &ether_fcc_info[i]; - - /* - * reset actual phy addr - */ - efis->actual_phy_addr = -1; - - dev->priv = efis; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; - - eth_register(dev); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = fec8xx_miiphy_read; - mdiodev->write = fec8xx_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - } - return 1; -} - -static int fec_send(struct eth_device *dev, void *packet, int length) -{ - int j, rc; - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); - - /* section 16.9.23.3 - * Wait for ready - */ - j = 0; - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { - udelay(1); - j++; - } - if (j>=TOUT_LOOP) { - printf("TX not ready\n"); - } - - rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST; - __asm__ ("eieio"); - - /* Activate transmit Buffer Descriptor polling */ - fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */ - - j = 0; - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { - udelay(1); - j++; - } - if (j>=TOUT_LOOP) { - printf("TX timeout\n"); - } -#ifdef ET_DEBUG - printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", - __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc, - (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2); -#endif - /* return only status bits */; - rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS); - - txIdx = (txIdx + 1) % TX_BUF_CNT; - - return rc; -} - -static int fec_recv (struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = - (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset); - int length; - - for (;;) { - /* section 16.9.23.2 */ - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { -#ifdef ET_DEBUG - printf ("%s[%d] err: %x\n", - __FUNCTION__, __LINE__, - rtx->rxbd[rxIdx].cbd_sc); -#endif - } else { - uchar *rx = net_rx_packets[rxIdx]; - - length -= 4; - -#if defined(CONFIG_CMD_CDP) - if ((rx[0] & 1) != 0 && - memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 && - !is_cdp_packet((uchar *)rx)) - rx = NULL; -#endif - /* - * Pass the packet up to the protocol layers. - */ - if (rx != NULL) - net_process_received_packet(rx, length); - } - - /* Give the buffer back to the FEC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - - __asm__ ("eieio"); - - /* Try to fill Buffer Descriptors */ - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ - } - - return length; -} - -/************************************************************** - * - * FEC Ethernet Initialization Routine - * - *************************************************************/ - -#define FEC_ECNTRL_PINMUX 0x00000004 -#define FEC_ECNTRL_ETHER_EN 0x00000002 -#define FEC_ECNTRL_RESET 0x00000001 - -#define FEC_RCNTRL_BC_REJ 0x00000010 -#define FEC_RCNTRL_PROM 0x00000008 -#define FEC_RCNTRL_MII_MODE 0x00000004 -#define FEC_RCNTRL_DRT 0x00000002 -#define FEC_RCNTRL_LOOP 0x00000001 - -#define FEC_TCNTRL_FDEN 0x00000004 -#define FEC_TCNTRL_HBC 0x00000002 -#define FEC_TCNTRL_GTS 0x00000001 - -#define FEC_RESET_DELAY 50 - -#if defined(CONFIG_RMII) - -static inline void fec_10Mbps(struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - int fecidx = efis->ether_index; - uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; - - if ((unsigned int)fecidx >= 2) - hang(); - - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask; -} - -static inline void fec_100Mbps(struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - int fecidx = efis->ether_index; - uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; - - if ((unsigned int)fecidx >= 2) - hang(); - - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask; -} - -#endif - -static inline void fec_full_duplex(struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); - - fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT; - fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */ -} - -static inline void fec_half_duplex(struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); - - fecp->fec_r_cntrl |= FEC_RCNTRL_DRT; - fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */ -} - -static void fec_pin_init(int fecidx) -{ - bd_t *bd = gd->bd; - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* - * Set MII speed to 2.5 MHz or slightly below. - * - * According to the MPC860T (Rev. D) Fast ethernet controller user - * manual (6.2.14), - * the MII management interface clock must be less than or equal - * to 2.5 MHz. - * This MDC frequency is equal to system clock / (2 * MII_SPEED). - * Then MII_SPEED = system_clock / 2 * 2,5 MHz. - * - * All MII configuration is done via FEC1 registers: - */ - immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; - -#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) - /* use MDC for MII */ - immr->im_ioport.iop_pdpar |= 0x0080; - immr->im_ioport.iop_pddir &= ~0x0080; -#endif - - if (fecidx == 0) { -#if defined(CONFIG_ETHER_ON_FEC1) - -#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ - -#if !defined(CONFIG_RMII) - - immr->im_ioport.iop_papar |= 0xf830; - immr->im_ioport.iop_padir |= 0x0830; - immr->im_ioport.iop_padir &= ~0xf000; - - immr->im_cpm.cp_pbpar |= 0x00001001; - immr->im_cpm.cp_pbdir &= ~0x00001001; - - immr->im_ioport.iop_pcpar |= 0x000c; - immr->im_ioport.iop_pcdir &= ~0x000c; - - immr->im_cpm.cp_pepar |= 0x00000003; - immr->im_cpm.cp_pedir |= 0x00000003; - immr->im_cpm.cp_peso &= ~0x00000003; - - immr->im_cpm.cp_cptr &= ~0x00000100; - -#else - -#if !defined(CONFIG_FEC1_PHY_NORXERR) - immr->im_ioport.iop_papar |= 0x1000; - immr->im_ioport.iop_padir &= ~0x1000; -#endif - immr->im_ioport.iop_papar |= 0xe810; - immr->im_ioport.iop_padir |= 0x0810; - immr->im_ioport.iop_padir &= ~0xe000; - - immr->im_cpm.cp_pbpar |= 0x00000001; - immr->im_cpm.cp_pbdir &= ~0x00000001; - - immr->im_cpm.cp_cptr |= 0x00000100; - immr->im_cpm.cp_cptr &= ~0x00000050; - -#endif /* !CONFIG_RMII */ - -#else - /* - * Configure all of port D for MII. - */ - immr->im_ioport.iop_pdpar = 0x1fff; - - /* - * Bits moved from Rev. D onward - */ - if ((get_immr(0) & 0xffff) < 0x0501) - immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ - else - immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ -#endif - -#endif /* CONFIG_ETHER_ON_FEC1 */ - } else if (fecidx == 1) { - -#if defined(CONFIG_ETHER_ON_FEC2) - -#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ - -#if !defined(CONFIG_RMII) - immr->im_cpm.cp_pepar |= 0x0003fffc; - immr->im_cpm.cp_pedir |= 0x0003fffc; - immr->im_cpm.cp_peso &= ~0x000087fc; - immr->im_cpm.cp_peso |= 0x00037800; - - immr->im_cpm.cp_cptr &= ~0x00000080; -#else - -#if !defined(CONFIG_FEC2_PHY_NORXERR) - immr->im_cpm.cp_pepar |= 0x00000010; - immr->im_cpm.cp_pedir |= 0x00000010; - immr->im_cpm.cp_peso &= ~0x00000010; -#endif - immr->im_cpm.cp_pepar |= 0x00039620; - immr->im_cpm.cp_pedir |= 0x00039620; - immr->im_cpm.cp_peso |= 0x00031000; - immr->im_cpm.cp_peso &= ~0x00008620; - - immr->im_cpm.cp_cptr |= 0x00000080; - immr->im_cpm.cp_cptr &= ~0x00000028; -#endif /* CONFIG_RMII */ - -#endif /* CONFIG_MPC885_FAMILY */ - -#endif /* CONFIG_ETHER_ON_FEC2 */ - - } -} - -static int fec_reset(volatile fec_t *fecp) -{ - int i; - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) - return -1; - - return 0; -} - -static int fec_init (struct eth_device *dev, bd_t * bd) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile fec_t *fecp = - (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset); - int i; - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - /* the MII interface is connected to FEC1 - * so for the miiphy_xxx function to work we must - * call mii_init since fec_halt messes the thing up - */ - if (efis->ether_index != 0) - __mii_init(); -#endif - - if (fec_reset(fecp) < 0) - printf ("FEC_RESET_DELAY timeout\n"); - - /* We use strictly polling mode only - */ - fecp->fec_imask = 0; - - /* Clear any pending interrupt - */ - fecp->fec_ievent = 0xffc0; - - /* No need to set the IVEC register */ - - /* Set station address - */ -#define ea dev->enetaddr - fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); - fecp->fec_addr_high = (ea[4] << 8) | (ea[5]); -#undef ea - -#if defined(CONFIG_CMD_CDP) - /* - * Turn on multicast address hash table - */ - fecp->fec_hash_table_high = 0xffffffff; - fecp->fec_hash_table_low = 0xffffffff; -#else - /* Clear multicast address hash table - */ - fecp->fec_hash_table_high = 0; - fecp->fec_hash_table_low = 0; -#endif - - /* Set maximum receive buffer size. - */ - fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; - - /* Set maximum frame length - */ - fecp->fec_r_hash = PKT_MAXBUF_SIZE; - - /* - * Setup Buffers and Buffer Desriptors - */ - rxIdx = 0; - txIdx = 0; - - if (!rtx) - rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_FEC_BASE); - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; - } - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Last, Tx CRC - */ - for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); - } - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* Set receive and transmit descriptor base - */ - fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]); - fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]); - - /* Enable MII mode - */ -#if 0 /* Full duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; - fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; -#else /* Half duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; - fecp->fec_x_cntrl = 0; -#endif - - /* Enable big endian and don't care about SDMA FC. - */ - fecp->fec_fun_code = 0x78000000; - - /* - * Setup the pin configuration of the FEC - */ - fec_pin_init (efis->ether_index); - - rxIdx = 0; - txIdx = 0; - - /* - * Now enable the transmit and receive processing - */ - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; - - if (efis->phy_addr == -1) { -#ifdef CONFIG_SYS_DISCOVER_PHY - /* - * wait for the PHY to wake up after reset - */ - efis->actual_phy_addr = mii_discover_phy (dev); - - if (efis->actual_phy_addr == -1) { - printf ("Unable to discover phy!\n"); - return -1; - } -#else - efis->actual_phy_addr = -1; -#endif - } else { - efis->actual_phy_addr = efis->phy_addr; - } - -#if defined(CONFIG_MII) && defined(CONFIG_RMII) - /* - * adapt the RMII speed to the speed of the phy - */ - if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) { - fec_100Mbps (dev); - } else { - fec_10Mbps (dev); - } -#endif - -#if defined(CONFIG_MII) - /* - * adapt to the half/full speed settings - */ - if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) { - fec_full_duplex (dev); - } else { - fec_half_duplex (dev); - } -#endif - - /* And last, try to fill Rx Buffer Descriptors */ - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ - - efis->initialized = 1; - - return 0; -} - - -static void fec_halt(struct eth_device* dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); - int i; - - /* avoid halt if initialized; mii gets stuck otherwise */ - if (!efis->initialized) - return; - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) { - printf ("FEC_RESET_DELAY timeout\n"); - return; - } - - efis->initialized = 0; -} - -#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - -/* Make MII read/write commands for the FEC. -*/ - -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18) | \ - (VAL & 0xffff)) - -/* Interrupt events/masks. -*/ -#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ -#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ -#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ -#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ -#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ -#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ -#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ -#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ -#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ -#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ - -/* PHY identification - */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */ -#define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */ - -/* send command to phy using mii, wait for result */ -static uint -mii_send(uint mii_cmd) -{ - uint mii_reply; - volatile fec_t *ep; - int cnt; - - ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec); - - ep->fec_mii_data = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - cnt = 0; - while (!(ep->fec_ievent & FEC_ENET_MII)) { - if (++cnt > 1000) { - printf("mii_send STUCK!\n"); - break; - } - } - mii_reply = ep->fec_mii_data; /* result from phy */ - ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */ -#if 0 - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply); -#endif - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif - -#if defined(CONFIG_SYS_DISCOVER_PHY) -static int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - uint phyno; - int pass; - uint phytype; - int phyaddr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type ", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype |= mii_send(mk_mii_read(phyno, - MII_PHYSID1)) << 16; - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ",phyno,pass); - switch (phytype & 0xfffffff0) { - case PHY_ID_LXT970: - printf("LXT970\n"); - break; - case PHY_ID_LXT971: - printf("LXT971\n"); - break; - case PHY_ID_82555: - printf("82555\n"); - break; - case PHY_ID_QS6612: - printf("QS6612\n"); - break; - case PHY_ID_AMD79C784: - printf("AMD79C784\n"); - break; - case PHY_ID_LSI80225B: - printf("LSI L80225/B\n"); - break; - case PHY_ID_DM9161: - printf("Davicom DM9161\n"); - break; - case PHY_ID_KSM8995M: - printf("MICREL KS8995M\n"); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) { - printf("No PHY device found.\n"); - } - return phyaddr; -} -#endif /* CONFIG_SYS_DISCOVER_PHY */ - -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) - -/**************************************************************************** - * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -static void __mii_init(void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile fec_t *fecp = &(immr->im_cpm.cp_fec); - - if (fec_reset(fecp) < 0) - printf ("FEC_RESET_DELAY timeout\n"); - - /* We use strictly polling mode only - */ - fecp->fec_imask = 0; - - /* Clear any pending interrupt - */ - fecp->fec_ievent = 0xffc0; - - /* Now enable the transmit and receive processing - */ - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; -} - -void mii_init (void) -{ - int i; - - __mii_init(); - - /* Setup the pin configuration of the FEC(s) - */ - for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) - fec_pin_init(ether_fcc_info[i].ether_index); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) -{ - unsigned short value = 0; - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - value = rdreg; -#ifdef MII_DEBUG - printf ("0x%04x\n", value); -#endif - return value; -} - -int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, - u16 value) -{ -#ifdef MII_DEBUG - printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - (void)mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf ("0x%04x\n", value); -#endif - return 0; -} -#endif - -#endif diff --git a/arch/powerpc/cpu/mpc8xx/fec.h b/arch/powerpc/cpu/mpc8xx/fec.h deleted file mode 100644 index e025c3f..0000000 --- a/arch/powerpc/cpu/mpc8xx/fec.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FEC_H_ -#define _FEC_H_ - - -#endif /* _FEC_H_ */ diff --git a/arch/powerpc/cpu/mpc8xx/interrupts.c b/arch/powerpc/cpu/mpc8xx/interrupts.c deleted file mode 100644 index 482ceec..0000000 --- a/arch/powerpc/cpu/mpc8xx/interrupts.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <mpc8xx_irq.h> -#include <asm/processor.h> -#include <commproc.h> - -/************************************************************************/ - -/* - * CPM interrupt vector functions. - */ -struct interrupt_action { - interrupt_handler_t *handler; - void *arg; -}; - -static struct interrupt_action cpm_vecs[CPMVEC_NR]; -static struct interrupt_action irq_vecs[NR_IRQS]; - -static void cpm_interrupt_init (void); -static void cpm_interrupt (void *regs); - -/************************************************************************/ - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; - - /* disable all interrupts */ - immr->im_siu_conf.sc_simask = 0; - - /* Configure CPM interrupts */ - cpm_interrupt_init (); - - return (0); -} - -/************************************************************************/ - -/* - * Handle external interrupts - */ -void external_interrupt (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int irq; - ulong simask, newmask; - ulong vec, v_bit; - - /* - * read the SIVEC register and shift the bits down - * to get the irq number - */ - vec = immr->im_siu_conf.sc_sivec; - irq = vec >> 26; - v_bit = 0x80000000UL >> irq; - - /* - * Read Interrupt Mask Register and Mask Interrupts - */ - simask = immr->im_siu_conf.sc_simask; - newmask = simask & (~(0xFFFF0000 >> irq)); - immr->im_siu_conf.sc_simask = newmask; - - if (!(irq & 0x1)) { /* External Interrupt ? */ - ulong siel; - - /* - * Read Interrupt Edge/Level Register - */ - siel = immr->im_siu_conf.sc_siel; - - if (siel & v_bit) { /* edge triggered interrupt ? */ - /* - * Rewrite SIPEND Register to clear interrupt - */ - immr->im_siu_conf.sc_sipend = v_bit; - } - } - - if (irq_vecs[irq].handler != NULL) { - irq_vecs[irq].handler (irq_vecs[irq].arg); - } else { - printf ("\nBogus External Interrupt IRQ %d Vector %ld\n", - irq, vec); - /* turn off the bogus interrupt to avoid it from now */ - simask &= ~v_bit; - } - /* - * Re-Enable old Interrupt Mask - */ - immr->im_siu_conf.sc_simask = simask; -} - -/************************************************************************/ - -/* - * CPM interrupt handler - */ -static void cpm_interrupt (void *regs) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - uint vec; - - /* - * Get the vector by setting the ACK bit - * and then reading the register. - */ - immr->im_cpic.cpic_civr = 1; - vec = immr->im_cpic.cpic_civr; - vec >>= 11; - - if (cpm_vecs[vec].handler != NULL) { - (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg); - } else { - immr->im_cpic.cpic_cimr &= ~(1 << vec); - printf ("Masking bogus CPM interrupt vector 0x%x\n", vec); - } - /* - * After servicing the interrupt, - * we have to remove the status indicator. - */ - immr->im_cpic.cpic_cisr |= (1 << vec); -} - -/* - * The CPM can generate the error interrupt when there is a race - * condition between generating and masking interrupts. All we have - * to do is ACK it and return. This is a no-op function so we don't - * need any special tests in the interrupt handler. - */ -static void cpm_error_interrupt (void *dummy) -{ -} - -/************************************************************************/ -/* - * Install and free an interrupt handler - */ -void irq_install_handler (int vec, interrupt_handler_t * handler, - void *arg) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - if ((vec & CPMVEC_OFFSET) != 0) { - /* CPM interrupt */ - vec &= 0xffff; - if (cpm_vecs[vec].handler != NULL) { - printf ("CPM interrupt 0x%x replacing 0x%x\n", - (uint) handler, - (uint) cpm_vecs[vec].handler); - } - cpm_vecs[vec].handler = handler; - cpm_vecs[vec].arg = arg; - immr->im_cpic.cpic_cimr |= (1 << vec); -#if 0 - printf ("Install CPM interrupt for vector %d ==> %p\n", - vec, handler); -#endif - } else { - /* SIU interrupt */ - if (irq_vecs[vec].handler != NULL) { - printf ("SIU interrupt %d 0x%x replacing 0x%x\n", - vec, - (uint) handler, - (uint) cpm_vecs[vec].handler); - } - irq_vecs[vec].handler = handler; - irq_vecs[vec].arg = arg; - immr->im_siu_conf.sc_simask |= 1 << (31 - vec); -#if 0 - printf ("Install SIU interrupt for vector %d ==> %p\n", - vec, handler); -#endif - } -} - -void irq_free_handler (int vec) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - if ((vec & CPMVEC_OFFSET) != 0) { - /* CPM interrupt */ - vec &= 0xffff; -#if 0 - printf ("Free CPM interrupt for vector %d ==> %p\n", - vec, cpm_vecs[vec].handler); -#endif - immr->im_cpic.cpic_cimr &= ~(1 << vec); - cpm_vecs[vec].handler = NULL; - cpm_vecs[vec].arg = NULL; - } else { - /* SIU interrupt */ -#if 0 - printf ("Free CPM interrupt for vector %d ==> %p\n", - vec, cpm_vecs[vec].handler); -#endif - immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec)); - irq_vecs[vec].handler = NULL; - irq_vecs[vec].arg = NULL; - } -} - -/************************************************************************/ - -static void cpm_interrupt_init (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* - * Initialize the CPM interrupt controller. - */ - - immr->im_cpic.cpic_cicr = - (CICR_SCD_SCC4 | - CICR_SCC_SCC3 | - CICR_SCB_SCC2 | - CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK; - - immr->im_cpic.cpic_cimr = 0; - - /* - * Install the error handler. - */ - irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL); - - immr->im_cpic.cpic_cicr |= CICR_IEN; - - /* - * Install the cpm interrupt handler - */ - irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL); -} - -/************************************************************************/ - -/* - * timer_interrupt - gets called when the decrementer overflows, - * with interrupts disabled. - * Trivial implementation - no need to be really accurate. - */ -void timer_interrupt_cpu (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - -#if 0 - printf ("*** Timer Interrupt *** "); -#endif - /* Reset Timer Expired and Timers Interrupt Status */ - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - __asm__ ("nop"); - /* - Clear TEXPS (and TMIST on older chips). SPLSS (on older - chips) is cleared too. - - Bitwise OR is a read-modify-write operation so ALL bits - which are cleared by writing `1' would be cleared by - operations like - - immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS; - - The same can be achieved by simple writing of the PLPRCR - to itself. If a bit value should be preserved, read the - register, ZERO the bit and write, not OR, the result back. - */ - immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr; -} - -/************************************************************************/ diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S deleted file mode 100644 index 0ea1a06..0000000 --- a/arch/powerpc/cpu/mpc8xx/kgdb.S +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2000 Murray Jensen Murray.Jensen@cmst.csiro.au - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <command.h> -#include <mpc8xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#if defined(CONFIG_CMD_KGDB) - - /* - * cache flushing routines for kgdb - */ - - .globl kgdb_flush_cache_all -kgdb_flush_cache_all: - lis r3, IDC_INVALL@h - mtspr DC_CST, r3 - sync - lis r3, IDC_INVALL@h - mtspr IC_CST, r3 - SYNC - blr - - .globl kgdb_flush_cache_range -kgdb_flush_cache_range: - li r5,CONFIG_SYS_CACHELINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CONFIG_SYS_CACHELINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CONFIG_SYS_CACHELINE_SIZE - bdnz 2b - SYNC - blr - -#endif diff --git a/arch/powerpc/cpu/mpc8xx/plprcr_write.S b/arch/powerpc/cpu/mpc8xx/plprcr_write.S deleted file mode 100644 index e28292f..0000000 --- a/arch/powerpc/cpu/mpc8xx/plprcr_write.S +++ /dev/null @@ -1,119 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <mpc8xx.h> -#include <ppc_asm.tmpl> -#include <asm/cache.h> - -#define CACHE_CMD_ENABLE 0x02000000 -#define CACHE_CMD_DISABLE 0x04000000 -#define CACHE_CMD_LOAD_LOCK 0x06000000 -#define CACHE_CMD_UNLOCK_LINE 0x08000000 -#define CACHE_CMD_UNLOCK_ALL 0x0A000000 -#define CACHE_CMD_INVALIDATE 0x0C000000 -#define SPEED_PLPRCR_WAIT_5CYC 150 -#define _CACHE_ALIGN_SIZE 16 - - - .text - .align 2 - .globl plprcr_write_866 - -/* - * void plprcr_write_866 (long plprcr) - * Write PLPRCR, including workaround for device errata SIU4 and SIU9. - */ - -plprcr_write_866: - mfspr r10, LR /* save the Link Register value */ - - /* turn instruction cache on (no MMU required for instructions) - */ - lis r4, CACHE_CMD_ENABLE@h - ori r4, r4, CACHE_CMD_ENABLE@l - mtspr IC_CST, r4 - isync - - /* clear IC_CST error bits - */ - mfspr r4, IC_CST - - bl plprcr_here - -plprcr_here: - mflr r5 - - /* calculate relocation offset - */ - lis r4, plprcr_here@h - ori r4, r4, plprcr_here@l - sub r5, r5, r4 - - /* calculate first address of this function - */ - lis r6, plprcr_write_866@h - ori r6, r6, plprcr_write_866@l - add r6, r6, r5 - - /* calculate end address of this function - */ - lis r7, plprcr_end@h - ori r7, r7, plprcr_end@l - add r7, r7, r5 - - /* load and lock code addresses - */ - mr r5, r6 - -plprcr_loop: - mtspr IC_ADR, r5 - addi r5, r5, _CACHE_ALIGN_SIZE /* increment by one line */ - - lis r4, CACHE_CMD_LOAD_LOCK@h - ori r4, r4, CACHE_CMD_LOAD_LOCK@l - mtspr IC_CST, r4 - isync - - cmpw r5, r7 - blt plprcr_loop - - /* IC_CST error bits not evaluated - */ - - /* switch PLPRCR - */ - mfspr r4, IMMR /* read IMMR */ - rlwinm r4, r4, 0, 0, 15 /* only high 16 bits count */ - - /* write sequence according to MPC866 Errata - */ - stw r3, PLPRCR(r4) - isync - - lis r3, SPEED_PLPRCR_WAIT_5CYC@h - ori r3, r3, SPEED_PLPRCR_WAIT_5CYC@l - -plprcr_wait: - cmpwi r3, 0 - beq plprcr_wait_end - nop - subi r3, r3, 1 - b plprcr_wait - -plprcr_wait_end: - - /* unlock instruction cache but leave it enabled - */ - lis r4, CACHE_CMD_UNLOCK_ALL@h - ori r4, r4, CACHE_CMD_UNLOCK_ALL@l - mtspr IC_CST, r4 - isync - - mtspr LR, r10 /* restore original Link Register value */ - blr - -plprcr_end: diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c deleted file mode 100644 index 17bcc2f..0000000 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ /dev/null @@ -1,472 +0,0 @@ -/* - * File: scc.c - * Description: - * Basic ET HW initialization and packet RX/TX routines - * - * NOTE <<<IMPORTANT: PLEASE READ>>>: - * Do not cache Rx/Tx buffers! - */ - -/* - * MPC823 <-> MC68160 Connections: - * - * Setup MPC823 to work with MC68160 Enhanced Ethernet - * Serial Tranceiver as follows: - * - * MPC823 Signal MC68160 Comments - * ------ ------ ------- -------- - * PA-12 ETHTX --------> TX Eth. Port Transmit Data - * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable - * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock - * PA-13 ETHRX <-------- RX Eth. Port Receive Data - * PC-8 E_RENA <-------- RENA Eth. Receive Enable - * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock - * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication - * - * FADS Board Signal MC68160 Comments - * ----------------- ------- -------- - * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable - * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable - * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex - * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back - * - */ - -#include <common.h> -#include <malloc.h> -#include <commproc.h> -#include <net.h> -#include <command.h> - -#if defined(CONFIG_CMD_NET) && defined(SCC_ENET) - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 10000 /* 10 ms to have a packet sent */ - -static char txbuf[DBUF_LENGTH]; - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * SCC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx; - -static int scc_send(struct eth_device *dev, void *packet, int length); -static int scc_recv(struct eth_device* dev); -static int scc_init (struct eth_device* dev, bd_t * bd); -static void scc_halt(struct eth_device* dev); - -int scc_initialize(bd_t *bis) -{ - struct eth_device* dev; - - dev = (struct eth_device*) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - strcpy(dev->name, "SCC"); - dev->iobase = 0; - dev->priv = 0; - dev->init = scc_init; - dev->halt = scc_halt; - dev->send = scc_send; - dev->recv = scc_recv; - - eth_register(dev); - - return 1; -} - -static int scc_send(struct eth_device *dev, void *packet, int length) -{ - int i, j=0; -#if 0 - volatile char *in, *out; -#endif - - /* section 16.9.23.3 - * Wait for ready - */ -#if 0 - while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY); - out = (char *)(rtx->txbd[txIdx].cbd_bufaddr); - in = packet; - for(i = 0; i < length; i++) { - *out++ = *in++; - } - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST); - while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++; - -#ifdef ET_DEBUG - printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); -#endif - i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; - - /* wrap around buffer index when necessary */ - if (txIdx >= TX_BUF_CNT) txIdx = 0; -#endif - - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { - udelay (1); /* will also trigger Wd if needed */ - j++; - } - if (j>=TOUT_LOOP) printf("TX not ready\n"); - rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP); - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { - udelay (1); /* will also trigger Wd if needed */ - j++; - } - if (j>=TOUT_LOOP) printf("TX timeout\n"); -#ifdef ET_DEBUG - printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); -#endif - i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; - return i; -} - -static int scc_recv (struct eth_device *dev) -{ - int length; - - for (;;) { - /* section 16.9.23.2 */ - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { -#ifdef ET_DEBUG - printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); -#endif - } else { - /* Pass the packet up to the protocol layers. */ - net_process_received_packet(net_rx_packets[rxIdx], - length - 4); - } - - - /* Give the buffer back to the SCC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - -/************************************************************** - * - * SCC Ethernet Initialization Routine - * - *************************************************************/ - -static int scc_init (struct eth_device *dev, bd_t * bis) -{ - - int i; - scc_enet_t *pram_ptr; - - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]); - - rxIdx = 0; - txIdx = 0; - - if (!rtx) - rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_SCC_BASE); - -#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) - /* Configure port A pins for Txd and Rxd. - */ - immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_paodr &= ~PA_ENET_TXD; -#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) - /* Configure port B pins for Txd and Rxd. - */ - immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); - immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); - immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD; -#else -#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined -#endif - -#if defined(PC_ENET_LBK) - /* Configure port C pins to disable External Loopback - */ - immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK; - immr->im_ioport.iop_pcdir |= PC_ENET_LBK; - immr->im_ioport.iop_pcso &= ~PC_ENET_LBK; - immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ -#endif /* PC_ENET_LBK */ - - /* Configure port C pins to enable CLSN and RENA. - */ - immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); - - /* Configure port A for TCLK and RCLK. - */ - immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); - immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); - - /* - * Configure Serial Interface clock routing -- see section 16.7.5.3 - * First, clear all SCC bits to zero, then set the ones we want. - */ - - immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK; - immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT; - - - /* - * Initialize SDCR -- see section 16.9.23.7 - * SDMA configuration register - */ - immr->im_siu_conf.sc_sdcr = 0x01; - - - /* - * Setup SCC Ethernet Parameter RAM - */ - - pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */ - pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */ - - pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */ - - pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */ - pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */ - - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - - for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; - } - - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Add PADs to Short FRAMES, Wrap, Last, Tx CRC - */ - - for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = - (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); - } - - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* - * Enter Command: Initialize Rx Params for SCC - */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = - ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Ethernet Specific Parameter RAM - * see table 13-16, pg. 660, - * pg. 681 (example with suggested settings) - */ - - pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ - pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ - pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ - pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */ - pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ - pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ - - pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ - pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ - pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ - - pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ - pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ - - pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ - pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ - pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ - pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ - -#define ea eth_get_ethaddr() - pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - - pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ - pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ - pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ - pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ - pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ - pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ - pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ - pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ - - /* - * Enter Command: Initialize Tx Params for SCC - */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = - ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Mask all Events in SCCM - we use polling mode - */ - immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0; - - /* - * Clear Events in SCCE -- Clear bits by writing 1's - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0); - - - /* - * Initialize GSMR High 32-Bits - * Settings: Normal Mode - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0; - - /* - * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive - * Settings: - * TCI = Invert - * TPL = 48 bits - * TPP = Repeating 10's - * MODE = Ethernet - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI | - SCC_GSMRL_TPL_48 | - SCC_GSMRL_TPP_10 | - SCC_GSMRL_MODE_ENET); - - /* - * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4 - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555; - - /* - * Initialize the PSMR - * Settings: - * CRC = 32-Bit CCITT - * NIB = Begin searching for SFD 22 bits after RENA - * FDE = Full Duplex Enable - * LPB = Loopback Enable (Needed when FDE is set) - * BRO = Reject broadcast packets - * PROMISCOUS = Catch all packets regardless of dest. MAC adress - */ - immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC | - SCC_PSMR_NIB22 | -#if defined(CONFIG_SCC_ENET_FULL_DUPLEX) - SCC_PSMR_FDE | SCC_PSMR_LPB | -#endif -#if defined(CONFIG_SCC_ENET_NO_BROADCAST) - SCC_PSMR_BRO | -#endif -#if defined(CONFIG_SCC_ENET_PROMISCOUS) - SCC_PSMR_PRO | -#endif - 0; - - /* - * Configure Ethernet TENA Signal - */ - -#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA)) - immr->im_ioport.iop_pcpar |= PC_ENET_TENA; - immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA; -#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA)) - immr->im_cpm.cp_pbpar |= PB_ENET_TENA; - immr->im_cpm.cp_pbdir |= PB_ENET_TENA; -#else -#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined -#endif - - /* - * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= - (SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - return 1; -} - - -static void scc_halt (struct eth_device *dev) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= - ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA); -} - -#if 0 -void restart (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= - (SCC_GSMRL_ENR | SCC_GSMRL_ENT); -} -#endif -#endif diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c deleted file mode 100644 index b6e12d0..0000000 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ /dev/null @@ -1,676 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <commproc.h> -#include <command.h> -#include <serial.h> -#include <watchdog.h> -#include <linux/compiler.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */ - -#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */ -#define SMC_INDEX 0 -#define PROFF_SMC PROFF_SMC1 -#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 - -#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */ -#define SMC_INDEX 1 -#define PROFF_SMC PROFF_SMC2 -#define CPM_CR_CH_SMC CPM_CR_CH_SMC2 - -#endif /* CONFIG_8xx_CONS_SMCx */ - -#if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */ -#define SCC_INDEX 0 -#define PROFF_SCC PROFF_SCC1 -#define CPM_CR_CH_SCC CPM_CR_CH_SCC1 - -#elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */ -#define SCC_INDEX 1 -#define PROFF_SCC PROFF_SCC2 -#define CPM_CR_CH_SCC CPM_CR_CH_SCC2 - -#elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */ -#define SCC_INDEX 2 -#define PROFF_SCC PROFF_SCC3 -#define CPM_CR_CH_SCC CPM_CR_CH_SCC3 - -#elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */ -#define SCC_INDEX 3 -#define PROFF_SCC PROFF_SCC4 -#define CPM_CR_CH_SCC CPM_CR_CH_SCC4 - -#endif /* CONFIG_8xx_CONS_SCCx */ - -#if !defined(CONFIG_SYS_SMC_RXBUFLEN) -#define CONFIG_SYS_SMC_RXBUFLEN 1 -#define CONFIG_SYS_MAXIDLE 0 -#else -#if !defined(CONFIG_SYS_MAXIDLE) -#error "you must define CONFIG_SYS_MAXIDLE" -#endif -#endif - -typedef volatile struct serialbuffer { - cbd_t rxbd; /* Rx BD */ - cbd_t txbd; /* Tx BD */ - uint rxindex; /* index for next character to read */ - volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */ - volatile uchar txbuf; /* tx buffers */ -} serialbuffer_t; - -static void serial_setdivisor(volatile cpm8xx_t *cp) -{ - int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate; - - if(divisor/16>0x1000) { - /* bad divisor, assume 50MHz clock and 9600 baud */ - divisor=(50*1000*1000 + 8*9600)/16/9600; - } - -#ifdef CONFIG_SYS_BRGCLK_PRESCALE - divisor /= CONFIG_SYS_BRGCLK_PRESCALE; -#endif - - if(divisor<=0x1000) { - cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN; - } else { - cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16; - } -} - -#if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2)) - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -static void smc_setbrg (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG1 to SMCx - */ - - cp->cp_simode = 0x00000000; - - serial_setdivisor(cp); -} - -static int smc_init (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cpm8xx_t *cp = &(im->im_cpm); -#if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850)) - volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); -#endif - uint dpaddr; - volatile serialbuffer_t *rtx; - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); - up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; -#ifdef CONFIG_SYS_SMC_UCODE_PATCH - up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase]; -#else - /* Disable relocation */ - up->smc_rpbase = 0; -#endif - - /* Disable transmitter/receiver. */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* Enable SDMA. */ - im->im_siu_conf.sc_sdcr = 1; - - /* clear error conditions */ -#ifdef CONFIG_SYS_SDSR - im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; -#else - im->im_sdma.sdma_sdsr = 0x83; -#endif - - /* clear SDMA interrupt mask */ -#ifdef CONFIG_SYS_SDMR - im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; -#else - im->im_sdma.sdma_sdmr = 0x00; -#endif - -#if defined(CONFIG_8xx_CONS_SMC1) - /* Use Port B for SMC1 instead of other functions. */ - cp->cp_pbpar |= 0x000000c0; - cp->cp_pbdir &= ~0x000000c0; - cp->cp_pbodr &= ~0x000000c0; -#else /* CONFIG_8xx_CONS_SMC2 */ -# if defined(CONFIG_MPC823) || defined(CONFIG_MPC850) - /* Use Port A for SMC2 instead of other functions. */ - ip->iop_papar |= 0x00c0; - ip->iop_padir &= ~0x00c0; - ip->iop_paodr &= ~0x00c0; -# else /* must be a 860 then */ - /* Use Port B for SMC2 instead of other functions. - */ - cp->cp_pbpar |= 0x00000c00; - cp->cp_pbdir &= ~0x00000c00; - cp->cp_pbodr &= ~0x00000c00; -# endif -#endif - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - dpaddr = CPM_SERIAL_BASE; - - rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr]; - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - * damm: allocating space after the two buffers for rx/tx data - */ - - rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf; - rtx->rxbd.cbd_sc = 0; - - rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf; - rtx->txbd.cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; -#if defined (CONFIG_SYS_SMC_UCODE_PATCH) - up->smc_rbptr = up->smc_rbase; - up->smc_tbptr = up->smc_tbase; - up->smc_rstate = 0; - up->smc_tstate = 0; -#endif - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - -#ifdef CONFIG_SYS_SPC1920_SMC1_CLK4 - /* clock source is PLD */ - - /* set freq to 19200 Baud */ - *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3; - /* configure clk4 as input */ - im->im_ioport.iop_pdpar |= 0x800; - im->im_ioport.iop_pddir &= ~0x800; - - cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000); -#else - /* Set up the baud rate generator */ - smc_setbrg (); -#endif - - /* Make the first buffer the only buffer. */ - rtx->txbd.cbd_sc |= BD_SC_WRAP; - rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* single/multi character receive. */ - up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN; - up->smc_maxidl = CONFIG_SYS_MAXIDLE; - rtx->rxindex = 0; - - /* Initialize Tx/Rx parameters. */ - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - return (0); -} - -static void -smc_putc(const char c) -{ - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - volatile serialbuffer_t *rtx; - - if (c == '\n') - smc_putc ('\r'); - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; -#ifdef CONFIG_SYS_SMC_UCODE_PATCH - up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; -#endif - - rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for last character to go. */ - rtx->txbuf = c; - rtx->txbd.cbd_datlen = 1; - rtx->txbd.cbd_sc |= BD_SC_READY; - __asm__("eieio"); - - while (rtx->txbd.cbd_sc & BD_SC_READY) { - WATCHDOG_RESET (); - __asm__("eieio"); - } -} - -static void -smc_puts (const char *s) -{ - while (*s) { - smc_putc (*s++); - } -} - -static int -smc_getc(void) -{ - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - volatile serialbuffer_t *rtx; - unsigned char c; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; -#ifdef CONFIG_SYS_SMC_UCODE_PATCH - up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; -#endif - rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. */ - while (rtx->rxbd.cbd_sc & BD_SC_EMPTY) - WATCHDOG_RESET (); - - /* the characters are read one by one, - * use the rxindex to know the next char to deliver - */ - c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex); - rtx->rxindex++; - - /* check if all char are readout, then make prepare for next receive */ - if (rtx->rxindex >= rtx->rxbd.cbd_datlen) { - rtx->rxindex = 0; - rtx->rxbd.cbd_sc |= BD_SC_EMPTY; - } - return(c); -} - -static int -smc_tstc(void) -{ - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - volatile serialbuffer_t *rtx; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; -#ifdef CONFIG_SYS_SMC_UCODE_PATCH - up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; -#endif - - rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY); -} - -struct serial_device serial_smc_device = -{ - .name = "serial_smc", - .start = smc_init, - .stop = NULL, - .setbrg = smc_setbrg, - .getc = smc_getc, - .tstc = smc_tstc, - .putc = smc_putc, - .puts = smc_puts, -}; - -#endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */ - -#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \ - defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) - -static void -scc_setbrg (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG1 to SCCx - */ - - cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX)); - - serial_setdivisor(cp); -} - -static int scc_init (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; -#if (SCC_INDEX != 2) || !defined(CONFIG_MPC850) - volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); -#endif - - /* initialize pointers to SCC */ - - sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]); - up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC]; - - /* Disable transmitter/receiver. */ - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - -#if (SCC_INDEX == 2) && defined(CONFIG_MPC850) - /* - * The MPC850 has SCC3 on Port B - */ - cp->cp_pbpar |= 0x06; - cp->cp_pbdir &= ~0x06; - cp->cp_pbodr &= ~0x06; - -#elif (SCC_INDEX < 2) - /* - * Standard configuration for SCC's is on Part A - */ - ip->iop_papar |= ((3 << (2 * SCC_INDEX))); - ip->iop_padir &= ~((3 << (2 * SCC_INDEX))); - ip->iop_paodr &= ~((3 << (2 * SCC_INDEX))); -#endif - - /* Allocate space for two buffer descriptors in the DP ram. */ - dpaddr = dpram_alloc_align(sizeof(cbd_t)*2 + 2, 8); - - /* Enable SDMA. */ - im->im_siu_conf.sc_sdcr = 0x0001; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - - rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the baud rate generator. */ - scc_setbrg (); - - /* Set up the uart parameters in the parameter ram. */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); - - /* Initialize Tx/Rx parameters. */ - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - up->scc_genscc.scc_rfcr = SCC_EB | 0x05; - up->scc_genscc.scc_tfcr = SCC_EB | 0x05; - - up->scc_genscc.scc_mrblr = 1; /* Single character receive */ - up->scc_maxidl = 0; /* disable max idle */ - up->scc_brkcr = 1; /* send one break character on stop TX */ - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = 0x8000; - up->scc_char2 = 0x8000; - up->scc_char3 = 0x8000; - up->scc_char4 = 0x8000; - up->scc_char5 = 0x8000; - up->scc_char6 = 0x8000; - up->scc_char7 = 0x8000; - up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Set low latency / small fifo. */ - sp->scc_gsmrh = SCC_GSMRH_RFW; - - /* Set SCC(x) clock mode to 16x - * See 8xx_io/commproc.c for details. - * - * Wire BRG1 to SCCn - */ - - /* Set UART mode, clock divider 16 on Tx and Rx */ - sp->scc_gsmrl &= ~0xF; - sp->scc_gsmrl |= - (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); - - sp->scc_psmr = 0; - sp->scc_psmr |= SCU_PSMR_CL; - - /* Mask all interrupts and remove anything pending. */ - sp->scc_sccm = 0; - sp->scc_scce = 0xffff; - sp->scc_dsr = 0x7e7e; - sp->scc_psmr = 0x3000; - - /* Make the first buffer the only buffer. */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Enable transmitter/receiver. */ - sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - return (0); -} - -static void -scc_putc(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - if (c == '\n') - scc_putc ('\r'); - - up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; - - tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase]; - - /* Wait for last character to go. */ - - buf = (char *)tbdf->cbd_bufaddr; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__("eieio"); - - while (tbdf->cbd_sc & BD_SC_READY) { - __asm__("eieio"); - WATCHDOG_RESET (); - } -} - -static void -scc_puts (const char *s) -{ - while (*s) { - scc_putc (*s++); - } -} - -static int -scc_getc(void) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - - up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; - - /* Wait for character to show up. */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - - while (rbdf->cbd_sc & BD_SC_EMPTY) - WATCHDOG_RESET (); - - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -static int -scc_tstc(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); -} - -struct serial_device serial_scc_device = -{ - .name = "serial_scc", - .start = scc_init, - .stop = NULL, - .setbrg = scc_setbrg, - .getc = scc_getc, - .tstc = scc_tstc, - .putc = scc_putc, - .puts = scc_puts, -}; - -#endif /* CONFIG_8xx_CONS_SCCx */ - -__weak struct serial_device *default_serial_console(void) -{ -#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) - return &serial_smc_device; -#else - return &serial_scc_device; -#endif -} - -void mpc8xx_serial_initialize(void) -{ -#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) - serial_register(&serial_smc_device); -#endif -#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \ - defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) - serial_register(&serial_scc_device); -#endif -} - -#if defined(CONFIG_CMD_KGDB) - -void -kgdb_serial_init(void) -{ - int i = -1; - - if (strcmp(default_serial_console()->name, "serial_smc") == 0) - { -#if defined(CONFIG_8xx_CONS_SMC1) - i = 1; -#elif defined(CONFIG_8xx_CONS_SMC2) - i = 2; -#endif - } - else if (strcmp(default_serial_console()->name, "serial_scc") == 0) - { -#if defined(CONFIG_8xx_CONS_SCC1) - i = 1; -#elif defined(CONFIG_8xx_CONS_SCC2) - i = 2; -#elif defined(CONFIG_8xx_CONS_SCC3) - i = 3; -#elif defined(CONFIG_8xx_CONS_SCC4) - i = 4; -#endif - } - - if (i >= 0) - { - serial_printf("[on %s%d] ", default_serial_console()->name, i); - } -} - -void -putDebugChar (int c) -{ - serial_putc (c); -} - -void -putDebugStr (const char *str) -{ - serial_puts (str); -} - -int -getDebugChar (void) -{ - return serial_getc(); -} - -void -kgdb_interruptible (int yes) -{ - return; -} -#endif - -#endif /* CONFIG_8xx_CONS_NONE */ diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c deleted file mode 100644 index e2295d2..0000000 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ /dev/null @@ -1,403 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CONFIG_SYS_MEASURE_CPUCLK) || defined(DEBUG) - -#define PITC_SHIFT 16 -#define PITR_SHIFT 16 -/* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */ -#define SPEED_PIT_COUNTS 58 -#define SPEED_PITC ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT) -#define SPEED_PITC_INIT ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT) - -/* Access functions for the Machine State Register */ -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Measure CPU clock speed (core clock GCLK1, GCLK2), - * also determine bus clock speed (checking bus divider factor) - * - * (Approx. GCLK frequency in Hz) - * - * Initializes timer 2 and PIT, but disables them before return. - * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4] - * - * When measuring the CPU clock against the PIT, we count cpu clocks - * for 58/8192 seconds with a prescale divide by 177 for the cpu clock. - * These strange values for the timing interval and prescaling are used - * because the formula for the CPU clock is: - * - * CPU clock = count * (177 * (8192 / 58)) - * - * = count * 24999.7241 - * - * which is very close to - * - * = count * 25000 - * - * Since the count gives the CPU clock divided by 25000, we can get - * the CPU clock rounded to the nearest 0.1 MHz by - * - * CPU clock = ((count + 2) / 4) * 100000; - * - * The rounding is important since the measurement is sometimes going - * to be high or low by 0.025 MHz, depending on exactly how the clocks - * and counters interact. By rounding we get the exact answer for any - * CPU clock that is an even multiple of 0.1 MHz. - */ - -unsigned long measure_gclk(void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer; - ulong timer2_val; - ulong msr_val; - -#ifdef CONFIG_SYS_8XX_XIN - /* dont use OSCM, only use EXTCLK/512 */ - immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV; -#else - immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV); -#endif - - /* Reset + Stop Timer 2, no cascading - */ - timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2); - - /* Keep stopped, halt in debug mode - */ - timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2); - - /* Timer 2 setup: - * Output ref. interrupt disable, int. clock - * Prescale by 177. Note that prescaler divides by value + 1 - * so we must subtract 1 here. - */ - timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN; - - timerp->cpmt_tcn2 = 0; /* reset state */ - timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */ - - /* - * PIT setup: - * - * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz), - * so the count value would be SPEED_PITC_COUNTS - 1. - * But there would be an uncertainty in the start time of 1/4 - * count since when we enable the PIT the count is not - * synchronized to the 32768 Hz oscillator. The trick here is - * to start the count higher and wait until the PIT count - * changes to the required value before starting timer 2. - * - * One count high should be enough, but occasionally the start - * is off by 1 or 2 counts of 32768 Hz. With the start value - * set two counts high it seems very reliable. - */ - - immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */ - immr->im_sit.sit_pitc = SPEED_PITC_INIT; - - immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; - - /* - * Start measurement - disable interrupts, just in case - */ - msr_val = get_msr (); - set_msr (msr_val & ~MSR_EE); - - immr->im_sit.sit_piscr |= PISCR_PTE; - - /* spin until get exact count when we want to start */ - while (immr->im_sit.sit_pitr > SPEED_PITC); - - timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */ - while ((immr->im_sit.sit_piscr & PISCR_PS) == 0); - timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */ - - /* re-enable external interrupts if they were on */ - set_msr (msr_val); - - /* Disable timer and PIT - */ - timer2_val = timerp->cpmt_tcn2; /* save before reset timer */ - - timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2); - immr->im_sit.sit_piscr &= ~PISCR_PTE; - -#if defined(CONFIG_SYS_8XX_XIN) - /* not using OSCM, using XIN, so scale appropriately */ - return (((timer2_val + 2) / 4) * (CONFIG_SYS_8XX_XIN/512))/8192 * 100000L; -#else - return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */ -#endif -} - -#endif - -void get_brgclk(uint sccr) -{ - uint divider = 0; - - switch((sccr&SCCR_DFBRG11)>>11){ - case 0: - divider = 1; - break; - case 1: - divider = 4; - break; - case 2: - divider = 16; - break; - case 3: - divider = 64; - break; - } - gd->arch.brg_clk = gd->cpu_clk/divider; -} - -#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) - -/* - * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ - * or (if it is not defined) measure_gclk() (which uses the ref clock) - * from above. - */ -int get_clocks (void) -{ - uint immr = get_immr (0); /* Return full IMMR contents */ - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint sccr = immap->im_clkrst.car_sccr; - /* - * If for some reason measuring the gclk frequency won't - * work, we return the hardwired value. - * (For example, the cogent CMA286-60 CPU module has no - * separate oscillator for PITRTCLK) - */ -#if defined(CONFIG_8xx_GCLK_FREQ) - gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; -#elif defined(CONFIG_8xx_OSCLK) -#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) - uint pll = immap->im_clkrst.car_plprcr; - uint clk; - - if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ - clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) * - (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) / - (1<<PLPRCR_val(S)); - } else { - clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1); - } - if (pll & PLPRCR_CSRC) { /* Low frequency division factor is used */ - gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7)); - } else { /* High frequency division factor is used */ - gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7)); - } -#else - gd->cpu_clk = measure_gclk(); -#endif /* CONFIG_8xx_GCLK_FREQ */ - - if ((sccr & SCCR_EBDF11) == 0) { - /* No Bus Divider active */ - gd->bus_clk = gd->cpu_clk; - } else { - /* The MPC8xx has only one BDF: half clock speed */ - gd->bus_clk = gd->cpu_clk / 2; - } - - get_brgclk(sccr); - - return (0); -} - -#else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */ - -static long init_pll_866 (long clk); - -/* Adjust sdram refresh rate to actual CPU clock. - */ -static int sdram_adjust_866(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - long mamr; - - mamr = immr->im_memctl.memc_mamr; - mamr &= ~MAMR_PTA_MSK; - mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); - immr->im_memctl.memc_mamr = mamr; - - return 0; -} - -/* - * Adjust sdram refresh rate to actual CPU clock - * and set timebase source according to actual CPU clock - */ -static int adjust_sdram_tbs_8xx(void) -{ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) && \ - !defined(CONFIG_TQM885D) - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - long mamr; - long sccr; - - mamr = immr->im_memctl.memc_mamr; - mamr &= ~MAMR_PTA_MSK; - mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); - immr->im_memctl.memc_mamr = mamr; - - if (gd->cpu_clk < 67000000) { - sccr = immr->im_clkrst.car_sccr; - sccr |= SCCR_TBS; - immr->im_clkrst.car_sccr = sccr; - } -#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ - - return 0; -} - -/* This function sets up PLL (init_pll_866() is called) and - * fills gd->cpu_clk and gd->bus_clk according to the environment - * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk' - * contains invalid value). - * This functions requires an MPC866 or newer series CPU. - */ -int get_clocks(void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - char tmp[64]; - long cpuclk = 0; - long sccr_reg; - int ret; - - if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) - cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; - - if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk)) - cpuclk = CONFIG_8xx_CPUCLK_DEFAULT; - - gd->cpu_clk = init_pll_866 (cpuclk); -#if defined(CONFIG_SYS_MEASURE_CPUCLK) - gd->cpu_clk = measure_gclk (); -#endif - - get_brgclk(immr->im_clkrst.car_sccr); - - /* if cpu clock <= 66 MHz then set bus division factor to 1, - * otherwise set it to 2 - */ - sccr_reg = immr->im_clkrst.car_sccr; - sccr_reg &= ~SCCR_EBDF11; - - if (gd->cpu_clk <= 66000000) { - sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ - gd->bus_clk = gd->cpu_clk; - } else { - sccr_reg |= SCCR_EBDF01; /* bus division factor = 2 */ - gd->bus_clk = gd->cpu_clk / 2; - } - immr->im_clkrst.car_sccr = sccr_reg; - - ret = sdram_adjust_866(); - if (ret) - return ret; - - return adjust_sdram_tbs_8xx(); -} - -/* Configure PLL for MPC866/859/885 CPU series - * PLL multiplication factor is set to the value nearest to the desired clk, - * assuming a oscclk of 10 MHz. - */ -static long init_pll_866 (long clk) -{ - extern void plprcr_write_866 (long); - - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - long n, plprcr; - char mfi, mfn, mfd, s, pdf; - long step_mfi, step_mfn; - - if (clk < 20000000) { - clk *= 2; - pdf = 1; - } else { - pdf = 0; - } - - if (clk < 40000000) { - s = 2; - step_mfi = CONFIG_8xx_OSCLK / 4; - mfd = 7; - step_mfn = CONFIG_8xx_OSCLK / 30; - } else if (clk < 80000000) { - s = 1; - step_mfi = CONFIG_8xx_OSCLK / 2; - mfd = 14; - step_mfn = CONFIG_8xx_OSCLK / 30; - } else { - s = 0; - step_mfi = CONFIG_8xx_OSCLK; - mfd = 29; - step_mfn = CONFIG_8xx_OSCLK / 30; - } - - /* Calculate integer part of multiplication factor - */ - n = clk / step_mfi; - mfi = (char)n; - - /* Calculate numerator of fractional part of multiplication factor - */ - n = clk - (n * step_mfi); - mfn = (char)(n / step_mfn); - - /* Calculate effective clk - */ - n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1); - - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - - plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK - | PLPRCR_MFD_MSK | PLPRCR_S_MSK - | PLPRCR_MFI_MSK | PLPRCR_DBRMO - | PLPRCR_PDF_MSK)) - | (mfn << PLPRCR_MFN_SHIFT) - | (mfd << PLPRCR_MFD_SHIFT) - | (s << PLPRCR_S_SHIFT) - | (mfi << PLPRCR_MFI_SHIFT) - | (pdf << PLPRCR_PDF_SHIFT); - - if( (mfn > 0) && ((mfd / mfn) > 10) ) - plprcr |= PLPRCR_DBRMO; - - plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */ - immr->im_clkrstk.cark_plprcrk = 0x00000000; - - return (n); -} - -#endif /* CONFIG_8xx_CPUCLK_DEFAULT */ diff --git a/arch/powerpc/cpu/mpc8xx/spi.c b/arch/powerpc/cpu/mpc8xx/spi.c deleted file mode 100644 index 35b425e..0000000 --- a/arch/powerpc/cpu/mpc8xx/spi.c +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * nboppuri@trinetcommunication.com, - * pmpatel@trinetcommunication.com - * Copyright (c) 2001 Gerd Mennchen Gerd.Mennchen@icn.siemens.de - * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8xx CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd@denx.de - * - */ - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <linux/ctype.h> -#include <malloc.h> -#include <post.h> -#include <serial.h> - -#if (defined(CONFIG_SPI)) || (CONFIG_POST & CONFIG_SYS_POST_SPI) - -/* Warning: - * You cannot enable DEBUG for early system initalization, i. e. when - * this driver is used to read environment parameters like "baudrate" - * from EEPROM which are used to initialize the serial port which is - * needed to print the debug messages... - */ -#undef DEBUG - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - -/* --------------------------------------------------------------- - * Offset for initial SPI buffers in DPRAM: - * We need a 520 byte scratch DPRAM area to use at an early stage. - * It is used between the two initialization calls (spi_init_f() - * and spi_init_r()). - * The value 0xb00 makes it far enough from the start of the data - * area (as well as from the stack pointer). - * --------------------------------------------------------------- */ -#ifndef CONFIG_SYS_SPI_INIT_OFFSET -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 -#endif - -#ifdef DEBUG - -#define DPRINT(a) printf a; -/* ----------------------------------------------- - * Helper functions to peek into tx and rx buffers - * ----------------------------------------------- */ -static const char * const hex_digit = "0123456789ABCDEF"; - -static char quickhex (int i) -{ - return hex_digit[i]; -} - -static void memdump (void *pv, int num) -{ - int i; - unsigned char *pc = (unsigned char *) pv; - - for (i = 0; i < num; i++) - printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); - printf ("\t"); - for (i = 0; i < num; i++) - printf ("%c", isprint (pc[i]) ? pc[i] : '.'); - printf ("\n"); -} -#else /* !DEBUG */ - -#define DPRINT(a) - -#endif /* DEBUG */ - -/* ------------------- - * Function prototypes - * ------------------- */ -void spi_init (void); - -ssize_t spi_read (uchar *, int, uchar *, int); -ssize_t spi_write (uchar *, int, uchar *, int); -ssize_t spi_xfer (size_t); - -/* ------------------- - * Variables - * ------------------- */ - -#define MAX_BUFFER 0x104 - -/* ---------------------------------------------------------------------- - * Initially we place the RX and TX buffers at a fixed location in DPRAM! - * ---------------------------------------------------------------------- */ -static uchar *rxbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET]; -static uchar *txbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ -void spi_init_f (void) -{ - unsigned int dpaddr; - - volatile spi_t *spi; - volatile immap_t *immr; - volatile cpm8xx_t *cp; - volatile cbd_t *tbdf, *rbdf; - - immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8xx_t *) &immr->im_cpm; - -#ifdef CONFIG_SYS_SPI_UCODE_PATCH - spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; -#else - spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; - /* Disable relocation */ - spi->spi_rpbase = 0; -#endif - -/* 1 */ - /* ------------------------------------------------ - * Initialize Port B SPI pins -> page 34-8 MPC860UM - * (we are only in Master Mode !) - * ------------------------------------------------ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO) - * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI) - * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK) - * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM) - * -------------------------------------------- */ - cp->cp_pbpar |= 0x0000000E; /* set bits */ - cp->cp_pbpar &= ~0x00000001; /* reset bit */ - - /* ---------------------------------------------- - * In/Out or per. Function 0/1 - * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO - * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI - * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK - * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM - * ---------------------------------------------- */ - cp->cp_pbdir |= 0x0000000F; - - /* ---------------------------------------------- - * open drain or active output - * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO - * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI - * PBODR[30] = 0 [0x00000002] -> active output: SPICLK - * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM - * ---------------------------------------------- */ - - cp->cp_pbodr |= 0x00000008; - cp->cp_pbodr &= ~0x00000007; - - /* Initialize the parameter ram. - * We need to make sure many things are initialized to zero - */ - spi->spi_rstate = 0; - spi->spi_rdp = 0; - spi->spi_rbptr = 0; - spi->spi_rbc = 0; - spi->spi_rxtmp = 0; - spi->spi_tstate = 0; - spi->spi_tdp = 0; - spi->spi_tbptr = 0; - spi->spi_tbc = 0; - spi->spi_txtmp = 0; - - dpaddr = CPM_SPI_BASE; - -/* 3 */ - /* Set up the SPI parameters in the parameter ram */ - spi->spi_rbase = dpaddr; - spi->spi_tbase = dpaddr + sizeof (cbd_t); - - /***********IMPORTANT******************/ - - /* - * Setting transmit and receive buffer descriptor pointers - * initially to rbase and tbase. Only the microcode patches - * documentation talks about initializing this pointer. This - * is missing from the sample I2C driver. If you dont - * initialize these pointers, the kernel hangs. - */ - spi->spi_rbptr = spi->spi_rbase; - spi->spi_tbptr = spi->spi_tbase; - -/* 4 */ -#ifdef CONFIG_SYS_SPI_UCODE_PATCH - /* - * Initialize required parameters if using microcode patch. - */ - spi->spi_rstate = 0; - spi->spi_tstate = 0; -#else - /* Init SPI Tx + Rx Parameters */ - while (cp->cp_cpcr & CPM_CR_FLG) - ; - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG) - ; -#endif /* CONFIG_SYS_SPI_UCODE_PATCH */ - -/* 5 */ - /* Set SDMA configuration register */ - immr->im_siu_conf.sc_sdcr = 0x0001; - -/* 6 */ - /* Set to big endian. */ - spi->spi_tfcr = SMC_EB; - spi->spi_rfcr = SMC_EB; - -/* 7 */ - /* Set maximum receive size. */ - spi->spi_mrblr = MAX_BUFFER; - -/* 8 + 9 */ - /* tx and rx buffer descriptors */ - tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; - rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; - - tbdf->cbd_sc &= ~BD_SC_READY; - rbdf->cbd_sc &= ~BD_SC_EMPTY; - - /* Set the bd's rx and tx buffer address pointers */ - rbdf->cbd_bufaddr = (ulong) rxbuf; - tbdf->cbd_bufaddr = (ulong) txbuf; - -/* 10 + 11 */ - cp->cp_spim = 0; /* Mask all SPI events */ - cp->cp_spie = SPI_EMASK; /* Clear all SPI events */ - - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * - * return: --- - * - * *********************************************************************** */ -void spi_init_r (void) -{ - volatile cpm8xx_t *cp; - volatile spi_t *spi; - volatile immap_t *immr; - volatile cbd_t *tbdf, *rbdf; - - immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8xx_t *) &immr->im_cpm; - -#ifdef CONFIG_SYS_SPI_UCODE_PATCH - spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; -#else - spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; - /* Disable relocation */ - spi->spi_rpbase = 0; -#endif - - /* tx and rx buffer descriptors */ - tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; - rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; - - /* Allocate memory for RX and TX buffers */ - rxbuf = (uchar *) malloc (MAX_BUFFER); - txbuf = (uchar *) malloc (MAX_BUFFER); - - rbdf->cbd_bufaddr = (ulong) rxbuf; - tbdf->cbd_bufaddr = (ulong) txbuf; - - return; -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - *txbuf = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ - memcpy(alen + txbuf, buffer, len); - spi_xfer(alen + len); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - *txbuf = SPI_EEPROM_RDSR; /* read status */ - txbuf[1] = 0; - spi_xfer(2); - if (!(rxbuf[1] & 1)) { - break; - } - udelay(1000); - } - if (i >= 1000) { - printf ("*** spi_write: Time out while writing!\n"); - } - - return len; -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) -{ - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_READ; /* READ memory array */ - - /* - * There is a bug in 860T (?) that cuts the last byte of input - * if we're reading into DPRAM. The solution we choose here is - * to always read len+1 bytes (we have one extra byte at the - * end of the buffer). - */ - spi_xfer(alen + len + 1); - memcpy(buffer, alen + rxbuf, len); - - return len; -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer (size_t count) -{ - volatile immap_t *immr; - volatile cpm8xx_t *cp; - volatile spi_t *spi; - cbd_t *tbdf, *rbdf; - ushort loop; - int tm; - - DPRINT (("*** spi_xfer entered ***\n")); - - immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8xx_t *) &immr->im_cpm; - -#ifdef CONFIG_SYS_SPI_UCODE_PATCH - spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; -#else - spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; - /* Disable relocation */ - spi->spi_rpbase = 0; -#endif - - tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; - rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; - - /* Set CS for device */ - cp->cp_pbdat &= ~0x0001; - - /* Setting tx bd status and data length */ - tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP; - tbdf->cbd_datlen = count; - - DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", - tbdf->cbd_datlen)); - - /* Setting rx bd status and data length */ - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - rbdf->cbd_datlen = 0; /* rx length has no significance */ - - loop = cp->cp_spmode & SPMODE_LOOP; - cp->cp_spmode = /*SPMODE_DIV16 |*/ /* BRG/16 mode not used here */ - loop | - SPMODE_REV | - SPMODE_MSTR | - SPMODE_EN | - SPMODE_LEN(8) | /* 8 Bits per char */ - SPMODE_PM(0x8) ; /* medium speed */ - cp->cp_spim = 0; /* Mask all SPI events */ - cp->cp_spie = SPI_EMASK; /* Clear all SPI events */ - - /* start spi transfer */ - DPRINT (("*** spi_xfer: Performing transfer ...\n")); - cp->cp_spcom |= SPI_STR; /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm=0; tm<1000; ++tm) { - if (cp->cp_spie & SPI_TXB) { /* Tx Buffer Empty */ - DPRINT (("*** spi_xfer: Tx buffer empty\n")); - break; - } - if ((tbdf->cbd_sc & BD_SC_READY) == 0) { - DPRINT (("*** spi_xfer: Tx BD done\n")); - break; - } - udelay (1000); - } - if (tm >= 1000) { - printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); - } - DPRINT (("*** spi_xfer: ... transfer ended\n")); - -#ifdef DEBUG - printf ("\nspi_xfer: txbuf after xfer\n"); - memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */ - printf ("spi_xfer: rxbuf after xfer\n"); - memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */ - printf ("\n"); -#endif - - /* Clear CS for device */ - cp->cp_pbdat |= 0x0001; - - return count; -} -#endif /* CONFIG_SPI || (CONFIG_POST & CONFIG_SYS_POST_SPI) */ - -/* - * SPI test - * - * The Serial Peripheral Interface (SPI) is tested in the local loopback mode. - * The interface is configured accordingly and several packets - * are transferred. The configurable test parameters are: - * TEST_MIN_LENGTH - minimum size of packet to transfer - * TEST_MAX_LENGTH - maximum size of packet to transfer - * TEST_NUM - number of tests - */ - -#if CONFIG_POST & CONFIG_SYS_POST_SPI - -#define TEST_MIN_LENGTH 1 -#define TEST_MAX_LENGTH MAX_BUFFER -#define TEST_NUM 1 - -static void packet_fill (char * packet, int length) -{ - char c = (char) length; - int i; - - for (i = 0; i < length; i++) - { - packet[i] = c++; - } -} - -static int packet_check (char * packet, int length) -{ - char c = (char) length; - int i; - - for (i = 0; i < length; i++) { - if (packet[i] != c++) return -1; - } - - return 0; -} - -int spi_post_test (int flags) -{ - int res = -1; - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = (cpm8xx_t *) & immr->im_cpm; - int i; - int l; - - spi_init_f (); - spi_init_r (); - - cp->cp_spmode |= SPMODE_LOOP; - - for (i = 0; i < TEST_NUM; i++) { - for (l = TEST_MIN_LENGTH; l <= TEST_MAX_LENGTH; l += 8) { - packet_fill ((char *)txbuf, l); - - spi_xfer (l); - - if (packet_check ((char *)rxbuf, l) < 0) { - goto Done; - } - } - } - - res = 0; - - Done: - - cp->cp_spmode &= ~SPMODE_LOOP; - - /* - * SCC2 parameter RAM space overlaps - * the SPI parameter RAM space. So we need to restore - * the SCC2 configuration if it is used by UART. - */ - -#if !defined(CONFIG_8xx_CONS_NONE) - serial_reinit_all (); -#endif - - if (res != 0) { - post_log ("SPI test failed\n"); - } - - return res; -} -#endif /* CONFIG_POST & CONFIG_SYS_POST_SPI */ diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S deleted file mode 100644 index f8aa93d..0000000 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ /dev/null @@ -1,650 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek dmalek@jlc.net - * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> - * Copyright (C) 2000,2001,2002 Wolfgang Denk wd@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* U-Boot - Startup Code for PowerPC based Embedded Boards - * - * - * The processor starts at 0x00000100 and the code is executed - * from flash. The code is organized to be at an other address - * in memory, but as long we don't jump around before relocating, - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - * This works because the cpu gives the FLASH (CS0) the whole - * address space at startup, and board_init lies as a echo of - * the flash somewhere up there in the memory map. - * - * board_init will change CS0 to be positioned at the correct - * address and (s)dram will be positioned at address 0 - */ -#include <asm-offsets.h> -#include <config.h> -#include <mpc8xx.h> -#include <version.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> -#include <asm/u-boot.h> - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */ - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - lis r3, CONFIG_SYS_IMMR@h /* position IMMR */ - mtspr 638, r3 - - /* Initialize machine status; enable machine check interrupt */ - /*----------------------------------------------------------------------*/ - li r3, MSR_KERNEL /* Set ME, RI flags */ - mtmsr r3 - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - mfspr r3, ICR /* clear Interrupt Cause Register */ - - /* Initialize debug port registers */ - /*----------------------------------------------------------------------*/ - xor r0, r0, r0 /* Clear R0 */ - mtspr LCTRL1, r0 /* Initialize debug port regs */ - mtspr LCTRL2, r0 - mtspr COUNTA, r0 - mtspr COUNTB, r0 - - /* Reset the caches */ - /*----------------------------------------------------------------------*/ - - mfspr r3, IC_CST /* Clear error bits */ - mfspr r3, DC_CST - - lis r3, IDC_UNALL@h /* Unlock all */ - mtspr IC_CST, r3 - mtspr DC_CST, r3 - - lis r3, IDC_INVALL@h /* Invalidate all */ - mtspr IC_CST, r3 - mtspr DC_CST, r3 - - lis r3, IDC_DISABLE@h /* Disable data cache */ - mtspr DC_CST, r3 - -#if !defined(CONFIG_SYS_DELAYED_ICACHE) - /* On IP860 and PCU E, - * we cannot enable IC yet - */ - lis r3, IDC_ENABLE@h /* Enable instruction cache */ -#endif - mtspr IC_CST, r3 - - /* invalidate all tlb's */ - /*----------------------------------------------------------------------*/ - - tlbia - isync - - /* - * Calculate absolute address in FLASH and jump there - *----------------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_MONITOR_BASE@h - ori r3, r3, CONFIG_SYS_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: - - /* initialize some SPRs that are hard to access from C */ - /*----------------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */ - ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */ - /* Note: R0 is still 0 here */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* - * Disable serialized ifetch and show cycles - * (i.e. set processor to normal mode). - * This is also a silicon bug workaround, see errata - */ - - li r2, 0x0007 - mtspr ICTRL, r2 - - /* Set up debug mode entry */ - - lis r2, CONFIG_SYS_DER@h - ori r2, r2, CONFIG_SYS_DER@l - mtspr DER, r2 - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*----------------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - - bl board_init_f /* run 1st part of board init code (from Flash) */ - - /* NOTREACHED - board_init_f() does not return */ - - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - /* No FPU on MPC8xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - /* On the MPC8xx, this is a software emulation interrupt. It occurs - * for all unimplemented and illegal instructions. - */ - STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) - - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) - - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) - STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException) - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - - . = 0x2000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* Cache functions. -*/ - .globl icache_enable -icache_enable: - SYNC - lis r3, IDC_INVALL@h - mtspr IC_CST, r3 - lis r3, IDC_ENABLE@h - mtspr IC_CST, r3 - blr - - .globl icache_disable -icache_disable: - SYNC - lis r3, IDC_DISABLE@h - mtspr IC_CST, r3 - blr - - .globl icache_status -icache_status: - mfspr r3, IC_CST - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl dcache_enable -dcache_enable: -#if 0 - SYNC -#endif -#if 1 - lis r3, 0x0400 /* Set cache mode with MMU off */ - mtspr MD_CTR, r3 -#endif - - lis r3, IDC_INVALL@h - mtspr DC_CST, r3 -#if 0 - lis r3, DC_SFWT@h - mtspr DC_CST, r3 -#endif - lis r3, IDC_ENABLE@h - mtspr DC_CST, r3 - blr - - .globl dcache_disable -dcache_disable: - SYNC - lis r3, IDC_DISABLE@h - mtspr DC_CST, r3 - lis r3, IDC_INVALL@h - mtspr DC_CST, r3 - blr - - .globl dcache_status -dcache_status: - mfspr r3, DC_CST - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl dc_read -dc_read: - mtspr DC_ADR, r3 - mfspr r3, DC_DAT - blr - -/* - * unsigned int get_immr (unsigned int mask) - * - * return (mask ? (IMMR & mask) : IMMR); - */ - .globl get_immr -get_immr: - mr r4,r3 /* save mask */ - mfspr r3, IMMR /* IMMR */ - cmpwi 0,r4,0 /* mask != 0 ? */ - beq 4f - and r3,r3,r4 /* IMMR & mask */ -4: - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - - - .globl wr_ic_cst -wr_ic_cst: - mtspr IC_CST, r3 - blr - - .globl rd_ic_cst -rd_ic_cst: - mfspr r3, IC_CST - blr - - .globl wr_ic_adr -wr_ic_adr: - mtspr IC_ADR, r3 - blr - - - .globl wr_dc_cst -wr_dc_cst: - mtspr DC_CST, r3 - blr - - .globl rd_dc_cst -rd_dc_cst: - mfspr r3, DC_CST - blr - - .globl wr_dc_adr -wr_dc_adr: - mtspr DC_ADR, r3 - blr - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3, r5 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - cmpwi r0,0 - add r0,r0,r11 - stw r4,0(r3) - beq- 5f - stw r0,0(r4) -5: bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mtlr r4 /* restore link register */ - blr diff --git a/arch/powerpc/cpu/mpc8xx/traps.c b/arch/powerpc/cpu/mpc8xx/traps.c deleted file mode 100644 index 01f24ac..0000000 --- a/arch/powerpc/cpu/mpc8xx/traps.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * linux/arch/powerpc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include <common.h> -#include <command.h> -#include <kgdb.h> -#include <asm/processor.h> - -#if defined(CONFIG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x02000000 - -/* - * Trap & Exception support - */ - -static void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void show_regs(struct pt_regs *regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -static void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void AlignmentException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void ProgramCheckException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void SoftEmuException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void UnknownException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -void DebugException(struct pt_regs *regs) -{ - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,"ax"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,"a"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xx/upatch.c b/arch/powerpc/cpu/mpc8xx/upatch.c deleted file mode 100644 index a8cb735..0000000 --- a/arch/powerpc/cpu/mpc8xx/upatch.c +++ /dev/null @@ -1,194 +0,0 @@ -#include <common.h> -#include <commproc.h> - -#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ - defined(CONFIG_SYS_SMC_UCODE_PATCH) - -static void UcodeCopy (volatile cpm8xx_t *cpm); - -void cpm_load_patch (volatile immap_t *immr) -{ - immr->im_cpm.cp_rccr &= ~0x0003; /* Disable microcode program area */ - - UcodeCopy ((cpm8xx_t *)&immr->im_cpm); /* Copy ucode patch to DPRAM */ -#ifdef CONFIG_SYS_SPI_UCODE_PATCH - { - volatile spi_t *spi = (spi_t *) & immr->im_cpm.cp_dparam[PROFF_SPI]; - /* Activate the microcode per the instructions in the microcode manual */ - /* NOTE: We're only relocating the SPI parameters (not I2C). */ - immr->im_cpm.cp_cpmcr1 = 0x802a; /* Write Trap register 1 value */ - immr->im_cpm.cp_cpmcr2 = 0x8028; /* Write Trap register 2 value */ - spi->spi_rpbase = CONFIG_SYS_SPI_DPMEM_OFFSET; /* Where to relocte SPI params */ - } -#endif - -#ifdef CONFIG_SYS_I2C_UCODE_PATCH - { - volatile iic_t *iip = (iic_t *) & immr->im_cpm.cp_dparam[PROFF_IIC]; - /* Activate the microcode per the instructions in the microcode manual */ - /* NOTE: We're only relocating the I2C parameters (not SPI). */ - immr->im_cpm.cp_cpmcr3 = 0x802e; /* Write Trap register 3 value */ - immr->im_cpm.cp_cpmcr4 = 0x802c; /* Write Trap register 4 value */ - iip->iic_rpbase = CONFIG_SYS_I2C_DPMEM_OFFSET; /* Where to relocte I2C params */ - } -#endif - -#ifdef CONFIG_SYS_SMC_UCODE_PATCH - { - volatile smc_uart_t *up = (smc_uart_t *) & immr->im_cpm.cp_dparam[PROFF_SMC1]; - /* Activate the microcode per the instructions in the microcode manual */ - /* NOTE: We're only relocating the SMC parameters. */ - immr->im_cpm.cp_cpmcr1 = 0x8080; /* Write Trap register 1 value */ - immr->im_cpm.cp_cpmcr2 = 0x8088; /* Write Trap register 2 value */ - up->smc_rpbase = CONFIG_SYS_SMC_DPMEM_OFFSET; /* Where to relocte SMC params */ - } -#endif - - /* - * Enable DPRAM microcode to execute from the first 512 bytes - * and a 256 byte extension of DPRAM. - */ -#ifdef CONFIG_SYS_SMC_UCODE_PATCH - immr->im_cpm.cp_rccr |= 0x0002; -#else - immr->im_cpm.cp_rccr |= 0x0001; -#endif -} - -#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCh) -static ulong patch_2000[] = { - 0x7FFFEFD9, 0x3FFD0000, 0x7FFB49F7, 0x7FF90000, - 0x5FEFADF7, 0x5F88ADF7, 0x5FEFAFF7, 0x5F88AFF7, - 0x3A9CFBC8, 0x77CAE1BB, 0xF4DE7FAD, 0xABAE9330, - 0x4E08FDCF, 0x6E0FAFF8, 0x7CCF76CF, 0xFDAFF9CF, - 0xABF88DC8, 0xAB5879F7, 0xB0927383, 0xDFD079F7, - 0xB090E6BB, 0xE5BBE74F, 0xB3FA6F0F, 0x6FFB76CE, - 0xEE0CF9CF, 0x2BFBEFEF, 0xCFEEF9CF, 0x76CEAD23, - 0x90B3DF99, 0x7FDDD0C1, 0x4BF847FD, 0x7CCF76CE, - 0xCFEF77CA, 0x7EAF7FAD, 0x7DFDF0B7, 0xEF7A7FCA, - 0x77CAFBC8, 0x6079E722, 0xFBC85FFF, 0xDFFF5FB3, - 0xFFFBFBC8, 0xF3C894A5, 0xE7C9EDF9, 0x7F9A7FAD, - 0x5F36AFE8, 0x5F5BFFDF, 0xDF95CB9E, 0xAF7D5FC3, - 0xAFED8C1B, 0x5FC3AFDD, 0x5FC5DF99, 0x7EFDB0B3, - 0x5FB3FFFE, 0xABAE5FB3, 0xFFFE5FD0, 0x600BE6BB, - 0x600B5FD0, 0xDFC827FB, 0xEFDF5FCA, 0xCFDE3A9C, - 0xE7C9EDF9, 0xF3C87F9E, 0x54CA7FED, 0x2D3A3637, - 0x756F7E9A, 0xF1CE37EF, 0x2E677FEE, 0x10EBADF8, - 0xEFDECFEA, 0xE52F7D9F, 0xE12BF1CE, 0x5F647E9A, - 0x4DF8CFEA, 0x5F717D9B, 0xEFEECFEA, 0x5F73E522, - 0xEFDE5F73, 0xCFDA0B61, 0x7385DF61, 0xE7C9EDF9, - 0x7E9A30D5, 0x1458BFFF, 0xF3C85FFF, 0xDFFFA7F8, - 0x5F5BBFFE, 0x7F7D10D0, 0x144D5F33, 0xBFFFAF78, - 0x5F5BBFFD, 0xA7F85F33, 0xBFFE77FD, 0x30BD4E08, - 0xFDCFE5FF, 0x6E0FAFF8, 0x7EEF7E9F, 0xFDEFF1CF, - 0x5F17ABF8, 0x0D5B5F5B, 0xFFEF79F7, 0x309EAFDD, - 0x5F3147F8, 0x5F31AFED, 0x7FDD50AF, 0x497847FD, - 0x7F9E7FED, 0x7DFD70A9, 0xEF7E7ECE, 0x6BA07F9E, - 0x2D227EFD, 0x30DB5F5B, 0xFFFD5F5B, 0xFFEF5F5B, - 0xFFDF0C9C, 0xAFED0A9A, 0xAFDD0C37, 0x5F37AFBD, - 0x7FBDB081, 0x5F8147F8, -}; - -static ulong patch_2F00[] = { - 0x3E303430, 0x34343737, 0xABBF9B99, 0x4B4FBDBD, - 0x59949334, 0x9FFF37FB, 0x9B177DD9, 0x936956BB, - 0xFBDD697B, 0xDD2FD113, 0x1DB9F7BB, 0x36313963, - 0x79373369, 0x3193137F, 0x7331737A, 0xF7BB9B99, - 0x9BB19795, 0x77FDFD3D, 0x573B773F, 0x737933F7, - 0xB991D115, 0x31699315, 0x31531694, 0xBF4FBDBD, - 0x35931497, 0x35376956, 0xBD697B9D, 0x96931313, - 0x19797937, 0x69350000, -}; -#else - -static ulong patch_2000[] = { - 0x3fff0000, 0x3ffd0000, 0x3ffb0000, 0x3ff90000, - 0x5fefeff8, 0x5f91eff8, 0x3ff30000, 0x3ff10000, - 0x3a11e710, 0xedf0ccb9, 0xf318ed66, 0x7f0e5fe2, - 0x7fedbb38, 0x3afe7468, 0x7fedf4d8, 0x8ffbb92d, - 0xb83b77fd, 0xb0bb5eb9, 0xdfda7fed, 0x90bde74d, - 0x6f0dcbd3, 0xe7decfed, 0xcb50cfed, 0xcfeddf6d, - 0x914d4f74, 0x5eaedfcb, 0x9ee0e7df, 0xefbb6ffb, - 0xe7ef7f0e, 0x9ee57fed, 0xebb7effa, 0xeb30affb, - 0x7fea90b3, 0x7e0cf09f, 0xbffff318, 0x5fffdfff, - 0xac35efea, 0x7fce1fc1, 0xe2ff5fbd, 0xaffbe2ff, - 0x5fbfaffb, 0xf9a87d0f, 0xaef8770f, 0x7d0fb0a2, - 0xeffbbfff, 0xcfef5fba, 0x7d0fbfff, 0x5fba4cf8, - 0x7fddd09b, 0x49f847fd, 0x7efdf097, 0x7fedfffd, - 0x7dfdf093, 0xef7e7e1e, 0x5fba7f0e, 0x3a11e710, - 0xedf0cc87, 0xfb18ad0a, 0x1f85bbb8, 0x74283b7e, - 0x7375e4bb, 0x2ab64fb8, 0x5c7de4bb, 0x32fdffbf, - 0x5f0843f8, 0x7ce3e1bb, 0xe74f7ded, 0x6f0f4fe8, - 0xc7ba32be, 0x73f2efeb, 0x600b4f78, 0xe5bb760b, - 0x5388aef8, 0x4ef80b6a, 0xcfef9ee5, 0xabf8751f, - 0xefef5b88, 0x741f4fe8, 0x751e760d, 0x7fdb70dd, - 0x741cafce, 0xefcc7fce, 0x751e7088, 0x741ce7bb, - 0x334ecfed, 0xafdbefeb, 0xe5bb760b, 0x53ceaef8, - 0xafe8e7eb, 0x4bf8771e, 0x7e007fed, 0x4fcbe2cc, - 0x7fbc3085, 0x7b0f7a0f, 0x34b177fd, 0xb0e75e93, - 0xdf313e3b, 0xaf78741f, 0x741f30cc, 0xcfef5f08, - 0x741f3e88, 0xafb8771e, 0x5f437fed, 0x0bafe2cc, - 0x741ccfec, 0xe5ca53a9, 0x6fcb4f74, 0x5e89df27, - 0x2a923d14, 0x4b8fdf0c, 0x751f741c, 0x6c1eeffa, - 0xefea7fce, 0x6ffc309a, 0xefec3fca, 0x308fdf0a, - 0xadf85e7a, 0xaf7daefd, 0x5e7adf0a, 0x5e7aafdd, - 0x761f1088, 0x1e7c7efd, 0x3089fffe, 0x4908fb18, - 0x5fffdfff, 0xafbbf0f7, 0x4ef85f43, 0xadf81489, - 0x7a0f7089, 0xcfef5089, 0x7a0fdf0c, 0x5e7cafed, - 0xbc6e780f, 0xefef780f, 0xefef790f, 0xa7f85eeb, - 0xffef790f, 0xefef790f, 0x1489df0a, 0x5e7aadfd, - 0x5f09fffb, 0xe79aded9, 0xeff96079, 0x607ae79a, - 0xded8eff9, 0x60795edb, 0x607acfef, 0xefefefdf, - 0xefbfef7f, 0xeeffedff, 0xebffe7ff, 0xafefafdf, - 0xafbfaf7f, 0xaeffadff, 0xabffa7ff, 0x6fef6fdf, - 0x6fbf6f7f, 0x6eff6dff, 0x6bff67ff, 0x2fef2fdf, - 0x2fbf2f7f, 0x2eff2dff, 0x2bff27ff, 0x4e08fd1f, - 0xe5ff6e0f, 0xaff87eef, 0x7e0ffdef, 0xf11f6079, - 0xabf8f51e, 0x7e0af11c, 0x37cfae16, 0x7fec909a, - 0xadf8efdc, 0xcfeae52f, 0x7d0fe12b, 0xf11c6079, - 0x7e0a4df8, 0xcfea5ea0, 0x7d0befec, 0xcfea5ea2, - 0xe522efdc, 0x5ea2cfda, 0x4e08fd1f, 0x6e0faff8, - 0x7c1f761f, 0xfdeff91f, 0x6079abf8, 0x761cee00, - 0xf91f2bfb, 0xefefcfec, 0xf91f6079, 0x761c27fb, - 0xefdf5e83, 0xcfdc7fdd, 0x50f84bf8, 0x47fd7c1f, - 0x761ccfcf, 0x7eef7fed, 0x7dfd70ef, 0xef7e7f1e, - 0x771efb18, 0x6079e722, 0xe6bbe5bb, 0x2e66e5bb, - 0x600b2ee1, 0xe2bbe2bb, 0xe2bbe2bb, 0x2f5ee2bb, - 0xe2bb2ff9, 0x6079e2bb, -}; - -static ulong patch_2F00[] = { - 0x30303030, 0x3e3e3030, 0xaf79b9b3, 0xbaa3b979, - 0x9693369f, 0x79f79777, 0x97333fff, 0xfb3b9e9f, - 0x79b91d11, 0x9e13f3ff, 0x3f9b6bd9, 0xe173d136, - 0x695669d1, 0x697b3daf, 0x79b93a3a, 0x3f979f91, - 0x379ff976, 0xf99777fd, 0x9779737d, 0xe9d6bbf9, - 0xbfffd9df, 0x97f7fd97, 0x6f7b9bff, 0xf9bd9683, - 0x397db973, 0xd97b3b9f, 0xd7f9f733, 0x9993bb9e, - 0xe1f9ef93, 0x73773337, 0xb936917d, 0x11f87379, - 0xb979d336, 0x8b7ded73, 0x1b7d9337, 0x31f3f22f, - 0x3f2327ee, 0xeeeeeeee, 0xeeeeeeee, 0xeeeeeeee, - 0xeeeeee4b, 0xf4fbdbd2, 0x58bb1878, 0x577fdfd2, - 0xd573b773, 0xf7374b4f, 0xbdbd25b8, 0xb177d2d1, - 0x7376856b, 0xbfdd687b, 0xdd2fff8f, 0x78ffff8f, - 0xf22f0000, -}; -#endif - -static void UcodeCopy (volatile cpm8xx_t *cpm) -{ - vu_long *p; - int i; - - p = (vu_long *)&(cpm->cp_dpmem[0x0000]); - for (i=0; i < sizeof(patch_2000)/4; ++i) { - p[i] = patch_2000[i]; - } - - p = (vu_long *)&(cpm->cp_dpmem[0x0F00]); - for (i=0; i < sizeof(patch_2F00)/4; ++i) { - p[i] = patch_2F00[i]; - } -} - -#endif /* CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_SPI_UCODE_PATCH */ diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c deleted file mode 100644 index c35406d..0000000 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ /dev/null @@ -1,1123 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * (C) Copyright 2002 - * Wolfgang Denk, wd@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* #define DEBUG */ - -/************************************************************************/ -/* ** HEADER FILES */ -/************************************************************************/ - -#include <stdarg.h> -#include <common.h> -#include <config.h> -#include <version.h> -#include <i2c.h> -#include <linux/types.h> -#include <stdio_dev.h> - -#ifdef CONFIG_VIDEO - -DECLARE_GLOBAL_DATA_PTR; - -/************************************************************************/ -/* ** DEBUG SETTINGS */ -/************************************************************************/ - -#if 0 -#define VIDEO_DEBUG_COLORBARS /* Force colorbars output */ -#endif - -/************************************************************************/ -/* ** VIDEO MODE SETTINGS */ -/************************************************************************/ - -#if 0 -#define VIDEO_MODE_EXTENDED /* Allow screen size bigger than visible area */ -#define VIDEO_MODE_NTSC -#endif - -#define VIDEO_MODE_PAL - -#if 0 -#define VIDEO_BLINK /* This enables cursor blinking (under construction) */ -#endif - -#define VIDEO_INFO /* Show U-Boot information */ -#define VIDEO_INFO_X VIDEO_LOGO_WIDTH+8 -#define VIDEO_INFO_Y 16 - -/************************************************************************/ -/* ** VIDEO MODE CONSTANTS */ -/************************************************************************/ - -#ifdef VIDEO_MODE_EXTENDED -#define VIDEO_COLS VIDEO_ACTIVE_COLS -#define VIDEO_ROWS VIDEO_ACTIVE_ROWS -#else -#define VIDEO_COLS VIDEO_VISIBLE_COLS -#define VIDEO_ROWS VIDEO_VISIBLE_ROWS -#endif - -#define VIDEO_PIXEL_SIZE (VIDEO_MODE_BPP/8) -#define VIDEO_SIZE (VIDEO_ROWS*VIDEO_COLS*VIDEO_PIXEL_SIZE) /* Total size of buffer */ -#define VIDEO_PIX_BLOCKS (VIDEO_SIZE >> 2) /* Number of ints */ -#define VIDEO_LINE_LEN (VIDEO_COLS*VIDEO_PIXEL_SIZE) /* Number of bytes per line */ -#define VIDEO_BURST_LEN (VIDEO_COLS/8) - -#ifdef VIDEO_MODE_YUYV -#define VIDEO_BG_COL 0x80D880D8 /* Background color in YUYV format */ -#else -#define VIDEO_BG_COL 0xF8F8F8F8 /* Background color in RGB format */ -#endif - -/************************************************************************/ -/* ** FONT AND LOGO DATA */ -/************************************************************************/ - -#include <video_font.h> /* Get font data, width and height */ - -#ifdef CONFIG_VIDEO_LOGO -#include <video_logo.h> /* Get logo data, width and height */ - -#define VIDEO_LOGO_WIDTH DEF_U_BOOT_LOGO_WIDTH -#define VIDEO_LOGO_HEIGHT DEF_U_BOOT_LOGO_HEIGHT -#define VIDEO_LOGO_ADDR &u_boot_logo -#endif - -/************************************************************************/ -/* ** VIDEO CONTROLLER CONSTANTS */ -/************************************************************************/ - -/* VCCR - VIDEO CONTROLLER CONFIGURATION REGISTER */ - -#define VIDEO_VCCR_VON 0 /* Video controller ON */ -#define VIDEO_VCCR_CSRC 1 /* Clock source */ -#define VIDEO_VCCR_PDF 13 /* Pixel display format */ -#define VIDEO_VCCR_IEN 11 /* Interrupt enable */ - -/* VSR - VIDEO STATUS REGISTER */ - -#define VIDEO_VSR_CAS 6 /* Active set */ -#define VIDEO_VSR_EOF 0 /* End of frame */ - -/* VCMR - VIDEO COMMAND REGISTER */ - -#define VIDEO_VCMR_BD 0 /* Blank display */ -#define VIDEO_VCMR_ASEL 1 /* Active set selection */ - -/* VBCB - VIDEO BACKGROUND COLOR BUFFER REGISTER */ - -#define VIDEO_BCSR4_RESET_BIT 21 /* BCSR4 - Extern video encoder reset */ -#define VIDEO_BCSR4_EXTCLK_BIT 22 /* BCSR4 - Extern clock enable */ -#define VIDEO_BCSR4_VIDLED_BIT 23 /* BCSR4 - Video led disable */ - -/************************************************************************/ -/* ** CONSOLE CONSTANTS */ -/************************************************************************/ - -#ifdef CONFIG_VIDEO_LOGO -#define CONSOLE_ROWS ((VIDEO_ROWS - VIDEO_LOGO_HEIGHT) / VIDEO_FONT_HEIGHT) -#define VIDEO_LOGO_SKIP (VIDEO_COLS - VIDEO_LOGO_WIDTH) -#else -#define CONSOLE_ROWS (VIDEO_ROWS / VIDEO_FONT_HEIGHT) -#endif - -#define CONSOLE_COLS (VIDEO_COLS / VIDEO_FONT_WIDTH) -#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN) -#define CONSOLE_ROW_FIRST (video_console_address) -#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE) -#define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE) -#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) -#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) - -/* - * Simple color definitions - */ -#define CONSOLE_COLOR_BLACK 0 -#define CONSOLE_COLOR_RED 1 -#define CONSOLE_COLOR_GREEN 2 -#define CONSOLE_COLOR_YELLOW 3 -#define CONSOLE_COLOR_BLUE 4 -#define CONSOLE_COLOR_MAGENTA 5 -#define CONSOLE_COLOR_CYAN 6 -#define CONSOLE_COLOR_GREY 13 -#define CONSOLE_COLOR_GREY2 14 -#define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ - -/************************************************************************/ -/* ** BITOPS MACROS */ -/************************************************************************/ - -#define HISHORT(i) ((i >> 16)&0xffff) -#define LOSHORT(i) (i & 0xffff) -#define HICHAR(s) ((i >> 8)&0xff) -#define LOCHAR(s) (i & 0xff) -#define HI(c) ((c >> 4)&0xf) -#define LO(c) (c & 0xf) -#define SWAPINT(i) (HISHORT(i) | (LOSHORT(i) << 16)) -#define SWAPSHORT(s) (HICHAR(s) | (LOCHAR(s) << 8)) -#define SWAPCHAR(c) (HI(c) | (LO(c) << 4)) -#define BITMASK(b) (1 << (b)) -#define GETBIT(v,b) (((v) & BITMASK(b)) > 0) -#define SETBIT(v,b,d) (v = (((d)>0) ? (v) | BITMASK(b): (v) & ~BITMASK(b))) - -/************************************************************************/ -/* ** STRUCTURES */ -/************************************************************************/ - -typedef struct { - unsigned char V, Y1, U, Y2; -} tYUYV; - -/* This structure is based on the Video Ram in the MPC823. */ -typedef struct VRAM { - unsigned hx:2, /* Horizontal sync */ - vx:2, /* Vertical sync */ - fx:2, /* Frame */ - bx:2, /* Blank */ - res1:6, /* Reserved */ - vds:2, /* Video Data Select */ - inter:1, /* Interrupt */ - res2:2, /* Reserved */ - lcyc:11, /* Loop/video cycles */ - lp:1, /* Loop start/end */ - lst:1; /* Last entry */ -} VRAM; - -/************************************************************************/ -/* ** VARIABLES */ -/************************************************************************/ - -static int - video_panning_range_x = 0, /* Video mode invisible pixels x range */ - video_panning_range_y = 0, /* Video mode invisible pixels y range */ - video_panning_value_x = 0, /* Video mode x panning value (absolute) */ - video_panning_value_y = 0, /* Video mode y panning value (absolute) */ - video_panning_factor_x = 0, /* Video mode x panning value (-127 +127) */ - video_panning_factor_y = 0, /* Video mode y panning value (-127 +127) */ - console_col = 0, /* Cursor col */ - console_row = 0, /* Cursor row */ - video_palette[16]; /* Our palette */ - -static const int video_font_draw_table[] = - { 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff }; - -static char - video_color_fg = 0, /* Current fg color index (0-15) */ - video_color_bg = 0, /* Current bg color index (0-15) */ - video_enable = 0; /* Video has been initialized? */ - -static void - *video_fb_address, /* Frame buffer address */ - *video_console_address; /* Console frame buffer start address */ - -/************************************************************************/ -/* ** MEMORY FUNCTIONS (32bit) */ -/************************************************************************/ - -static void memsetl (int *p, int c, int v) -{ - while (c--) - *(p++) = v; -} - -static void memcpyl (int *d, int *s, int c) -{ - while (c--) - *(d++) = *(s++); -} - -/************************************************************************/ -/* ** VIDEO DRAWING AND COLOR FUNCTIONS */ -/************************************************************************/ - -static int video_maprgb (int r, int g, int b) -{ -#ifdef VIDEO_MODE_YUYV - unsigned int pR, pG, pB; - tYUYV YUYV; - unsigned int *ret = (unsigned int *) &YUYV; - - /* Transform (0-255) components to (0-100) */ - - pR = r * 100 / 255; - pG = g * 100 / 255; - pB = b * 100 / 255; - - /* Calculate YUV values (0-255) from RGB beetween 0-100 */ - - YUYV.Y1 = YUYV.Y2 = 209 * (pR + pG + pB) / 300 + 16; - YUYV.U = pR - (pG * 3 / 4) - (pB / 4) + 128; - YUYV.V = pB - (pR / 4) - (pG * 3 / 4) + 128; - return *ret; -#endif -#ifdef VIDEO_MODE_RGB - return ((r >> 3) << 11) | ((g > 2) << 6) | (b >> 3); -#endif -} - -static void video_setpalette (int color, int r, int g, int b) -{ - color &= 0xf; - - video_palette[color] = video_maprgb (r, g, b); - - /* Swap values if our panning offset is odd */ - if (video_panning_value_x & 1) - video_palette[color] = SWAPINT (video_palette[color]); -} - -static void video_fill (int color) -{ - memsetl (video_fb_address, VIDEO_PIX_BLOCKS, color); -} - -static void video_setfgcolor (int i) -{ - video_color_fg = i & 0xf; -} - -static void video_setbgcolor (int i) -{ - video_color_bg = i & 0xf; -} - -static int video_pickcolor (int i) -{ - return video_palette[i & 0xf]; -} - -/* Absolute console plotting functions */ - -#ifdef VIDEO_BLINK -static void video_revchar (int xx, int yy) -{ - int rows; - u8 *dest; - - dest = video_fb_address + yy * VIDEO_LINE_LEN + xx * 2; - - for (rows = VIDEO_FONT_HEIGHT; rows--; dest += VIDEO_LINE_LEN) { - switch (VIDEO_FONT_WIDTH) { - case 16: - ((u32 *) dest)[6] ^= 0xffffffff; - ((u32 *) dest)[7] ^= 0xffffffff; - /* FALL THROUGH */ - case 12: - ((u32 *) dest)[4] ^= 0xffffffff; - ((u32 *) dest)[5] ^= 0xffffffff; - /* FALL THROUGH */ - case 8: - ((u32 *) dest)[2] ^= 0xffffffff; - ((u32 *) dest)[3] ^= 0xffffffff; - /* FALL THROUGH */ - case 4: - ((u32 *) dest)[0] ^= 0xffffffff; - ((u32 *) dest)[1] ^= 0xffffffff; - } - } -} -#endif - -static void video_drawchars (int xx, int yy, unsigned char *s, int count) -{ - u8 *cdat, *dest, *dest0; - int rows, offset, c; - u32 eorx, fgx, bgx; - - offset = yy * VIDEO_LINE_LEN + xx * 2; - dest0 = video_fb_address + offset; - - fgx = video_pickcolor (video_color_fg); - bgx = video_pickcolor (video_color_bg); - - if (xx & 1) { - fgx = SWAPINT (fgx); - bgx = SWAPINT (bgx); - } - - eorx = fgx ^ bgx; - - switch (VIDEO_FONT_WIDTH) { - case 4: - case 8: - while (count--) { - c = *s; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; - dest += VIDEO_LINE_LEN) { - u8 bits = *cdat++; - - ((u32 *) dest)[0] = - (video_font_draw_table[bits >> 6] & eorx) ^ bgx; - ((u32 *) dest)[1] = - (video_font_draw_table[bits >> 4 & 3] & eorx) ^ bgx; - if (VIDEO_FONT_WIDTH == 8) { - ((u32 *) dest)[2] = - (video_font_draw_table[bits >> 2 & 3] & eorx) ^ bgx; - ((u32 *) dest)[3] = - (video_font_draw_table[bits & 3] & eorx) ^ bgx; - } - } - dest0 += VIDEO_FONT_WIDTH * 2; - s++; - } - break; - case 12: - case 16: - while (count--) { - cdat = video_fontdata + (*s) * (VIDEO_FONT_HEIGHT << 1); - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; - dest += VIDEO_LINE_LEN) { - u8 bits = *cdat++; - - ((u32 *) dest)[0] = - (video_font_draw_table[bits >> 6] & eorx) ^ bgx; - ((u32 *) dest)[1] = - (video_font_draw_table[bits >> 4 & 3] & eorx) ^ bgx; - ((u32 *) dest)[2] = - (video_font_draw_table[bits >> 2 & 3] & eorx) ^ bgx; - ((u32 *) dest)[3] = - (video_font_draw_table[bits & 3] & eorx) ^ bgx; - bits = *cdat++; - ((u32 *) dest)[4] = - (video_font_draw_table[bits >> 6] & eorx) ^ bgx; - ((u32 *) dest)[5] = - (video_font_draw_table[bits >> 4 & 3] & eorx) ^ bgx; - if (VIDEO_FONT_WIDTH == 16) { - ((u32 *) dest)[6] = - (video_font_draw_table[bits >> 2 & 3] & eorx) ^ bgx; - ((u32 *) dest)[7] = - (video_font_draw_table[bits & 3] & eorx) ^ bgx; - } - } - s++; - dest0 += VIDEO_FONT_WIDTH * 2; - } - break; - } -} - -static inline void video_drawstring (int xx, int yy, char *s) -{ - video_drawchars (xx, yy, (unsigned char *)s, strlen (s)); -} - -/* Relative to console plotting functions */ - -static void video_putchars (int xx, int yy, unsigned char *s, int count) -{ -#ifdef CONFIG_VIDEO_LOGO - video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, s, count); -#else - video_drawchars (xx, yy, s, count); -#endif -} - -static void video_putchar (int xx, int yy, unsigned char c) -{ -#ifdef CONFIG_VIDEO_LOGO - video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, &c, 1); -#else - video_drawchars (xx, yy, &c, 1); -#endif -} - -static inline void video_putstring (int xx, int yy, unsigned char *s) -{ - video_putchars (xx, yy, (unsigned char *)s, strlen ((char *)s)); -} - -/************************************************************************/ -/* ** VIDEO CONTROLLER LOW-LEVEL FUNCTIONS */ -/************************************************************************/ - -static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries) -{ - int i; - - for (i = 0; i < entries; i++) { - dest[i] = source[i]; /* Copy the entire record */ - dest[i].fx = (!dest[i].fx) * 3; /* Negate field bit */ - } - - dest[0].lcyc++; /* Add a cycle to the first entry */ - dest[entries - 1].lst = 1; /* Set end of ram entries */ -} - -static void inline video_mode_addentry (VRAM * vr, - int Hx, int Vx, int Fx, int Bx, - int VDS, int INT, int LCYC, int LP, int LST) -{ - vr->hx = Hx; - vr->vx = Vx; - vr->fx = Fx; - vr->bx = Bx; - vr->vds = VDS; - vr->inter = INT; - vr->lcyc = LCYC; - vr->lp = LP; - vr->lst = LST; -} - -#define ADDENTRY(a,b,c,d,e,f,g,h,i) video_mode_addentry(&vr[entry++],a,b,c,d,e,f,g,h,i) - -static int video_mode_generate (void) -{ - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - VRAM *vr = (VRAM *) (((void *) immap) + 0xb00); /* Pointer to the VRAM table */ - int DX, X1, X2, DY, Y1, Y2, entry = 0, fifo; - - /* CHECKING PARAMETERS */ - - if (video_panning_factor_y < -128) - video_panning_factor_y = -128; - - if (video_panning_factor_y > 128) - video_panning_factor_y = 128; - - if (video_panning_factor_x < -128) - video_panning_factor_x = -128; - - if (video_panning_factor_x > 128) - video_panning_factor_x = 128; - - /* Setting panning */ - - DX = video_panning_range_x = (VIDEO_ACTIVE_COLS - VIDEO_COLS) * 2; - DY = video_panning_range_y = (VIDEO_ACTIVE_ROWS - VIDEO_ROWS) / 2; - - video_panning_value_x = (video_panning_factor_x + 128) * DX / 256; - video_panning_value_y = (video_panning_factor_y + 128) * DY / 256; - - /* We assume these are burst units (multiplied by 2, we need it pari) */ - X1 = video_panning_value_x & 0xfffe; - X2 = DX - X1; - - /* We assume these are field line units (divided by 2, we need it pari) */ - Y1 = video_panning_value_y & 0xfffe; - Y2 = DY - Y1; - - debug("X1=%d, X2=%d, Y1=%d, Y2=%d, DX=%d, DY=%d VIDEO_COLS=%d \n", - X1, X2, Y1, Y2, DX, DY, VIDEO_COLS); - -#ifdef VIDEO_MODE_NTSC -/* - * Hx Vx Fx Bx VDS INT LCYC LP LST - * - * Retrace blanking - */ - ADDENTRY (0, 0, 3, 0, 1, 0, 3, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); -/* - * Vertical blanking - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 18, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); -/* - * Odd field active area (TOP) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 0, 0, 1, 0, Y1, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); - } -/* - * Odd field active area - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 240 - DY, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 8 + X1, 0, 0); - ADDENTRY (3, 0, 0, 3, 0, 0, VIDEO_COLS * 2, 0, 0); - - if (X2 > 0) - ADDENTRY (3, 0, 0, 3, 1, 0, X2, 0, 0); - - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); - -/* - * Odd field active area (BOTTOM) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 0, 0, 1, 0, Y2, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); - } -/* - * Vertical blanking - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 4, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); -/* - * Vertical blanking - */ - ADDENTRY (0, 0, 3, 0, 1, 0, 19, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); -/* - * Even field active area (TOP) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 3, 0, 1, 0, Y1, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 3, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); - } -/* - * Even field active area (CENTER) - */ - ADDENTRY (0, 0, 3, 0, 1, 0, 240 - DY, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 3, 3, 1, 0, 8 + X1, 0, 0); - ADDENTRY (3, 0, 3, 3, 0, 0, VIDEO_COLS * 2, 0, 0); - - if (X2 > 0) - ADDENTRY (3, 0, 3, 3, 1, 0, X2, 0, 0); - - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); -/* - * Even field active area (BOTTOM) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 3, 0, 1, 0, Y2, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 3, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); - } -/* - * Vertical blanking - */ - ADDENTRY (0, 0, 3, 0, 1, 0, 1, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 1, 32, 1, 1); -#endif - -#ifdef VIDEO_MODE_PAL - -/* - * Hx Vx Fx Bx VDS INT LCYC LP LST - * - * vertical; blanking - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 22, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 263, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); -/* - * active area (TOP) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 0, 0, 1, 0, Y1, 1, 0); /* 11? */ - ADDENTRY (3, 0, 0, 0, 1, 0, 255, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); - } -/* - * field active area (CENTER) - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 288 - DY, 1, 0); /* 265? */ - ADDENTRY (3, 0, 0, 0, 1, 0, 255, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 8 + X1, 0, 0); - ADDENTRY (3, 0, 0, 3, 0, 0, VIDEO_COLS * 2, 0, 0); - - if (X2 > 0) - ADDENTRY (3, 0, 0, 1, 1, 0, X2, 0, 0); - - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); -/* - * field active area (BOTTOM) - */ - if (Y2 > 0) { - ADDENTRY (0, 0, 0, 0, 1, 0, Y2, 1, 0); /* 12? */ - ADDENTRY (3, 0, 0, 0, 1, 0, 255, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); - } -/* - * field vertical; blanking - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 2, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 263, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); -/* - * Create the other field (like this, but whit other field selected, - * one more cycle loop and a last identifier) - */ - video_mode_dupefield (vr, &vr[entry], entry); - -#endif /* VIDEO_MODE_PAL */ - - /* See what FIFO are we using */ - fifo = GETBIT (immap->im_vid.vid_vsr, VIDEO_VSR_CAS); - - /* Set number of lines and burst (only one frame for now) */ - if (fifo) { - immap->im_vid.vid_vfcr0 = VIDEO_BURST_LEN | - (VIDEO_BURST_LEN << 8) | ((VIDEO_ROWS / 2) << 19); - } else { - immap->im_vid.vid_vfcr1 = VIDEO_BURST_LEN | - (VIDEO_BURST_LEN << 8) | ((VIDEO_ROWS / 2) << 19); - } - - SETBIT (immap->im_vid.vid_vcmr, VIDEO_VCMR_ASEL, !fifo); - -/* - * Wait until changes are applied (not done) - * while (GETBIT(immap->im_vid.vid_vsr, VIDEO_VSR_CAS) == fifo) ; - */ - - /* Return number of VRAM entries */ - return entry * 2; -} - -static void video_encoder_init (void) -{ - return; -} - -static void video_ctrl_init (void *memptr) -{ - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - video_fb_address = memptr; - - /* Set background */ - debug ("[VIDEO CTRL] Setting background color...\n"); - immap->im_vid.vid_vbcb = VIDEO_BG_COL; - - /* Show the background */ - debug ("[VIDEO CTRL] Forcing background...\n"); - SETBIT (immap->im_vid.vid_vcmr, VIDEO_VCMR_BD, 1); - - /* Turn off video controller */ - debug ("[VIDEO CTRL] Turning off video controller...\n"); - SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 0); - - /* Generate and make active a new video mode */ - debug ("[VIDEO CTRL] Generating video mode...\n"); - video_mode_generate (); - - /* Start of frame buffer (even and odd frame, to make it working with */ - /* any selected active set) */ - debug ("[VIDEO CTRL] Setting frame buffer address...\n"); - immap->im_vid.vid_vfaa1 = - immap->im_vid.vid_vfaa0 = (u32) video_fb_address; - immap->im_vid.vid_vfba1 = - immap->im_vid.vid_vfba0 = - (u32) video_fb_address + VIDEO_LINE_LEN; - - /* YUV, Big endian, SHIFT/CLK/CLK input (BEFORE ENABLING 27MHZ EXT CLOCK) */ - debug ("[VIDEO CTRL] Setting pixel mode and clocks...\n"); - immap->im_vid.vid_vccr = 0x2042; - - /* Configure port pins */ - debug ("[VIDEO CTRL] Configuring input/output pins...\n"); - immap->im_ioport.iop_pdpar = 0x1fff; - immap->im_ioport.iop_pddir = 0x0000; - - /* Blanking the screen. */ - debug ("[VIDEO CTRL] Blanking the screen...\n"); - video_fill (VIDEO_BG_COL); - - /* - * Turns on Aggressive Mode. Normally, turning on the caches - * will cause the screen to flicker when the caches try to - * fill. This gives the FIFO's for the Video Controller - * higher priority and prevents flickering because of - * underrun. This may still be an issue when using FLASH, - * since accessing data from Flash is so slow. - */ - debug ("[VIDEO CTRL] Turning on aggressive mode...\n"); - immap->im_siu_conf.sc_sdcr = 0x40; - - /* Turn on video controller */ - debug ("[VIDEO CTRL] Turning on video controller...\n"); - SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 1); - - /* Show the display */ - debug ("[VIDEO CTRL] Enabling the video...\n"); - SETBIT (immap->im_vid.vid_vcmr, VIDEO_VCMR_BD, 0); -} - -/************************************************************************/ -/* ** CONSOLE FUNCTIONS */ -/************************************************************************/ - -static void console_scrollup (void) -{ - /* Copy up rows ignoring the first one */ - memcpyl (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE >> 2); - - /* Clear the last one */ - memsetl (CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, VIDEO_BG_COL); -} - -static inline void console_back (void) -{ - console_col--; - - if (console_col < 0) { - console_col = CONSOLE_COLS - 1; - console_row--; - if (console_row < 0) - console_row = 0; - } - - video_putchar ( console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, ' '); -} - -static inline void console_newline (void) -{ - console_row++; - console_col = 0; - - /* Check if we need to scroll the terminal */ - if (console_row >= CONSOLE_ROWS) { - /* Scroll everything up */ - console_scrollup (); - - /* Decrement row number */ - console_row--; - } -} - -void video_putc(struct stdio_dev *dev, const char c) -{ - if (!video_enable) { - serial_putc (c); - return; - } - - switch (c) { - case 13: /* Simply ignore this */ - break; - - case '\n': /* Next line, please */ - console_newline (); - break; - - case 9: /* Tab (8 chars alignment) */ - console_col |= 0x0008; /* Next 8 chars boundary */ - console_col &= ~0x0007; /* Set this bit to zero */ - - if (console_col >= CONSOLE_COLS) - console_newline (); - break; - - case 8: /* Eat last character */ - console_back (); - break; - - default: /* Add to the console */ - video_putchar ( console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, c); - console_col++; - /* Check if we need to go to next row */ - if (console_col >= CONSOLE_COLS) - console_newline (); - } -} - -void video_puts(struct stdio_dev *dev, const char *s) -{ - int count = strlen (s); - - if (!video_enable) - while (count--) - serial_putc (*s++); - else - while (count--) - video_putc(dev, *s++); -} - -/************************************************************************/ -/* ** CURSOR BLINKING FUNCTIONS */ -/************************************************************************/ - -#ifdef VIDEO_BLINK - -#define BLINK_TIMER_ID 0 -#define BLINK_TIMER_HZ 2 - -static unsigned char blink_enabled = 0; -static timer_t blink_timer; - -static void blink_update (void) -{ - static int blink_row = -1, blink_col = -1, blink_old = 0; - - /* Check if we have a new position to invert */ - if ((console_row != blink_row) || (console_col != blink_col)) { - /* Check if we need to reverse last character */ - if (blink_old) - video_revchar ( blink_col * VIDEO_FONT_WIDTH, - (blink_row -#ifdef CONFIG_VIDEO_LOGO - + VIDEO_LOGO_HEIGHT -#endif - ) * VIDEO_FONT_HEIGHT); - - /* Update values */ - blink_row = console_row; - blink_col = console_col; - blink_old = 0; - } - -/* Reverse this character */ - blink_old = !blink_old; - video_revchar ( console_col * VIDEO_FONT_WIDTH, - (console_row -#ifdef CONFIG_VIDEO_LOGO - + VIDEO_LOGO_HEIGHT -#endif - ) * VIDEO_FONT_HEIGHT); - -} - -/* - * Handler for blinking cursor - */ -static void blink_handler (void *arg) -{ -/* Blink */ - blink_update (); -/* Ack the timer */ - timer_ack (&blink_timer); -} - -int blink_set (int blink) -{ - int ret = blink_enabled; - - if (blink) - timer_enable (&blink_timer); - else - timer_disable (&blink_timer); - - blink_enabled = blink; - - return ret; -} - -static inline void blink_close (void) -{ - timer_close (&blink_timer); -} - -static inline void blink_init (void) -{ - timer_init (&blink_timer, - BLINK_TIMER_ID, BLINK_TIMER_HZ, - blink_handler); -} -#endif - -/************************************************************************/ -/* ** LOGO PLOTTING FUNCTIONS */ -/************************************************************************/ - -#ifdef CONFIG_VIDEO_LOGO -void easylogo_plot (fastimage_t * image, void *screen, int width, int x, - int y) -{ - int skip = width - image->width, xcount, ycount = image->height; - -#ifdef VIDEO_MODE_YUYV - ushort *source = (ushort *) image->data; - ushort *dest = (ushort *) screen + y * width + x; - - while (ycount--) { - xcount = image->width; - while (xcount--) - *dest++ = *source++; - dest += skip; - } -#endif -#ifdef VIDEO_MODE_RGB - unsigned char - *source = (unsigned short *) image->data, - *dest = (unsigned short *) screen + ((y * width) + x) * 3; - - while (ycount--) { - xcount = image->width * 3; - memcpy (dest, source, xcount); - source += xcount; - dest += ycount; - } -#endif -} - -static void *video_logo (void) -{ - u16 *screen = video_fb_address, width = VIDEO_COLS; -#ifdef VIDEO_INFO - char temp[32]; - char info[80]; -#endif /* VIDEO_INFO */ - - easylogo_plot (VIDEO_LOGO_ADDR, screen, width, 0, 0); - -#ifdef VIDEO_INFO - sprintf (info, "%s (%s - %s) ", - U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info); - - strcpy(info, "(C) 2002 DENX Software Engineering"); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, - info); - - strcpy(info, " Wolfgang DENK, wd@denx.de"); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, - info); - - /* leave one blank line */ - - sprintf(info, "MPC823 CPU at %s MHz, %ld MiB RAM, %ld MiB Flash", - strmhz(temp, gd->cpu_clk), - gd->ram_size >> 20, - gd->bd->bi_flashsize >> 20 ); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 4, - info); -#endif - - return video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN; -} -#endif - -/************************************************************************/ -/* ** VIDEO HIGH-LEVEL FUNCTIONS */ -/************************************************************************/ - -static int video_init (void *videobase) -{ - /* Initialize the encoder */ - debug ("[VIDEO] Initializing video encoder...\n"); - video_encoder_init (); - - /* Initialize the video controller */ - debug ("[VIDEO] Initializing video controller at %08x...\n", - (int) videobase); - video_ctrl_init (videobase); - - /* Setting the palette */ - video_setpalette (CONSOLE_COLOR_BLACK, 0, 0, 0); - video_setpalette (CONSOLE_COLOR_RED, 0xFF, 0, 0); - video_setpalette (CONSOLE_COLOR_GREEN, 0, 0xFF, 0); - video_setpalette (CONSOLE_COLOR_YELLOW, 0xFF, 0xFF, 0); - video_setpalette (CONSOLE_COLOR_BLUE, 0, 0, 0xFF); - video_setpalette (CONSOLE_COLOR_MAGENTA, 0xFF, 0, 0xFF); - video_setpalette (CONSOLE_COLOR_CYAN, 0, 0xFF, 0xFF); - video_setpalette (CONSOLE_COLOR_GREY, 0xAA, 0xAA, 0xAA); - video_setpalette (CONSOLE_COLOR_GREY2, 0xF8, 0xF8, 0xF8); - video_setpalette (CONSOLE_COLOR_WHITE, 0xFF, 0xFF, 0xFF); - -#ifndef CONFIG_SYS_WHITE_ON_BLACK - video_setfgcolor (CONSOLE_COLOR_BLACK); - video_setbgcolor (CONSOLE_COLOR_GREY2); -#else - video_setfgcolor (CONSOLE_COLOR_GREY2); - video_setbgcolor (CONSOLE_COLOR_BLACK); -#endif /* CONFIG_SYS_WHITE_ON_BLACK */ - -#ifdef CONFIG_VIDEO_LOGO - /* Paint the logo and retrieve tv base address */ - debug ("[VIDEO] Drawing the logo...\n"); - video_console_address = video_logo (); -#else - video_console_address = video_fb_address; -#endif - -#ifdef VIDEO_BLINK - /* Enable the blinking (under construction) */ - blink_init (); - blink_set (0); /* To Fix! */ -#endif - - /* Initialize the console */ - console_col = 0; - console_row = 0; - video_enable = 1; - -#ifdef VIDEO_MODE_PAL -# define VIDEO_MODE_TMP1 "PAL" -#endif -#ifdef VIDEO_MODE_NTSC -# define VIDEO_MODE_TMP1 "NTSC" -#endif -#ifdef VIDEO_MODE_YUYV -# define VIDEO_MODE_TMP2 "YCbYCr" -#endif -#ifdef VIDEO_MODE_RGB -# define VIDEO_MODE_TMP2 "RGB" -#endif - debug ( VIDEO_MODE_TMP1 - " %dx%dx%d (" VIDEO_MODE_TMP2 ") on %s - console %dx%d\n", - VIDEO_COLS, VIDEO_ROWS, VIDEO_MODE_BPP, - VIDEO_ENCODER_NAME, CONSOLE_COLS, CONSOLE_ROWS); - return 0; -} - -int drv_video_init (void) -{ - int error, devices = 1; - - struct stdio_dev videodev; - - video_init ((void *)(gd->fb_base)); /* Video initialization */ - -/* Device initialization */ - - memset (&videodev, 0, sizeof (videodev)); - - strcpy (videodev.name, "video"); - videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */ - videodev.putc = video_putc; /* 'putc' function */ - videodev.puts = video_puts; /* 'puts' function */ - - error = stdio_register (&videodev); - - return (error == 0) ? devices : error; -} - -/************************************************************************/ -/* ** ROM capable initialization part - needed to reserve FB memory */ -/************************************************************************/ - -/* - * This is called early in the system initialization to grab memory - * for the video controller. - * Returns new address for monitor, after reserving video buffer memory - * - * Note that this is running from ROM, so no write access to global data. - */ -ulong video_setmem (ulong addr) -{ - /* Allocate pages for the frame buffer. */ - addr -= VIDEO_SIZE; - - debug ("Reserving %dk for Video Framebuffer at: %08lx\n", - VIDEO_SIZE>>10, addr); - - return (addr); -} - -#endif diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c index c02058f..bca8393 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c @@ -9,7 +9,6 @@ */

#include <common.h> -#include <commproc.h> #include <asm/processor.h> #include <asm/io.h> #include <watchdog.h> diff --git a/arch/powerpc/cpu/ppc4xx/interrupts.c b/arch/powerpc/cpu/ppc4xx/interrupts.c index 45997d6..599f2c2 100644 --- a/arch/powerpc/cpu/ppc4xx/interrupts.c +++ b/arch/powerpc/cpu/ppc4xx/interrupts.c @@ -22,7 +22,6 @@ #include <asm/interrupt.h> #include <asm/ppc4xx.h> #include <ppc_asm.tmpl> -#include <commproc.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index aef267e..6273772 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -21,7 +21,6 @@ #include <asm/processor.h> #include <asm/io.h> #include <ppc_asm.tmpl> -#include <commproc.h> #include <asm/ppc4xx.h> #include <asm/ppc4xx-emac.h> #include <asm/ppc4xx-mal.h> diff --git a/arch/powerpc/cpu/ppc4xx/uic.c b/arch/powerpc/cpu/ppc4xx/uic.c index fb453b1..acc232d 100644 --- a/arch/powerpc/cpu/ppc4xx/uic.c +++ b/arch/powerpc/cpu/ppc4xx/uic.c @@ -22,7 +22,6 @@ #include <asm/interrupt.h> #include <asm/ppc4xx.h> #include <ppc_asm.tmpl> -#include <commproc.h>

#if (UIC_MAX > 3) #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ diff --git a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c index 1a2e917..acb933e 100644 --- a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c +++ b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c @@ -12,7 +12,6 @@ #include <asm/interrupt.h> #include <asm/ppc4xx.h> #include <ppc_asm.tmpl> -#include <commproc.h> #include <asm/io.h> #include <asm/xilinx_irq.h>

diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h deleted file mode 100644 index dfaddb6..0000000 --- a/arch/powerpc/include/asm/8xx_immap.h +++ /dev/null @@ -1,515 +0,0 @@ -/* - * MPC8xx Internal Memory Map - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * The I/O on the MPC860 is comprised of blocks of special registers - * and the dual port ram for the Communication Processor Module. - * Within this space are functional units such as the SIU, memory - * controller, system timers, and other control functions. It is - * a combination that I found difficult to separate into logical - * functional files.....but anyone else is welcome to try. -- Dan - */ -#ifndef __IMMAP_8XX__ -#define __IMMAP_8XX__ - -/* System configuration registers. -*/ -typedef struct sys_conf { - uint sc_siumcr; - uint sc_sypcr; - uint sc_swt; - char res1[2]; - ushort sc_swsr; - uint sc_sipend; - uint sc_simask; - uint sc_siel; - uint sc_sivec; - uint sc_tesr; - char res2[0xc]; - uint sc_sdcr; - char res3[0x4c]; -} sysconf8xx_t; - -/* PCMCIA configuration registers. -*/ -typedef struct pcmcia_conf { - uint pcmc_pbr0; - uint pcmc_por0; - uint pcmc_pbr1; - uint pcmc_por1; - uint pcmc_pbr2; - uint pcmc_por2; - uint pcmc_pbr3; - uint pcmc_por3; - uint pcmc_pbr4; - uint pcmc_por4; - uint pcmc_pbr5; - uint pcmc_por5; - uint pcmc_pbr6; - uint pcmc_por6; - uint pcmc_pbr7; - uint pcmc_por7; - char res1[0x20]; - uint pcmc_pgcra; - uint pcmc_pgcrb; - uint pcmc_pscr; - char res2[4]; - uint pcmc_pipr; - char res3[4]; - uint pcmc_per; - char res4[4]; -} pcmconf8xx_t; - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - uint memc_br0; - uint memc_or0; - uint memc_br1; - uint memc_or1; - uint memc_br2; - uint memc_or2; - uint memc_br3; - uint memc_or3; - uint memc_br4; - uint memc_or4; - uint memc_br5; - uint memc_or5; - uint memc_br6; - uint memc_or6; - uint memc_br7; - uint memc_or7; - char res1[0x24]; - uint memc_mar; - uint memc_mcr; - char res2[4]; - uint memc_mamr; - uint memc_mbmr; - ushort memc_mstat; - ushort memc_mptpr; - uint memc_mdr; - char res3[0x80]; -} memctl8xx_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - ushort sit_tbscr; - char res0[0x02]; - uint sit_tbreff0; - uint sit_tbreff1; - char res1[0x14]; - ushort sit_rtcsc; - char res2[0x02]; - uint sit_rtc; - uint sit_rtsec; - uint sit_rtcal; - char res3[0x10]; - ushort sit_piscr; - char res4[2]; - uint sit_pitc; - uint sit_pitr; - char res5[0x34]; -} sit8xx_t; - -#define TBSCR_TBIRQ_MASK ((ushort)0xff00) -#define TBSCR_REFA ((ushort)0x0080) -#define TBSCR_REFB ((ushort)0x0040) -#define TBSCR_REFAE ((ushort)0x0008) -#define TBSCR_REFBE ((ushort)0x0004) -#define TBSCR_TBF ((ushort)0x0002) -#define TBSCR_TBE ((ushort)0x0001) - -#define RTCSC_RTCIRQ_MASK ((ushort)0xff00) -#define RTCSC_SEC ((ushort)0x0080) -#define RTCSC_ALR ((ushort)0x0040) -#define RTCSC_38K ((ushort)0x0010) -#define RTCSC_SIE ((ushort)0x0008) -#define RTCSC_ALE ((ushort)0x0004) -#define RTCSC_RTF ((ushort)0x0002) -#define RTCSC_RTE ((ushort)0x0001) - -#define PISCR_PIRQ_MASK ((ushort)0xff00) -#define PISCR_PS ((ushort)0x0080) -#define PISCR_PIE ((ushort)0x0004) -#define PISCR_PTF ((ushort)0x0002) -#define PISCR_PTE ((ushort)0x0001) - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - uint car_sccr; - uint car_plprcr; - uint car_rsr; - char res[0x74]; /* Reserved area */ -} car8xx_t; - -/* System Integration Timers keys. -*/ -typedef struct sitk { - uint sitk_tbscrk; - uint sitk_tbreff0k; - uint sitk_tbreff1k; - uint sitk_tbk; - char res1[0x10]; - uint sitk_rtcsck; - uint sitk_rtck; - uint sitk_rtseck; - uint sitk_rtcalk; - char res2[0x10]; - uint sitk_piscrk; - uint sitk_pitck; - char res3[0x38]; -} sitk8xx_t; - -/* Clocks and reset keys. -*/ -typedef struct cark { - uint cark_sccrk; - uint cark_plprcrk; - uint cark_rsrk; - char res[0x474]; -} cark8xx_t; - -/* The key to unlock registers maintained by keep-alive power. -*/ -#define KAPWR_KEY ((unsigned int)0x55ccaa33) - -/* Video interface. MPC823 Only. -*/ -typedef struct vid823 { - ushort vid_vccr; - ushort res1; - u_char vid_vsr; - u_char res2; - u_char vid_vcmr; - u_char res3; - uint vid_vbcb; - uint res4; - uint vid_vfcr0; - uint vid_vfaa0; - uint vid_vfba0; - uint vid_vfcr1; - uint vid_vfaa1; - uint vid_vfba1; - u_char res5[0x18]; -} vid823_t; - -/* LCD interface. 823 Only. -*/ -typedef struct lcd { - uint lcd_lccr; - uint lcd_lchcr; - uint lcd_lcvcr; - char res1[4]; - uint lcd_lcfaa; - uint lcd_lcfba; - char lcd_lcsr; - char res2[0x7]; -} lcd823_t; - -/* I2C -*/ -typedef struct i2c { - u_char i2c_i2mod; - char res1[3]; - u_char i2c_i2add; - char res2[3]; - u_char i2c_i2brg; - char res3[3]; - u_char i2c_i2com; - char res4[3]; - u_char i2c_i2cer; - char res5[3]; - u_char i2c_i2cmr; - char res6[0x8b]; -} i2c8xx_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - char res1[4]; - uint sdma_sdar; - u_char sdma_sdsr; - char res3[3]; - u_char sdma_sdmr; - char res4[3]; - u_char sdma_idsr1; - char res5[3]; - u_char sdma_idmr1; - char res6[3]; - u_char sdma_idsr2; - char res7[3]; - u_char sdma_idmr2; - char res8[0x13]; -} sdma8xx_t; - -/* Communication Processor Module Interrupt Controller. -*/ -typedef struct cpm_ic { - ushort cpic_civr; - char res[0xe]; - uint cpic_cicr; - uint cpic_cipr; - uint cpic_cimr; - uint cpic_cisr; -} cpic8xx_t; - -/* Input/Output Port control/status registers. -*/ -typedef struct io_port { - ushort iop_padir; - ushort iop_papar; - ushort iop_paodr; - ushort iop_padat; - char res1[8]; - ushort iop_pcdir; - ushort iop_pcpar; - ushort iop_pcso; - ushort iop_pcdat; - ushort iop_pcint; - char res2[6]; - ushort iop_pddir; - ushort iop_pdpar; - char res3[2]; - ushort iop_pddat; - uint utmode; - char res4[4]; -} iop8xx_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - ushort cpmt_tgcr; - char res1[0xe]; - ushort cpmt_tmr1; - ushort cpmt_tmr2; - ushort cpmt_trr1; - ushort cpmt_trr2; - ushort cpmt_tcr1; - ushort cpmt_tcr2; - ushort cpmt_tcn1; - ushort cpmt_tcn2; - ushort cpmt_tmr3; - ushort cpmt_tmr4; - ushort cpmt_trr3; - ushort cpmt_trr4; - ushort cpmt_tcr3; - ushort cpmt_tcr4; - ushort cpmt_tcn3; - ushort cpmt_tcn4; - ushort cpmt_ter1; - ushort cpmt_ter2; - ushort cpmt_ter3; - ushort cpmt_ter4; - char res2[8]; -} cpmtimer8xx_t; - -/* Finally, the Communication Processor stuff..... -*/ -typedef struct scc { /* Serial communication channels */ - uint scc_gsmrl; - uint scc_gsmrh; - ushort scc_psmr; - char res1[2]; - ushort scc_todr; - ushort scc_dsr; - ushort scc_scce; - char res2[2]; - ushort scc_sccm; - char res3; - u_char scc_sccs; - char res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - char res1[2]; - ushort smc_smcmr; - char res2[2]; - u_char smc_smce; - char res3[3]; - u_char smc_smcm; - char res4[5]; -} smc_t; - -/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but - * it fits within the address space. - */ - -typedef struct fec { - uint fec_addr_low; /* lower 32 bits of station address */ - ushort fec_addr_high; /* upper 16 bits of station address */ - ushort res1; /* reserved */ - uint fec_hash_table_high; /* upper 32-bits of hash table */ - uint fec_hash_table_low; /* lower 32-bits of hash table */ - uint fec_r_des_start; /* beginning of Rx descriptor ring */ - uint fec_x_des_start; /* beginning of Tx descriptor ring */ - uint fec_r_buff_size; /* Rx buffer size */ - uint res2[9]; /* reserved */ - uint fec_ecntrl; /* ethernet control register */ - uint fec_ievent; /* interrupt event register */ - uint fec_imask; /* interrupt mask register */ - uint fec_ivec; /* interrupt level and vector status */ - uint fec_r_des_active; /* Rx ring updated flag */ - uint fec_x_des_active; /* Tx ring updated flag */ - uint res3[10]; /* reserved */ - uint fec_mii_data; /* MII data register */ - uint fec_mii_speed; /* MII speed control register */ - uint res4[17]; /* reserved */ - uint fec_r_bound; /* end of RAM (read-only) */ - uint fec_r_fstart; /* Rx FIFO start address */ - uint res5[6]; /* reserved */ - uint fec_x_fstart; /* Tx FIFO start address */ - uint res6[17]; /* reserved */ - uint fec_fun_code; /* fec SDMA function code */ - uint res7[3]; /* reserved */ - uint fec_r_cntrl; /* Rx control register */ - uint fec_r_hash; /* Rx hash register */ - uint res8[14]; /* reserved */ - uint fec_x_cntrl; /* Tx control register */ - uint res9[0x1e]; /* reserved */ -} fec_t; - -/* The FEC and LCD color map share the same address space.... - * I guess we will never see an 823T :-). - */ -union fec_lcd { - fec_t fl_un_fec; - u_char fl_un_cmap[0x200]; -}; - -typedef struct comm_proc { - /* General control and status registers. - */ - ushort cp_cpcr; - u_char res1[2]; - ushort cp_rccr; - u_char res2; - u_char cp_rmds; - u_char res3[4]; - ushort cp_cpmcr1; - ushort cp_cpmcr2; - ushort cp_cpmcr3; - ushort cp_cpmcr4; - u_char res4[2]; - ushort cp_rter; - u_char res5[2]; - ushort cp_rtmr; - u_char res6[0x14]; - - /* Baud rate generators. - */ - uint cp_brgc1; - uint cp_brgc2; - uint cp_brgc3; - uint cp_brgc4; - - /* Serial Communication Channels. - */ - scc_t cp_scc[4]; - - /* Serial Management Channels. - */ - smc_t cp_smc[2]; - - /* Serial Peripheral Interface. - */ - ushort cp_spmode; - u_char res7[4]; - u_char cp_spie; - u_char res8[3]; - u_char cp_spim; - u_char res9[2]; - u_char cp_spcom; - u_char res10[2]; - - /* Parallel Interface Port. - */ - u_char res11[2]; - ushort cp_pipc; - u_char res12[2]; - ushort cp_ptpr; - uint cp_pbdir; - uint cp_pbpar; - u_char res13[2]; - ushort cp_pbodr; - uint cp_pbdat; - - /* Port E - MPC87x/88x only. - */ - uint cp_pedir; - uint cp_pepar; - uint cp_peso; - uint cp_peodr; - uint cp_pedat; - - /* Communications Processor Timing Register - - Contains RMII Timing for the FECs on MPC87x/88x only. - */ - uint cp_cptr; - - /* Serial Interface and Time Slot Assignment. - */ - uint cp_simode; - u_char cp_sigmr; - u_char res15; - u_char cp_sistr; - u_char cp_sicmr; - u_char res16[4]; - uint cp_sicr; - uint cp_sirp; - u_char res17[0xc]; - - /* 256 bytes of MPC823 video controller RAM array. - */ - u_char cp_vcram[0x100]; - u_char cp_siram[0x200]; - - /* The fast ethernet controller is not really part of the CPM, - * but it resides in the address space. - * The LCD color map is also here. - */ - union fec_lcd fl_un; -#define cp_fec fl_un.fl_un_fec -#define lcd_cmap fl_un.fl_un_cmap - char res18[0xE00]; - - /* The MPC885 family has a second FEC here */ - fec_t cp_fec2; -#define cp_fec1 cp_fec /* consistency macro */ - - /* Dual Ported RAM follows. - * There are many different formats for this memory area - * depending upon the devices used and options chosen. - * Some processors don't have all of it populated. - */ - u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ - - /* Parameter RAM */ - union { - u_char cp_dparam[0x400]; - u16 cp_dparam16[0x200]; - }; -} cpm8xx_t; - -/* Internal memory map. -*/ -typedef struct immap { - sysconf8xx_t im_siu_conf; /* SIU Configuration */ - pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ - memctl8xx_t im_memctl; /* Memory Controller */ - sit8xx_t im_sit; /* System integration timers */ - car8xx_t im_clkrst; /* Clocks and reset */ - sitk8xx_t im_sitk; /* Sys int timer keys */ - cark8xx_t im_clkrstk; /* Clocks and reset keys */ - vid823_t im_vid; /* Video (823 only) */ - lcd823_t im_lcd; /* LCD (823 only) */ - i2c8xx_t im_i2c; /* I2C control/status */ - sdma8xx_t im_sdma; /* SDMA control/status */ - cpic8xx_t im_cpic; /* CPM Interrupt Controller */ - iop8xx_t im_ioport; /* IO Port control/status */ - cpmtimer8xx_t im_cpmtimer; /* CPM timers */ - cpm8xx_t im_cpm; /* Communication processor */ -} immap_t; - -#endif /* __IMMAP_8XX__ */ diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index d3a8391..20c52fc 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -7,9 +7,7 @@ #include <asm/processor.h>

/* bytes per L1 cache line */ -#if defined(CONFIG_8xx) -#define L1_CACHE_SHIFT 4 -#elif defined(CONFIG_PPC64BRIDGE) +#if defined(CONFIG_PPC64BRIDGE) #define L1_CACHE_SHIFT 7 #elif defined(CONFIG_E500MC) #define L1_CACHE_SHIFT 6 @@ -72,41 +70,4 @@ void disable_cpc_sram(void); #define L2CACHE_NONE 0x03 /* NONE */ #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */

-#ifdef CONFIG_8xx -/* Cache control on the MPC8xx is provided through some additional - * special purpose registers. - */ -#define IC_CST 560 /* Instruction cache control/status */ -#define IC_ADR 561 /* Address needed for some commands */ -#define IC_DAT 562 /* Read-only data register */ -#define DC_CST 568 /* Data cache control/status */ -#define DC_ADR 569 /* Address needed for some commands */ -#define DC_DAT 570 /* Read-only data register */ - -/* Commands. Only the first few are available to the instruction cache. -*/ -#define IDC_ENABLE 0x02000000 /* Cache enable */ -#define IDC_DISABLE 0x04000000 /* Cache disable */ -#define IDC_LDLCK 0x06000000 /* Load and lock */ -#define IDC_UNLINE 0x08000000 /* Unlock line */ -#define IDC_UNALL 0x0a000000 /* Unlock all */ -#define IDC_INVALL 0x0c000000 /* Invalidate all */ - -#define DC_FLINE 0x0e000000 /* Flush data cache line */ -#define DC_SFWT 0x01000000 /* Set forced writethrough mode */ -#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ -#define DC_SLES 0x05000000 /* Set little endian swap mode */ -#define DC_CLES 0x07000000 /* Clear little endian swap mode */ - -/* Status. -*/ -#define IDC_ENABLED 0x80000000 /* Cache is enabled */ -#define IDC_CERR1 0x00200000 /* Cache error 1 */ -#define IDC_CERR2 0x00100000 /* Cache error 2 */ -#define IDC_CERR3 0x00080000 /* Cache error 3 */ - -#define DC_DFWT 0x40000000 /* Data cache is forced write through */ -#define DC_LES 0x20000000 /* Caches are little endian mode */ -#endif /* CONFIG_8xx */ - #endif diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 3943d0e..cdf4be2 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -19,9 +19,6 @@ struct arch_global_data { u8 sdhc_adapter; #endif #endif -#if defined(CONFIG_8xx) - unsigned long brg_clk; -#endif #if defined(CONFIG_CPM2) /* There are many clocks on the MPC8260 - see page 9-5 */ unsigned long vco_out; diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h deleted file mode 100644 index 8db0fa2..0000000 --- a/arch/powerpc/include/asm/iopin_8xx.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8xx I/O port pin manipulation functions - * Roughly based on iopin_8260.h - */ - -#ifndef _ASM_IOPIN_8XX_H_ -#define _ASM_IOPIN_8XX_H_ - -#include <linux/types.h> -#include <asm/8xx_immap.h> - -#ifdef __KERNEL__ - -typedef struct { - u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ - u_char pin:5; /* port pin (0-31) */ - u_char flag:1; /* for whatever */ -} iopin_t; - -#define IOPIN_PORTA 0 -#define IOPIN_PORTB 1 -#define IOPIN_PORTC 2 -#define IOPIN_PORTD 3 - -static __inline__ void -iopin_set_high(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; - *datp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; - *datp |= (1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; - *datp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; - *datp |= (1 << (15 - iopin->pin)); - } -} - -static __inline__ void -iopin_set_low(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; - *datp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; - *datp &= ~(1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; - *datp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; - *datp &= ~(1 << (15 - iopin->pin)); - } -} - -static __inline__ uint -iopin_is_high(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; - return (*datp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; - return (*datp >> (31 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; - return (*datp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; - return (*datp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -static __inline__ uint -iopin_is_low(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; - return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; - return ((*datp >> (31 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; - return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; - return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -static __inline__ void -iopin_set_out(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; - *dirp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; - *dirp |= (1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; - *dirp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; - *dirp |= (1 << (15 - iopin->pin)); - } -} - -static __inline__ void -iopin_set_in(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; - *dirp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; - *dirp &= ~(1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; - *dirp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; - *dirp &= ~(1 << (15 - iopin->pin)); - } -} - -static __inline__ uint -iopin_is_out(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; - return (*dirp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; - return (*dirp >> (31 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; - return (*dirp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; - return (*dirp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -static __inline__ uint -iopin_is_in(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; - return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; - return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; - return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; - return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -static __inline__ void -iopin_set_odr(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; - *odrp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; - *odrp |= (1 << (31 - iopin->pin)); - } -} - -static __inline__ void -iopin_set_act(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; - *odrp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; - *odrp &= ~(1 << (31 - iopin->pin)); - } -} - -static __inline__ uint -iopin_is_odr(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; - return (*odrp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; - return (*odrp >> (31 - iopin->pin)) & 1; - } - return 0; -} - -static __inline__ uint -iopin_is_act(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; - return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; - return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -static __inline__ void -iopin_set_ded(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; - *parp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; - *parp |= (1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; - *parp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; - *parp |= (1 << (15 - iopin->pin)); - } -} - -static __inline__ void -iopin_set_gen(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; - *parp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; - *parp &= ~(1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; - *parp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; - *parp &= ~(1 << (15 - iopin->pin)); - } -} - -static __inline__ uint -iopin_is_ded(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; - return (*parp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; - return (*parp >> (31 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; - return (*parp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; - return (*parp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -static __inline__ uint -iopin_is_gen(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; - return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; - return ((*parp >> (31 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; - return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; - return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -static __inline__ void -iopin_set_opt2(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; - *sorp |= (1 << (15 - iopin->pin)); - } -} - -static __inline__ void -iopin_set_opt1(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; - *sorp &= ~(1 << (15 - iopin->pin)); - } -} - -static __inline__ uint -iopin_is_opt2(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; - return (*sorp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -static __inline__ uint -iopin_is_opt1(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; - return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -static __inline__ void -iopin_set_falledge(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; - *intp |= (1 << (15 - iopin->pin)); - } -} - -static __inline__ void -iopin_set_anyedge(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; - *intp &= ~(1 << (15 - iopin->pin)); - } -} - -static __inline__ uint -iopin_is_falledge(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; - return (*intp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -static __inline__ uint -iopin_is_anyedge(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; - return ((*intp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IOPIN_8XX_H_ */ diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h index 4e1c596..8abe727 100644 --- a/arch/powerpc/include/asm/ppc.h +++ b/arch/powerpc/include/asm/ppc.h @@ -13,19 +13,7 @@

#ifndef __ASSEMBLY__

-#if defined(CONFIG_8xx) -#include <asm/8xx_immap.h> -#if defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \ - defined(CONFIG_MPC866) || defined(CONFIG_MPC866P) -# define CONFIG_MPC866_FAMILY 1 -#elif defined(CONFIG_MPC885) -# define CONFIG_MPC885_FAMILY 1 -#endif -#if defined(CONFIG_MPC860) || defined(CONFIG_MPC860T) || \ - defined(CONFIG_MPC866_FAMILY) || defined(CONFIG_MPC885_FAMILY) -# define CONFIG_MPC86x 1 -#endif -#elif defined(CONFIG_5xx) +#if defined(CONFIG_5xx) #include <asm/5xx_immap.h> #elif defined(CONFIG_MPC5xxx) #include <mpc5xxx.h> @@ -62,29 +50,7 @@ #include <asm/arch/immap_lsch2.h> #endif

-/* - * enable common handling for all TQM8xxL/M boards: - * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards - * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards - * and for the TQM885D board - */ -#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \ - defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) -# ifndef CONFIG_TQM8xxM -# define CONFIG_TQM8xxM -# endif -#endif -#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \ - defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \ - defined(CONFIG_TQM885D) -# ifndef CONFIG_TQM8xxL -# define CONFIG_TQM8xxL -# endif -#endif - -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) +#if defined(CONFIG_5xx) uint get_immr(uint); #endif #if defined(CONFIG_MPC5xxx) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fd38da9..aaabae0 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1361,10 +1361,7 @@ int prt_8260_clks(void); #endif /* ndef ASSEMBLY*/

#ifdef CONFIG_MACH_SPECIFIC -#if defined(CONFIG_8xx) -#define _machine _MACH_8xx -#define have_of 0 -#elif defined(CONFIG_WALNUT) +#if defined(CONFIG_WALNUT) #define _machine _MACH_walnut #define have_of 0 #elif defined(CONFIG_MPC8260) diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h index 1ae1b17..c151b54 100644 --- a/arch/powerpc/include/asm/status_led.h +++ b/arch/powerpc/include/asm/status_led.h @@ -9,9 +9,7 @@

/* if not overridden */ #ifndef CONFIG_LED_STATUS_BOARD_SPECIFIC -# if defined(CONFIG_8xx) -# include <mpc8xx.h> -# elif defined(CONFIG_MPC8260) +# if defined(CONFIG_MPC8260) # include <mpc8260.h> # elif defined(CONFIG_5xx) # include <mpc5xx.h> diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index e09bd9a..5e55385 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -36,7 +36,6 @@ obj-y += extable.o obj-$(CONFIG_CMD_IMMAP) += immap.o obj-y += interrupts.o obj-$(CONFIG_CMD_KGDB) += kgdb.o -obj-$(CONFIG_IDE) += ide.o obj-y += stack.o obj-y += time.o

diff --git a/arch/powerpc/lib/ide.c b/arch/powerpc/lib/ide.c deleted file mode 100644 index b4ead72..0000000 --- a/arch/powerpc/lib/ide.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * (C) Copyright 2000-2011 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Code taken from cmd_ide.c */ -#include <common.h> -#include <ata.h> -#include "ide.h" - -#ifdef CONFIG_IDE_8xx_DIRECT -#include <mpc8xx.h> -#include <pcmcia.h> -DECLARE_GLOBAL_DATA_PTR; - -/* Timings for IDE Interface - * - * SETUP / LENGTH / HOLD - cycles valid for 50 MHz clk - * 70 165 30 PIO-Mode 0, [ns] - * 4 9 2 [Cycles] - * 50 125 20 PIO-Mode 1, [ns] - * 3 7 2 [Cycles] - * 30 100 15 PIO-Mode 2, [ns] - * 2 6 1 [Cycles] - * 30 80 10 PIO-Mode 3, [ns] - * 2 5 1 [Cycles] - * 25 70 10 PIO-Mode 4, [ns] - * 2 4 1 [Cycles] - */ - -static const pio_config_t pio_config_ns[IDE_MAX_PIO_MODE+1] = { - /* Setup Length Hold */ - { 70, 165, 30 }, /* PIO-Mode 0, [ns] */ - { 50, 125, 20 }, /* PIO-Mode 1, [ns] */ - { 30, 101, 15 }, /* PIO-Mode 2, [ns] */ - { 30, 80, 10 }, /* PIO-Mode 3, [ns] */ - { 25, 70, 10 }, /* PIO-Mode 4, [ns] */ -}; - -static pio_config_t pio_config_clk[IDE_MAX_PIO_MODE+1]; - -#ifndef CONFIG_SYS_PIO_MODE -#define CONFIG_SYS_PIO_MODE 0 /* use a relaxed default */ -#endif -static int pio_mode = CONFIG_SYS_PIO_MODE; - -/* Make clock cycles and always round up */ - -#define PCMCIA_MK_CLKS(t, T) (((t) * (T) + 999U) / 1000U) - -static void set_pcmcia_timing(int pmode) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia); - ulong timings; - - debug("Set timing for PIO Mode %d\n", pmode); - - timings = PCMCIA_SHT(pio_config_clk[pmode].t_hold) - | PCMCIA_SST(pio_config_clk[pmode].t_setup) - | PCMCIA_SL(pio_config_clk[pmode].t_length); - - /* - * IDE 0 - */ - pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_PBR0; -#if (CONFIG_SYS_PCMCIA_POR0 != 0) - pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0 | timings; -#else - pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0; -#endif - debug("PBR0: %08x POR0: %08x\n", pcmp->pcmc_pbr0, pcmp->pcmc_por0); - - pcmp->pcmc_pbr1 = CONFIG_SYS_PCMCIA_PBR1; -#if (CONFIG_SYS_PCMCIA_POR1 != 0) - pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1 | timings; -#else - pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1; -#endif - debug("PBR1: %08x POR1: %08x\n", pcmp->pcmc_pbr1, pcmp->pcmc_por1); - - pcmp->pcmc_pbr2 = CONFIG_SYS_PCMCIA_PBR2; -#if (CONFIG_SYS_PCMCIA_POR2 != 0) - pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2 | timings; -#else - pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2; -#endif - debug("PBR2: %08x POR2: %08x\n", pcmp->pcmc_pbr2, pcmp->pcmc_por2); - - pcmp->pcmc_pbr3 = CONFIG_SYS_PCMCIA_PBR3; -#if (CONFIG_SYS_PCMCIA_POR3 != 0) - pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3 | timings; -#else - pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3; -#endif - debug("PBR3: %08x POR3: %08x\n", pcmp->pcmc_pbr3, pcmp->pcmc_por3); - - /* - * IDE 1 - */ - pcmp->pcmc_pbr4 = CONFIG_SYS_PCMCIA_PBR4; -#if (CONFIG_SYS_PCMCIA_POR4 != 0) - pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4 | timings; -#else - pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4; -#endif - debug("PBR4: %08x POR4: %08x\n", pcmp->pcmc_pbr4, pcmp->pcmc_por4); - - pcmp->pcmc_pbr5 = CONFIG_SYS_PCMCIA_PBR5; -#if (CONFIG_SYS_PCMCIA_POR5 != 0) - pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5 | timings; -#else - pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5; -#endif - debug("PBR5: %08x POR5: %08x\n", pcmp->pcmc_pbr5, pcmp->pcmc_por5); - - pcmp->pcmc_pbr6 = CONFIG_SYS_PCMCIA_PBR6; -#if (CONFIG_SYS_PCMCIA_POR6 != 0) - pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6 | timings; -#else - pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6; -#endif - debug("PBR6: %08x POR6: %08x\n", pcmp->pcmc_pbr6, pcmp->pcmc_por6); - - pcmp->pcmc_pbr7 = CONFIG_SYS_PCMCIA_PBR7; -#if (CONFIG_SYS_PCMCIA_POR7 != 0) - pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7 | timings; -#else - pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7; -#endif - debug("PBR7: %08x POR7: %08x\n", pcmp->pcmc_pbr7, pcmp->pcmc_por7); - -} - -int ide_preinit(void) -{ - int i; - /* Initialize PIO timing tables */ - for (i = 0; i <= IDE_MAX_PIO_MODE; ++i) { - pio_config_clk[i].t_setup = - PCMCIA_MK_CLKS(pio_config_ns[i].t_setup, gd->bus_clk); - pio_config_clk[i].t_length = - PCMCIA_MK_CLKS(pio_config_ns[i].t_length, gd->bus_clk); - pio_config_clk[i].t_hold = - PCMCIA_MK_CLKS(pio_config_ns[i].t_hold, gd->bus_clk); - debug("PIO Mode %d: setup=%2d ns/%d clk" " len=%3d ns/%d clk" - " hold=%2d ns/%d clk\n", i, pio_config_ns[i].t_setup, - pio_config_clk[i].t_setup, pio_config_ns[i].t_length, - pio_config_clk[i].t_length, pio_config_ns[i].t_hold, - pio_config_clk[i].t_hold); - } - - return 0; -} - -int ide_init_postreset(void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia); - - /* PCMCIA / IDE initialization for common mem space */ - pcmp->pcmc_pgcrb = 0; - - /* start in PIO mode 0 - most relaxed timings */ - pio_mode = 0; - set_pcmcia_timing(pio_mode); - return 0; -} -#endif /* CONFIG_IDE_8xx_DIRECT */ - -#ifdef CONFIG_IDE_8xx_PCCARD -int ide_preinit(void) -{ - ide_devices_found = 0; - /* initialize the PCMCIA IDE adapter card */ - pcmcia_on(); - if (!ide_devices_found) - return 1; - udelay(1000000);/* 1 s */ - return 0; -} -#endif diff --git a/arch/powerpc/lib/ide.h b/arch/powerpc/lib/ide.h deleted file mode 100644 index e0b2e61..0000000 --- a/arch/powerpc/lib/ide.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2012 - * Pavel Herrmann morpheus.ibis@gmail.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MPC8XX_IDE_H_ -#define _MPC8XX_IDE_H_ 1 - -#ifdef CONFIG_IDE_8xx_PCCARD -int pcmcia_on(void); -extern int ide_devices_found; -#endif -#endif diff --git a/arch/powerpc/lib/immap.c b/arch/powerpc/lib/immap.c index 1414f9a..85527a1 100644 --- a/arch/powerpc/lib/immap.c +++ b/arch/powerpc/lib/immap.c @@ -12,17 +12,11 @@ #include <common.h> #include <command.h>

-#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260)

-#if defined(CONFIG_8xx) -#include <asm/8xx_immap.h> -#include <commproc.h> -#include <asm/iopin_8xx.h> -#elif defined(CONFIG_MPC8260) #include <asm/immap_8260.h> #include <asm/cpm_8260.h> #include <asm/iopin_8260.h> -#endif

DECLARE_GLOBAL_DATA_PTR;

@@ -38,19 +32,12 @@ do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

-#if defined(CONFIG_8xx) - volatile sysconf8xx_t *sc = &immap->im_siu_conf; -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) volatile sysconf8260_t *sc = &immap->im_siu_conf; #endif

printf ("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr); -#if defined(CONFIG_8xx) - printf ("SWT = %08x\n", sc->sc_swt); - printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask); - printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec); - printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr); -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) printf ("BCR = %08x\n", sc->sc_bcr); printf ("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n", sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl); @@ -69,10 +56,7 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

-#if defined(CONFIG_8xx) - volatile memctl8xx_t *memctl = &immap->im_memctl; - int nbanks = 8; -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) volatile memctl8260_t *memctl = &immap->im_memctl; int nbanks = 12; #endif @@ -90,16 +74,12 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) }

printf ("MAR = %08x", memctl->memc_mar); -#if defined(CONFIG_8xx) - printf (" MCR = %08x\n", memctl->memc_mcr); -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) putc ('\n'); #endif printf ("MAMR = %08x MBMR = %08x", memctl->memc_mamr, memctl->memc_mbmr); -#if defined(CONFIG_8xx) - printf ("\nMSTAT = %04x\n", memctl->memc_mstat); -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) printf (" MCMR = %08x\n", memctl->memc_mcmr); #endif printf ("MPTPR = %04x MDR = %08x\n", @@ -137,17 +117,11 @@ do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

-#if defined(CONFIG_8xx) - volatile car8xx_t *car = &immap->im_clkrst; -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) volatile car8260_t *car = &immap->im_clkrst; #endif

-#if defined(CONFIG_8xx) - printf ("SCCR = %08x\n", car->car_sccr); - printf ("PLPRCR= %08x\n", car->car_plprcr); - printf ("RSR = %08x\n", car->car_rsr); -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) printf ("SCCR = %08x\n", car->car_sccr); printf ("SCMR = %08x\n", car->car_scmr); printf ("RSR = %08x\n", car->car_rsr); @@ -200,14 +174,7 @@ static void binary (char *label, uint value, int nbits) putc ('\n'); }

-#if defined(CONFIG_8xx) -#define PA_NBITS 16 -#define PA_NB_ODR 8 -#define PB_NBITS 18 -#define PB_NB_ODR 16 -#define PC_NBITS 12 -#define PD_NBITS 13 -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) #define PA_NBITS 32 #define PA_NB_ODR 32 #define PB_NBITS 28 @@ -221,10 +188,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

-#if defined(CONFIG_8xx) - volatile iop8xx_t *iop = &immap->im_ioport; - volatile ushort *l, *r; -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) volatile iop8260_t *iop = &immap->im_ioport; volatile uint *l, *r; #endif @@ -237,10 +201,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * Ports A & B */

-#if defined(CONFIG_8xx) - l = &iop->iop_padir; - R = &immap->im_cpm.cp_pbdir; -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) l = &iop->iop_pdira; R = &iop->iop_pdirb; #endif @@ -263,10 +224,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * Ports C & D */

-#if defined(CONFIG_8xx) - l = &iop->iop_pcdir; - r = &iop->iop_pddir; -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) l = &iop->iop_pdirc; r = &iop->iop_pdird; #endif @@ -274,11 +232,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) binary ("PD_DIR", *r++, PD_NBITS); binary ("PC_PAR", *l++, PC_NBITS); binary ("PD_PAR", *r++, PD_NBITS); -#if defined(CONFIG_8xx) - binary ("PC_SO ", *l++, PC_NBITS); - binary (" ", 0, 0); - r++; -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) binary ("PC_SOR", *l++, PC_NBITS); binary ("PD_SOR", *r++, PD_NBITS); binary ("PC_ODR", *l++, PC_NBITS); @@ -286,9 +240,6 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif binary ("PC_DAT", *l++, PC_NBITS); binary ("PD_DAT", *r++, PD_NBITS); -#if defined(CONFIG_8xx) - binary ("PC_INT", *l++, PC_NBITS); -#endif

header (); return 0; @@ -313,9 +264,6 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) SOR, ODR, DAT, -#if defined(CONFIG_8xx) - INT -#endif } cmd = DAT;

if (argc != 5) { @@ -350,11 +298,6 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) case 's': cmd = SOR; break; -#if defined(CONFIG_8xx) - case 'i': - cmd = INT; - break; -#endif default: printf ("iopset: unknown command %s\n", argv[3]); rcode = 1; @@ -400,14 +343,6 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) else iopin_set_low (&iopin); break; -#if defined(CONFIG_8xx) - case INT: - if (value) - iopin_set_falledge (&iopin); - else - iopin_set_anyedge (&iopin); - break; -#endif }

} @@ -434,9 +369,7 @@ static void prbrg (int n, uint val) uint cd = (val & CPM_BRG_CD_MASK) >> 1; uint div16 = (val & CPM_BRG_DIV16) != 0;

-#if defined(CONFIG_8xx) - ulong clock = gd->cpu_clk; -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) ulong clock = gd->arch.brg_clk; #endif

@@ -486,10 +419,7 @@ do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

-#if defined(CONFIG_8xx) - volatile cpm8xx_t *cp = &immap->im_cpm; - volatile uint *p = &cp->cp_brgc1; -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) volatile uint *p = &immap->im_brgc1; #endif int i = 1; @@ -510,11 +440,7 @@ do_i2cinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

-#if defined(CONFIG_8xx) - volatile i2c8xx_t *i2c = &immap->im_i2c; - volatile cpm8xx_t *cp = &immap->im_cpm; - volatile iic_t *iip = (iic_t *) & cp->cp_dparam[PROFF_IIC]; -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260) volatile i2c8260_t *i2c = &immap->im_i2c; volatile iic_t *iip; uint dpaddr; diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c index de5f0be..c1a0a69 100644 --- a/arch/powerpc/lib/time.c +++ b/arch/powerpc/lib/time.c @@ -64,7 +64,7 @@ int timer_init(void) { unsigned long temp;

-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) +#if defined(CONFIG_5xx) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

/* unlock */ @@ -75,7 +75,7 @@ int timer_init(void) asm volatile("li %0,0 ; mttbu %0 ; mttbl %0;" : "=&r"(temp) );

-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) +#if defined(CONFIG_5xx) /* enable */ immap->im_sit.sit_tbscr |= TBSCR_TBE; #endif diff --git a/board/tqc/tqm8xx/Kconfig b/board/tqc/tqm8xx/Kconfig deleted file mode 100644 index 857fedb..0000000 --- a/board/tqc/tqm8xx/Kconfig +++ /dev/null @@ -1,155 +0,0 @@ -if TARGET_TQM823L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM823L" - -endif - -if TARGET_TQM823M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM823M" - -endif - -if TARGET_TQM850L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM850L" - -endif - -if TARGET_TQM850M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM850M" - -endif - -if TARGET_TQM855L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM855L" - -endif - -if TARGET_TQM855M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM855M" - -endif - -if TARGET_TQM860L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM860L" - -endif - -if TARGET_TQM860M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM860M" - -endif - -if TARGET_TQM862L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM862L" - -endif - -if TARGET_TQM862M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM862M" - -endif - -if TARGET_TQM866M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM866M" - -endif - -if TARGET_TQM885D - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM885D" - -endif diff --git a/board/tqc/tqm8xx/MAINTAINERS b/board/tqc/tqm8xx/MAINTAINERS deleted file mode 100644 index f3ddc6a..0000000 --- a/board/tqc/tqm8xx/MAINTAINERS +++ /dev/null @@ -1,31 +0,0 @@ -TQM8XX BOARD -M: Wolfgang Denk wd@denx.de -S: Maintained -F: board/tqc/tqm8xx/ -F: include/configs/TQM823L.h -F: configs/TQM823L_defconfig -F: configs/TQM823L_LCD_defconfig -F: include/configs/TQM823M.h -F: configs/TQM823M_defconfig -F: include/configs/TQM850L.h -F: configs/TQM850L_defconfig -F: include/configs/TQM850M.h -F: configs/TQM850M_defconfig -F: include/configs/TQM855L.h -F: configs/TQM855L_defconfig -F: include/configs/TQM855M.h -F: configs/TQM855M_defconfig -F: include/configs/TQM860L.h -F: configs/TQM860L_defconfig -F: include/configs/TQM860M.h -F: configs/TQM860M_defconfig -F: include/configs/TQM862L.h -F: configs/TQM862L_defconfig -F: include/configs/TQM862M.h -F: configs/TQM862M_defconfig -F: include/configs/TQM866M.h -F: configs/TQM866M_defconfig -F: include/configs/TQM885D.h -F: configs/TQM885D_defconfig -F: configs/TTTech_defconfig -F: configs/wtk_defconfig diff --git a/board/tqc/tqm8xx/Makefile b/board/tqc/tqm8xx/Makefile deleted file mode 100644 index 2651a2f..0000000 --- a/board/tqc/tqm8xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = tqm8xx.o load_sernum_ethaddr.o diff --git a/board/tqc/tqm8xx/load_sernum_ethaddr.c b/board/tqc/tqm8xx/load_sernum_ethaddr.c deleted file mode 100644 index 0070da1..0000000 --- a/board/tqc/tqm8xx/load_sernum_ethaddr.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -/*----------------------------------------------------------------------- - * Process Hardware Information Block: - * - * If we boot on a system fresh from factory, check if the Hardware - * Information Block exists and save the information it contains. - * - * The TQM8xxL / TQM82xx Hardware Information Block is defined as - * follows: - * - located in first flash bank - * - starts at offset 0x0003FFC0 - * - size 0x00000040 - * - * Internal structure: - * - sequence of ASCII character strings - * - fields separated by a single space character (0x20) - * - last field terminated by NUL character (0x00) - * - remaining space filled with NUL characters (0x00) - * - * Fields in Hardware Information Block: - * 1) Module Type - * 2) Serial Number - * 3) First MAC Address - * 4) Number of additional MAC addresses - */ - -void load_sernum_ethaddr (void) -{ - unsigned char *hwi; - unsigned char serial [CONFIG_SYS_HWINFO_SIZE]; - unsigned char ethaddr[CONFIG_SYS_HWINFO_SIZE]; - unsigned short ih, is, ie, part; - - hwi = (unsigned char *)(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET); - ih = is = ie = 0; - - if (*((unsigned long *)hwi) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - return; - } - - part = 1; - - /* copy serial # / MAC address */ - while ((hwi[ih] != '\0') && (ih < CONFIG_SYS_HWINFO_SIZE)) { - if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */ - return; - } - switch (part) { - default: /* Copy serial # */ - if (hwi[ih] == ' ') { - ++part; - } - serial[is++] = hwi[ih]; - break; - case 3: /* Copy MAC address */ - if (hwi[ih] == ' ') { - ++part; - break; - } - ethaddr[ie++] = hwi[ih]; - if ((ie % 3) == 2) - ethaddr[ie++] = ':'; - break; - } - ++ih; - } - serial[is] = '\0'; - if (ie && ethaddr[ie-1] == ':') - --ie; - ethaddr[ie] = '\0'; - - /* set serial# and ethaddr if not yet defined */ - if (getenv("serial#") == NULL) { - setenv ((char *)"serial#", (char *)serial); - } - - if (getenv("ethaddr") == NULL) { - setenv ((char *)"ethaddr", (char *)ethaddr); - } -} diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c deleted file mode 100644 index 58bd7fa..0000000 --- a/board/tqc/tqm8xx/tqm8xx.c +++ /dev/null @@ -1,677 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <hwconfig.h> -#include <mpc8xx.h> -#ifdef CONFIG_PS2MULT -#include <ps2mult.h> -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#endif - -extern flash_info_t flash_info[]; /* FLASH chips info */ - -DECLARE_GLOBAL_DATA_PTR; - -static long int dram_size (long int, long int *, long int); - -#define _NOT_USED_ 0xFFFFFFFF - -/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */ -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, - 0x1FF5FC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44, - 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test TQ ID string (TQM8xx...) - * If present, check for "L" type (no second DRAM bank), - * otherwise "L" type is assumed as default. - * - * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else. - */ - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: "); - - if (l < 0 || strncmp(buf, "TQM8", 4)) { - puts ("### No HW ID - assuming TQM8xxL\n"); - return (0); - } - - if ((buf[6] == 'L')) { /* a TQM8xxL type */ - gd->board_type = 'L'; - } - - if ((buf[6] == 'M')) { /* a TQM8xxM type */ - gd->board_type = 'M'; - } - - if ((buf[6] == 'D')) { /* a TQM885D type */ - gd->board_type = 'D'; - } - - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc (buf[i]); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int dram_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9, size10; - long int size_b0 = 0; - long int size_b1 = 0; - int board_type = gd->board_type; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - /* - * The following value is used as an address (i.e. opcode) for - * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If - * the port size is 32bit the SDRAM does NOT "see" the lower two - * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for - * MICRON SDRAMs: - * -> 0 00 010 0 010 - * | | | | +- Burst Length = 4 - * | | | +----- Burst Type = Sequential - * | | +------- CAS Latency = 2 - * | +----------- Operating Mode = Standard - * +-------------- Write Burst Mode = Programmed Burst Length - */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - -#ifndef CONFIG_CAN_DRIVER - if ((board_type != 'L') && - (board_type != 'M') && - (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - } -#endif /* CONFIG_CAN_DRIVER */ - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay (1); - -#ifndef CONFIG_CAN_DRIVER - if ((board_type != 'L') && - (board_type != 'M') && - (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ - memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */ - udelay (1); - } -#endif /* CONFIG_CAN_DRIVER */ - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20); - - udelay(1000); - -#if defined(CONFIG_SYS_MAMR_10COL) - /* - * try 10 column mode - */ - size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20); -#else - size10 = 0; -#endif /* CONFIG_SYS_MAMR_10COL */ - - if ((size8 < size10) && (size9 < size10)) { - size_b0 = size10; - } else if ((size8 < size9) && (size10 < size9)) { - size_b0 = size9; - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL; - udelay (500); - } else { - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); - } - debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20); - -#ifndef CONFIG_CAN_DRIVER - if ((board_type != 'L') && - (board_type != 'M') && - (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ - /* - * Check Bank 1 Memory Size - * use current column settings - * [9 column SDRAM may also be used in 8 column mode, - * but then only half the real size will be used.] - */ - size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); - debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20); - } else { - size_b1 = 0; - } -#endif /* CONFIG_CAN_DRIVER */ - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - - memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b0 > 0) { - /* - * Position Bank 0 immediately above Bank 1 - */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b1; - } else { - unsigned long reg; - - /* - * No bank 0 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - } else { /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or3 = - ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br3 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b0; - } else { - unsigned long reg; - -#ifndef CONFIG_CAN_DRIVER - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br3 = 0; -#endif /* CONFIG_CAN_DRIVER */ - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - } - - udelay (10000); - -#ifdef CONFIG_CAN_DRIVER - /* UPM initialization for CAN @ CLKOUT <= 66 MHz */ - - /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CONFIG_SYS_OR3_CAN; - memctl->memc_br3 = CONFIG_SYS_BR3_CAN; - - /* Initialize MBMR */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFCC04; - memctl->memc_mcr = 0x0100 | UPMB; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMB; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMB; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMB; - - memctl->memc_mdr = 0xFFFFDC07; - memctl->memc_mcr = 0x0104 | UPMB; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCCC04; - memctl->memc_mcr = 0x0118 | UPMB; - - memctl->memc_mdr = 0xCFFCDC04; - memctl->memc_mcr = 0x0119 | UPMB; - - memctl->memc_mdr = 0x3FFCC000; - memctl->memc_mcr = 0x011A | UPMB; - - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x011B | UPMB; - - memctl->memc_mdr = 0xFFFDC405; - memctl->memc_mcr = 0x011C | UPMB; -#endif /* CONFIG_CAN_DRIVER */ - -#ifdef CONFIG_ISP1362_USB - /* Initialize OR5 / BR5 */ - memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362; - memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362; -#endif /* CONFIG_ISP1362_USB */ - gd->ram_size = size_b0 + size_b1; - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_MISC_INIT_R -extern void load_sernum_ethaddr(void); -int misc_init_r (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - load_sernum_ethaddr(); - -#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ - int scy, trlx, flash_or_timing, clk_diff; - - scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; - if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { - trlx = OR_TRLX; - scy *= 2; - } else { - trlx = 0; - } - - /* - * We assume that each 10MHz of bus clock require 1-clk SCY - * adjustment. - */ - clk_diff = (gd->bus_clk / 1000000) - 50; - - /* - * We need proper rounding here. This is what the "+5" and "-5" - * are here for. - */ - if (clk_diff >= 0) - scy += (clk_diff + 5) / 10; - else - scy += (clk_diff - 5) / 10; - - /* - * For bus frequencies above 50MHz, we want to use relaxed timing - * (OR_TRLX). - */ - if (gd->bus_clk >= 50000000) - trlx = OR_TRLX; - else - trlx = 0; - - if (trlx) - scy /= 2; - - if (scy > 0xf) - scy = 0xf; - if (scy < 1) - scy = 1; - - flash_or_timing = (scy << 4) | trlx | - (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); - - memctl->memc_or0 = - flash_or_timing | (-flash_info[0].size & OR_AM_MSK); -#else - memctl->memc_or0 = - CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK); -#endif - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - debug ("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - if (flash_info[1].size) { -#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ - memctl->memc_or1 = flash_or_timing | - (-flash_info[1].size & 0xFFFF8000); -#else - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | - (-flash_info[1].size & 0xFFFF8000); -#endif - memctl->memc_br1 = - ((CONFIG_SYS_FLASH_BASE + - flash_info[0]. - size) & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - debug ("## BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - } - -# ifdef CONFIG_IDE_LED - /* Configure PA15 as output port */ - immap->im_ioport.iop_padir |= 0x0001; - immap->im_ioport.iop_paodr |= 0x0001; - immap->im_ioport.iop_papar &= ~0x0001; - immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */ -# endif - - return (0); -} -#endif /* CONFIG_MISC_INIT_R */ - - -# ifdef CONFIG_IDE_LED -void ide_led (uchar led, uchar status) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* We have one led for both pcmcia slots */ - if (status) { /* led on */ - immap->im_ioport.iop_padat |= 0x0001; - } else { - immap->im_ioport.iop_padat &= ~0x0001; - } -} -# endif - -#ifdef CONFIG_LCD_INFO -#include <lcd.h> -#include <version.h> -#include <timestamp.h> - -void lcd_show_board_info(void) -{ - char temp[32]; - - lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME); - lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n"); - lcd_printf (" Wolfgang DENK, wd@denx.de\n"); -#ifdef CONFIG_LCD_INFO_BELOW_LOGO - lcd_printf ("MPC823 CPU at %s MHz\n", - strmhz(temp, gd->cpu_clk)); - lcd_printf (" %ld MB RAM, %ld MB Flash\n", - gd->ram_size >> 20, - gd->bd->bi_flashsize >> 20 ); -#else - /* leave one blank line */ - lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n", - strmhz(temp, gd->cpu_clk), - gd->ram_size >> 20, - gd->bd->bi_flashsize >> 20 ); -#endif /* CONFIG_LCD_INFO_BELOW_LOGO */ -} -#endif /* CONFIG_LCD_INFO */ - -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -int fdt_set_node_and_value (void *blob, - char *nodename, - char *regname, - void *var, - int size) -{ - int ret = 0; - int nodeoffset = 0; - - nodeoffset = fdt_path_offset (blob, nodename); - if (nodeoffset >= 0) { - ret = fdt_setprop (blob, nodeoffset, regname, var, - size); - if (ret < 0) { - printf("ft_blob_update(): " - "cannot set %s/%s property; err: %s\n", - nodename, regname, fdt_strerror (ret)); - } - } else { - printf("ft_blob_update(): " - "cannot find %s node err:%s\n", - nodename, fdt_strerror (nodeoffset)); - } - return ret; -} - -int fdt_del_node_name (void *blob, char *nodename) -{ - int ret = 0; - int nodeoffset = 0; - - nodeoffset = fdt_path_offset (blob, nodename); - if (nodeoffset >= 0) { - ret = fdt_del_node (blob, nodeoffset); - if (ret < 0) { - printf("%s: cannot delete %s; err: %s\n", - __func__, nodename, fdt_strerror (ret)); - } - } else { - printf("%s: cannot find %s node err:%s\n", - __func__, nodename, fdt_strerror (nodeoffset)); - } - return ret; -} - -int fdt_del_prop_name (void *blob, char *nodename, char *propname) -{ - int ret = 0; - int nodeoffset = 0; - - nodeoffset = fdt_path_offset (blob, nodename); - if (nodeoffset >= 0) { - ret = fdt_delprop (blob, nodeoffset, propname); - if (ret < 0) { - printf("%s: cannot delete %s %s; err: %s\n", - __func__, nodename, propname, - fdt_strerror (ret)); - } - } else { - printf("%s: cannot find %s node err:%s\n", - __func__, nodename, fdt_strerror (nodeoffset)); - } - return ret; -} - -/* - * update "brg" property in the blob - */ -void ft_blob_update (void *blob, bd_t *bd) -{ - uchar enetaddr[6]; - ulong brg_data = 0; - - /* BRG */ - brg_data = cpu_to_be32(bd->bi_busfreq); - fdt_set_node_and_value(blob, - "/soc/cpm", "brg-frequency", - &brg_data, sizeof(brg_data)); - - /* MAC addr */ - if (eth_getenv_enetaddr("ethaddr", enetaddr)) { - fdt_set_node_and_value(blob, - "ethernet0", "local-mac-address", - enetaddr, sizeof(u8) * 6); - } - - if (hwconfig_arg_cmp("fec", "off")) { - /* no FEC on this plattform, delete DTS nodes */ - fdt_del_node_name (blob, "ethernet1"); - fdt_del_node_name (blob, "mdio1"); - /* also the aliases entries */ - fdt_del_prop_name (blob, "/aliases", "ethernet1"); - fdt_del_prop_name (blob, "/aliases", "mdio1"); - } else { - /* adjust local-mac-address for FEC ethernet */ - if (eth_getenv_enetaddr("eth1addr", enetaddr)) { - fdt_set_node_and_value(blob, - "ethernet1", "local-mac-address", - enetaddr, sizeof(u8) * 6); - } - } -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - ft_blob_update(blob, bd); - - return 0; -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds deleted file mode 100644 index 44dfafa..0000000 --- a/board/tqc/tqm8xx/u-boot.lds +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2000-2012 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - arch/powerpc/cpu/mpc8xx/built-in.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - board/tqc/tqm8xx/built-in.o (.text*) - disk/built-in.o (.text*) - drivers/net/built-in.o (.text*) - drivers/built-in.o (.text.pcmcia_on) - drivers/built-in.o (.text.pcmcia_hardware_enable) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 41ab8e8..484a853 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -183,7 +183,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_bi_flash(bd); print_num("sramstart", bd->bi_sramstart); print_num("sramsize", bd->bi_sramsize); -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \ +#if defined(CONFIG_5xx) || \ defined(CONFIG_MPC8260) || defined(CONFIG_E500) print_num("immr_base", bd->bi_immr_base); #endif diff --git a/cmd/bedbug.c b/cmd/bedbug.c index 69afeaf..14663dc 100644 --- a/cmd/bedbug.c +++ b/cmd/bedbug.c @@ -52,10 +52,6 @@ void bedbug_init (void) void bedbug405_init (void);

bedbug405_init (); -#elif defined(CONFIG_8xx) - void bedbug860_init (void); - - bedbug860_init (); #endif

#if defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260) diff --git a/cmd/ide.c b/cmd/ide.c index 0fd401b..10fb2f9 100644 --- a/cmd/ide.c +++ b/cmd/ide.c @@ -18,7 +18,7 @@ #include <asm/byteorder.h> #include <asm/io.h>

-#if defined(CONFIG_IDE_8xx_DIRECT) || defined(CONFIG_IDE_PCMCIA) +#if defined(CONFIG_IDE_PCMCIA) # include <pcmcia.h> #endif

@@ -42,12 +42,7 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) return CMD_RET_USAGE; case 2: if (strncmp(argv[1], "res", 3) == 0) { - puts("\nReset IDE" -#ifdef CONFIG_IDE_8xx_DIRECT - " on PCMCIA " PCMCIA_SLOT_MSG -#endif - ": "); - + puts("\nReset IDE: "); ide_init(); return 0; } else if (strncmp(argv[1], "inf", 3) == 0) { diff --git a/cmd/pcmcia.c b/cmd/pcmcia.c index 044fb9e..0bf2bd6 100644 --- a/cmd/pcmcia.c +++ b/cmd/pcmcia.c @@ -83,10 +83,6 @@ U_BOOT_CMD(

#undef CHECK_IDE_DEVICE

-#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CHECK_IDE_DEVICE -#endif - #if defined(CONFIG_PXA_PCMCIA) #define CHECK_IDE_DEVICE #endif diff --git a/cmd/reginfo.c b/cmd/reginfo.c index a3696d1..d971a8f 100644 --- a/cmd/reginfo.c +++ b/cmd/reginfo.c @@ -7,9 +7,7 @@

#include <common.h> #include <command.h> -#if defined(CONFIG_8xx) -#include <mpc8xx.h> -#elif defined (CONFIG_4xx) +#if defined (CONFIG_4xx) extern void ppc4xx_reginfo(void); #elif defined (CONFIG_5xx) #include <mpc5xx.h> @@ -24,60 +22,7 @@ extern void mpc85xx_reginfo(void); static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { -#if defined(CONFIG_8xx) - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile sysconf8xx_t *sysconf = &immap->im_siu_conf; - volatile sit8xx_t *timers = &immap->im_sit; - - /* Hopefully more PowerPC knowledgable people will add code to display - * other useful registers - */ - - printf ("\nSystem Configuration registers\n" - - "\tIMMR\t0x%08X\n", get_immr(0)); - - printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr); - printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr); - - printf("\tSWT\t0x%08X", sysconf->sc_swt); - printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr); - - printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n", - sysconf->sc_sipend, sysconf->sc_simask); - printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n", - sysconf->sc_siel, sysconf->sc_sivec); - printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n", - sysconf->sc_tesr, sysconf->sc_sdcr); - - printf ("Memory Controller Registers\n" - - "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); - printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); - printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); - printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); - printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4); - printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5); - printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6); - printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7); - printf ("\n" - "\tmamr\t0x%08X\tmbmr\t0x%08X \n", - memctl->memc_mamr, memctl->memc_mbmr ); - printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n", - memctl->memc_mstat, memctl->memc_mptpr ); - printf("\tmdr\t0x%08X \n", memctl->memc_mdr); - - printf ("\nSystem Integration Timers\n" - "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", - timers->sit_tbscr, timers->sit_rtcsc); - printf("\tPISCR\t0x%08X \n", timers->sit_piscr); - - /* - * May be some CPM info here? - */ - -#elif defined (CONFIG_4xx) +#if defined (CONFIG_4xx) ppc4xx_reginfo(); #elif defined(CONFIG_5xx)

diff --git a/cmd/source.c b/cmd/source.c index db7ab7e..177f86b 100644 --- a/cmd/source.c +++ b/cmd/source.c @@ -22,9 +22,6 @@ #include <mapmem.h> #include <asm/byteorder.h> #include <asm/io.h> -#if defined(CONFIG_8xx) -#include <mpc8xx.h> -#endif

int source (ulong addr, const char *fit_uname) diff --git a/common/board_f.c b/common/board_f.c index 46e5284..a3f8704 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -387,7 +387,7 @@ static int reserve_video(void) gd->fb_base = gd->relocaddr; # endif /* CONFIG_FB_ADDR */ #elif defined(CONFIG_VIDEO) && \ - (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ + (!defined(CONFIG_PPC)) && \ !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ !defined(CONFIG_M68K) /* reserve memory for video display (always full pages) */ @@ -547,7 +547,7 @@ static int setup_board_part1(void) bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ #endif

-#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ +#if defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ #endif diff --git a/common/board_r.c b/common/board_r.c index 15977e4..adc1f19 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -227,13 +227,6 @@ static int initr_post_backlog(void) } #endif

-#ifdef CONFIG_SYS_DELAYED_ICACHE -static int initr_icache_enable(void) -{ - return 0; -} -#endif - #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) static int initr_unlock_ram_in_cache(void) { @@ -639,11 +632,7 @@ static int initr_pcmcia(void) #if defined(CONFIG_IDE) static int initr_ide(void) { -#ifdef CONFIG_IDE_8xx_PCCARD - puts("PCMCIA:"); -#else puts("IDE: "); -#endif #if defined(CONFIG_START_IDE) if (board_start_ide()) ide_init(); @@ -786,9 +775,6 @@ static init_fnc_t init_sequence_r[] = { initr_post_backlog, #endif INIT_FUNC_WATCHDOG_RESET -#ifdef CONFIG_SYS_DELAYED_ICACHE - initr_icache_enable, -#endif #if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) /* * Do early PCI configuration _before_ the flash gets initialised, diff --git a/common/bootm_os.c b/common/bootm_os.c index e102406..d9e6e93 100644 --- a/common/bootm_os.c +++ b/common/bootm_os.c @@ -56,7 +56,6 @@ static int do_bootm_netbsd(int flag, int argc, char * const argv[], void (*loader)(bd_t *, image_header_t *, char *, char *); image_header_t *os_hdr, *hdr; ulong kernel_data, kernel_len; - char *consdev; char *cmdline;

if (flag != BOOTM_STATE_OS_GO) @@ -88,17 +87,6 @@ static int do_bootm_netbsd(int flag, int argc, char * const argv[], os_hdr = hdr; }

- consdev = ""; -#if defined(CONFIG_8xx_CONS_SMC1) - consdev = "smc1"; -#elif defined(CONFIG_8xx_CONS_SMC2) - consdev = "smc2"; -#elif defined(CONFIG_8xx_CONS_SCC2) - consdev = "scc2"; -#elif defined(CONFIG_8xx_CONS_SCC3) - consdev = "scc3"; -#endif - if (argc > 0) { ulong len; int i; @@ -127,7 +115,7 @@ static int do_bootm_netbsd(int flag, int argc, char * const argv[], * arg[2]: char pointer to the console device to use * arg[3]: char pointer to the boot arguments */ - (*loader)(gd->bd, os_hdr, consdev, cmdline); + (*loader)(gd->bd, os_hdr, "", cmdline);

return 1; } diff --git a/common/lcd.c b/common/lcd.c index 2405146..7e399ce 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -562,11 +562,7 @@ __weak void lcd_set_cmap(struct bmp_image *bmp, unsigned colors) *cmap = (((cte.red) << 8) & 0xf800) | (((cte.green) << 3) & 0x07e0) | (((cte.blue) >> 3) & 0x001f); -#if defined(CONFIG_MPC823) - cmap--; -#else cmap++; -#endif } }

diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig deleted file mode 100644 index ccb68b2..0000000 --- a/configs/TQM823L_LCD_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM823L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="NEC_NL6448BC20" -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM823L_defconfig b/configs/TQM823L_defconfig deleted file mode 100644 index c588948..0000000 --- a/configs/TQM823L_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM823L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM823M_defconfig b/configs/TQM823M_defconfig deleted file mode 100644 index 0490828..0000000 --- a/configs/TQM823M_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM823M=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM850L_defconfig b/configs/TQM850L_defconfig deleted file mode 100644 index 0e42d8c..0000000 --- a/configs/TQM850L_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM850L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM850M_defconfig b/configs/TQM850M_defconfig deleted file mode 100644 index a464fe5..0000000 --- a/configs/TQM850M_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM850M=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM855L_defconfig b/configs/TQM855L_defconfig deleted file mode 100644 index aa37001..0000000 --- a/configs/TQM855L_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM855L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM855M_defconfig b/configs/TQM855M_defconfig deleted file mode 100644 index faab826..0000000 --- a/configs/TQM855M_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM855M=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM860L_defconfig b/configs/TQM860L_defconfig deleted file mode 100644 index b18cf31..0000000 --- a/configs/TQM860L_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM860L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM860M_defconfig b/configs/TQM860M_defconfig deleted file mode 100644 index fe2fe6d..0000000 --- a/configs/TQM860M_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM860M=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM862L_defconfig b/configs/TQM862L_defconfig deleted file mode 100644 index 6f5f772..0000000 --- a/configs/TQM862L_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM862L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM862M_defconfig b/configs/TQM862M_defconfig deleted file mode 100644 index 4430776..0000000 --- a/configs/TQM862M_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM862M=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM866M_defconfig b/configs/TQM866M_defconfig deleted file mode 100644 index d892290..0000000 --- a/configs/TQM866M_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM866M=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM885D_defconfig b/configs/TQM885D_defconfig deleted file mode 100644 index 48421e3..0000000 --- a/configs/TQM885D_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM885D=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig deleted file mode 100644 index 9d26e94..0000000 --- a/configs/TTTech_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM823L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SHARP_LQ104V7DS01" -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig deleted file mode 100644 index 2b81535..0000000 --- a/configs/wtk_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM823L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SHARP_LQ065T9DR51U" -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/doc/README.LED b/doc/README.LED index 7aa95bd..c21c9d5 100644 --- a/doc/README.LED +++ b/doc/README.LED @@ -73,6 +73,5 @@ These are weakly defined in arch/arm/lib/board.c to noops. Where applicable, def these functions in the board specific source.

TBD : Describe older board dependent macros similar to what is done for -CONFIG_TQM8xxL.

TBD : Describe general support via asm/status_led.h diff --git a/doc/README.MPC866 b/doc/README.MPC866 deleted file mode 100644 index 4707cb7..0000000 --- a/doc/README.MPC866 +++ /dev/null @@ -1,24 +0,0 @@ -The current implementation allows the user to specify the desired CPU -clock value, in MHz, via an environment variable "cpuclk". - -Four compile-time constants are used: - - CONFIG_8xx_OSCLK - input quartz clock - CONFIG_SYS_8xx_CPUCLK_MIN - minimum allowed CPU clock - CONFIG_SYS_8xx_CPUCLK_MAX - maximum allowed CPU clock - CONFIG_8xx_CPUCLK_DEFAULT - default CPU clock value - -If the "cpuclk" environment variable value is within the CPUCLK_MIN / -CPUCLK_MAX limits, the specified value is used. Otherwise, the -default CPU clock value is set. - -Please make sure you understand what you are doing, and understand -the restrictions of your hardware (board, processor). For example, -ethernet will stop working for CPU clock frequencies below 25 MHz. - -Please note that the new clock-handling code is enabled if -CONFIG_8xx_CPUCLK_DEFAULT is defined. Since this mechanism supports -only MPC866 and newer CPUs, this constant MUST NOT be defined for -MPC823/850/860/862 series. The clock generation algorithm for older -chips is different and has not been implemented yet. If you need it, -your patch is welcome. diff --git a/doc/README.fsl-clk b/doc/README.fsl-clk deleted file mode 100644 index 9e83c24..0000000 --- a/doc/README.fsl-clk +++ /dev/null @@ -1,6 +0,0 @@ -Freescale system clock options - - - CONFIG_SYS_FSL_CLK - Enable to call get_clocks() in board_init_f() for - non-PPC platforms and PCC 8xx platforms such as - TQM866M and TQM885D. diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 200f670..11d3acc 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -316,7 +316,6 @@ ADCIOP powerpc ppc4xx 99bcad1 2012-09-19 Matthias Fuc DASA_SIM powerpc ppc4xx 99bcad1 2012-09-19 Matthias Fuchs matthias.fuchs@esd-electronics.com apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park kyungmin.park@samsung.com tb0229 mips mips32 3f3110d 2011-12-12 -rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk wd@denx.de OXC powerpc MPC8240 309a292 2011-12-07 BAB7xx powerpc MPC740/MPC750 c53043b 2011-12-07 Frank Gottschling fgottschling@eltec.de xm250 arm pxa c477d72 2011-11-25 diff --git a/drivers/block/ide.c b/drivers/block/ide.c index ac5b91c..308ad73 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -770,10 +770,6 @@ void ide_init(void) unsigned char c; int i, bus;

-#ifdef CONFIG_IDE_8xx_PCCARD - extern int ide_devices_found; /* Initialized in check_ide_device() */ -#endif /* CONFIG_IDE_8xx_PCCARD */ - #ifdef CONFIG_IDE_PREINIT WATCHDOG_RESET();

@@ -812,13 +808,6 @@ void ide_init(void) bus * (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS);

-#ifdef CONFIG_IDE_8xx_PCCARD - /* Skip non-ide devices from probing */ - if ((ide_devices_found & (1 << bus)) == 0) { - ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */ - continue; - } -#endif printf("Bus %d: ", bus);

ide_bus_ok[bus] = 0; diff --git a/drivers/block/sil680.c b/drivers/block/sil680.c index b1db257..bca3397 100644 --- a/drivers/block/sil680.c +++ b/drivers/block/sil680.c @@ -18,7 +18,6 @@ * #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 * * #define CONFIG_IDE - * #undef CONFIG_IDE_8xx_DIRECT * #undef CONFIG_IDE_LED * #undef CONFIG_IDE_RESET * #define CONFIG_IDE_PREINIT diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c index d5ce450..f922cfb 100644 --- a/drivers/bootcount/bootcount.c +++ b/drivers/bootcount/bootcount.c @@ -24,11 +24,6 @@ #define CONFIG_SYS_BOOTCOUNT_SINGLEWORD #endif /* defined(CONFIG_MPC512X) */

-#if defined(CONFIG_8xx) -#define CONFIG_SYS_BOOTCOUNT_ADDR (((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + \ - CPM_BOOTCOUNT_ADDR) -#endif /* defined(CONFIG_8xx) */ - #if defined(CONFIG_MPC8260) #include <asm/cpm_8260.h> #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR) diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 19769da..911563b 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -323,11 +323,6 @@ uint8_t i2c_reg_read(uint8_t addr, uint8_t reg) { uint8_t buf;

-#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - /* maybe it is now the time for it ... */ - i2c_set_bus_num(i2c_get_bus_num()); -#endif i2c_read(addr, reg, 1, &buf, 1);

#ifdef DEBUG @@ -340,12 +335,6 @@ uint8_t i2c_reg_read(uint8_t addr, uint8_t reg)

void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val) { -#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - /* maybe it is now the time for it ... */ - i2c_set_bus_num(i2c_get_bus_num()); -#endif - #ifdef DEBUG printf("%s: bus=%d addr=0x%02x, reg=0x%02x, val=0x%02x\n", __func__, i2c_get_bus_num(), addr, reg, val); diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index c102a1a..9380a04 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -97,9 +97,6 @@ DECLARE_GLOBAL_DATA_PTR; # if defined(CONFIG_MPC8260) # define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = \ ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); -# elif defined(CONFIG_8xx) -# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = \ - (immap_t *)CONFIG_SYS_IMMR; # else # define I2C_SOFT_DECLARATIONS # endif diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index ca11396..e759339 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -67,7 +67,6 @@ #include <asm/io.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <commproc.h> #include <asm/ppc4xx.h> #include <asm/ppc4xx-emac.h> #include <asm/ppc4xx-mal.h> diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index c506f79..b7e6188 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -5,7 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-$(CONFIG_8xx) += mpc8xx_pcmcia.o obj-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o -obj-y += tqm8xx_pcmcia.o obj-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c deleted file mode 100644 index dae5560..0000000 --- a/drivers/pcmcia/mpc8xx_pcmcia.c +++ /dev/null @@ -1,258 +0,0 @@ -#include <common.h> -#include <mpc8xx.h> -#include <pcmcia.h> -#include <linux/compiler.h> - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_PCMCIA) - -#if defined(CONFIG_IDE_8xx_PCCARD) -extern int check_ide_device (int slot); -#endif - -extern int pcmcia_hardware_enable (int slot); -extern int pcmcia_voltage_set(int slot, int vcc, int vpp); - -#if defined(CONFIG_CMD_PCMCIA) -extern int pcmcia_hardware_disable(int slot); -#endif - -static u_int m8xx_get_graycode(u_int size); -#if 0 /* Disabled */ -static u_int m8xx_get_speed(u_int ns, u_int is_io); -#endif - -/* look up table for pgcrx registers */ -u_int *pcmcia_pgcrx[2] = { - &((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcra, - &((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb, -}; - -/* - * Search this table to see if the windowsize is - * supported... - */ - -#define M8XX_SIZES_NO 32 - -static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] = -{ 0x00000001, 0x00000002, 0x00000008, 0x00000004, - 0x00000080, 0x00000040, 0x00000010, 0x00000020, - 0x00008000, 0x00004000, 0x00001000, 0x00002000, - 0x00000100, 0x00000200, 0x00000800, 0x00000400, - - 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0x01000000, 0x02000000, 0xffffffff, 0x04000000, - 0x00010000, 0x00020000, 0x00080000, 0x00040000, - 0x00800000, 0x00400000, 0x00100000, 0x00200000 }; - - -/* -------------------------------------------------------------------- */ - -#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(2) \ - | PCMCIA_SST(4) \ - | PCMCIA_SL(9)) - -/* -------------------------------------------------------------------- */ - -int pcmcia_on (void) -{ - u_long reg, base; - pcmcia_win_t *win; - u_int rc, slot; - __maybe_unused u_int slotbit; - int i; - - debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - /* intialize the fixed memory windows */ - win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0); - base = CONFIG_SYS_PCMCIA_MEM_ADDR; - - if((reg = m8xx_get_graycode(CONFIG_SYS_PCMCIA_MEM_SIZE)) == -1) { - printf ("Cannot set window size to 0x%08x\n", - CONFIG_SYS_PCMCIA_MEM_SIZE); - return (1); - } - - slotbit = PCMCIA_SLOT_x; - for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) { - win->br = base; - -#if (PCMCIA_SOCKETS_NO == 2) - if (i == 4) /* Another slot starting from win 4 */ - slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B); -#endif - switch (i) { -#ifdef CONFIG_IDE_8xx_PCCARD - case 4: - case 0: { /* map attribute memory */ - win->or = ( PCMCIA_BSIZE_64M - | PCMCIA_PPS_8 - | PCMCIA_PRS_ATTR - | slotbit - | PCMCIA_PV - | CONFIG_SYS_PCMCIA_TIMING ); - break; - } - case 5: - case 1: { /* map I/O window for data reg */ - win->or = ( PCMCIA_BSIZE_1K - | PCMCIA_PPS_16 - | PCMCIA_PRS_IO - | slotbit - | PCMCIA_PV - | CONFIG_SYS_PCMCIA_TIMING ); - break; - } - case 6: - case 2: { /* map I/O window for cmd/ctrl reg block */ - win->or = ( PCMCIA_BSIZE_1K - | PCMCIA_PPS_8 - | PCMCIA_PRS_IO - | slotbit - | PCMCIA_PV - | CONFIG_SYS_PCMCIA_TIMING ); - break; - } -#endif /* CONFIG_IDE_8xx_PCCARD */ - default: /* set to not valid */ - win->or = 0; - break; - } - - debug ("MemWin %d: PBR 0x%08lX POR %08lX\n", - i, win->br, win->or); - base += CONFIG_SYS_PCMCIA_MEM_SIZE; - ++win; - } - - for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) { - /* turn off voltage */ - if ((rc = pcmcia_voltage_set(slot, 0, 0))) - continue; - - /* Enable external hardware */ - if ((rc = pcmcia_hardware_enable(slot))) - continue; - -#ifdef CONFIG_IDE_8xx_PCCARD - if ((rc = check_ide_device(i))) - continue; -#endif - } - return rc; -} - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_off (void) -{ - int i; - pcmcia_win_t *win; - - printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - /* clear interrupt state, and disable interrupts */ - ((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_); - ((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* turn off interrupt and disable CxOE */ - PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE; - - /* turn off memory windows */ - win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0); - - for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) { - /* disable memory window */ - win->or = 0; - ++win; - } - - /* turn off voltage */ - pcmcia_voltage_set(_slot_, 0, 0); - - /* disable external hardware */ - printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n"); - pcmcia_hardware_disable(_slot_); - return 0; -} -#endif - - -static u_int m8xx_get_graycode(u_int size) -{ - u_int k; - - for (k = 0; k < M8XX_SIZES_NO; k++) { - if(m8xx_size_to_gray[k] == size) - break; - } - - if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) - k = -1; - - return k; -} - -#if 0 - -static u_int m8xx_get_speed(u_int ns, u_int is_io) -{ - u_int reg, clocks, psst, psl, psht; - - if(!ns) { - - /* - * We get called with IO maps setup to 0ns - * if not specified by the user. - * They should be 255ns. - */ - - if(is_io) - ns = 255; - else - ns = 100; /* fast memory if 0 */ - } - - /* - * In PSST, PSL, PSHT fields we tell the controller - * timing parameters in CLKOUT clock cycles. - * CLKOUT is the same as GCLK2_50. - */ - - /* how we want to adjust the timing - in percent */ - -#define ADJ 180 /* 80 % longer accesstime - to be sure */ - - clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000; - clocks = (clocks * ADJ) / (100*1000); - - if(clocks >= PCMCIA_BMT_LIMIT) { - DEBUG(0, "Max access time limit reached\n"); - clocks = PCMCIA_BMT_LIMIT-1; - } - - psst = clocks / 7; /* setup time */ - psht = clocks / 7; /* hold time */ - psl = (clocks * 5) / 7; /* strobe length */ - - psst += clocks - (psst + psht + psl); - - reg = psst << 12; - reg |= psl << 7; - reg |= psht << 16; - - return reg; -} -#endif /* 0 */ - -#endif /* CONFIG_PCMCIA */ diff --git a/drivers/pcmcia/tqm8xx_pcmcia.c b/drivers/pcmcia/tqm8xx_pcmcia.c deleted file mode 100644 index edff50f..0000000 --- a/drivers/pcmcia/tqm8xx_pcmcia.c +++ /dev/null @@ -1,254 +0,0 @@ -/* -------------------------------------------------------------------- */ -/* TQM8xxL Boards by TQ Components */ -/* SC8xx Boards by SinoVee Microsystems */ -/* -------------------------------------------------------------------- */ -#include <common.h> -#include <asm/io.h> -#ifdef CONFIG_8xx -#include <mpc8xx.h> -#endif -#include <pcmcia.h> - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_PCMCIA) \ - && defined(CONFIG_TQM8xxL) - -#if defined(CONFIG_TQM8xxL) -#define PCMCIA_BOARD_MSG "TQM8xxL" -#endif - -static inline void power_config(int slot) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable - */ - clrbits_be16(&immap->im_ioport.iop_pcpar, 0x0002 | 0x0004); - clrbits_be16(&immap->im_ioport.iop_pcso, 0x0002 | 0x0004); -} - -static inline void power_off(int slot) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - clrbits_be16(&immap->im_ioport.iop_pcdat, 0x0002 | 0x0004); -} - -static inline void power_on_5_0(int slot) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - setbits_be16(&immap->im_ioport.iop_pcdat, 0x0004); - setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004); -} - -static inline void power_on_3_3(int slot) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - setbits_be16(&immap->im_ioport.iop_pcdat, 0x0002); - setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004); -} - -/* - * Function to retrieve the PIPR register, used for debuging purposes. - */ -static inline uint32_t debug_get_pipr(void) -{ - uint32_t pipr = 0; -#ifdef DEBUG - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - pipr = in_be32(&immap->im_pcmcia.pcmc_pipr); -#endif - return pipr; -} - - -static inline int check_card_is_absent(int slot) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - uint32_t pipr = in_be32(&immap->im_pcmcia.pcmc_pipr); - return pipr & (0x18000000 >> (slot << 4)); -} - -#define NSCU_GCRX_CXOE __MY_PCMCIA_GCRX_CXOE - -int pcmcia_hardware_enable(int slot) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - uint reg, mask; - - debug("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - - /* Set DBGC to 00 */ - clrbits_be32(&immap->im_siu_conf.sc_siumcr, SIUMCR_DBGC11); - - /* Clear interrupt state, and disable interrupts */ - out_be32(&immap->im_pcmcia.pcmc_pscr, PCMCIA_MASK(slot)); - clrbits_be32(&immap->im_pcmcia.pcmc_per, PCMCIA_MASK(slot)); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= NSCU_GCRX_CXOE; - - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - power_config(slot); - power_off(slot); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - reg = debug_get_pipr(); - debug("[%d] %s: PIPR(%p)=0x%x\n", __LINE__, __FUNCTION__, - &immap->im_pcmcia.pcmc_pipr, reg); - - if (check_card_is_absent(slot)) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - reg = in_be32(&immap->im_pcmcia.pcmc_pipr); - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - reg, - (reg & PCMCIA_VS1(slot)) ? "n" : "ff", - (reg & PCMCIA_VS2(slot)) ? "n" : "ff"); - - if ((reg & mask) == mask) { - power_on_5_0(slot); - puts (" 5.0V card found: "); - } else { - power_on_3_3(slot); - puts (" 3.3V card found: "); - } - -#if 0 - /* VCC switch error flag, PCMCIA slot INPACK_ pin */ - cp->cp_pbdir &= ~(0x0020 | 0x0010); - cp->cp_pbpar &= ~(0x0020 | 0x0010); - udelay(500000); -#endif - - udelay(1000); - debug("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - reg &= ~NSCU_GCRX_CXOE; - - PCMCIA_PGCRX(slot) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug("# hardware_enable done\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - u_long reg; - - debug("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - /* remove all power */ - power_off(slot); - - debug("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= NSCU_GCRX_CXOE; /* active low */ - - PCMCIA_PGCRX(slot) = reg; - - udelay(10000); - - return (0); -} -#endif - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - u_long reg; - uint32_t pipr = 0; - - debug("voltage_set: " PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - reg |= NSCU_GCRX_CXOE; /* active low */ - - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - debug("PCMCIA power OFF\n"); - power_config(slot); - power_off(slot); - - switch(vcc) { - case 0: break; - case 33: power_on_3_3(slot); break; - case 50: power_on_5_0(slot); break; - default: goto done; - } - - /* Checking supported voltages */ - pipr = debug_get_pipr(); - debug("PIPR: 0x%x --> %s\n", pipr, - (pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - if (vcc) - debug("PCMCIA powered at %sV\n", (vcc == 50) ? "5.0" : "3.3"); - else - debug("PCMCIA powered down\n"); - -done: - debug("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - reg &= ~NSCU_GCRX_CXOE; /* active low */ - - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A'); - return 0; -} - -#endif /* CONFIG_PCMCIA && CONFIG_TQM8xxL */ diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 438681d..3bc918c1 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -39,7 +39,6 @@ obj-$(CONFIG_RTC_MCP79411) += ds1307.o obj-$(CONFIG_MCFRTC) += mcfrtc.o obj-$(CONFIG_RTC_MK48T59) += mk48t59.o obj-$(CONFIG_RTC_MPC5200) += mpc5xxx.o -obj-$(CONFIG_RTC_MPC8xx) += mpc8xx.o obj-$(CONFIG_RTC_MV) += mvrtc.o obj-$(CONFIG_RTC_MX27) += mx27rtc.o obj-$(CONFIG_RTC_MXS) += mxsrtc.o diff --git a/drivers/rtc/mpc8xx.c b/drivers/rtc/mpc8xx.c deleted file mode 100644 index 147a225..0000000 --- a/drivers/rtc/mpc8xx.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Date & Time support for internal RTC of MPC8xx - */ - -/*#define DEBUG*/ - -#include <common.h> -#include <command.h> -#include <rtc.h> - -#if defined(CONFIG_CMD_DATE) - -/* ------------------------------------------------------------------------- */ - -int rtc_get (struct rtc_time *tmp) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - ulong tim; - - tim = immr->im_sit.sit_rtc; - - rtc_to_tm(tim, tmp); - - debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - ulong tim; - - debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - tim = rtc_mktime(tmp); - - immr->im_sitk.sitk_rtck = KAPWR_KEY; - immr->im_sit.sit_rtc = tim; - - return 0; -} - -void rtc_reset (void) -{ - return; /* nothing to do */ -} - -#endif diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 0fbbb7c..5e316a7 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -41,7 +41,6 @@ ifdef CONFIG_USB_DEVICE obj-y += core.o obj-y += ep0.o obj-$(CONFIG_DW_UDC) += designware_udc.o -obj-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o obj-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o endif endif diff --git a/drivers/usb/gadget/mpc8xx_udc.c b/drivers/usb/gadget/mpc8xx_udc.c deleted file mode 100644 index ad5ea7a..0000000 --- a/drivers/usb/gadget/mpc8xx_udc.c +++ /dev/null @@ -1,1386 +0,0 @@ -/* - * Copyright (C) 2006 by Bryan O'Donoghue, CodeHermit - * bodonoghue@CodeHermit.ie - * - * References - * DasUBoot/drivers/usb/gadget/omap1510_udc.c, for design and implementation - * ideas. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Notes : - * 1. #define __SIMULATE_ERROR__ to inject a CRC error into every 2nd TX - * packet to force the USB re-transmit protocol. - * - * 2. #define __DEBUG_UDC__ to switch on debug tracing to serial console - * be careful that tracing doesn't create Hiesen-bugs with respect to - * response timeouts to control requests. - * - * 3. This driver should be able to support any higher level driver that - * that wants to do either of the two standard UDC implementations - * Control-Bulk-Interrupt or Bulk-IN/Bulk-Out standards. Hence - * gserial and cdc_acm should work with this code. - * - * 4. NAK events never actually get raised at all, the documentation - * is just wrong ! - * - * 5. For some reason, cbd_datlen is *always* +2 the value it should be. - * this means that having an RX cbd of 16 bytes is not possible, since - * the same size is reported for 14 bytes received as 16 bytes received - * until we can find out why this happens, RX cbds must be limited to 8 - * bytes. TODO: check errata for this behaviour. - * - * 6. Right now this code doesn't support properly powering up with the USB - * cable attached to the USB host my development board the Adder87x doesn't - * have a pull-up fitted to allow this, so it is necessary to power the - * board and *then* attached the USB cable to the host. However somebody - * with a different design in their board may be able to keep the cable - * constantly connected and simply enable/disable a pull-up re - * figure 31.1 in MPC885RM.pdf instead of having to power up the board and - * then attach the cable ! - * - */ -#include <common.h> -#include <config.h> -#include <commproc.h> -#include <usbdevice.h> -#include <usb/mpc8xx_udc.h> -#include <usb/udc.h> - -#include "ep0.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define ERR(fmt, args...)\ - serial_printf("ERROR : [%s] %s:%d: "fmt,\ - __FILE__,__FUNCTION__,__LINE__, ##args) -#ifdef __DEBUG_UDC__ -#define DBG(fmt,args...)\ - serial_printf("[%s] %s:%d: "fmt,\ - __FILE__,__FUNCTION__,__LINE__, ##args) -#else -#define DBG(fmt,args...) -#endif - -/* Static Data */ -#ifdef __SIMULATE_ERROR__ -static char err_poison_test = 0; -#endif -static struct mpc8xx_ep ep_ref[MAX_ENDPOINTS]; -static u32 address_base = STATE_NOT_READY; -static mpc8xx_udc_state_t udc_state = 0; -static struct usb_device_instance *udc_device = 0; -static volatile usb_epb_t *endpoints[MAX_ENDPOINTS]; -static volatile cbd_t *tx_cbd[TX_RING_SIZE]; -static volatile cbd_t *rx_cbd[RX_RING_SIZE]; -static volatile immap_t *immr = 0; -static volatile cpm8xx_t *cp = 0; -static volatile usb_pram_t *usb_paramp = 0; -static volatile usb_t *usbp = 0; -static int rx_ct = 0; -static int tx_ct = 0; - -/* Static Function Declarations */ -static void mpc8xx_udc_state_transition_up (usb_device_state_t initial, - usb_device_state_t final); -static void mpc8xx_udc_state_transition_down (usb_device_state_t initial, - usb_device_state_t final); -static void mpc8xx_udc_stall (unsigned int ep); -static void mpc8xx_udc_flush_tx_fifo (int epid); -static void mpc8xx_udc_flush_rx_fifo (void); -static void mpc8xx_udc_clear_rxbd (volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_init_tx (struct usb_endpoint_instance *epi, - struct urb *tx_urb); -static void mpc8xx_udc_dump_request (struct usb_device_request *request); -static void mpc8xx_udc_clock_init (volatile immap_t * immr, - volatile cpm8xx_t * cp); -static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi); -static int mpc8xx_udc_epn_rx (unsigned int epid, volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_ep0_rx (volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_cbd_init (void); -static void mpc8xx_udc_endpoint_init (void); -static void mpc8xx_udc_cbd_attach (int ep, uchar tx_size, uchar rx_size); -static u32 mpc8xx_udc_alloc (u32 data_size, u32 alignment); -static int mpc8xx_udc_ep0_rx_setup (volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_set_nak (unsigned int ep); -static short mpc8xx_udc_handle_txerr (void); -static void mpc8xx_udc_advance_rx (volatile cbd_t ** rx_cbdp, int epid); - -/****************************************************************************** - Global Linkage - *****************************************************************************/ - -/* udc_init - * - * Do initial bus gluing - */ -int udc_init (void) -{ - /* Init various pointers */ - immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8xx_t *) & (immr->im_cpm); - usb_paramp = (usb_pram_t *) & (cp->cp_dparam[PROFF_USB]); - usbp = (usb_t *) & (cp->cp_scc[0]); - - memset (ep_ref, 0x00, (sizeof (struct mpc8xx_ep) * MAX_ENDPOINTS)); - - udc_device = 0; - udc_state = STATE_NOT_READY; - - usbp->usmod = 0x00; - usbp->uscom = 0; - - /* Set USB Frame #0, Respond at Address & Get a clock source */ - usbp->usaddr = 0x00; - mpc8xx_udc_clock_init (immr, cp); - - /* PA15, PA14 as perhiperal USBRXD and USBOE */ - immr->im_ioport.iop_padir &= ~0x0003; - immr->im_ioport.iop_papar |= 0x0003; - - /* PC11/PC10 as peripheral USBRXP USBRXN */ - immr->im_ioport.iop_pcso |= 0x0030; - - /* PC7/PC6 as perhiperal USBTXP and USBTXN */ - immr->im_ioport.iop_pcdir |= 0x0300; - immr->im_ioport.iop_pcpar |= 0x0300; - - /* Set the base address */ - address_base = (u32) (cp->cp_dpmem + CPM_USB_BASE); - - /* Initialise endpoints and circular buffers */ - mpc8xx_udc_endpoint_init (); - mpc8xx_udc_cbd_init (); - - /* Assign allocated Dual Port Endpoint descriptors */ - usb_paramp->ep0ptr = (u32) endpoints[0]; - usb_paramp->ep1ptr = (u32) endpoints[1]; - usb_paramp->ep2ptr = (u32) endpoints[2]; - usb_paramp->ep3ptr = (u32) endpoints[3]; - usb_paramp->frame_n = 0; - - DBG ("ep0ptr=0x%08x ep1ptr=0x%08x ep2ptr=0x%08x ep3ptr=0x%08x\n", - usb_paramp->ep0ptr, usb_paramp->ep1ptr, usb_paramp->ep2ptr, - usb_paramp->ep3ptr); - - return 0; -} - -/* udc_irq - * - * Poll for whatever events may have occurred - */ -void udc_irq (void) -{ - int epid = 0; - volatile cbd_t *rx_cbdp = 0; - volatile cbd_t *rx_cbdp_base = 0; - - if (udc_state != STATE_READY) { - return; - } - - if (usbp->usber & USB_E_BSY) { - /* This shouldn't happen. If it does then it's a bug ! */ - usbp->usber |= USB_E_BSY; - mpc8xx_udc_flush_rx_fifo (); - } - - /* Scan all RX/Bidirectional Endpoints for RX data. */ - for (epid = 0; epid < MAX_ENDPOINTS; epid++) { - if (!ep_ref[epid].prx) { - continue; - } - rx_cbdp = rx_cbdp_base = ep_ref[epid].prx; - - do { - if (!(rx_cbdp->cbd_sc & RX_BD_E)) { - - if (rx_cbdp->cbd_sc & 0x1F) { - /* Corrupt data discard it. - * Controller has NAK'd this packet. - */ - mpc8xx_udc_clear_rxbd (rx_cbdp); - - } else { - if (!epid) { - mpc8xx_udc_ep0_rx (rx_cbdp); - - } else { - /* Process data */ - mpc8xx_udc_set_nak (epid); - mpc8xx_udc_epn_rx (epid, rx_cbdp); - mpc8xx_udc_clear_rxbd (rx_cbdp); - } - } - - /* Advance RX CBD pointer */ - mpc8xx_udc_advance_rx (&rx_cbdp, epid); - ep_ref[epid].prx = rx_cbdp; - } else { - /* Advance RX CBD pointer */ - mpc8xx_udc_advance_rx (&rx_cbdp, epid); - } - - } while (rx_cbdp != rx_cbdp_base); - } - - /* Handle TX events as appropiate, the correct place to do this is - * in a tx routine. Perhaps TX on epn was pre-empted by ep0 - */ - - if (usbp->usber & USB_E_TXB) { - usbp->usber |= USB_E_TXB; - } - - if (usbp->usber & (USB_TX_ERRMASK)) { - mpc8xx_udc_handle_txerr (); - } - - /* Switch to the default state, respond at the default address */ - if (usbp->usber & USB_E_RESET) { - usbp->usber |= USB_E_RESET; - usbp->usaddr = 0x00; - udc_device->device_state = STATE_DEFAULT; - } - - /* if(usbp->usber&USB_E_IDLE){ - We could suspend here ! - usbp->usber|=USB_E_IDLE; - DBG("idle state change\n"); - } - if(usbp->usbs){ - We could resume here when IDLE is deasserted ! - Not worth doing, so long as we are self powered though. - } - */ - - return; -} - -/* udc_endpoint_write - * - * Write some data to an endpoint - */ -int udc_endpoint_write (struct usb_endpoint_instance *epi) -{ - int ep = 0; - short epid = 1, unnak = 0, ret = 0; - - if (udc_state != STATE_READY) { - ERR ("invalid udc_state != STATE_READY!\n"); - return -1; - } - - if (!udc_device || !epi) { - return -1; - } - - if (udc_device->device_state != STATE_CONFIGURED) { - return -1; - } - - ep = epi->endpoint_address & 0x03; - if (ep >= MAX_ENDPOINTS) { - return -1; - } - - /* Set NAK for all RX endpoints during TX */ - for (epid = 1; epid < MAX_ENDPOINTS; epid++) { - - /* Don't set NAK on DATA IN/CONTROL endpoints */ - if (ep_ref[epid].sc & USB_DIR_IN) { - continue; - } - - if (!(usbp->usep[epid] & (USEP_THS_NAK | USEP_RHS_NAK))) { - unnak |= 1 << epid; - } - - mpc8xx_udc_set_nak (epid); - } - - mpc8xx_udc_init_tx (&udc_device->bus->endpoint_array[ep], - epi->tx_urb); - ret = mpc8xx_udc_ep_tx (&udc_device->bus->endpoint_array[ep]); - - /* Remove temporary NAK */ - for (epid = 1; epid < MAX_ENDPOINTS; epid++) { - if (unnak & (1 << epid)) { - udc_unset_nak (epid); - } - } - - return ret; -} - -/* mpc8xx_udc_assign_urb - * - * Associate a given urb to an endpoint TX or RX transmit/receive buffers - */ -static int mpc8xx_udc_assign_urb (int ep, char direction) -{ - struct usb_endpoint_instance *epi = 0; - - if (ep >= MAX_ENDPOINTS) { - goto err; - } - epi = &udc_device->bus->endpoint_array[ep]; - if (!epi) { - goto err; - } - - if (!ep_ref[ep].urb) { - ep_ref[ep].urb = usbd_alloc_urb (udc_device, udc_device->bus->endpoint_array); - if (!ep_ref[ep].urb) { - goto err; - } - } else { - ep_ref[ep].urb->actual_length = 0; - } - - switch (direction) { - case USB_DIR_IN: - epi->tx_urb = ep_ref[ep].urb; - break; - case USB_DIR_OUT: - epi->rcv_urb = ep_ref[ep].urb; - break; - default: - goto err; - } - return 0; - - err: - udc_state = STATE_ERROR; - return -1; -} - -/* udc_setup_ep - * - * Associate U-Boot software endpoints to mpc8xx endpoint parameter ram - * Isochronous endpoints aren't yet supported! - */ -void udc_setup_ep (struct usb_device_instance *device, unsigned int ep, - struct usb_endpoint_instance *epi) -{ - uchar direction = 0; - int ep_attrib = 0; - - if (epi && (ep < MAX_ENDPOINTS)) { - - if (ep == 0) { - if (epi->rcv_attributes != USB_ENDPOINT_XFER_CONTROL - || epi->tx_attributes != - USB_ENDPOINT_XFER_CONTROL) { - - /* ep0 must be a control endpoint */ - udc_state = STATE_ERROR; - return; - - } - if (!(ep_ref[ep].sc & EP_ATTACHED)) { - mpc8xx_udc_cbd_attach (ep, epi->tx_packetSize, - epi->rcv_packetSize); - } - usbp->usep[ep] = 0x0000; - return; - } - - if ((epi->endpoint_address & USB_ENDPOINT_DIR_MASK) - == USB_DIR_IN) { - - direction = 1; - ep_attrib = epi->tx_attributes; - epi->rcv_packetSize = 0; - ep_ref[ep].sc |= USB_DIR_IN; - } else { - - direction = 0; - ep_attrib = epi->rcv_attributes; - epi->tx_packetSize = 0; - ep_ref[ep].sc &= ~USB_DIR_IN; - } - - if (mpc8xx_udc_assign_urb (ep, epi->endpoint_address - & USB_ENDPOINT_DIR_MASK)) { - return; - } - - switch (ep_attrib) { - case USB_ENDPOINT_XFER_CONTROL: - if (!(ep_ref[ep].sc & EP_ATTACHED)) { - mpc8xx_udc_cbd_attach (ep, - epi->tx_packetSize, - epi->rcv_packetSize); - } - usbp->usep[ep] = ep << 12; - epi->rcv_urb = epi->tx_urb = ep_ref[ep].urb; - - break; - case USB_ENDPOINT_XFER_BULK: - case USB_ENDPOINT_XFER_INT: - if (!(ep_ref[ep].sc & EP_ATTACHED)) { - if (direction) { - mpc8xx_udc_cbd_attach (ep, - epi->tx_packetSize, - 0); - } else { - mpc8xx_udc_cbd_attach (ep, - 0, - epi->rcv_packetSize); - } - } - usbp->usep[ep] = (ep << 12) | ((ep_attrib) << 8); - - break; - case USB_ENDPOINT_XFER_ISOC: - default: - serial_printf ("Error endpoint attrib %d>3\n", ep_attrib); - udc_state = STATE_ERROR; - break; - } - } - -} - -/* udc_connect - * - * Move state, switch on the USB - */ -void udc_connect (void) -{ - /* Enable pull-up resistor on D+ - * TODO: fit a pull-up resistor to drive SE0 for > 2.5us - */ - - if (udc_state != STATE_ERROR) { - udc_state = STATE_READY; - usbp->usmod |= USMOD_EN; - } -} - -/* udc_disconnect - * - * Disconnect is not used but, is included for completeness - */ -void udc_disconnect (void) -{ - /* Disable pull-up resistor on D- - * TODO: fix a pullup resistor to control this - */ - - if (udc_state != STATE_ERROR) { - udc_state = STATE_NOT_READY; - } - usbp->usmod &= ~USMOD_EN; -} - -/* udc_enable - * - * Grab an EP0 URB, register interest in a subset of USB events - */ -void udc_enable (struct usb_device_instance *device) -{ - if (udc_state == STATE_ERROR) { - return; - } - - udc_device = device; - - if (!ep_ref[0].urb) { - ep_ref[0].urb = usbd_alloc_urb (device, device->bus->endpoint_array); - } - - /* Register interest in all events except SOF, enable transceiver */ - usbp->usber = 0x03FF; - usbp->usbmr = 0x02F7; - - return; -} - -/* udc_disable - * - * disable the currently hooked device - */ -void udc_disable (void) -{ - int i = 0; - - if (udc_state == STATE_ERROR) { - DBG ("Won't disable UDC. udc_state==STATE_ERROR !\n"); - return; - } - - udc_device = 0; - - for (; i < MAX_ENDPOINTS; i++) { - if (ep_ref[i].urb) { - usbd_dealloc_urb (ep_ref[i].urb); - ep_ref[i].urb = 0; - } - } - - usbp->usbmr = 0x00; - usbp->usmod = ~USMOD_EN; - udc_state = STATE_NOT_READY; -} - -/* udc_startup_events - * - * Enable the specified device - */ -void udc_startup_events (struct usb_device_instance *device) -{ - udc_enable (device); - if (udc_state == STATE_READY) { - usbd_device_event_irq (device, DEVICE_CREATE, 0); - } -} - -/* udc_set_nak - * - * Allow upper layers to signal lower layers should not accept more RX data - * - */ -void udc_set_nak (int epid) -{ - if (epid) { - mpc8xx_udc_set_nak (epid); - } -} - -/* udc_unset_nak - * - * Suspend sending of NAK tokens for DATA OUT tokens on a given endpoint. - * Switch off NAKing on this endpoint to accept more data output from host. - * - */ -void udc_unset_nak (int epid) -{ - if (epid > MAX_ENDPOINTS) { - return; - } - - if (usbp->usep[epid] & (USEP_THS_NAK | USEP_RHS_NAK)) { - usbp->usep[epid] &= ~(USEP_THS_NAK | USEP_RHS_NAK); - __asm__ ("eieio"); - } -} - -/****************************************************************************** - Static Linkage -******************************************************************************/ - -/* udc_state_transition_up - * udc_state_transition_down - * - * Helper functions to implement device state changes. The device states and - * the events that transition between them are: - * - * STATE_ATTACHED - * || /\ - * / || - * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET - * || /\ - * / || - * STATE_POWERED - * || /\ - * / || - * DEVICE_RESET DEVICE_POWER_INTERRUPTION - * || /\ - * / || - * STATE_DEFAULT - * || /\ - * / || - * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET - * || /\ - * / || - * STATE_ADDRESSED - * || /\ - * / || - * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED - * || /\ - * / || - * STATE_CONFIGURED - * - * udc_state_transition_up transitions up (in the direction from STATE_ATTACHED - * to STATE_CONFIGURED) from the specified initial state to the specified final - * state, passing through each intermediate state on the way. If the initial - * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then - * no state transitions will take place. - * - * udc_state_transition_down transitions down (in the direction from - * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the - * specified final state, passing through each intermediate state on the way. - * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final - * state, then no state transitions will take place. - * - */ - -static void mpc8xx_udc_state_transition_up (usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial < final) { - switch (initial) { - case STATE_ATTACHED: - usbd_device_event_irq (udc_device, - DEVICE_HUB_CONFIGURED, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq (udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq (udc_device, - DEVICE_ADDRESS_ASSIGNED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq (udc_device, DEVICE_CONFIGURED, - 0); - case STATE_CONFIGURED: - break; - default: - break; - } - } -} - -static void mpc8xx_udc_state_transition_down (usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial > final) { - switch (initial) { - case STATE_CONFIGURED: - usbd_device_event_irq (udc_device, - DEVICE_DE_CONFIGURED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq (udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq (udc_device, - DEVICE_POWER_INTERRUPTION, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq (udc_device, DEVICE_HUB_RESET, - 0); - case STATE_ATTACHED: - break; - default: - break; - } - } -} - -/* mpc8xx_udc_stall - * - * Force returning of STALL tokens on the given endpoint. Protocol or function - * STALL conditions are permissable here - */ -static void mpc8xx_udc_stall (unsigned int ep) -{ - usbp->usep[ep] |= STALL_BITMASK; -} - -/* mpc8xx_udc_set_nak - * - * Force returning of NAK responses for the given endpoint as a kind of very - * simple flow control - */ -static void mpc8xx_udc_set_nak (unsigned int ep) -{ - usbp->usep[ep] |= NAK_BITMASK; - __asm__ ("eieio"); -} - -/* mpc8xx_udc_handle_txerr - * - * Handle errors relevant to TX. Return a status code to allow calling - * indicative of what if anything happened - */ -static short mpc8xx_udc_handle_txerr () -{ - short ep = 0, ret = 0; - - for (; ep < TX_RING_SIZE; ep++) { - if (usbp->usber & (0x10 << ep)) { - - /* Timeout or underrun */ - if (tx_cbd[ep]->cbd_sc & 0x06) { - ret = 1; - mpc8xx_udc_flush_tx_fifo (ep); - - } else { - if (usbp->usep[ep] & STALL_BITMASK) { - if (!ep) { - usbp->usep[ep] &= ~STALL_BITMASK; - } - } /* else NAK */ - } - usbp->usber |= (0x10 << ep); - } - } - return ret; -} - -/* mpc8xx_udc_advance_rx - * - * Advance cbd rx - */ -static void mpc8xx_udc_advance_rx (volatile cbd_t ** rx_cbdp, int epid) -{ - if ((*rx_cbdp)->cbd_sc & RX_BD_W) { - *rx_cbdp = (volatile cbd_t *) (endpoints[epid]->rbase + CONFIG_SYS_IMMR); - - } else { - (*rx_cbdp)++; - } -} - - -/* mpc8xx_udc_flush_tx_fifo - * - * Flush a given TX fifo. Assumes one tx cbd per endpoint - */ -static void mpc8xx_udc_flush_tx_fifo (int epid) -{ - volatile cbd_t *tx_cbdp = 0; - - if (epid > MAX_ENDPOINTS) { - return; - } - - /* TX stop */ - immr->im_cpm.cp_cpcr = ((epid << 2) | 0x1D01); - __asm__ ("eieio"); - while (immr->im_cpm.cp_cpcr & 0x01); - - usbp->uscom = 0x40 | 0; - - /* reset ring */ - tx_cbdp = (cbd_t *) (endpoints[epid]->tbptr + CONFIG_SYS_IMMR); - tx_cbdp->cbd_sc = (TX_BD_I | TX_BD_W); - - - endpoints[epid]->tptr = endpoints[epid]->tbase; - endpoints[epid]->tstate = 0x00; - endpoints[epid]->tbcnt = 0x00; - - /* TX start */ - immr->im_cpm.cp_cpcr = ((epid << 2) | 0x2D01); - __asm__ ("eieio"); - while (immr->im_cpm.cp_cpcr & 0x01); - - return; -} - -/* mpc8xx_udc_flush_rx_fifo - * - * For the sake of completeness of the namespace, it seems like - * a good-design-decision (tm) to include mpc8xx_udc_flush_rx_fifo(); - * If RX_BD_E is true => a driver bug either here or in an upper layer - * not polling frequently enough. If RX_BD_E is true we have told the host - * we have accepted data but, the CPM found it had no-where to put that data - * which needless to say would be a bad thing. - */ -static void mpc8xx_udc_flush_rx_fifo () -{ - int i = 0; - - for (i = 0; i < RX_RING_SIZE; i++) { - if (!(rx_cbd[i]->cbd_sc & RX_BD_E)) { - ERR ("buf %p used rx data len = 0x%x sc=0x%x!\n", - rx_cbd[i], rx_cbd[i]->cbd_datlen, - rx_cbd[i]->cbd_sc); - - } - } - ERR ("BUG : Input over-run\n"); -} - -/* mpc8xx_udc_clear_rxbd - * - * Release control of RX CBD to CP. - */ -static void mpc8xx_udc_clear_rxbd (volatile cbd_t * rx_cbdp) -{ - rx_cbdp->cbd_datlen = 0x0000; - rx_cbdp->cbd_sc = ((rx_cbdp->cbd_sc & RX_BD_W) | (RX_BD_E | RX_BD_I)); - __asm__ ("eieio"); -} - -/* mpc8xx_udc_tx_irq - * - * Parse for tx timeout, control RX or USB reset/busy conditions - * Return -1 on timeout, -2 on fatal error, else return zero - */ -static int mpc8xx_udc_tx_irq (int ep) -{ - int i = 0; - - if (usbp->usber & (USB_TX_ERRMASK)) { - if (mpc8xx_udc_handle_txerr ()) { - /* Timeout, controlling function must retry send */ - return -1; - } - } - - if (usbp->usber & (USB_E_RESET | USB_E_BSY)) { - /* Fatal, abandon TX transaction */ - return -2; - } - - if (usbp->usber & USB_E_RXB) { - for (i = 0; i < RX_RING_SIZE; i++) { - if (!(rx_cbd[i]->cbd_sc & RX_BD_E)) { - if ((rx_cbd[i] == ep_ref[0].prx) || ep) { - return -2; - } - } - } - } - - return 0; -} - -/* mpc8xx_udc_ep_tx - * - * Transmit in a re-entrant fashion outbound USB packets. - * Implement retry/timeout mechanism described in USB specification - * Toggle DATA0/DATA1 pids as necessary - * Introduces non-standard tx_retry. The USB standard has no scope for slave - * devices to give up TX, however tx_retry stops us getting stuck in an endless - * TX loop. - */ -static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi) -{ - struct urb *urb = epi->tx_urb; - volatile cbd_t *tx_cbdp = 0; - unsigned int ep = 0, pkt_len = 0, x = 0, tx_retry = 0; - int ret = 0; - - if (!epi || (epi->endpoint_address & 0x03) >= MAX_ENDPOINTS || !urb) { - return -1; - } - - ep = epi->endpoint_address & 0x03; - tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CONFIG_SYS_IMMR); - - if (tx_cbdp->cbd_sc & TX_BD_R || usbp->usber & USB_E_TXB) { - mpc8xx_udc_flush_tx_fifo (ep); - usbp->usber |= USB_E_TXB; - }; - - while (tx_retry++ < 100) { - ret = mpc8xx_udc_tx_irq (ep); - if (ret == -1) { - /* ignore timeout here */ - } else if (ret == -2) { - /* Abandon TX */ - mpc8xx_udc_flush_tx_fifo (ep); - return -1; - } - - tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CONFIG_SYS_IMMR); - while (tx_cbdp->cbd_sc & TX_BD_R) { - }; - tx_cbdp->cbd_sc = (tx_cbdp->cbd_sc & TX_BD_W); - - pkt_len = urb->actual_length - epi->sent; - - if (pkt_len > epi->tx_packetSize || pkt_len > EP_MAX_PKT) { - pkt_len = min(epi->tx_packetSize, EP_MAX_PKT); - } - - for (x = 0; x < pkt_len; x++) { - *((unsigned char *) (tx_cbdp->cbd_bufaddr + x)) = - urb->buffer[epi->sent + x]; - } - tx_cbdp->cbd_datlen = pkt_len; - tx_cbdp->cbd_sc |= (CBD_TX_BITMASK | ep_ref[ep].pid); - __asm__ ("eieio"); - -#ifdef __SIMULATE_ERROR__ - if (++err_poison_test == 2) { - err_poison_test = 0; - tx_cbdp->cbd_sc &= ~TX_BD_TC; - } -#endif - - usbp->uscom = (USCOM_STR | ep); - - while (!(usbp->usber & USB_E_TXB)) { - ret = mpc8xx_udc_tx_irq (ep); - if (ret == -1) { - /* TX timeout */ - break; - } else if (ret == -2) { - if (usbp->usber & USB_E_TXB) { - usbp->usber |= USB_E_TXB; - } - mpc8xx_udc_flush_tx_fifo (ep); - return -1; - } - }; - - if (usbp->usber & USB_E_TXB) { - usbp->usber |= USB_E_TXB; - } - - /* ACK must be present <= 18bit times from TX */ - if (ret == -1) { - continue; - } - - /* TX ACK : USB 2.0 8.7.2, Toggle PID, Advance TX */ - epi->sent += pkt_len; - epi->last = min(urb->actual_length - epi->sent, epi->tx_packetSize); - TOGGLE_TX_PID (ep_ref[ep].pid); - - if (epi->sent >= epi->tx_urb->actual_length) { - - epi->tx_urb->actual_length = 0; - epi->sent = 0; - - if (ep_ref[ep].sc & EP_SEND_ZLP) { - ep_ref[ep].sc &= ~EP_SEND_ZLP; - } else { - return 0; - } - } - } - - ERR ("TX fail, endpoint 0x%x tx bytes 0x%x/0x%x\n", ep, epi->sent, - epi->tx_urb->actual_length); - - return -1; -} - -/* mpc8xx_udc_dump_request - * - * Dump a control request to console - */ -static void mpc8xx_udc_dump_request (struct usb_device_request *request) -{ - DBG ("bmRequestType:%02x bRequest:%02x wValue:%04x " - "wIndex:%04x wLength:%04x ?\n", - request->bmRequestType, - request->bRequest, - request->wValue, request->wIndex, request->wLength); - - return; -} - -/* mpc8xx_udc_ep0_rx_setup - * - * Decode received ep0 SETUP packet. return non-zero on error - */ -static int mpc8xx_udc_ep0_rx_setup (volatile cbd_t * rx_cbdp) -{ - unsigned int x = 0; - struct urb *purb = ep_ref[0].urb; - struct usb_endpoint_instance *epi = - &udc_device->bus->endpoint_array[0]; - - for (; x < rx_cbdp->cbd_datlen; x++) { - *(((unsigned char *) &ep_ref[0].urb->device_request) + x) = - *((unsigned char *) (rx_cbdp->cbd_bufaddr + x)); - } - - mpc8xx_udc_clear_rxbd (rx_cbdp); - - if (ep0_recv_setup (purb)) { - mpc8xx_udc_dump_request (&purb->device_request); - return -1; - } - - if ((purb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) - == USB_REQ_HOST2DEVICE) { - - switch (purb->device_request.bRequest) { - case USB_REQ_SET_ADDRESS: - /* Send the Status OUT ZLP */ - ep_ref[0].pid = TX_BD_PID_DATA1; - purb->actual_length = 0; - mpc8xx_udc_init_tx (epi, purb); - mpc8xx_udc_ep_tx (epi); - - /* Move to the addressed state */ - usbp->usaddr = udc_device->address; - mpc8xx_udc_state_transition_up (udc_device->device_state, - STATE_ADDRESSED); - return 0; - - case USB_REQ_SET_CONFIGURATION: - if (!purb->device_request.wValue) { - /* Respond at default address */ - usbp->usaddr = 0x00; - mpc8xx_udc_state_transition_down (udc_device->device_state, - STATE_ADDRESSED); - } else { - /* TODO: Support multiple configurations */ - mpc8xx_udc_state_transition_up (udc_device->device_state, - STATE_CONFIGURED); - for (x = 1; x < MAX_ENDPOINTS; x++) { - if ((udc_device->bus->endpoint_array[x].endpoint_address & USB_ENDPOINT_DIR_MASK) - == USB_DIR_IN) { - ep_ref[x].pid = TX_BD_PID_DATA0; - } else { - ep_ref[x].pid = RX_BD_PID_DATA0; - } - /* Set configuration must unstall endpoints */ - usbp->usep[x] &= ~STALL_BITMASK; - } - } - break; - default: - /* CDC/Vendor specific */ - break; - } - - /* Send ZLP as ACK in Status OUT phase */ - ep_ref[0].pid = TX_BD_PID_DATA1; - purb->actual_length = 0; - mpc8xx_udc_init_tx (epi, purb); - mpc8xx_udc_ep_tx (epi); - - } else { - - if (purb->actual_length) { - ep_ref[0].pid = TX_BD_PID_DATA1; - mpc8xx_udc_init_tx (epi, purb); - - if (!(purb->actual_length % EP0_MAX_PACKET_SIZE)) { - ep_ref[0].sc |= EP_SEND_ZLP; - } - - if (purb->device_request.wValue == - USB_DESCRIPTOR_TYPE_DEVICE) { - if (le16_to_cpu (purb->device_request.wLength) - > purb->actual_length) { - /* Send EP0_MAX_PACKET_SIZE bytes - * unless correct size requested. - */ - if (purb->actual_length > epi->tx_packetSize) { - purb->actual_length = epi->tx_packetSize; - } - } - } - mpc8xx_udc_ep_tx (epi); - - } else { - /* Corrupt SETUP packet? */ - ERR ("Zero length data or SETUP with DATA-IN phase ?\n"); - return 1; - } - } - return 0; -} - -/* mpc8xx_udc_init_tx - * - * Setup some basic parameters for a TX transaction - */ -static void mpc8xx_udc_init_tx (struct usb_endpoint_instance *epi, - struct urb *tx_urb) -{ - epi->sent = 0; - epi->last = 0; - epi->tx_urb = tx_urb; -} - -/* mpc8xx_udc_ep0_rx - * - * Receive ep0/control USB data. Parse and possibly send a response. - */ -static void mpc8xx_udc_ep0_rx (volatile cbd_t * rx_cbdp) -{ - if (rx_cbdp->cbd_sc & RX_BD_PID_SETUP) { - - /* Unconditionally accept SETUP packets */ - if (mpc8xx_udc_ep0_rx_setup (rx_cbdp)) { - mpc8xx_udc_stall (0); - } - - } else { - - mpc8xx_udc_clear_rxbd (rx_cbdp); - - if ((rx_cbdp->cbd_datlen - 2)) { - /* SETUP with a DATA phase - * outside of SETUP packet. - * Reply with STALL. - */ - mpc8xx_udc_stall (0); - } - } -} - -/* mpc8xx_udc_epn_rx - * - * Receive some data from cbd into USB system urb data abstraction - * Upper layers should NAK if there is insufficient RX data space - */ -static int mpc8xx_udc_epn_rx (unsigned int epid, volatile cbd_t * rx_cbdp) -{ - struct usb_endpoint_instance *epi = 0; - struct urb *urb = 0; - unsigned int x = 0; - - if (epid >= MAX_ENDPOINTS || !rx_cbdp->cbd_datlen) { - return 0; - } - - /* USB 2.0 PDF section 8.6.4 - * Discard data with invalid PID it is a resend. - */ - if (ep_ref[epid].pid != (rx_cbdp->cbd_sc & 0xC0)) { - return 1; - } - TOGGLE_RX_PID (ep_ref[epid].pid); - - epi = &udc_device->bus->endpoint_array[epid]; - urb = epi->rcv_urb; - - for (; x < (rx_cbdp->cbd_datlen - 2); x++) { - *((unsigned char *) (urb->buffer + urb->actual_length + x)) = - *((unsigned char *) (rx_cbdp->cbd_bufaddr + x)); - } - - if (x) { - usbd_rcv_complete (epi, x, 0); - if (ep_ref[epid].urb->status == RECV_ERROR) { - DBG ("RX error unset NAK\n"); - udc_unset_nak (epid); - } - } - return x; -} - -/* mpc8xx_udc_clock_init - * - * Obtain a clock reference for Full Speed Signaling - */ -static void mpc8xx_udc_clock_init (volatile immap_t * immr, - volatile cpm8xx_t * cp) -{ - -#if defined(CONFIG_SYS_USB_EXTC_CLK) - - /* This has been tested with a 48MHz crystal on CLK6 */ - switch (CONFIG_SYS_USB_EXTC_CLK) { - case 1: - immr->im_ioport.iop_papar |= 0x0100; - immr->im_ioport.iop_padir &= ~0x0100; - cp->cp_sicr |= 0x24; - break; - case 2: - immr->im_ioport.iop_papar |= 0x0200; - immr->im_ioport.iop_padir &= ~0x0200; - cp->cp_sicr |= 0x2D; - break; - case 3: - immr->im_ioport.iop_papar |= 0x0400; - immr->im_ioport.iop_padir &= ~0x0400; - cp->cp_sicr |= 0x36; - break; - case 4: - immr->im_ioport.iop_papar |= 0x0800; - immr->im_ioport.iop_padir &= ~0x0800; - cp->cp_sicr |= 0x3F; - break; - default: - udc_state = STATE_ERROR; - break; - } - -#elif defined(CONFIG_SYS_USB_BRGCLK) - - /* This has been tested with brgclk == 50MHz */ - int divisor = 0; - - if (gd->cpu_clk < 48000000L) { - ERR ("brgclk is too slow for full-speed USB!\n"); - udc_state = STATE_ERROR; - return; - } - - /* Assume the brgclk is 'good enough', we want !(gd->cpu_clk%48MHz) - * but, can /probably/ live with close-ish alternative rates. - */ - divisor = (gd->cpu_clk / 48000000L) - 1; - cp->cp_sicr &= ~0x0000003F; - - switch (CONFIG_SYS_USB_BRGCLK) { - case 1: - cp->cp_brgc1 |= (divisor | CPM_BRG_EN); - cp->cp_sicr &= ~0x2F; - break; - case 2: - cp->cp_brgc2 |= (divisor | CPM_BRG_EN); - cp->cp_sicr |= 0x00000009; - break; - case 3: - cp->cp_brgc3 |= (divisor | CPM_BRG_EN); - cp->cp_sicr |= 0x00000012; - break; - case 4: - cp->cp_brgc4 = (divisor | CPM_BRG_EN); - cp->cp_sicr |= 0x0000001B; - break; - default: - udc_state = STATE_ERROR; - break; - } - -#else -#error "CONFIG_SYS_USB_EXTC_CLK or CONFIG_SYS_USB_BRGCLK must be defined" -#endif - -} - -/* mpc8xx_udc_cbd_attach - * - * attach a cbd to and endpoint - */ -static void mpc8xx_udc_cbd_attach (int ep, uchar tx_size, uchar rx_size) -{ - - if (!tx_cbd[ep] || !rx_cbd[ep] || ep >= MAX_ENDPOINTS) { - udc_state = STATE_ERROR; - return; - } - - if (tx_size > USB_MAX_PKT || rx_size > USB_MAX_PKT || - (!tx_size && !rx_size)) { - udc_state = STATE_ERROR; - return; - } - - /* Attach CBD to appropiate Parameter RAM Endpoint data structure */ - if (rx_size) { - endpoints[ep]->rbase = (u32) rx_cbd[rx_ct]; - endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct]; - rx_ct++; - - if (!ep) { - - endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct]; - rx_cbd[rx_ct]->cbd_sc |= RX_BD_W; - rx_ct++; - - } else { - rx_ct += 2; - endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct]; - rx_cbd[rx_ct]->cbd_sc |= RX_BD_W; - rx_ct++; - } - - /* Where we expect to RX data on this endpoint */ - ep_ref[ep].prx = rx_cbd[rx_ct - 1]; - } else { - - ep_ref[ep].prx = 0; - endpoints[ep]->rbase = 0; - endpoints[ep]->rbptr = 0; - } - - if (tx_size) { - endpoints[ep]->tbase = (u32) tx_cbd[tx_ct]; - endpoints[ep]->tbptr = (u32) tx_cbd[tx_ct]; - tx_ct++; - } else { - endpoints[ep]->tbase = 0; - endpoints[ep]->tbptr = 0; - } - - endpoints[ep]->tstate = 0; - endpoints[ep]->tbcnt = 0; - endpoints[ep]->mrblr = EP_MAX_PKT; - endpoints[ep]->rfcr = 0x18; - endpoints[ep]->tfcr = 0x18; - ep_ref[ep].sc |= EP_ATTACHED; - - DBG ("ep %d rbase 0x%08x rbptr 0x%08x tbase 0x%08x tbptr 0x%08x prx = %p\n", - ep, endpoints[ep]->rbase, endpoints[ep]->rbptr, - endpoints[ep]->tbase, endpoints[ep]->tbptr, - ep_ref[ep].prx); - - return; -} - -/* mpc8xx_udc_cbd_init - * - * Allocate space for a cbd and allocate TX/RX data space - */ -static void mpc8xx_udc_cbd_init (void) -{ - int i = 0; - - for (; i < TX_RING_SIZE; i++) { - tx_cbd[i] = (cbd_t *) - mpc8xx_udc_alloc (sizeof (cbd_t), sizeof (int)); - } - - for (i = 0; i < RX_RING_SIZE; i++) { - rx_cbd[i] = (cbd_t *) - mpc8xx_udc_alloc (sizeof (cbd_t), sizeof (int)); - } - - for (i = 0; i < TX_RING_SIZE; i++) { - tx_cbd[i]->cbd_bufaddr = - mpc8xx_udc_alloc (EP_MAX_PKT, sizeof (int)); - - tx_cbd[i]->cbd_sc = (TX_BD_I | TX_BD_W); - tx_cbd[i]->cbd_datlen = 0x0000; - } - - - for (i = 0; i < RX_RING_SIZE; i++) { - rx_cbd[i]->cbd_bufaddr = - mpc8xx_udc_alloc (EP_MAX_PKT, sizeof (int)); - rx_cbd[i]->cbd_sc = (RX_BD_I | RX_BD_E); - rx_cbd[i]->cbd_datlen = 0x0000; - - } - - return; -} - -/* mpc8xx_udc_endpoint_init - * - * Attach an endpoint to some dpram - */ -static void mpc8xx_udc_endpoint_init (void) -{ - int i = 0; - - for (; i < MAX_ENDPOINTS; i++) { - endpoints[i] = (usb_epb_t *) - mpc8xx_udc_alloc (sizeof (usb_epb_t), 32); - } -} - -/* mpc8xx_udc_alloc - * - * Grab the address of some dpram - */ -static u32 mpc8xx_udc_alloc (u32 data_size, u32 alignment) -{ - u32 retaddr = address_base; - - while (retaddr % alignment) { - retaddr++; - } - address_base += data_size; - - return retaddr; -} diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 58f5de5..ac5371f 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o obj-$(CONFIG_L5F31188) += l5f31188.o -obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o obj-$(CONFIG_PXA_LCD) += pxa_lcd.o obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o obj-$(CONFIG_S6E8AX0) += s6e8ax0.o diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c deleted file mode 100644 index b08576e..0000000 --- a/drivers/video/mpc8xx_lcd.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering -- wd@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************/ -/* ** HEADER FILES */ -/************************************************************************/ - -/* #define DEBUG */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <watchdog.h> -#include <stdarg.h> -#include <lcdvideo.h> -#include <linux/types.h> -#include <stdio_dev.h> -#if defined(CONFIG_POST) -#include <post.h> -#endif -#include <lcd.h> - -#ifdef CONFIG_LCD - -/************************************************************************/ -/* ** CONFIG STUFF -- should be moved to board config file */ -/************************************************************************/ -#ifndef CONFIG_LCD_INFO -#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */ -#endif - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_KYOCERA_KCS057QV1AJ -/* - * Kyocera KCS057QV1AJ-G23. Passive, color, single scan. - */ -#define LCD_BPP LCD_COLOR4 - -vidinfo_t panel_info = { - 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, - LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_KYOCERA_KCS057QV1AJ */ -/*----------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_HITACHI_SP19X001_Z1A -/* - * Hitachi SP19X001-. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, - LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_HITACHI_SP19X001_Z1A */ -/*----------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_NEC_NL6448AC33 -/* - * NEC NL6448AC33-18. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_NEC_NL6448AC33 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_NEC_NL6448BC20 -/* - * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_NEC_NL6448BC20 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_NEC_NL6448BC33_54 -/* - * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_NEC_NL6448BC33_54 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_LQ104V7DS01 -/* - * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, - 3, 0, 0, 1, 1, 25, 1, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_SHARP_LQ104V7DS01 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_16x9 -/* - * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am - * not sure what it is....... - */ -vidinfo_t panel_info = { - 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 15, 4, 0, 3 -}; -#endif /* CONFIG_SHARP_16x9 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_LQ057Q3DC02 -/* - * Sharp LQ057Q3DC02 display. Active, color, single scan. - */ -#undef LCD_DF -#define LCD_DF 12 - -vidinfo_t panel_info = { - 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 15, 4, 0, 3 - /* wbl, vpw, lcdac, wbf */ -}; -#define CONFIG_LCD_INFO_BELOW_LOGO -#endif /* CONFIG_SHARP_LQ057Q3DC02 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_LQ64D341 -/* - * Sharp LQ64D341 display, 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 128, 16, 0, 32 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_SHARP_LQ64D341 */ - -#ifdef CONFIG_SHARP_LQ065T9DR51U -/* - * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan. - */ -vidinfo_t panel_info = { - 400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 248, 4, 0, 35 - /* wbl, vpw, lcdac, wbf */ -}; -#define CONFIG_LCD_INFO_BELOW_LOGO -#endif /* CONFIG_SHARP_LQ065T9DR51U */ - -#ifdef CONFIG_SHARP_LQ084V1DG21 -/* - * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, - 3, 0, 0, 1, 1, 160, 3, 0, 48 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_SHARP_LQ084V1DG21 */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_HLD1045 -/* - * HLD1045 display, 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 160, 3, 0, 48 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_HLD1045 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_PRIMEVIEW_V16C6448AC -/* - * Prime View V16C6448AC - */ -vidinfo_t panel_info = { - 640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 35 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_PRIMEVIEW_V16C6448AC */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_OPTREX_BW -/* - * Optrex CBL50840-2 NF-FW 99 22 M5 - * or - * Hitachi LMG6912RPFC-00T - * or - * Hitachi SP14Q002 - * - * 320x240. Black & white. - */ -#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */ - /* 1 - 4 grey levels, 2 bpp */ - /* 2 - 16 grey levels, 4 bpp */ -vidinfo_t panel_info = { - 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, - OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4 -}; -#endif /* CONFIG_OPTREX_BW */ - -/************************************************************************/ -/* ----------------- chipset specific functions ----------------------- */ -/************************************************************************/ - -/* - * Calculate fb size for VIDEOLFB_ATAG. - */ -ulong calc_fbsize (void) -{ - ulong size; - int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; - - size = line_length * panel_info.vl_row; - - return size; -} - -void lcd_ctrl_init (void *lcdbase) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile lcd823_t *lcdp = &immr->im_lcd; - - uint lccrtmp; - uint lchcr_hpc_tmp; - - /* Initialize the LCD control register according to the LCD - * parameters defined. We do everything here but enable - * the controller. - */ - - lccrtmp = LCDBIT (LCCR_BNUM_BIT, - (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128)); - - lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) | - LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) | - LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) | - LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) | - LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) | - LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) | - LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) | - LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) | - LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) | - LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft); - -#if 0 - lccrtmp |= ((SIU_LEVEL5 / 2) << 12); - lccrtmp |= LCCR_EIEN; -#endif - - lcdp->lcd_lccr = lccrtmp; - lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */ - - /* Initialize LCD controller bus priorities. - */ - immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */ - - /* set SHFT/CLOCK division factor 4 - * This needs to be set based upon display type and processor - * speed. The TFT displays run about 20 to 30 MHz. - * I was running 64 MHz processor speed. - * The value for this divider must be chosen so the result is - * an integer of the processor speed (i.e., divide by 3 with - * 64 MHz would be bad). - */ - immr->im_clkrst.car_sccr &= ~0x1F; - immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */ - - /* Enable LCD on port D. - */ - immr->im_ioport.iop_pdpar |= 0x1FFF; - immr->im_ioport.iop_pddir |= 0x1FFF; - - /* Enable LCD_A/B/C on port B. - */ - immr->im_cpm.cp_pbpar |= 0x00005001; - immr->im_cpm.cp_pbdir |= 0x00005001; - - /* Load the physical address of the linear frame buffer - * into the LCD controller. - * BIG NOTE: This has to be modified to load A and B depending - * upon the split mode of the LCD. - */ - lcdp->lcd_lcfaa = (ulong)lcdbase; - lcdp->lcd_lcfba = (ulong)lcdbase; - - /* MORE HACKS...This must be updated according to 823 manual - * for different panels. - * Udi Finkelstein - done - see below: - * Note: You better not try unsupported combinations such as - * 4-bit wide passive dual scan LCD at 4/8 Bit color. - */ - lchcr_hpc_tmp = - (panel_info.vl_col * - (panel_info.vl_tft ? 8 : - (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */ - /* use << to mult by: single scan = 1, dual scan = 2 */ - panel_info.vl_splt) * - (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */ - - lcdp->lcd_lchcr = LCHCR_BO | - LCDBIT (LCHCR_AT_BIT, 4) | - LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) | - panel_info.vl_wbl; - - lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) | - LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) | - LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) | - panel_info.vl_wbf; - -} - -/*----------------------------------------------------------------------*/ - -#if LCD_BPP == LCD_COLOR8 -void -lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(immr->im_cpm); - unsigned short colreg, *cmap_ptr; - - cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; - - colreg = ((red & 0x0F) << 8) | - ((green & 0x0F) << 4) | - (blue & 0x0F) ; - - *cmap_ptr = colreg; - - debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n", - regno, &(cp->lcd_cmap[regno * 2]), - red, green, blue, - cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]); -} -#endif /* LCD_COLOR8 */ - -/*----------------------------------------------------------------------*/ - -ushort *configuration_get_cmap(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - cpm8xx_t *cp = &(immr->im_cpm); - return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]); -} - -#if defined(CONFIG_MPC823) -void fb_put_byte(uchar **fb, uchar **from) -{ - *(*fb)++ = (255 - *(*from)++); -} -#endif - -#ifdef CONFIG_LCD_LOGO -#include <bmp_logo.h> -void lcd_logo_set_cmap(void) -{ - int i; - ushort *cmap; - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - cpm8xx_t *cp = &(immr->im_cpm); - cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET * sizeof(ushort)]); - - for (i = 0; i < BMP_LOGO_COLORS; ++i) - *cmap++ = bmp_logo_palette[i]; -} -#endif - -void lcd_enable (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile lcd823_t *lcdp = &immr->im_lcd; - - /* Enable the LCD panel */ - immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */ - lcdp->lcd_lccr |= LCCR_PON; -} - -/************************************************************************/ - -#endif /* CONFIG_LCD */ diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 5a6ae00..4c25f6f 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -10,7 +10,6 @@ extra-$(CONFIG_SMC91111) += smc91111_eeprom extra-$(CONFIG_SMC911X) += smc911x_eeprom extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2 extra-$(CONFIG_MPC5xxx) += interrupt -extra-$(CONFIG_8xx) += test_burst timer extra-$(CONFIG_MPC8260) += mem_to_mem_idma2intr extra-$(CONFIG_PPC) += sched

@@ -29,7 +28,6 @@ COBJS := $(ELF:=.o) LIB = $(obj)/libstubs.o

LIBOBJS-$(CONFIG_PPC) += ppc_longjmp.o ppc_setjmp.o -LIBOBJS-$(CONFIG_8xx) += test_burst_lib.o LIBOBJS-y += stubs.o

.SECONDARY: $(call objectify,$(COBJS)) diff --git a/examples/standalone/test_burst.c b/examples/standalone/test_burst.c deleted file mode 100644 index f2fdbf1..0000000 --- a/examples/standalone/test_burst.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * The test exercises SDRAM accesses in burst mode - */ - -#include <common.h> -#include <exports.h> - -#include <commproc.h> -#include <asm/mmu.h> -#include <asm/processor.h> - -#include <serial.h> -#include <watchdog.h> - -#include "test_burst.h" - -/* 8 MB test region of physical RAM */ -#define TEST_PADDR 0x00800000 -/* The uncached virtual region */ -#define TEST_VADDR_NC 0x00800000 -/* The cached virtual region */ -#define TEST_VADDR_C 0x01000000 -/* When an error is detected, the address where the error has been found, - and also the current and the expected data will be written to - the following flash address -*/ -#define TEST_FLASH_ADDR 0x40100000 - -static void test_prepare (void); -static int test_burst_start (unsigned long size, unsigned long pattern); -static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached); -static int test_mmu_is_on(void); -static void test_desc(unsigned long size); -static void test_error(char * step, volatile void * addr, unsigned long val, unsigned long pattern); -static void signal_init(void); -static void signal_start(void); -static void signal_error(void); -static void test_usage(void); - -static unsigned long test_pattern [] = { - 0x00000000, - 0xffffffff, - 0x55555555, - 0xaaaaaaaa, -}; - - -int test_burst (int argc, char * const argv[]) -{ - unsigned long size = CACHE_LINE_SIZE; - unsigned int pass = 0; - int res = 0; - int i, j; - - if (argc == 3) { - char * d; - for (size = 0, d = argv[1]; *d >= '0' && *d <= '9'; d++) { - size *= 10; - size += *d - '0'; - } - if (size == 0 || *d) { - test_usage(); - return 1; - } - for (d = argv[2]; *d >= '0' && *d <= '9'; d++) { - pass *= 10; - pass += *d - '0'; - } - if (*d) { - test_usage(); - return 1; - } - } else if (argc > 3) { - test_usage(); - return 1; - } - - size += (CACHE_LINE_SIZE - 1); - size &= ~(CACHE_LINE_SIZE - 1); - - if (!test_mmu_is_on()) { - test_prepare(); - } - - test_desc(size); - - for (j = 0; !pass || j < pass; j++) { - for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]); - i++) { - res = test_burst_start(size, test_pattern[i]); - if (res != 0) { - goto Done; - } - } - - printf ("Iteration #%d passed\n", j + 1); - - if (tstc() && 0x03 == getc()) - break; - } -Done: - return res; -} - -static void test_prepare (void) -{ - printf ("\n"); - - caches_init(); - disable_interrupts(); - mmu_init(); - - printf ("Interrupts are disabled\n"); - printf ("I-Cache is ON\n"); - printf ("D-Cache is ON\n"); - printf ("MMU is ON\n"); - - printf ("\n"); - - test_map_8M (TEST_PADDR, TEST_VADDR_NC, 0); - test_map_8M (TEST_PADDR, TEST_VADDR_C, 1); - - test_map_8M (TEST_FLASH_ADDR & 0xFF800000, TEST_FLASH_ADDR & 0xFF800000, 0); - - /* Configure GPIO ports */ - signal_init(); -} - -static int test_burst_start (unsigned long size, unsigned long pattern) -{ - volatile unsigned long * vaddr_c = (unsigned long *)TEST_VADDR_C; - volatile unsigned long * vaddr_nc = (unsigned long *)TEST_VADDR_NC; - int i, n; - int res = 1; - - printf ("Test pattern %08lx ...", pattern); - - n = size / 4; - - for (i = 0; i < n; i ++) { - vaddr_c [i] = pattern; - } - signal_start(); - flush_dcache_range((unsigned long)vaddr_c, (unsigned long)(vaddr_c + n) - 1); - - for (i = 0; i < n; i ++) { - register unsigned long tmp = vaddr_nc [i]; - if (tmp != pattern) { - test_error("2a", vaddr_nc + i, tmp, pattern); - goto Done; - } - } - - for (i = 0; i < n; i ++) { - register unsigned long tmp = vaddr_c [i]; - if (tmp != pattern) { - test_error("2b", vaddr_c + i, tmp, pattern); - goto Done; - } - } - - for (i = 0; i < n; i ++) { - vaddr_nc [i] = pattern; - } - - for (i = 0; i < n; i ++) { - register unsigned long tmp = vaddr_nc [i]; - if (tmp != pattern) { - test_error("3a", vaddr_nc + i, tmp, pattern); - goto Done; - } - } - - signal_start(); - for (i = 0; i < n; i ++) { - register unsigned long tmp = vaddr_c [i]; - if (tmp != pattern) { - test_error("3b", vaddr_c + i, tmp, pattern); - goto Done; - } - } - - res = 0; -Done: - printf(" %s\n", res == 0 ? "OK" : ""); - - return res; -} - -static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached) -{ - mtspr (MD_EPN, (vaddr & 0xFFFFFC00) | MI_EVALID); - mtspr (MD_TWC, MI_PS8MEG | MI_SVALID); - mtspr (MD_RPN, (paddr & 0xFFFFF000) | MI_BOOTINIT | (cached ? 0 : 2)); - mtspr (MD_AP, MI_Kp); -} - -static int test_mmu_is_on(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - - return msr & MSR_DR; -} - -static void test_desc(unsigned long size) -{ - printf( - "The following tests will be conducted:\n" - "1) Map %ld-byte region of physical RAM at 0x%08x\n" - " into two virtual regions:\n" - " one cached at 0x%08x and\n" - " the the other uncached at 0x%08x.\n", - size, TEST_PADDR, TEST_VADDR_NC, TEST_VADDR_C); - - puts( - "2) Fill the cached region with a pattern, and flush the cache\n" - "2a) Check the uncached region to match the pattern\n" - "2b) Check the cached region to match the pattern\n" - "3) Fill the uncached region with a pattern\n" - "3a) Check the cached region to match the pattern\n" - "3b) Check the uncached region to match the pattern\n" - "2b) Change the patterns and go to step 2\n" - "\n" - ); -} - -static void test_error( - char * step, volatile void * addr, unsigned long val, unsigned long pattern) -{ - volatile unsigned long * p = (void *)TEST_FLASH_ADDR; - - signal_error(); - - p[0] = (unsigned long)addr; - p[1] = val; - p[2] = pattern; - - printf ("\nError at step %s, addr %08lx: read %08lx, pattern %08lx", - step, (unsigned long)addr, val, pattern); -} - -static void signal_init(void) -{ -#if defined(GPIO1_INIT) - GPIO1_INIT; -#endif -#if defined(GPIO2_INIT) - GPIO2_INIT; -#endif -} - -static void signal_start(void) -{ -#if defined(GPIO1_INIT) - if (GPIO1_DAT & GPIO1_BIT) { - GPIO1_DAT &= ~GPIO1_BIT; - } else { - GPIO1_DAT |= GPIO1_BIT; - } -#endif -} - -static void signal_error(void) -{ -#if defined(GPIO2_INIT) - if (GPIO2_DAT & GPIO2_BIT) { - GPIO2_DAT &= ~GPIO2_BIT; - } else { - GPIO2_DAT |= GPIO2_BIT; - } -#endif -} - -static void test_usage(void) -{ - printf("Usage: go 0x40004 [size] [count]\n"); -} diff --git a/examples/standalone/test_burst.h b/examples/standalone/test_burst.h deleted file mode 100644 index 87f5927..0000000 --- a/examples/standalone/test_burst.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEST_BURST_H -#define _TEST_BURST_H - -/* Cache line size */ -#define CACHE_LINE_SIZE 16 -/* Binary logarithm of the cache line size */ -#define LG_CACHE_LINE_SIZE 4 - -#ifndef __ASSEMBLY__ -extern void mmu_init(void); -extern void caches_init(void); -extern void flush_dcache_range(unsigned long start, unsigned long stop); -#endif - -#endif /* _TEST_BURST_H */ diff --git a/examples/standalone/test_burst_lib.S b/examples/standalone/test_burst_lib.S deleted file mode 100644 index fd3256e..0000000 --- a/examples/standalone/test_burst_lib.S +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> -#include "test_burst.h" - - .text -/* - * void mmu_init(void); - * - * This function turns the MMU on - * - * Three 8 MByte regions are mapped 1:1, uncached - * - SDRAM lower 8 MByte - * - SDRAM higher 8 MByte - * - IMMR - */ - .global mmu_init -mmu_init: - tlbia /* Invalidate all TLB entries */ - li r8, 0 - mtspr MI_CTR, r8 /* Set instruction control to zero */ - lis r8, MD_RESETVAL@h - mtspr MD_CTR, r8 /* Set data TLB control */ - - /* Now map the lower 8 Meg into the TLBs. For this quick hack, - * we can load the instruction and data TLB registers with the - * same values. - */ - li r8, MI_EVALID /* Create EPN for address 0 */ - mtspr MI_EPN, r8 - mtspr MD_EPN, r8 - li r8, MI_PS8MEG /* Set 8M byte page */ - ori r8, r8, MI_SVALID /* Make it valid */ - mtspr MI_TWC, r8 - mtspr MD_TWC, r8 - li r8, MI_BOOTINIT|0x2 /* Create RPN for address 0 */ - mtspr MI_RPN, r8 /* Store TLB entry */ - mtspr MD_RPN, r8 - lis r8, MI_Kp@h /* Set the protection mode */ - mtspr MI_AP, r8 - mtspr MD_AP, r8 - - /* Now map the higher 8 Meg into the TLBs. For this quick hack, - * we can load the instruction and data TLB registers with the - * same values. - */ - lwz r9,20(r2) /* gd->ram_size */ - addis r9,r9,-0x80 - - mr r8, r9 /* Higher 8 Meg in SDRAM */ - ori r8, r8, MI_EVALID /* Mark page valid */ - mtspr MI_EPN, r8 - mtspr MD_EPN, r8 - li r8, MI_PS8MEG /* Set 8M byte page */ - ori r8, r8, MI_SVALID /* Make it valid */ - mtspr MI_TWC, r8 - mtspr MD_TWC, r8 - mr r8, r9 - ori r8, r8, MI_BOOTINIT|0x2 - mtspr MI_RPN, r8 /* Store TLB entry */ - mtspr MD_RPN, r8 - lis r8, MI_Kp@h /* Set the protection mode */ - mtspr MI_AP, r8 - mtspr MD_AP, r8 - - /* Map another 8 MByte at the IMMR to get the processor - * internal registers (among other things). - */ - mfspr r9, 638 /* Get current IMMR */ - andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ - - mr r8, r9 /* Create vaddr for TLB */ - ori r8, r8, MD_EVALID /* Mark it valid */ - mtspr MD_EPN, r8 - li r8, MD_PS8MEG /* Set 8M byte page */ - ori r8, r8, MD_SVALID /* Make it valid */ - mtspr MD_TWC, r8 - mr r8, r9 /* Create paddr for TLB */ - ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ - mtspr MD_RPN, r8 - - /* We now have the lower and higher 8 Meg mapped into TLB entries, - * and the caches ready to work. - */ - mfmsr r0 - ori r0,r0,MSR_DR|MSR_IR - mtspr SRR1,r0 - mflr r0 - mtspr SRR0,r0 - SYNC - rfi /* enables MMU */ - -/* - * void caches_init(void); - */ - .globl caches_init -caches_init: - sync - - mfspr r3, IC_CST /* Clear error bits */ - mfspr r3, DC_CST - - lis r3, IDC_UNALL@h /* Unlock all */ - mtspr IC_CST, r3 - mtspr DC_CST, r3 - - lis r3, IDC_INVALL@h /* Invalidate all */ - mtspr IC_CST, r3 - mtspr DC_CST, r3 - - lis r3, IDC_ENABLE@h /* Enable all */ - mtspr IC_CST, r3 - mtspr DC_CST, r3 - - blr - -/* - * void flush_dcache_range(unsigned long start, unsigned long stop); - */ - .global flush_dcache_range -flush_dcache_range: - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE - beqlr - mtctr r4 - -1: dcbf 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbf's to get to ram */ - blr - -/* - * void disable_interrupts(void); - */ - .global disable_interrupts -disable_interrupts: - mfmsr r0 - rlwinm r0,r0,0,17,15 - mtmsr r0 - blr diff --git a/examples/standalone/timer.c b/examples/standalone/timer.c deleted file mode 100644 index dbd5c16..0000000 --- a/examples/standalone/timer.c +++ /dev/null @@ -1,333 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <commproc.h> -#include <mpc8xx_irq.h> -#include <exports.h> - -DECLARE_GLOBAL_DATA_PTR; - -#undef DEBUG - -#define TIMER_PERIOD 1000000 /* 1 second clock */ - -static void timer_handler (void *arg); - - -/* Access functions for the Machine State Register */ -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - -/* - * Definitions to access the CPM Timer registers - * See 8xx_immap.h for Internal Memory Map layout, - * and commproc.h for CPM Interrupt vectors (aka "IRQ"s) - */ - -typedef struct tid_8xx_cpmtimer_s { - int cpm_vec; /* CPM Interrupt Vector for this timer */ - ushort *tgcrp; /* Pointer to Timer Global Config Reg. */ - ushort *tmrp; /* Pointer to Timer Mode Register */ - ushort *trrp; /* Pointer to Timer Reference Register */ - ushort *tcrp; /* Pointer to Timer Capture Register */ - ushort *tcnp; /* Pointer to Timer Counter Register */ - ushort *terp; /* Pointer to Timer Event Register */ -} tid_8xx_cpmtimer_t; - -#ifndef CLOCKRATE -# define CLOCKRATE 64 -#endif - -#define CPMT_CLOCK_DIV 16 -#define CPMT_MAX_PRESCALER 256 -#define CPMT_MAX_REFERENCE 65535 /* max. unsigned short */ - -#define CPMT_MAX_TICKS (CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER) -#define CPMT_MAX_TICKS_WITH_DIV (CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER * CPMT_CLOCK_DIV) -#define CPMT_MAX_INTERVAL (CPMT_MAX_TICKS_WITH_DIV / CLOCKRATE) - -/* For now: always use max. prescaler value */ -#define CPMT_PRESCALER (CPMT_MAX_PRESCALER) - -/* CPM Timer Event Register Bits */ -#define CPMT_EVENT_CAP 0x0001 /* Capture Event */ -#define CPMT_EVENT_REF 0x0002 /* Reference Counter Event */ - -/* CPM Timer Global Config Register */ -#define CPMT_GCR_RST 0x0001 /* Reset Timer */ -#define CPMT_GCR_STP 0x0002 /* Stop Timer */ -#define CPMT_GCR_FRZ 0x0004 /* Freeze Timer */ -#define CPMT_GCR_GM_CAS 0x0008 /* Gate Mode / Cascade Timers */ -#define CPMT_GCR_MASK (CPMT_GCR_RST|CPMT_GCR_STP|CPMT_GCR_FRZ|CPMT_GCR_GM_CAS) - -/* CPM Timer Mode register */ -#define CPMT_MR_GE 0x0001 /* Gate Enable */ -#define CPMT_MR_ICLK_CASC 0x0000 /* Clock internally cascaded */ -#define CPMT_MR_ICLK_CLK 0x0002 /* Clock = system clock */ -#define CPMT_MR_ICLK_CLKDIV 0x0004 /* Clock = system clock / 16 */ -#define CPMT_MR_ICLK_TIN 0x0006 /* Clock = TINx signal */ -#define CPMT_MR_FRR 0x0008 /* Free Run / Restart */ -#define CPMT_MR_ORI 0x0010 /* Out. Reference Interrupt En. */ -#define CPMT_MR_OM 0x0020 /* Output Mode */ -#define CPMT_MR_CE_DIS 0x0000 /* Capture/Interrupt disabled */ -#define CPMT_MR_CE_RISE 0x0040 /* Capt./Interr. on rising TIN */ -#define CPMT_MR_CE_FALL 0x0080 /* Capt./Interr. on falling TIN */ -#define CPMT_MR_CE_ANY 0x00C0 /* Capt./Interr. on any TIN edge*/ - - -/* - * which CPM timer to use - index starts at 0 (= timer 1) - */ -#define TID_TIMER_ID 0 /* use CPM timer 1 */ - -void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval); - -static const char usage[] = "\n[q, b, e, ?] "; - -int timer (int argc, char * const argv[]) -{ - cpmtimer8xx_t *cpmtimerp; /* Pointer to the CPM Timer structure */ - tid_8xx_cpmtimer_t hw; - tid_8xx_cpmtimer_t *hwp = &hw; - int c; - int running; - - app_startup(argv); - - /* Pointer to CPM Timer structure */ - cpmtimerp = &((immap_t *) gd->bd->bi_immr_base)->im_cpmtimer; - - printf ("TIMERS=0x%x\n", (unsigned) cpmtimerp); - - /* Initialize pointers depending on which timer we use */ - switch (TID_TIMER_ID) { - case 0: - hwp->tmrp = &(cpmtimerp->cpmt_tmr1); - hwp->trrp = &(cpmtimerp->cpmt_trr1); - hwp->tcrp = &(cpmtimerp->cpmt_tcr1); - hwp->tcnp = &(cpmtimerp->cpmt_tcn1); - hwp->terp = &(cpmtimerp->cpmt_ter1); - hwp->cpm_vec = CPMVEC_TIMER1; - break; - case 1: - hwp->tmrp = &(cpmtimerp->cpmt_tmr2); - hwp->trrp = &(cpmtimerp->cpmt_trr2); - hwp->tcrp = &(cpmtimerp->cpmt_tcr2); - hwp->tcnp = &(cpmtimerp->cpmt_tcn2); - hwp->terp = &(cpmtimerp->cpmt_ter2); - hwp->cpm_vec = CPMVEC_TIMER2; - break; - case 2: - hwp->tmrp = &(cpmtimerp->cpmt_tmr3); - hwp->trrp = &(cpmtimerp->cpmt_trr3); - hwp->tcrp = &(cpmtimerp->cpmt_tcr3); - hwp->tcnp = &(cpmtimerp->cpmt_tcn3); - hwp->terp = &(cpmtimerp->cpmt_ter3); - hwp->cpm_vec = CPMVEC_TIMER3; - break; - case 3: - hwp->tmrp = &(cpmtimerp->cpmt_tmr4); - hwp->trrp = &(cpmtimerp->cpmt_trr4); - hwp->tcrp = &(cpmtimerp->cpmt_tcr4); - hwp->tcnp = &(cpmtimerp->cpmt_tcn4); - hwp->terp = &(cpmtimerp->cpmt_ter4); - hwp->cpm_vec = CPMVEC_TIMER4; - break; - } - - hwp->tgcrp = &cpmtimerp->cpmt_tgcr; - - printf ("Using timer %d\n" - "tgcr @ 0x%x, tmr @ 0x%x, trr @ 0x%x," - " tcr @ 0x%x, tcn @ 0x%x, ter @ 0x%x\n", - TID_TIMER_ID + 1, - (unsigned) hwp->tgcrp, - (unsigned) hwp->tmrp, - (unsigned) hwp->trrp, - (unsigned) hwp->tcrp, - (unsigned) hwp->tcnp, - (unsigned) hwp->terp - ); - - /* reset timer */ - *hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID); - - /* clear all events */ - *hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF); - - puts(usage); - running = 0; - while ((c = getc()) != 'q') { - if (c == 'b') { - - setPeriod (hwp, TIMER_PERIOD); /* Set period and start ticking */ - - /* Install interrupt handler (enable timer in CIMR) */ - install_hdlr (hwp->cpm_vec, timer_handler, hwp); - - printf ("Enabling timer\n"); - - /* enable timer */ - *hwp->tgcrp |= (CPMT_GCR_RST << TID_TIMER_ID); - running = 1; - -#ifdef DEBUG - printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x," - " tcr=0x%x, tcn=0x%x, ter=0x%x\n", - *hwp->tgcrp, *hwp->tmrp, *hwp->trrp, - *hwp->tcrp, *hwp->tcnp, *hwp->terp - ); -#endif - } else if (c == 'e') { - - printf ("Stopping timer\n"); - - *hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID); - running = 0; - -#ifdef DEBUG - printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x," - " tcr=0x%x, tcn=0x%x, ter=0x%x\n", - *hwp->tgcrp, *hwp->tmrp, *hwp->trrp, - *hwp->tcrp, *hwp->tcnp, *hwp->terp - ); -#endif - /* Uninstall interrupt handler */ - free_hdlr (hwp->cpm_vec); - - } else if (c == '?') { -#ifdef DEBUG - cpic8xx_t *cpm_icp = &((immap_t *) gd->bd->bi_immr_base)->im_cpic; - sysconf8xx_t *siup = &((immap_t *) gd->bd->bi_immr_base)->im_siu_conf; -#endif - - printf ("\ntgcr=0x%x, tmr=0x%x, trr=0x%x," - " tcr=0x%x, tcn=0x%x, ter=0x%x\n", - *hwp->tgcrp, *hwp->tmrp, *hwp->trrp, - *hwp->tcrp, *hwp->tcnp, *hwp->terp - ); -#ifdef DEBUG - printf ("SIUMCR=0x%08lx, SYPCR=0x%08lx," - " SIMASK=0x%08lx, SIPEND=0x%08lx\n", - siup->sc_siumcr, - siup->sc_sypcr, - siup->sc_simask, - siup->sc_sipend - ); - - printf ("CIMR=0x%08lx, CICR=0x%08lx, CIPR=0x%08lx\n", - cpm_icp->cpic_cimr, - cpm_icp->cpic_cicr, - cpm_icp->cpic_cipr - ); -#endif - } else { - printf ("\nEnter: q - quit, b - start timer, e - stop timer, ? - get status\n"); - } - puts(usage); - } - if (running) { - printf ("Stopping timer\n"); - *hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID); - free_hdlr (hwp->cpm_vec); - } - - return (0); -} - - -/* Set period in microseconds and start. - * Truncate to maximum period if more than this is requested - but warn about it. - */ - -void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval) -{ - unsigned short prescaler; - unsigned long ticks; - - printf ("Set interval %ld us\n", interval); - - /* Warn if requesting longer period than possible */ - if (interval > CPMT_MAX_INTERVAL) { - printf ("Truncate interval %ld to maximum (%d)\n", - interval, CPMT_MAX_INTERVAL); - interval = CPMT_MAX_INTERVAL; - } - /* - * Check if we want to use clock divider: - * Since the reference counter can be incremented only in integer steps, - * we try to keep it as big as possible to allow the resulting period to be - * as precise as possible. - */ - /* prescaler, enable interrupt, restart after ref count is reached */ - prescaler = (ushort) ((CPMT_PRESCALER - 1) << 8) | - CPMT_MR_ORI | - CPMT_MR_FRR; - - ticks = ((ulong) CLOCKRATE * interval); - - if (ticks > CPMT_MAX_TICKS) { - ticks /= CPMT_CLOCK_DIV; - prescaler |= CPMT_MR_ICLK_CLKDIV; /* use system clock divided by 16 */ - } else { - prescaler |= CPMT_MR_ICLK_CLK; /* use system clock without divider */ - } - -#ifdef DEBUG - printf ("clock/%d, prescale factor %d, reference %ld, ticks %ld\n", - (ticks > CPMT_MAX_TICKS) ? CPMT_CLOCK_DIV : 1, - CPMT_PRESCALER, - (ticks / CPMT_PRESCALER), - ticks - ); -#endif - - /* set prescaler register */ - *hwp->tmrp = prescaler; - - /* clear timer counter */ - *hwp->tcnp = 0; - - /* set reference register */ - *hwp->trrp = (unsigned short) (ticks / CPMT_PRESCALER); - -#ifdef DEBUG - printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x," - " tcr=0x%x, tcn=0x%x, ter=0x%x\n", - *hwp->tgcrp, *hwp->tmrp, *hwp->trrp, - *hwp->tcrp, *hwp->tcnp, *hwp->terp - ); -#endif -} - -/* - * Handler for CPMVEC_TIMER1 interrupt - */ -static -void timer_handler (void *arg) -{ - tid_8xx_cpmtimer_t *hwp = (tid_8xx_cpmtimer_t *)arg; - - /* printf ("** TER1=%04x ** ", *hwp->terp); */ - - /* just for demonstration */ - printf ("."); - - /* clear all possible events: Ref. and Cap. */ - *hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF); -} diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 9f3351d..4374c2e 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -41,7 +41,7 @@ typedef struct bd_info { unsigned long bi_dsp_freq; /* dsp core frequency */ unsigned long bi_ddr_freq; /* ddr frequency */ #endif -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \ +#if defined(CONFIG_5xx) || defined(CONFIG_MPC8260) \ || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif diff --git a/include/commproc.h b/include/commproc.h deleted file mode 100644 index 9d4cb10..0000000 --- a/include/commproc.h +++ /dev/null @@ -1,849 +0,0 @@ -/* - * MPC8xx Communication Processor Module. - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file contains structures and information for the communication - * processor channels. Some CPM control and status is available - * throught the MPC8xx internal memory map. See immap.h for details. - * This file only contains what I need for the moment, not the total - * CPM capabilities. I (or someone else) will add definitions as they - * are needed. -- Dan - * - */ -#ifndef __CPM_8XX__ -#define __CPM_8XX__ - -#include <asm/8xx_immap.h> - -/* CPM Command register. -*/ -#define CPM_CR_RST ((ushort)0x8000) -#define CPM_CR_OPCODE ((ushort)0x0f00) -#define CPM_CR_CHAN ((ushort)0x00f0) -#define CPM_CR_FLG ((ushort)0x0001) - -/* Some commands (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_SET_GADDR ((ushort)0x0008) - -/* Channel numbers. -*/ -#define CPM_CR_CH_SCC1 ((ushort)0x0000) -#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ -#define CPM_CR_CH_SCC2 ((ushort)0x0004) -#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */ -#define CPM_CR_CH_SCC3 ((ushort)0x0008) -#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ -#define CPM_CR_CH_SCC4 ((ushort)0x000c) -#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ - -#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) - -/* - * DPRAM defines and allocation functions - */ -#define CPM_SERIAL_BASE 0x0800 -#define CPM_I2C_BASE 0x0820 -#define CPM_SPI_BASE 0x0840 -#define CPM_FEC_BASE 0x0860 -#define CPM_SERIAL2_BASE 0x08E0 -#define CPM_SCC_BASE 0x0900 -#define CPM_POST_BASE 0x0980 -#define CPM_WLKBD_BASE 0x0a00 - -#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR -#define CPM_POST_WORD_ADDR 0x07FC -#else -#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR -#endif - -#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR -#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) -#else -#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR -#endif - -#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -extern cpm8xx_t *cpmp; /* Pointer to comm processor */ - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ - -/* Parameter RAM offsets. -*/ -#define PROFF_SCC1 ((uint)0x0000) -#define PROFF_IIC ((uint)0x0080) -#define PROFF_REVNUM ((uint)0x00b0) -#define PROFF_SCC2 ((uint)0x0100) -#define PROFF_SPI ((uint)0x0180) -#define PROFF_SCC3 ((uint)0x0200) -#define PROFF_SMC1 ((uint)0x0280) -#define PROFF_SCC4 ((uint)0x0300) -#define PROFF_SMC2 ((uint)0x0380) - -/* Define enough so I can at least use the serial port as a UART. - */ -typedef struct smc_uart { - ushort smc_rbase; /* Rx Buffer descriptor base address */ - ushort smc_tbase; /* Tx Buffer descriptor base address */ - u_char smc_rfcr; /* Rx function code */ - u_char smc_tfcr; /* Tx function code */ - ushort smc_mrblr; /* Max receive buffer length */ - uint smc_rstate; /* Internal */ - uint smc_idp; /* Internal */ - ushort smc_rbptr; /* Internal */ - ushort smc_ibc; /* Internal */ - uint smc_rxtmp; /* Internal */ - uint smc_tstate; /* Internal */ - uint smc_tdp; /* Internal */ - ushort smc_tbptr; /* Internal */ - ushort smc_tbc; /* Internal */ - uint smc_txtmp; /* Internal */ - ushort smc_maxidl; /* Maximum idle characters */ - ushort smc_tmpidl; /* Temporary idle counter */ - ushort smc_brklen; /* Last received break length */ - ushort smc_brkec; /* rcv'd break condition counter */ - ushort smc_brkcr; /* xmt break count register */ - ushort smc_rmask; /* Temporary bit mask */ - u_char res1[8]; - ushort smc_rpbase; /* Relocation pointer */ -} smc_uart_t; - -/* Function code bits. -*/ -#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ - -/* SMC uart mode register. -*/ -#define SMCMR_REN ((ushort)0x0001) -#define SMCMR_TEN ((ushort)0x0002) -#define SMCMR_DM ((ushort)0x000c) -#define SMCMR_SM_GCI ((ushort)0x0000) -#define SMCMR_SM_UART ((ushort)0x0020) -#define SMCMR_SM_TRANS ((ushort)0x0030) -#define SMCMR_SM_MASK ((ushort)0x0030) -#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ -#define SMCMR_REVD SMCMR_PM_EVEN -#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ -#define SMCMR_BS SMCMR_PEN -#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ -#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ -#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) - -/* SMC2 as Centronics parallel printer. It is half duplex, in that - * it can only receive or transmit. The parameter ram values for - * each direction are either unique or properly overlap, so we can - * include them in one structure. - */ -typedef struct smc_centronics { - ushort scent_rbase; - ushort scent_tbase; - u_char scent_cfcr; - u_char scent_smask; - ushort scent_mrblr; - uint scent_rstate; - uint scent_r_ptr; - ushort scent_rbptr; - ushort scent_r_cnt; - uint scent_rtemp; - uint scent_tstate; - uint scent_t_ptr; - ushort scent_tbptr; - ushort scent_t_cnt; - uint scent_ttemp; - ushort scent_max_sl; - ushort scent_sl_cnt; - ushort scent_character1; - ushort scent_character2; - ushort scent_character3; - ushort scent_character4; - ushort scent_character5; - ushort scent_character6; - ushort scent_character7; - ushort scent_character8; - ushort scent_rccm; - ushort scent_rccr; -} smc_cent_t; - -/* Centronics Status Mask Register. -*/ -#define SMC_CENT_F ((u_char)0x08) -#define SMC_CENT_PE ((u_char)0x04) -#define SMC_CENT_S ((u_char)0x02) - -/* SMC Event and Mask register. -*/ -#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ -#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ -#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ -#define SMCM_BSY ((unsigned char)0x04) -#define SMCM_TX ((unsigned char)0x02) -#define SMCM_RX ((unsigned char)0x01) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SI Clock Route Register -*/ -#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) -#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) -#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) -#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) -#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) -#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) -#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) -#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - -/* Function code bits. -*/ -#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ - -/* CPM Ethernet through SCCx. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - -/********************************************************************** - * - * Board specific configuration settings. - * - * Please note that we use the presence of a #define SCC_ENET and/or - * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. - **********************************************************************/ - -/*** BSEIP **********************************************************/ - -#ifdef CONFIG_BSEIP -/* This ENET stuff is for the MPC823 with ethernet on SCC2. - * This is unique to the BSE ip-Engine board. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -/* BSE uses port B and C bits for PHY control also. -*/ -#define PB_BSE_POWERUP ((uint)0x00000004) -#define PB_BSE_FDXDIS ((uint)0x00008000) -#define PC_BSE_LOOPBACK ((ushort)0x0800) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002c00) -#endif /* CONFIG_BSEIP */ - -/*** KM8XX *********************************************************/ - -/* The KM8XX Service Module uses SCC3 for Ethernet */ - -#ifdef CONFIG_KM8XX -#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ -#define CPM_CR_ENET CPM_CR_CH_SCC3 -#define SCC_ENET 2 -#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */ -#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */ -#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */ -#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */ - -#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ - -#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */ -#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */ - -/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to - * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. - */ -#define SICR_ENET_MASK ((uint)0x00FF0000) -#define SICR_ENET_CLKRT ((uint)0x00250000) -#endif /* CONFIG_KM8XX */ - -/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/ - -#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ - defined(CONFIG_TQM823L) || \ - defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ - defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002600) - -# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ -#define FEC_ENET -# endif /* CONFIG_FEC_ENET */ - -#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ - -/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ - -#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ - defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ - defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) - -# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */ - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ -#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ -#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ -#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x00000026) - -# endif /* CONFIG_SCC1_ENET */ - -# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ - -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -# endif /* CONFIG_FEC_ENET */ -#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ - -/*********************************************************************/ - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PSMR) as used by Ethernet. -*/ -#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. -*/ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. -*/ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - uint scc_res1; /* Reserved */ - uint scc_res2; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PSMR when used as a UART. -*/ -#define SCU_PSMR_FLC ((ushort)0x8000) -#define SCU_PSMR_SL ((ushort)0x4000) -#define SCU_PSMR_CL ((ushort)0x3000) -#define SCU_PSMR_UM ((ushort)0x0c00) -#define SCU_PSMR_FRZ ((ushort)0x0200) -#define SCU_PSMR_RZS ((ushort)0x0100) -#define SCU_PSMR_SYN ((ushort)0x0080) -#define SCU_PSMR_DRT ((ushort)0x0040) -#define SCU_PSMR_PEN ((ushort)0x0010) -#define SCU_PSMR_RPM ((ushort)0x000c) -#define SCU_PSMR_REVP ((ushort)0x0008) -#define SCU_PSMR_TPM ((ushort)0x0003) -#define SCU_PSMR_TEVP ((ushort)0x0003) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - -/* IIC parameter RAM. -*/ -typedef struct iic { - ushort iic_rbase; /* Rx Buffer descriptor base address */ - ushort iic_tbase; /* Tx Buffer descriptor base address */ - u_char iic_rfcr; /* Rx function code */ - u_char iic_tfcr; /* Tx function code */ - ushort iic_mrblr; /* Max receive buffer length */ - uint iic_rstate; /* Internal */ - uint iic_rdp; /* Internal */ - ushort iic_rbptr; /* Internal */ - ushort iic_rbc; /* Internal */ - uint iic_rxtmp; /* Internal */ - uint iic_tstate; /* Internal */ - uint iic_tdp; /* Internal */ - ushort iic_tbptr; /* Internal */ - ushort iic_tbc; /* Internal */ - uint iic_txtmp; /* Internal */ - uint iic_res; /* reserved */ - ushort iic_rpbase; /* Relocation pointer */ - ushort iic_res2; /* reserved */ -} iic_t; - -/* SPI parameter RAM. -*/ -typedef struct spi { - ushort spi_rbase; /* Rx Buffer descriptor base address */ - ushort spi_tbase; /* Tx Buffer descriptor base address */ - u_char spi_rfcr; /* Rx function code */ - u_char spi_tfcr; /* Tx function code */ - ushort spi_mrblr; /* Max receive buffer length */ - uint spi_rstate; /* Internal */ - uint spi_rdp; /* Internal */ - ushort spi_rbptr; /* Internal */ - ushort spi_rbc; /* Internal */ - uint spi_rxtmp; /* Internal */ - uint spi_tstate; /* Internal */ - uint spi_tdp; /* Internal */ - ushort spi_tbptr; /* Internal */ - ushort spi_tbc; /* Internal */ - uint spi_txtmp; /* Internal */ - uint spi_res; - ushort spi_rpbase; /* Relocation pointer */ - ushort spi_res2; -} spi_t; - -/* SPI Mode register. -*/ -#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ -#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ -#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ -#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ -#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ -#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ -#define SPMODE_EN ((ushort)0x0100) /* Enable */ -#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ -#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ - -#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) -#define SPMODE_PM(x) ((x) &0xF) - -/* HDLC parameter RAM. -*/ - -typedef struct hdlc_pram_s { - /* - * SCC parameter RAM - */ - ushort rbase; /* Rx Buffer descriptor base address */ - ushort tbase; /* Tx Buffer descriptor base address */ - uchar rfcr; /* Rx function code */ - uchar tfcr; /* Tx function code */ - ushort mrblr; /* Rx buffer length */ - ulong rstate; /* Rx internal state */ - ulong rptr; /* Rx internal data pointer */ - ushort rbptr; /* rb BD Pointer */ - ushort rcount; /* Rx internal byte count */ - ulong rtemp; /* Rx temp */ - ulong tstate; /* Tx internal state */ - ulong tptr; /* Tx internal data pointer */ - ushort tbptr; /* Tx BD pointer */ - ushort tcount; /* Tx byte count */ - ulong ttemp; /* Tx temp */ - ulong rcrc; /* temp receive CRC */ - ulong tcrc; /* temp transmit CRC */ - /* - * HDLC specific parameter RAM - */ - uchar res[4]; /* reserved */ - ulong c_mask; /* CRC constant */ - ulong c_pres; /* CRC preset */ - ushort disfc; /* discarded frame counter */ - ushort crcec; /* CRC error counter */ - ushort abtsc; /* abort sequence counter */ - ushort nmarc; /* nonmatching address rx cnt */ - ushort retrc; /* frame retransmission cnt */ - ushort mflr; /* maximum frame length reg */ - ushort max_cnt; /* maximum length counter */ - ushort rfthr; /* received frames threshold */ - ushort rfcnt; /* received frames count */ - ushort hmask; /* user defined frm addr mask */ - ushort haddr1; /* user defined frm address 1 */ - ushort haddr2; /* user defined frm address 2 */ - ushort haddr3; /* user defined frm address 3 */ - ushort haddr4; /* user defined frm address 4 */ - ushort tmp; /* temp */ - ushort tmp_mb; /* temp */ -} hdlc_pram_t; - -/* CPM interrupts. There are nearly 32 interrupts generated by CPM - * channels or devices. All of these are presented to the PPC core - * as a single interrupt. The CPM interrupt handler dispatches its - * own handlers, in a similar fashion to the PPC core handler. We - * use the table as defined in the manuals (i.e. no special high - * priority and SCC1 == SCCa, etc...). - */ -#define CPMVEC_NR 32 -#define CPMVEC_OFFSET 0x00010000 -#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET) -#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET) -#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET) -#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET) -#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET) -#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET) -#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET) -#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET) -#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET) -#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET) -#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET) -#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET) -#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET) -#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET) -#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET) -#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET) -#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET) -#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET) - -extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id); - -/* CPM interrupt configuration vector. -*/ -#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ -#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ -#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ -#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ -#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ -#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ -#define CICR_IEN ((uint)0x00000080) /* Int. enable */ -#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ -#endif /* __CPM_8XX__ */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index ab4b060..c66b26f 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -139,7 +139,6 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */

diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index b13809f..3a1d4d9 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -306,7 +306,6 @@ #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */

-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET /* reset for ide supported... */ #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 393a02d..1f5b9f0 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -246,7 +246,6 @@ #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */

-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET /* reset for ide supported... */ #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 78ce91d..b8f23d7 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -150,7 +150,6 @@ /* * IDE/ATA stuff */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */

diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index e1f0445..2ba6b08 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -584,9 +584,6 @@ *----------------------------------------------------------------------- */

-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for ide not supported */

#define CONFIG_IDE_RESET /* reset for ide supported */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h deleted file mode 100644 index 74636b9..0000000 --- a/include/configs/TQM823L.h +++ /dev/null @@ -1,435 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_MPC8XX_LCD -#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ -#define CONFIG_LCD_INFO 1 /* ... and some board info */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM823L\0" \ - "bootfile=TQM823L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM823L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h deleted file mode 100644 index 6b345c4..0000000 --- a/include/configs/TQM823M.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_MPC8XX_LCD -/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM823M\0" \ - "bootfile=TQM823M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM823M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h deleted file mode 100644 index b4ed561..0000000 --- a/include/configs/TQM850L.h +++ /dev/null @@ -1,428 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM850L\0" \ - "bootfile=TQM850L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM850L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h deleted file mode 100644 index 1dc1329..0000000 --- a/include/configs/TQM850M.h +++ /dev/null @@ -1,429 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM850M\0" \ - "bootfile=TQM850M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM850M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h deleted file mode 100644 index b4c3a79..0000000 --- a/include/configs/TQM855L.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM855L\0" \ - "bootfile=TQM855L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM855L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h deleted file mode 100644 index 14b76a6..0000000 --- a/include/configs/TQM855M.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM855M\0" \ - "bootfile=TQM855M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM855M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#if 0 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h deleted file mode 100644 index f55fe56..0000000 --- a/include/configs/TQM860L.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM860L\0" \ - "bootfile=TQM860L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM860L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h deleted file mode 100644 index 52c4d68..0000000 --- a/include/configs/TQM860M.h +++ /dev/null @@ -1,438 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM860M\0" \ - "bootfile=TQM860M/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM860M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h deleted file mode 100644 index 06981c9..0000000 --- a/include/configs/TQM862L.h +++ /dev/null @@ -1,438 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM862L\0" \ - "bootfile=TQM862L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM862L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h deleted file mode 100644 index 3f87d8a..0000000 --- a/include/configs/TQM862M.h +++ /dev/null @@ -1,439 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM862M\0" \ - "bootfile=TQM862M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM862M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h deleted file mode 100644 index 975f4b7..0000000 --- a/include/configs/TQM866M.h +++ /dev/null @@ -1,457 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC866 1 /* This is a MPC866 CPU */ -#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */ - /* (function measure_gclk() */ - /* will be called) */ -#ifdef CONFIG_SYS_MEASURE_CPUCLK -#define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM866M\0" \ - "bootfile=TQM866M/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM866M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE - -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_15_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) - * - * CPUclock(MHz) * 31.2 - * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 - * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 - * - * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us - * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us - * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us - * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us - * - * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will - * be met also in the default configuration, i.e. if environment variable - * 'cpuclk' is not set. - */ -#define CONFIG_SYS_MAMR_PTA 97 - -/* - * Memory Periodic Timer Prescaler Register (MPTPR) values. - */ -/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 -/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h deleted file mode 100644 index 184cb62..0000000 --- a/include/configs/TQM885D.h +++ /dev/null @@ -1,451 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2006 - * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ -#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM885D/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 40000000 +${filesize};" \ - "erase 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "protect on 40000000 +${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -# define CONFIG_RTC_DS1337 1 -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ -#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive - memory test.*/ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_6_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) - * - * CPUclock(MHz) * 31.2 - * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 - * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 - * - * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us - * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us - * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us - * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us - * - * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will - * be met also in the default configuration, i.e. if environment variable - * 'cpuclk' is not set. - */ -#define CONFIG_SYS_MAMR_PTA 128 - -/* - * Memory Periodic Timer Prescaler Register (MPTPR) values. - */ -/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 -/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Network configuration - */ -#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ -#define CONFIG_FEC_ENET /* enable ethernet on FEC */ -#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ -#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ - -#if defined(CONFIG_CMD_MII) -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII_INIT 1 -#endif - -#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before - switching to another netwok (if the - tried network is unreachable) */ - -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index 6a26269..5ab063e 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -277,10 +277,6 @@ * IDE/ATA stuff Supports IDE harddisk *----------------------------------------------------------------------- */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for ide not supported */

#define CONFIG_IDE_PREINIT diff --git a/include/configs/aria.h b/include/configs/aria.h index 0a7ef99..3612e03 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -532,8 +532,6 @@ *----------------------------------------------------------------------- */

-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for IDE not supported */

#define CONFIG_IDE_RESET /* reset for IDE supported */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index d651eff..2816522 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -285,10 +285,6 @@ * IDE/ATA stuff Supports IDE harddisk *----------------------------------------------------------------------- */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for ide not supported */

#define CONFIG_IDE_PREINIT diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h index 68874dc..736bebb 100644 --- a/include/configs/manroland/mpc5200-common.h +++ b/include/configs/manroland/mpc5200-common.h @@ -140,9 +140,6 @@ *----------------------------------------------------------------------- */

-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for ide not supported */

#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index e11a0e6..a6aaf0e 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -538,9 +538,6 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for IDE not supported */

#define CONFIG_IDE_RESET /* reset for IDE supported */ diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h index 6da17be..500277f 100644 --- a/include/configs/pcm030.h +++ b/include/configs/pcm030.h @@ -346,8 +346,6 @@ IPB Bus clocking configuration. IDE/ATA stuff Supports IDE harddisk ----------------------------------------------------------------------------*/

-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for ide not supported */ #define CONFIG_SYS_ATA_CS_ON_TIMER01 #define CONFIG_IDE_RESET 1 /* reset for ide supported */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 2bd6cc1..c103215 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -232,8 +232,6 @@ /* * IDE/ATA (supports IDE harddisk) */ -#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for ide not supported */

#define CONFIG_IDE_RESET /* reset for ide supported */ diff --git a/include/i2c.h b/include/i2c.h index 7726028..fe3dca0 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -662,9 +662,6 @@ extern struct i2c_bus_hose i2c_bus[]; #ifndef I2C_SOFT_DECLARATIONS # if defined(CONFIG_MPC8260) # define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); -# elif defined(CONFIG_8xx) -# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - # elif (defined(CONFIG_AT91RM9200) || \ defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ defined(CONFIG_AT91SAM9263)) @@ -674,15 +671,6 @@ extern struct i2c_bus_hose i2c_bus[]; # endif #endif

-#ifdef CONFIG_8xx -/* Set default value for the I2C bus speed on 8xx. In the - * future, we'll define these in all 8xx board config files. - */ -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 50000 -#endif -#endif - /* * Many boards/controllers/drivers don't support an I2C slave interface so * provide a default slave address for them for use in common code. A real @@ -814,11 +802,6 @@ static inline u8 i2c_reg_read(u8 addr, u8 reg) { u8 buf;

-#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - #ifdef DEBUG printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); #endif @@ -830,11 +813,6 @@ static inline u8 i2c_reg_read(u8 addr, u8 reg)

static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) { -#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - #ifdef DEBUG printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n", __func__, addr, reg, val); diff --git a/include/lcd.h b/include/lcd.h index f76fca7..797d0b0 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -40,9 +40,7 @@ void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue); */ void lcd_set_flush_dcache(int flush);

-#if defined CONFIG_MPC823 -#include <mpc823_lcd.h> -#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ +#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ defined CONFIG_CPU_MONAHANS #include <pxa_lcd.h> #elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) diff --git a/include/mpc823_lcd.h b/include/mpc823_lcd.h deleted file mode 100644 index cc72cde..0000000 --- a/include/mpc823_lcd.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * mpc823_lcd.h - MPC823 LCD Controller structures - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MPC823_LCD_H_ -#define _MPC823_LCD_H_ - -/* - * LCD controller stucture for MPC823 CPU - */ -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ - ushort vl_width; /* Width of display area in millimeters */ - ushort vl_height; /* Height of display area in millimeters */ - - /* LCD configuration register */ - u_char vl_clkp; /* Clock polarity */ - u_char vl_oep; /* Output Enable polarity */ - u_char vl_hsp; /* Horizontal Sync polarity */ - u_char vl_vsp; /* Vertical Sync polarity */ - u_char vl_dp; /* Data polarity */ - u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ - u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ - u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ - u_char vl_clor; /* Color, 0 = mono, 1 = color */ - u_char vl_tft; /* 0 = passive, 1 = TFT */ - - /* Horizontal control register. Timing from data sheet */ - ushort vl_wbl; /* Wait between lines */ - - /* Vertical control register */ - u_char vl_vpw; /* Vertical sync pulse width */ - u_char vl_lcdac; /* LCD AC timing */ - u_char vl_wbf; /* Wait between frames */ -} vidinfo_t; - -#endif diff --git a/include/net.h b/include/net.h index ed5259a..2eaa882 100644 --- a/include/net.h +++ b/include/net.h @@ -12,10 +12,6 @@ #ifndef __NET_H__ #define __NET_H__

-#if defined(CONFIG_8xx) -#include <commproc.h> -#endif /* CONFIG_8xx */ - #include <asm/cache.h> #include <asm/byteorder.h> /* for nton* / ntoh* stuff */

diff --git a/include/pcmcia.h b/include/pcmcia.h index aaaf651..94b54c2 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -15,18 +15,10 @@ * Allow configuration to select PCMCIA slot, * or try to generate a useful default */ -#if defined(CONFIG_CMD_PCMCIA) || \ - (defined(CONFIG_IDE) && \ - (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) +#if defined(CONFIG_CMD_PCMCIA)

#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) - -#if defined(CONFIG_TQM8xxL) -# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ -#else # error "PCMCIA Slot not configured" -#endif - #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */

/* Make sure exactly one slot is defined - we support only one for now */ @@ -57,17 +49,6 @@ #endif

/* - * The TQM850L hardware has two pins swapped! Grrrrgh! - */ -#ifdef CONFIG_TQM850L -#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE -#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET -#else -#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET -#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE -#endif - -/* * This structure is used to address each window in the PCMCIA controller. * * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly @@ -263,13 +244,4 @@ typedef struct {

#endif

-#ifdef CONFIG_8xx -extern u_int *pcmcia_pgcrx[]; -#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) -#endif - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -extern int check_ide_device(int slot); -#endif - #endif /* _PCMCIA_H */ diff --git a/include/post.h b/include/post.h index 5ebd535..d5b4062 100644 --- a/include/post.h +++ b/include/post.h @@ -29,10 +29,6 @@ #define _POST_WORD_ADDR \ (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

-#elif defined(CONFIG_8xx) -#define _POST_WORD_ADDR \ - (((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR) - #elif defined(CONFIG_MPC8260) #include <asm/cpm_8260.h> #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) @@ -164,7 +160,6 @@ extern int memory_post_test(int flags); #define CONFIG_SYS_POST_CACHE 0x00000020 #define CONFIG_SYS_POST_UART 0x00000040 #define CONFIG_SYS_POST_ETHER 0x00000080 -#define CONFIG_SYS_POST_SPI 0x00000100 #define CONFIG_SYS_POST_USB 0x00000200 #define CONFIG_SYS_POST_SPR 0x00000400 #define CONFIG_SYS_POST_SYSMON 0x00000800 diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 379c493..8288433 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -82,21 +82,6 @@ #define r31 31

-#if defined(CONFIG_8xx) - -/* Some special registers */ - -#define ICR 148 /* Interrupt Cause Register (37-44) */ -#define DER 149 -#define COUNTA 150 /* Breakpoint Counter (37-44) */ -#define COUNTB 151 /* Breakpoint Counter (37-44) */ -#define LCTRL1 156 /* Load/Store Support (37-40) */ -#define LCTRL2 157 /* Load/Store Support (37-41) */ -#define ICTRL 158 - -#endif /* CONFIG_8xx */ - - #if defined(CONFIG_5xx) /* Some special purpose registers */ #define DER 149 /* Debug Enable Register */ @@ -108,36 +93,7 @@ #define EID 81 #endif /* CONFIG_5xx */

-#if defined(CONFIG_8xx) - -/* Registers in the processor's internal memory map that we use. -*/ -#define SYPCR 0x00000004 -#define BR0 0x00000100 -#define OR0 0x00000104 -#define BR1 0x00000108 -#define OR1 0x0000010c -#define BR2 0x00000110 -#define OR2 0x00000114 -#define BR3 0x00000118 -#define OR3 0x0000011c -#define BR4 0x00000120 -#define OR4 0x00000124 - -#define MAR 0x00000164 -#define MCR 0x00000168 -#define MAMR 0x00000170 -#define MBMR 0x00000174 -#define MSTAT 0x00000178 -#define MPTPR 0x0000017a -#define MDR 0x0000017c - -#define TBSCR 0x00000200 -#define TBREFF0 0x00000204 - -#define PLPRCR 0x00000284 - -#elif defined(CONFIG_MPC8260) +#if defined(CONFIG_MPC8260)

#define HID2 1011

diff --git a/include/status_led.h b/include/status_led.h index f838f36..e377346 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -40,17 +40,8 @@ void status_led_init(void); void status_led_tick (unsigned long timestamp); void status_led_set (int led, int state);

-/***** TQM8xxL ********************************************************/ -#if defined(CONFIG_TQM8xxL) -# define STATUS_LED_PAR im_cpm.cp_pbpar -# define STATUS_LED_DIR im_cpm.cp_pbdir -# define STATUS_LED_ODR im_cpm.cp_pbodr -# define STATUS_LED_DAT im_cpm.cp_pbdat - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - /***** MVS v1 **********************************************************/ -#elif (defined(CONFIG_MVS) && CONFIG_MVS < 2) +#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) # define STATUS_LED_PAR im_ioport.iop_pdpar # define STATUS_LED_DIR im_ioport.iop_pddir # undef STATUS_LED_ODR diff --git a/include/usb/mpc8xx_udc.h b/include/usb/mpc8xx_udc.h deleted file mode 100644 index 9906c75..0000000 --- a/include/usb/mpc8xx_udc.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) 2006 Bryan O'Donoghue, CodeHermit - * bodonoghue@codehermit.ie - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <commproc.h> - -/* Mode Register */ -#define USMOD_EN 0x01 -#define USMOD_HOST 0x02 -#define USMOD_TEST 0x04 -#define USMOD_SFTE 0x08 -#define USMOD_RESUME 0x40 -#define USMOD_LSS 0x80 - -/* Endpoint Registers */ -#define USEP_RHS_NORM 0x00 -#define USEP_RHS_IGNORE 0x01 -#define USEP_RHS_NAK 0x02 -#define USEP_RHS_STALL 0x03 - -#define USEP_THS_NORM 0x00 -#define USEP_THS_IGNORE 0x04 -#define USEP_THS_NAK 0x08 -#define USEP_THS_STALL 0x0C - -#define USEP_RTE 0x10 -#define USEP_MF 0x20 - -#define USEP_TM_CONTROL 0x00 -#define USEP_TM_INT 0x100 -#define USEP_TM_BULK 0x200 -#define USEP_TM_ISO 0x300 - -/* Command Register */ -#define USCOM_EP0 0x00 -#define USCOM_EP1 0x01 -#define USCOM_EP2 0x02 -#define USCOM_EP3 0x03 - -#define USCOM_FLUSH 0x40 -#define USCOM_STR 0x80 - -/* Event Register */ -#define USB_E_RXB 0x0001 -#define USB_E_TXB 0x0002 -#define USB_E_BSY 0x0004 -#define USB_E_SOF 0x0008 -#define USB_E_TXE1 0x0010 -#define USB_E_TXE2 0x0020 -#define USB_E_TXE3 0x0040 -#define USB_E_TXE4 0x0080 -#define USB_TX_ERRMASK (USB_E_TXE1|USB_E_TXE2|USB_E_TXE3|USB_E_TXE4) -#define USB_E_IDLE 0x0100 -#define USB_E_RESET 0x0200 - -/* Mask Register */ -#define USBS_IDLE 0x01 - -/* RX Buffer Descriptor */ -#define RX_BD_OV 0x02 -#define RX_BD_CR 0x04 -#define RX_BD_AB 0x08 -#define RX_BD_NO 0x10 -#define RX_BD_PID_DATA0 0x00 -#define RX_BD_PID_DATA1 0x40 -#define RX_BD_PID_SETUP 0x80 -#define RX_BD_F 0x400 -#define RX_BD_L 0x800 -#define RX_BD_I 0x1000 -#define RX_BD_W 0x2000 -#define RX_BD_E 0x8000 - -/* Useful masks */ -#define RX_BD_PID_BITMASK (RX_BD_PID_DATA1 | RX_BD_PID_SETUP) -#define STALL_BITMASK (USEP_THS_STALL | USEP_RHS_STALL) -#define NAK_BITMASK (USEP_THS_NAK | USEP_RHS_NAK) -#define CBD_TX_BITMASK (TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_I | TX_BD_CNF) - -/* TX Buffer Descriptor */ -#define TX_BD_UN 0x02 -#define TX_BD_TO 0x04 -#define TX_BD_NO_PID 0x00 -#define TX_BD_PID_DATA0 0x80 -#define TX_BD_PID_DATA1 0xC0 -#define TX_BD_CNF 0x200 -#define TX_BD_TC 0x400 -#define TX_BD_L 0x800 -#define TX_BD_I 0x1000 -#define TX_BD_W 0x2000 -#define TX_BD_R 0x8000 - -/* Implementation specific defines */ - -#define EP_MIN_PACKET_SIZE 0x08 -#define MAX_ENDPOINTS 0x04 -#define FIFO_SIZE 0x10 -#define EP_MAX_PKT FIFO_SIZE -#define TX_RING_SIZE 0x04 -#define RX_RING_SIZE 0x06 -#define USB_MAX_PKT 0x40 -#define TOGGLE_TX_PID(x) x= ((~x)&0x40)|0x80 -#define TOGGLE_RX_PID(x) x^= 0x40 -#define EP_ATTACHED 0x01 /* Endpoint has a urb attached or not */ -#define EP_SEND_ZLP 0x02 /* Send ZLP y/n ? */ - -#define PROFF_USB 0x00000000 -#define CPM_USB_BASE 0x00000A00 - -/* UDC device defines */ -#define EP0_MAX_PACKET_SIZE EP_MAX_PKT - -#define UDC_OUT_PACKET_SIZE EP_MIN_PACKET_SIZE -#define UDC_IN_PACKET_SIZE EP_MIN_PACKET_SIZE -#define UDC_INT_PACKET_SIZE UDC_IN_PACKET_SIZE -#define UDC_BULK_PACKET_SIZE EP_MIN_PACKET_SIZE - -struct mpc8xx_ep { - struct urb * urb; - unsigned char pid; - unsigned char sc; - volatile cbd_t * prx; -}; - -typedef struct mpc8xx_usb{ - char usmod; /* Mode Register */ - char usaddr; /* Slave Address Register */ - char uscom; /* Command Register */ - char res1; /* Reserved */ - ushort usep[4]; - ulong res2; /* Reserved */ - ushort usber; /* Event Register */ - ushort res3; /* Reserved */ - ushort usbmr; /* Mask Register */ - char res4; /* Reserved */ - char usbs; /* Status Register */ - char res5[8]; /* Reserved */ -}usb_t; - -typedef struct mpc8xx_parameter_ram{ - ushort ep0ptr; /* Endpoint Pointer Register 0 */ - ushort ep1ptr; /* Endpoint Pointer Register 1 */ - ushort ep2ptr; /* Endpoint Pointer Register 2 */ - ushort ep3ptr; /* Endpoint Pointer Register 3 */ - uint rstate; /* Receive state */ - uint rptr; /* Receive internal data pointer */ - ushort frame_n; /* Frame number */ - ushort rbcnt; /* Receive byte count */ - uint rtemp; /* Receive temp cp use only */ - uint rxusb; /* Rx Data Temp */ - ushort rxuptr; /* Rx microcode return address temp */ -}usb_pram_t; - -typedef struct endpoint_parameter_block_pointer{ - ushort rbase; /* RxBD base address */ - ushort tbase; /* TxBD base address */ - char rfcr; /* Rx Function code */ - char tfcr; /* Tx Function code */ - ushort mrblr; /* Maximum Receive Buffer Length */ - ushort rbptr; /* RxBD pointer Next Buffer Descriptor */ - ushort tbptr; /* TxBD pointer Next Buffer Descriptor */ - ulong tstate; /* Transmit internal state */ - ulong tptr; /* Transmit internal data pointer */ - ushort tcrc; /* Transmit temp CRC */ - ushort tbcnt; /* Transmit internal bye count */ - ulong ttemp; /* Tx temp */ - ushort txuptr; /* Tx microcode return address */ - ushort res1; /* Reserved */ -}usb_epb_t; - -typedef enum mpc8xx_udc_state{ - STATE_NOT_READY, - STATE_ERROR, - STATE_READY, -}mpc8xx_udc_state_t; - diff --git a/include/watchdog.h b/include/watchdog.h index 174c894..0055a83 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -72,11 +72,6 @@ int init_func_watchdog_reset(void); * Prototypes from $(CPU)/cpu.c. */

-/* MPC 8xx */ -#if (defined(CONFIG_8xx) || defined(CONFIG_MPC860)) && !defined(__ASSEMBLY__) - void reset_8xx_watchdog(volatile immap_t *immr); -#endif - /* MPC 5xx */ #if defined(CONFIG_5xx) && !defined(__ASSEMBLY__) void reset_5xx_watchdog(volatile immap_t *immr); diff --git a/post/Makefile b/post/Makefile index 78ede8c..09bf408 100644 --- a/post/Makefile +++ b/post/Makefile @@ -11,7 +11,6 @@ obj-$(CONFIG_POST_STD_LIST) += tests.o obj-y += drivers/ obj-$(CONFIG_PPC) += lib_powerpc/ obj-$(CONFIG_MPC83xx) += cpu/mpc83xx/ -obj-$(CONFIG_8xx) += cpu/mpc8xx/ obj-$(CONFIG_4xx) += cpu/ppc4xx/ ifneq ($(filter lwmon5 pdm360ng,$(BOARD)),) obj-y += board/$(BOARD)/ diff --git a/post/cpu/mpc8xx/Makefile b/post/cpu/mpc8xx/Makefile deleted file mode 100644 index f8bb6c9..0000000 --- a/post/cpu/mpc8xx/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_HAS_POST) += cache_8xx.o -obj-$(CONFIG_HAS_POST) += cache.o ether.o spr.o uart.o usb.o watchdog.o diff --git a/post/cpu/mpc8xx/cache.c b/post/cpu/mpc8xx/cache.c deleted file mode 100644 index af1281b..0000000 --- a/post/cpu/mpc8xx/cache.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -/* Cache test - * - * This test verifies the CPU data and instruction cache using - * several test scenarios. - */ - -#include <post.h> -#include <watchdog.h> - -#if CONFIG_POST & CONFIG_SYS_POST_CACHE - -#define CACHE_POST_SIZE 1024 - -extern int cache_post_test1 (char *, unsigned int); -extern int cache_post_test2 (char *, unsigned int); -extern int cache_post_test3 (char *, unsigned int); -extern int cache_post_test4 (char *, unsigned int); -extern int cache_post_test5 (void); -extern int cache_post_test6 (void); - -int cache_post_test (int flags) -{ - int ints = disable_interrupts (); - int res = 0; - static char ta[CACHE_POST_SIZE + 0xf]; - char *testarea = (char *) (((unsigned long) ta + 0xf) & ~0xf); - - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test1 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test2 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test3 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test4 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test5 (); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test6 (); - - WATCHDOG_RESET (); - if (ints) - enable_interrupts (); - return res; -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */ diff --git a/post/cpu/mpc8xx/cache_8xx.S b/post/cpu/mpc8xx/cache_8xx.S deleted file mode 100644 index 43649c8..0000000 --- a/post/cpu/mpc8xx/cache_8xx.S +++ /dev/null @@ -1,477 +0,0 @@ -/* - * Copyright (C) 2002 Wolfgang Denk wd@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> - -#if defined(CONFIG_MPC823) || \ - defined(CONFIG_MPC850) || \ - defined(CONFIG_MPC855) || \ - defined(CONFIG_MPC860) || \ - defined(CONFIG_MPC862) - -#include <post.h> -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> - -#if CONFIG_POST & CONFIG_SYS_POST_CACHE - - .text - -cache_post_dinvalidate: - lis r10, IDC_INVALL@h - mtspr DC_CST, r10 - blr - -cache_post_iinvalidate: - lis r10, IDC_INVALL@h - mtspr IC_CST, r10 - isync - blr - -cache_post_ddisable: - lis r10, IDC_DISABLE@h - mtspr DC_CST, r10 - blr - -cache_post_dwb: - lis r10, IDC_ENABLE@h - mtspr DC_CST, r10 - lis r10, DC_CFWT@h - mtspr DC_CST, r10 - blr - -cache_post_dwt: - lis r10, IDC_ENABLE@h - mtspr DC_CST, r10 - lis r10, DC_SFWT@h - mtspr DC_CST, r10 - blr - -cache_post_idisable: - lis r10, IDC_DISABLE@h - mtspr IC_CST, r10 - isync - blr - -cache_post_ienable: - lis r10, IDC_ENABLE@h - mtspr IC_CST, r10 - isync - blr - -cache_post_iunlock: - lis r10, IDC_UNALL@h - mtspr IC_CST, r10 - isync - blr - -cache_post_ilock: - mtspr IC_ADR, r3 - lis r10, IDC_LDLCK@h - mtspr IC_CST, r10 - isync - blr - -/* - * turn on the data cache - * switch the data cache to write-back or write-through mode - * invalidate the data cache - * write the negative pattern to a cached area - * read the area - * - * The negative pattern must be read at the last step - */ - .global cache_post_test1 -cache_post_test1: - mflr r0 - stw r0, 4(r1) - - stwu r3, -4(r1) - stwu r4, -4(r1) - - bl cache_post_dwb - bl cache_post_dinvalidate - - /* Write the negative pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0xff - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - /* Read the test area */ - lwz r0, 0(r1) - mtctr r0 - lwz r4, 4(r1) - subi r4, r4, 1 - li r3, 0 -1: - lbzu r0, 1(r4) - cmpli cr0, r0, 0xff - beq 2f - li r3, -1 - b 3f -2: - bdnz 1b -3: - - bl cache_post_ddisable - bl cache_post_dinvalidate - - addi r1, r1, 8 - - lwz r0, 4(r1) - mtlr r0 - blr - -/* - * turn on the data cache - * switch the data cache to write-back or write-through mode - * invalidate the data cache - * write the zero pattern to a cached area - * turn off the data cache - * write the negative pattern to the area - * turn on the data cache - * read the area - * - * The negative pattern must be read at the last step - */ - .global cache_post_test2 -cache_post_test2: - mflr r0 - stw r0, 4(r1) - - stwu r3, -4(r1) - stwu r4, -4(r1) - - bl cache_post_dwb - bl cache_post_dinvalidate - - /* Write the zero pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0 - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_ddisable - - /* Write the negative pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0xff - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_dwb - - /* Read the test area */ - lwz r0, 0(r1) - mtctr r0 - lwz r4, 4(r1) - subi r4, r4, 1 - li r3, 0 -1: - lbzu r0, 1(r4) - cmpli cr0, r0, 0xff - beq 2f - li r3, -1 - b 3f -2: - bdnz 1b -3: - - bl cache_post_ddisable - bl cache_post_dinvalidate - - addi r1, r1, 8 - - lwz r0, 4(r1) - mtlr r0 - blr - -/* - * turn on the data cache - * switch the data cache to write-through mode - * invalidate the data cache - * write the zero pattern to a cached area - * flush the data cache - * write the negative pattern to the area - * turn off the data cache - * read the area - * - * The negative pattern must be read at the last step - */ - .global cache_post_test3 -cache_post_test3: - mflr r0 - stw r0, 4(r1) - - stwu r3, -4(r1) - stwu r4, -4(r1) - - bl cache_post_ddisable - bl cache_post_dinvalidate - - /* Write the zero pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0 - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_dwt - bl cache_post_dinvalidate - - /* Write the negative pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0xff - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_ddisable - bl cache_post_dinvalidate - - /* Read the test area */ - lwz r0, 0(r1) - mtctr r0 - lwz r4, 4(r1) - subi r4, r4, 1 - li r3, 0 -1: - lbzu r0, 1(r4) - cmpli cr0, r0, 0xff - beq 2f - li r3, -1 - b 3f -2: - bdnz 1b -3: - - addi r1, r1, 8 - - lwz r0, 4(r1) - mtlr r0 - blr - -/* - * turn on the data cache - * switch the data cache to write-back mode - * invalidate the data cache - * write the negative pattern to a cached area - * flush the data cache - * write the zero pattern to the area - * invalidate the data cache - * read the area - * - * The negative pattern must be read at the last step - */ - .global cache_post_test4 -cache_post_test4: - mflr r0 - stw r0, 4(r1) - - stwu r3, -4(r1) - stwu r4, -4(r1) - - bl cache_post_ddisable - bl cache_post_dinvalidate - - /* Write the negative pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0xff - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_dwb - bl cache_post_dinvalidate - - /* Write the zero pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0 - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_ddisable - bl cache_post_dinvalidate - - /* Read the test area */ - lwz r0, 0(r1) - mtctr r0 - lwz r4, 4(r1) - subi r4, r4, 1 - li r3, 0 -1: - lbzu r0, 1(r4) - cmpli cr0, r0, 0xff - beq 2f - li r3, -1 - b 3f -2: - bdnz 1b -3: - - addi r1, r1, 8 - - lwz r0, 4(r1) - mtlr r0 - blr - -cache_post_test5_1: - li r3, 0 -cache_post_test5_2: - li r3, -1 - -/* - * turn on the instruction cache - * unlock the entire instruction cache - * invalidate the instruction cache - * lock a branch instruction in the instruction cache - * replace the branch instruction with "nop" - * jump to the branch instruction - * check that the branch instruction was executed -*/ - .global cache_post_test5 -cache_post_test5: - mflr r0 - stw r0, 4(r1) - - bl cache_post_ienable - bl cache_post_iunlock - bl cache_post_iinvalidate - - /* Compute r9 = cache_post_test5_reloc */ - bl cache_post_test5_reloc -cache_post_test5_reloc: - mflr r9 - - /* Copy the test instruction to cache_post_test5_data */ - lis r3, (cache_post_test5_1 - cache_post_test5_reloc)@h - ori r3, r3, (cache_post_test5_1 - cache_post_test5_reloc)@l - add r3, r3, r9 - lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h - ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l - add r4, r4, r9 - lwz r0, 0(r3) - stw r0, 0(r4) - - bl cache_post_iinvalidate - - /* Lock the branch instruction */ - lis r3, (cache_post_test5_data - cache_post_test5_reloc)@h - ori r3, r3, (cache_post_test5_data - cache_post_test5_reloc)@l - add r3, r3, r9 - bl cache_post_ilock - - /* Replace the test instruction */ - lis r3, (cache_post_test5_2 - cache_post_test5_reloc)@h - ori r3, r3, (cache_post_test5_2 - cache_post_test5_reloc)@l - add r3, r3, r9 - lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h - ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l - add r4, r4, r9 - lwz r0, 0(r3) - stw r0, 0(r4) - - bl cache_post_iinvalidate - - /* Execute to the test instruction */ -cache_post_test5_data: - nop - - bl cache_post_iunlock - - lwz r0, 4(r1) - mtlr r0 - blr - -cache_post_test6_1: - li r3, -1 -cache_post_test6_2: - li r3, 0 - -/* - * turn on the instruction cache - * unlock the entire instruction cache - * invalidate the instruction cache - * lock a branch instruction in the instruction cache - * replace the branch instruction with "nop" - * jump to the branch instruction - * check that the branch instruction was executed - */ - .global cache_post_test6 -cache_post_test6: - mflr r0 - stw r0, 4(r1) - - bl cache_post_ienable - bl cache_post_iunlock - bl cache_post_iinvalidate - - /* Compute r9 = cache_post_test6_reloc */ - bl cache_post_test6_reloc -cache_post_test6_reloc: - mflr r9 - - /* Copy the test instruction to cache_post_test6_data */ - lis r3, (cache_post_test6_1 - cache_post_test6_reloc)@h - ori r3, r3, (cache_post_test6_1 - cache_post_test6_reloc)@l - add r3, r3, r9 - lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h - ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l - add r4, r4, r9 - lwz r0, 0(r3) - stw r0, 0(r4) - - bl cache_post_iinvalidate - - /* Replace the test instruction */ - lis r3, (cache_post_test6_2 - cache_post_test6_reloc)@h - ori r3, r3, (cache_post_test6_2 - cache_post_test6_reloc)@l - add r3, r3, r9 - lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h - ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l - add r4, r4, r9 - lwz r0, 0(r3) - stw r0, 0(r4) - - bl cache_post_iinvalidate - - /* Execute to the test instruction */ -cache_post_test6_data: - nop - - lwz r0, 4(r1) - mtlr r0 - blr - -#endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 */ -#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */ diff --git a/post/cpu/mpc8xx/ether.c b/post/cpu/mpc8xx/ether.c deleted file mode 100644 index 47f6f32..0000000 --- a/post/cpu/mpc8xx/ether.c +++ /dev/null @@ -1,532 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -/* - * Ethernet test - * - * The Serial Communication Controllers (SCC) listed in ctlr_list array below - * are tested in the loopback ethernet mode. - * The controllers are configured accordingly and several packets - * are transmitted. The configurable test parameters are: - * MIN_PACKET_LENGTH - minimum size of packet to transmit - * MAX_PACKET_LENGTH - maximum size of packet to transmit - * TEST_NUM - number of tests - */ - -#include <post.h> -#if CONFIG_POST & CONFIG_SYS_POST_ETHER -#if defined(CONFIG_8xx) -#include <commproc.h> -#elif defined(CONFIG_MPC8260) -#include <asm/cpm_8260.h> -#else -#error "Apparently a bad configuration, please fix." -#endif - -#include <command.h> -#include <net.h> -#include <serial.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define MIN_PACKET_LENGTH 64 -#define MAX_PACKET_LENGTH 256 -#define TEST_NUM 1 - -#define CTLR_SCC 0 - -extern void spi_init_f (void); -extern void spi_init_r (void); - -/* The list of controllers to test */ -#if defined(CONFIG_MPC823) -static int ctlr_list[][2] = { {CTLR_SCC, 1} }; -#else -static int ctlr_list[][2] = { }; -#endif - -static struct { - void (*init) (int index); - void (*halt) (int index); - int (*send) (int index, volatile void *packet, int length); - int (*recv) (int index, void *packet, int length); -} ctlr_proc[1]; - -static char *ctlr_name[1] = { "SCC" }; - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 100 - -static char txbuf[DBUF_LENGTH]; - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * SCC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx; - - /* - * SCC callbacks - */ - -static void scc_init (int scc_index) -{ - uchar ea[6]; - - static int proff[] = { - PROFF_SCC1, - PROFF_SCC2, - PROFF_SCC3, - PROFF_SCC4, - }; - static unsigned int cpm_cr[] = { - CPM_CR_CH_SCC1, - CPM_CR_CH_SCC2, - CPM_CR_CH_SCC3, - CPM_CR_CH_SCC4, - }; - - int i; - scc_enet_t *pram_ptr; - - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - immr->im_cpm.cp_scc[scc_index].scc_gsmrl &= - ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]); - - rxIdx = 0; - txIdx = 0; - - rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE); - -#if 0 - -#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) - /* Configure port A pins for Txd and Rxd. - */ - immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_paodr &= ~PA_ENET_TXD; -#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) - /* Configure port B pins for Txd and Rxd. - */ - immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); - immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); - immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD; -#else -#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined -#endif - -#if defined(PC_ENET_LBK) - /* Configure port C pins to disable External Loopback - */ - immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK; - immr->im_ioport.iop_pcdir |= PC_ENET_LBK; - immr->im_ioport.iop_pcso &= ~PC_ENET_LBK; - immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ -#endif /* PC_ENET_LBK */ - - /* Configure port C pins to enable CLSN and RENA. - */ - immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); - - /* Configure port A for TCLK and RCLK. - */ - immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); - immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); - - /* - * Configure Serial Interface clock routing -- see section 16.7.5.3 - * First, clear all SCC bits to zero, then set the ones we want. - */ - - immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK; - immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT; -#else - /* - * SCC2 receive clock is BRG2 - * SCC2 transmit clock is BRG3 - */ - immr->im_cpm.cp_brgc2 = 0x0001000C; - immr->im_cpm.cp_brgc3 = 0x0001000C; - - immr->im_cpm.cp_sicr &= ~0x00003F00; - immr->im_cpm.cp_sicr |= 0x00000a00; -#endif /* 0 */ - - - /* - * Initialize SDCR -- see section 16.9.23.7 - * SDMA configuration register - */ - immr->im_siu_conf.sc_sdcr = 0x01; - - - /* - * Setup SCC Ethernet Parameter RAM - */ - - pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */ - pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */ - - pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */ - - pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */ - pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */ - - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - - for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; - } - - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Add PADs to Short FRAMES, Wrap, Last, Tx CRC - */ - - for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = - (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); - } - - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* - * Enter Command: Initialize Rx Params for SCC - */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = - ((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) | - CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Ethernet Specific Parameter RAM - * see table 13-16, pg. 660, - * pg. 681 (example with suggested settings) - */ - - pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ - pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ - pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ - pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */ - pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ - pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ - - pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ - pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ - pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ - - pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ - pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ - - pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ - pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ - pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ - pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ - - eth_getenv_enetaddr("ethaddr", ea); - pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; - - pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ - pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ - pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ - pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ - pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ - pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ - pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ - pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ - - /* - * Enter Command: Initialize Tx Params for SCC - */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = - ((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) | - CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Mask all Events in SCCM - we use polling mode - */ - immr->im_cpm.cp_scc[scc_index].scc_sccm = 0; - - /* - * Clear Events in SCCE -- Clear bits by writing 1's - */ - - immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0); - - - /* - * Initialize GSMR High 32-Bits - * Settings: Normal Mode - */ - - immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0; - - /* - * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive - * Settings: - * TCI = Invert - * TPL = 48 bits - * TPP = Repeating 10's - * LOOP = Loopback - * MODE = Ethernet - */ - - immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI | - SCC_GSMRL_TPL_48 | - SCC_GSMRL_TPP_10 | - SCC_GSMRL_DIAG_LOOP | - SCC_GSMRL_MODE_ENET); - - /* - * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4 - */ - - immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555; - - /* - * Initialize the PSMR - * Settings: - * CRC = 32-Bit CCITT - * NIB = Begin searching for SFD 22 bits after RENA - * LPB = Loopback Enable (Needed when FDE is set) - */ - immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC | - SCC_PSMR_NIB22 | SCC_PSMR_LPB; - - /* - * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive - */ - - immr->im_cpm.cp_scc[scc_index].scc_gsmrl |= - (SCC_GSMRL_ENR | SCC_GSMRL_ENT); -} - -static void scc_halt (int scc_index) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - immr->im_cpm.cp_scc[scc_index].scc_gsmrl &= - ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA); -} - -static int scc_send (int index, volatile void *packet, int length) -{ - int i, j = 0; - - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) { - udelay (1); /* will also trigger Wd if needed */ - j++; - } - if (j >= TOUT_LOOP) - printf ("TX not ready\n"); - rtx->txbd[txIdx].cbd_bufaddr = (uint) packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= - (BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP); - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) { - udelay (1); /* will also trigger Wd if needed */ - j++; - } - if (j >= TOUT_LOOP) - printf ("TX timeout\n"); - i = (rtx->txbd[txIdx]. - cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ; - return i; -} - -static int scc_recv (int index, void *packet, int max_length) -{ - int length = -1; - - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - goto Done; /* nothing received */ - } - - if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) { - length = rtx->rxbd[rxIdx].cbd_datlen - 4; - memcpy (packet, - (void *)(net_rx_packets[rxIdx]), - length < max_length ? length : max_length); - } - - /* Give the buffer back to the SCC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - -Done: - return length; -} - - /* - * Test routines - */ - -static void packet_fill (char *packet, int length) -{ - char c = (char) length; - int i; - - packet[0] = 0xFF; - packet[1] = 0xFF; - packet[2] = 0xFF; - packet[3] = 0xFF; - packet[4] = 0xFF; - packet[5] = 0xFF; - - for (i = 6; i < length; i++) { - packet[i] = c++; - } -} - -static int packet_check (char *packet, int length) -{ - char c = (char) length; - int i; - - for (i = 6; i < length; i++) { - if (packet[i] != c++) - return -1; - } - - return 0; -} - -static int test_ctlr (int ctlr, int index) -{ - int res = -1; - char packet_send[MAX_PACKET_LENGTH]; - char packet_recv[MAX_PACKET_LENGTH]; - int length; - int i; - int l; - - ctlr_proc[ctlr].init (index); - - for (i = 0; i < TEST_NUM; i++) { - for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) { - packet_fill (packet_send, l); - - ctlr_proc[ctlr].send (index, packet_send, l); - - length = ctlr_proc[ctlr].recv (index, packet_recv, - MAX_PACKET_LENGTH); - - if (length != l || packet_check (packet_recv, length) < 0) { - goto Done; - } - } - } - - res = 0; - -Done: - - ctlr_proc[ctlr].halt (index); - - /* - * SCC2 Ethernet parameter RAM space overlaps - * the SPI parameter RAM space. So we need to restore - * the SPI configuration after SCC2 ethernet test. - */ -#if defined(CONFIG_SPI) - if (ctlr == CTLR_SCC && index == 1) { - spi_init_f (); - spi_init_r (); - } -#endif - - if (res != 0) { - post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr], - index + 1); - } - - return res; -} - -int ether_post_test (int flags) -{ - int res = 0; - int i; - - ctlr_proc[CTLR_SCC].init = scc_init; - ctlr_proc[CTLR_SCC].halt = scc_halt; - ctlr_proc[CTLR_SCC].send = scc_send; - ctlr_proc[CTLR_SCC].recv = scc_recv; - - for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) { - if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) { - res = -1; - } - } - -#if !defined(CONFIG_8xx_CONS_NONE) - serial_reinit_all (); -#endif - return res; -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */ diff --git a/post/cpu/mpc8xx/spr.c b/post/cpu/mpc8xx/spr.c deleted file mode 100644 index d20da8d..0000000 --- a/post/cpu/mpc8xx/spr.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -/* - * SPR test - * - * The test checks the contents of Special Purpose Registers (SPR) listed - * in the spr_test_list array below. - * Each SPR value is read using mfspr instruction, some bits are masked - * according to the table and the resulting value is compared to the - * corresponding table value. - */ - -#include <post.h> - -#if CONFIG_POST & CONFIG_SYS_POST_SPR - -static struct -{ - int number; - char * name; - unsigned long mask; - unsigned long value; -} spr_test_list [] = { - /* Standard Special-Purpose Registers */ - - {1, "XER", 0x00000000, 0x00000000}, - {8, "LR", 0x00000000, 0x00000000}, - {9, "CTR", 0x00000000, 0x00000000}, - {18, "DSISR", 0x00000000, 0x00000000}, - {19, "DAR", 0x00000000, 0x00000000}, - {22, "DEC", 0x00000000, 0x00000000}, - {26, "SRR0", 0x00000000, 0x00000000}, - {27, "SRR1", 0x00000000, 0x00000000}, - {272, "SPRG0", 0x00000000, 0x00000000}, - {273, "SPRG1", 0x00000000, 0x00000000}, - {274, "SPRG2", 0x00000000, 0x00000000}, - {275, "SPRG3", 0x00000000, 0x00000000}, - {287, "PVR", 0xFFFF0000, 0x00500000}, - - /* Additional Special-Purpose Registers */ - - {144, "CMPA", 0x00000000, 0x00000000}, - {145, "CMPB", 0x00000000, 0x00000000}, - {146, "CMPC", 0x00000000, 0x00000000}, - {147, "CMPD", 0x00000000, 0x00000000}, - {148, "ICR", 0xFFFFFFFF, 0x00000000}, - {149, "DER", 0x00000000, 0x00000000}, - {150, "COUNTA", 0xFFFFFFFF, 0x00000000}, - {151, "COUNTB", 0xFFFFFFFF, 0x00000000}, - {152, "CMPE", 0x00000000, 0x00000000}, - {153, "CMPF", 0x00000000, 0x00000000}, - {154, "CMPG", 0x00000000, 0x00000000}, - {155, "CMPH", 0x00000000, 0x00000000}, - {156, "LCTRL1", 0xFFFFFFFF, 0x00000000}, - {157, "LCTRL2", 0xFFFFFFFF, 0x00000000}, - {158, "ICTRL", 0xFFFFFFFF, 0x00000007}, - {159, "BAR", 0x00000000, 0x00000000}, - {630, "DPDR", 0x00000000, 0x00000000}, - {631, "DPIR", 0x00000000, 0x00000000}, - {638, "IMMR", 0xFFFF0000, CONFIG_SYS_IMMR }, - {560, "IC_CST", 0x8E380000, 0x00000000}, - {561, "IC_ADR", 0x00000000, 0x00000000}, - {562, "IC_DAT", 0x00000000, 0x00000000}, - {568, "DC_CST", 0xEF380000, 0x00000000}, - {569, "DC_ADR", 0x00000000, 0x00000000}, - {570, "DC_DAT", 0x00000000, 0x00000000}, - {784, "MI_CTR", 0xFFFFFFFF, 0x00000000}, - {786, "MI_AP", 0x00000000, 0x00000000}, - {787, "MI_EPN", 0x00000000, 0x00000000}, - {789, "MI_TWC", 0xFFFFFE02, 0x00000000}, - {790, "MI_RPN", 0x00000000, 0x00000000}, - {816, "MI_DBCAM", 0x00000000, 0x00000000}, - {817, "MI_DBRAM0", 0x00000000, 0x00000000}, - {818, "MI_DBRAM1", 0x00000000, 0x00000000}, - {792, "MD_CTR", 0xFFFFFFFF, 0x04000000}, - {793, "M_CASID", 0xFFFFFFF0, 0x00000000}, - {794, "MD_AP", 0x00000000, 0x00000000}, - {795, "MD_EPN", 0x00000000, 0x00000000}, - {796, "M_TWB", 0x00000003, 0x00000000}, - {797, "MD_TWC", 0x00000003, 0x00000000}, - {798, "MD_RPN", 0x00000000, 0x00000000}, - {799, "M_TW", 0x00000000, 0x00000000}, - {824, "MD_DBCAM", 0x00000000, 0x00000000}, - {825, "MD_DBRAM0", 0x00000000, 0x00000000}, - {826, "MD_DBRAM1", 0x00000000, 0x00000000}, -}; - -static int spr_test_list_size = ARRAY_SIZE(spr_test_list); - -int spr_post_test (int flags) -{ - int ret = 0; - int ic = icache_status (); - int i; - - unsigned long code[] = { - 0x7c6002a6, /* mfspr r3,SPR */ - 0x4e800020 /* blr */ - }; - unsigned long (*get_spr) (void) = (void *) code; - - if (ic) - icache_disable (); - - for (i = 0; i < spr_test_list_size; i++) { - int num = spr_test_list[i].number; - - /* mfspr r3,num */ - code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6); - - if ((get_spr () & spr_test_list[i].mask) != - (spr_test_list[i].value & spr_test_list[i].mask)) { - post_log ("The value of %s special register " - "is incorrect: 0x%08X\n", - spr_test_list[i].name, get_spr ()); - ret = -1; - } - } - - if (ic) - icache_enable (); - - return ret; -} -#endif /* CONFIG_POST & CONFIG_SYS_POST_SPR */ diff --git a/post/cpu/mpc8xx/uart.c b/post/cpu/mpc8xx/uart.c deleted file mode 100644 index 64ca7e4..0000000 --- a/post/cpu/mpc8xx/uart.c +++ /dev/null @@ -1,510 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -/* - * UART test - * - * The Serial Management Controllers (SMC) and the Serial Communication - * Controllers (SCC) listed in ctlr_list array below are tested in - * the loopback UART mode. - * The controllers are configured accordingly and several characters - * are transmitted. The configurable test parameters are: - * MIN_PACKET_LENGTH - minimum size of packet to transmit - * MAX_PACKET_LENGTH - maximum size of packet to transmit - * TEST_NUM - number of tests - */ - -#include <post.h> -#if CONFIG_POST & CONFIG_SYS_POST_UART -#if defined(CONFIG_8xx) -#include <commproc.h> -#elif defined(CONFIG_MPC8260) -#include <asm/cpm_8260.h> -#else -#error "Apparently a bad configuration, please fix." -#endif -#include <command.h> -#include <serial.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define CTLR_SMC 0 -#define CTLR_SCC 1 - -/* The list of controllers to test */ -#if defined(CONFIG_MPC823) -static int ctlr_list[][2] = - { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} }; -#else -static int ctlr_list[][2] = { }; -#endif - -static struct { - void (*init) (int index); - void (*halt) (int index); - void (*putc) (int index, const char c); - int (*getc) (int index); -} ctlr_proc[2]; - -static char *ctlr_name[2] = { "SMC", "SCC" }; - -static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 }; -static int proff_scc[] = - { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 }; - -/* - * SMC callbacks - */ - -static void smc_init (int smc_index) -{ - static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 }; - - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SMC */ - - sp = (smc_t *) & (cp->cp_smc[smc_index]); - up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* Enable SDMA. - */ - im->im_siu_conf.sc_sdcr = 1; - - /* clear error conditions */ -#ifdef CONFIG_SYS_SDSR - im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; -#else - im->im_sdma.sdma_sdsr = 0x83; -#endif - - /* clear SDMA interrupt mask */ -#ifdef CONFIG_SYS_SDMR - im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; -#else - im->im_sdma.sdma_sdmr = 0x00; -#endif - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - dpaddr = CPM_POST_BASE; - - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - * damm: allocating space after the two buffers for rx/tx data - */ - - rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf + 2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr + sizeof (cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - * Set local loopback mode. - */ - sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* Set up the baud rate generator. - */ - cp->cp_simode = 0x00000000; - - cp->cp_brgc1 = - (((gd->cpu_clk / 16 / gd->baudrate) - - 1) << 1) | CPM_BRG_EN; - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = - mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; -} - -static void smc_halt(int smc_index) -{ -} - -static void smc_putc (int smc_index, const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]]; - - tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *) tbdf->cbd_bufaddr; -#if 0 - __asm__ ("eieio"); - while (tbdf->cbd_sc & BD_SC_READY) - __asm__ ("eieio"); -#endif - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__ ("eieio"); -#if 1 - while (tbdf->cbd_sc & BD_SC_READY) - __asm__ ("eieio"); -#endif -} - -static int smc_getc (int smc_index) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - int i; - - up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]]; - - rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *) rbdf->cbd_bufaddr; -#if 0 - while (rbdf->cbd_sc & BD_SC_EMPTY); -#else - for (i = 100; i > 0; i--) { - if (!(rbdf->cbd_sc & BD_SC_EMPTY)) - break; - udelay (1000); - } - - if (i == 0) - return -1; -#endif - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - - /* - * SCC callbacks - */ - -static void scc_init (int scc_index) -{ - static int cpm_cr_ch[] = { - CPM_CR_CH_SCC1, - CPM_CR_CH_SCC2, - CPM_CR_CH_SCC3, - CPM_CR_CH_SCC4, - }; - - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SCC */ - - sp = (scc_t *) & (cp->cp_scc[scc_index]); - up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]]; - - /* Disable transmitter/receiver. - */ - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - dpaddr = CPM_POST_BASE; - - /* Enable SDMA. - */ - im->im_siu_conf.sc_sdcr = 0x0001; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - - rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf + 2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the baud rate generator. - */ - cp->cp_sicr &= ~(0x000000FF << (8 * scc_index)); - /* no |= needed, since BRG1 is 000 */ - - cp->cp_brgc1 = - (((gd->cpu_clk / 16 / gd->baudrate) - - 1) << 1) | CPM_BRG_EN; - - /* Set up the uart parameters in the parameter ram. - */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t); - - /* Initialize Tx/Rx parameters. - */ - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - cp->cp_cpcr = - mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - up->scc_genscc.scc_rfcr = SCC_EB | 0x05; - up->scc_genscc.scc_tfcr = SCC_EB | 0x05; - - up->scc_genscc.scc_mrblr = 1; /* Single character receive */ - up->scc_maxidl = 0; /* disable max idle */ - up->scc_brkcr = 1; /* send one break character on stop TX */ - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = 0x8000; - up->scc_char2 = 0x8000; - up->scc_char3 = 0x8000; - up->scc_char4 = 0x8000; - up->scc_char5 = 0x8000; - up->scc_char6 = 0x8000; - up->scc_char7 = 0x8000; - up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Set low latency / small fifo. - */ - sp->scc_gsmrh = SCC_GSMRH_RFW; - - /* Set UART mode - */ - sp->scc_gsmrl &= ~0xF; - sp->scc_gsmrl |= SCC_GSMRL_MODE_UART; - - /* Set local loopback mode. - */ - sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE; - sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP; - - /* Set clock divider 16 on Tx and Rx - */ - sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); - - sp->scc_psmr |= SCU_PSMR_CL; - - /* Mask all interrupts and remove anything pending. - */ - sp->scc_sccm = 0; - sp->scc_scce = 0xffff; - sp->scc_dsr = 0x7e7e; - sp->scc_psmr = 0x3000; - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Enable transmitter/receiver. - */ - sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); -} - -static void scc_halt(int scc_index) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]); - - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE); -} - -static void scc_putc (int scc_index, const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]]; - - tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *) tbdf->cbd_bufaddr; -#if 0 - __asm__ ("eieio"); - while (tbdf->cbd_sc & BD_SC_READY) - __asm__ ("eieio"); -#endif - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__ ("eieio"); -#if 1 - while (tbdf->cbd_sc & BD_SC_READY) - __asm__ ("eieio"); -#endif -} - -static int scc_getc (int scc_index) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - int i; - - up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]]; - - rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *) rbdf->cbd_bufaddr; -#if 0 - while (rbdf->cbd_sc & BD_SC_EMPTY); -#else - for (i = 100; i > 0; i--) { - if (!(rbdf->cbd_sc & BD_SC_EMPTY)) - break; - udelay (1000); - } - - if (i == 0) - return -1; -#endif - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - - /* - * Test routines - */ - -static int test_ctlr (int ctlr, int index) -{ - int res = -1; - char test_str[] = "*** UART Test String ***\r\n"; - int i; - - ctlr_proc[ctlr].init (index); - - for (i = 0; i < sizeof (test_str) - 1; i++) { - ctlr_proc[ctlr].putc (index, test_str[i]); - if (ctlr_proc[ctlr].getc (index) != test_str[i]) - goto Done; - } - - res = 0; - -Done: - ctlr_proc[ctlr].halt (index); - - if (res != 0) { - post_log ("uart %s%d test failed\n", - ctlr_name[ctlr], index + 1); - } - - return res; -} - -int uart_post_test (int flags) -{ - int res = 0; - int i; - - ctlr_proc[CTLR_SMC].init = smc_init; - ctlr_proc[CTLR_SMC].halt = smc_halt; - ctlr_proc[CTLR_SMC].putc = smc_putc; - ctlr_proc[CTLR_SMC].getc = smc_getc; - - ctlr_proc[CTLR_SCC].init = scc_init; - ctlr_proc[CTLR_SCC].halt = scc_halt; - ctlr_proc[CTLR_SCC].putc = scc_putc; - ctlr_proc[CTLR_SCC].getc = scc_getc; - - for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) { - if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) { - res = -1; - } - } - -#if !defined(CONFIG_8xx_CONS_NONE) - serial_reinit_all (); -#endif - - return res; -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_UART */ diff --git a/post/cpu/mpc8xx/usb.c b/post/cpu/mpc8xx/usb.c deleted file mode 100644 index 6334088..0000000 --- a/post/cpu/mpc8xx/usb.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -/* - * USB test - * - * The USB controller is tested in the local loopback mode. - * It is configured so that endpoint 0 operates as host and endpoint 1 - * operates as function endpoint. After that an IN token transaction - * is performed. - * Refer to MPC850 User Manual, Section 32.11.1 USB Host Controller - * Initialization Example. - */ - -#include <post.h> - -#if CONFIG_POST & CONFIG_SYS_POST_USB - -#include <commproc.h> -#include <command.h> - -#define TOUT_LOOP 100 - -#define PROFF_USB ((uint)0x0000) - -#define CPM_USB_EP0_BASE 0x0a00 -#define CPM_USB_EP1_BASE 0x0a20 - -#define CPM_USB_DT0_BASE 0x0a80 -#define CPM_USB_DT1_BASE 0x0a90 -#define CPM_USB_DR0_BASE 0x0aa0 -#define CPM_USB_DR1_BASE 0x0ab0 - -#define CPM_USB_RX0_BASE 0x0b00 -#define CPM_USB_RX1_BASE 0x0b08 -#define CPM_USB_TX0_BASE 0x0b20 -#define CPM_USB_TX1_BASE 0x0b28 - -#define USB_EXPECT(x) if (!(x)) goto Done; - -typedef struct usb_param { - ushort ep0ptr; - ushort ep1ptr; - ushort ep2ptr; - ushort ep3ptr; - uint rstate; - uint rptr; - ushort frame_n; - ushort rbcnt; - ushort rtemp; -} usb_param_t; - -typedef struct usb_param_block { - ushort rbase; - ushort tbase; - uchar rfcr; - uchar tfcr; - ushort mrblr; - ushort rbptr; - ushort tbptr; - uint tstate; - uint tptr; - ushort tcrc; - ushort tbcnt; - uint res[2]; -} usb_param_block_t; - -typedef struct usb { - uchar usmod; - uchar usadr; - uchar uscom; - uchar res1; - ushort usep[4]; - uchar res2[4]; - ushort usber; - uchar res3[2]; - ushort usbmr; - uchar res4; - uchar usbs; - uchar res5[8]; -} usb_t; - -int usb_post_test (int flags) -{ - int res = -1; - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile usb_param_t *pram_ptr; - uint dpram; - ushort DPRAM; - volatile cbd_t *tx; - volatile cbd_t *rx; - volatile usb_t *usbr; - volatile usb_param_block_t *ep0; - volatile usb_param_block_t *ep1; - int j; - - pram_ptr = (usb_param_t *) & (im->im_cpm.cp_dparam[PROFF_USB]); - dpram = (uint) im->im_cpm.cp_dpmem; - DPRAM = dpram; - tx = (cbd_t *) (dpram + CPM_USB_TX0_BASE); - rx = (cbd_t *) (dpram + CPM_USB_RX0_BASE); - ep0 = (usb_param_block_t *) (dpram + CPM_USB_EP0_BASE); - ep1 = (usb_param_block_t *) (dpram + CPM_USB_EP1_BASE); - usbr = (usb_t *) & (im->im_cpm.cp_scc[0]); - - /* 01 */ - im->im_ioport.iop_padir &= ~(ushort) 0x0200; - im->im_ioport.iop_papar |= (ushort) 0x0200; - - cp->cp_sicr &= ~0x000000FF; - cp->cp_sicr |= 0x00000018; - - cp->cp_brgc4 = 0x00010001; - - /* 02 */ - im->im_ioport.iop_padir &= ~(ushort) 0x0002; - im->im_ioport.iop_padir &= ~(ushort) 0x0001; - - im->im_ioport.iop_papar |= (ushort) 0x0002; - im->im_ioport.iop_papar |= (ushort) 0x0001; - - /* 03 */ - im->im_ioport.iop_pcdir &= ~(ushort) 0x0020; - im->im_ioport.iop_pcdir &= ~(ushort) 0x0010; - - im->im_ioport.iop_pcpar &= ~(ushort) 0x0020; - im->im_ioport.iop_pcpar &= ~(ushort) 0x0010; - - im->im_ioport.iop_pcso |= (ushort) 0x0020; - im->im_ioport.iop_pcso |= (ushort) 0x0010; - - /* 04 */ - im->im_ioport.iop_pcdir |= (ushort) 0x0200; - im->im_ioport.iop_pcdir |= (ushort) 0x0100; - - im->im_ioport.iop_pcpar |= (ushort) 0x0200; - im->im_ioport.iop_pcpar |= (ushort) 0x0100; - - /* 05 */ - pram_ptr->frame_n = 0; - - /* 06 */ - pram_ptr->ep0ptr = DPRAM + CPM_USB_EP0_BASE; - pram_ptr->ep1ptr = DPRAM + CPM_USB_EP1_BASE; - - /* 07-10 */ - tx[0].cbd_sc = 0xB800; - tx[0].cbd_datlen = 3; - tx[0].cbd_bufaddr = dpram + CPM_USB_DT0_BASE; - - tx[1].cbd_sc = 0xBC80; - tx[1].cbd_datlen = 3; - tx[1].cbd_bufaddr = dpram + CPM_USB_DT1_BASE; - - rx[0].cbd_sc = 0xA000; - rx[0].cbd_datlen = 0; - rx[0].cbd_bufaddr = dpram + CPM_USB_DR0_BASE; - - rx[1].cbd_sc = 0xA000; - rx[1].cbd_datlen = 0; - rx[1].cbd_bufaddr = dpram + CPM_USB_DR1_BASE; - - /* 11-12 */ - *(volatile int *) (dpram + CPM_USB_DT0_BASE) = 0x69856000; - *(volatile int *) (dpram + CPM_USB_DT1_BASE) = 0xABCD1234; - - *(volatile int *) (dpram + CPM_USB_DR0_BASE) = 0; - *(volatile int *) (dpram + CPM_USB_DR1_BASE) = 0; - - /* 13-16 */ - ep0->rbase = DPRAM + CPM_USB_RX0_BASE; - ep0->tbase = DPRAM + CPM_USB_TX0_BASE; - ep0->rfcr = 0x18; - ep0->tfcr = 0x18; - ep0->mrblr = 0x100; - ep0->rbptr = DPRAM + CPM_USB_RX0_BASE; - ep0->tbptr = DPRAM + CPM_USB_TX0_BASE; - ep0->tstate = 0; - - /* 17-20 */ - ep1->rbase = DPRAM + CPM_USB_RX1_BASE; - ep1->tbase = DPRAM + CPM_USB_TX1_BASE; - ep1->rfcr = 0x18; - ep1->tfcr = 0x18; - ep1->mrblr = 0x100; - ep1->rbptr = DPRAM + CPM_USB_RX1_BASE; - ep1->tbptr = DPRAM + CPM_USB_TX1_BASE; - ep1->tstate = 0; - - /* 21-24 */ - usbr->usep[0] = 0x0000; - usbr->usep[1] = 0x1100; - usbr->usep[2] = 0x2200; - usbr->usep[3] = 0x3300; - - /* 25 */ - usbr->usmod = 0x06; - - /* 26 */ - usbr->usadr = 0x05; - - /* 27 */ - usbr->uscom = 0; - - /* 28 */ - usbr->usmod |= 0x01; - udelay (1); - - /* 29-30 */ - usbr->uscom = 0x80; - usbr->uscom = 0x81; - - /* Wait for the data packet to be transmitted */ - for (j = 0; j < TOUT_LOOP; j++) { - if (tx[1].cbd_sc & (ushort) 0x8000) - udelay (1); - else - break; - } - - USB_EXPECT (j < TOUT_LOOP); - - USB_EXPECT (tx[0].cbd_sc == 0x3800); - USB_EXPECT (tx[0].cbd_datlen == 3); - - USB_EXPECT (tx[1].cbd_sc == 0x3C80); - USB_EXPECT (tx[1].cbd_datlen == 3); - - USB_EXPECT (rx[0].cbd_sc == 0x2C00); - USB_EXPECT (rx[0].cbd_datlen == 5); - - USB_EXPECT (*(volatile int *) (dpram + CPM_USB_DR0_BASE) == - 0xABCD122B); - USB_EXPECT (*(volatile char *) (dpram + CPM_USB_DR0_BASE + 4) == 0x42); - - res = 0; - Done: - - return res; -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_USB */ diff --git a/post/cpu/mpc8xx/watchdog.c b/post/cpu/mpc8xx/watchdog.c deleted file mode 100644 index a070539..0000000 --- a/post/cpu/mpc8xx/watchdog.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -/* - * Watchdog test - * - * The test verifies the watchdog timer operation. - * On the first iteration, the test routine disables interrupts and - * makes a 10-second delay. If the system does not reboot during this delay, - * the watchdog timer is not operational and the test fails. If the system - * reboots, on the second iteration the test routine reports a success. - */ - -#include <post.h> -#include <watchdog.h> - -#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG - -static ulong gettbl (void) -{ - ulong r; - - asm ("mftbl %0":"=r" (r)); - - return r; -} - -int watchdog_post_test (int flags) -{ - if (flags & POST_REBOOT) { - /* Test passed */ - - return 0; - } else { - /* 10-second delay */ - int ints = disable_interrupts (); - ulong base = gettbl (); - ulong clk = get_tbclk (); - - while ((gettbl () - base) / 10 < clk); - - if (ints) - enable_interrupts (); - - /* - * If we have reached this point, the watchdog timer - * does not work - */ - return -1; - } -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_WATCHDOG */ diff --git a/post/tests.c b/post/tests.c index d8ac54e..bc8e398 100644 --- a/post/tests.c +++ b/post/tests.c @@ -180,18 +180,6 @@ struct post_test post_list[] = CONFIG_SYS_POST_ETHER }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_SPI - { - "SPI test", - "spi", - "This test verifies the SPI operation.", - POST_RAM | POST_ALWAYS, - &spi_post_test, - NULL, - NULL, - CONFIG_SYS_POST_SPI - }, -#endif #if CONFIG_POST & CONFIG_SYS_POST_USB { "USB test", diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c8cf428..9619ff4 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -43,14 +43,6 @@ CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES CONFIG_83XX_PCICLK CONFIG_83XX_PCI_STREAMING CONFIG_88F5182 -CONFIG_8xx_CONS_NONE -CONFIG_8xx_CONS_SCCx -CONFIG_8xx_CONS_SMC1 -CONFIG_8xx_CONS_SMC2 -CONFIG_8xx_CONS_SMCx -CONFIG_8xx_CPUCLK_DEFAULT -CONFIG_8xx_GCLK_FREQ -CONFIG_8xx_OSCLK CONFIG_A003399_NOR_WORKAROUND CONFIG_A008044_WORKAROUND CONFIG_A3M071 @@ -809,8 +801,6 @@ CONFIG_ETHER_ON_FCC CONFIG_ETHER_ON_FCC1 CONFIG_ETHER_ON_FCC2 CONFIG_ETHER_ON_FCC3 -CONFIG_ETHER_ON_FEC1 -CONFIG_ETHER_ON_FEC2 CONFIG_ETHER_ON_SCC CONFIG_ETHPRIME CONFIG_ETH_BUFSIZE @@ -870,8 +860,6 @@ CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN CONFIG_FEATURE_SH_EXTRA_QUIET CONFIG_FEATURE_SH_FANCY_PROMPT CONFIG_FEATURE_SH_STANDALONE_SHELL -CONFIG_FEC1_PHY -CONFIG_FEC2_PHY CONFIG_FEC_10MBIT CONFIG_FEC_AN_TIMEOUT CONFIG_FEC_ENET @@ -1278,8 +1266,6 @@ CONFIG_IBM_EMAC4_V4 CONFIG_ICACHE CONFIG_ICON CONFIG_ICS307_REFCLK_HZ -CONFIG_IDE_8xx_DIRECT -CONFIG_IDE_8xx_PCCARD CONFIG_IDE_INIT_POSTRESET CONFIG_IDE_LED CONFIG_IDE_PCMCIA @@ -1328,7 +1314,6 @@ CONFIG_IOMUX_LPSR CONFIG_IOMUX_SHARE_CONF_REG CONFIG_IOS CONFIG_IO_TRACE -CONFIG_IP86x CONFIG_IPADDR CONFIG_IPADDR1 CONFIG_IPADDR2 @@ -1351,7 +1336,6 @@ CONFIG_IS_ENABLED CONFIG_IS_INVALID CONFIG_IS_MODULE CONFIG_IS_VALID -CONFIG_IVMS8 CONFIG_JFFS2_CMDLINE CONFIG_JFFS2_DEV CONFIG_JFFS2_LZO @@ -1387,7 +1371,6 @@ CONFIG_KIRKWOOD_RGMII_PAD_1V8 CONFIG_KIRKWOOD_SPI CONFIG_KIRQ_EN CONFIG_KM8321 -CONFIG_KM8XX CONFIG_KMCOGE4 CONFIG_KMCOGE5NE CONFIG_KMETER1 @@ -1689,7 +1672,6 @@ CONFIG_MPC555 CONFIG_MPC5xxx_FEC CONFIG_MPC5xxx_FEC_MII10 CONFIG_MPC5xxx_FEC_MII100 -CONFIG_MPC823 CONFIG_MPC8247 CONFIG_MPC8255 CONFIG_MPC8272_FAMILY @@ -1722,22 +1704,15 @@ CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN CONFIG_MPC83XX_GPIO_1_INIT_VALUE CONFIG_MPC83XX_PCI2 -CONFIG_MPC850 -CONFIG_MPC855 -CONFIG_MPC857 CONFIG_MPC85XX_FEC CONFIG_MPC85XX_FEC_NAME CONFIG_MPC85XX_PCI2 CONFIG_MPC860 CONFIG_MPC860T -CONFIG_MPC862 CONFIG_MPC866 CONFIG_MPC866_FAMILY -CONFIG_MPC86x CONFIG_MPC885 -CONFIG_MPC885_FAMILY CONFIG_MPC8XXX_SPI -CONFIG_MPC8XX_LCD CONFIG_MPC8xxx_DISABLE_BPTR CONFIG_MPLL_FREQ CONFIG_MPR2 @@ -2282,7 +2257,6 @@ CONFIG_RTC_MC146818 CONFIG_RTC_MCFRRTC CONFIG_RTC_MCP79411 CONFIG_RTC_MPC5200 -CONFIG_RTC_MPC8xx CONFIG_RTC_MV CONFIG_RTC_MXS CONFIG_RTC_PCF8563 @@ -2730,9 +2704,6 @@ CONFIG_SYS_64BIT_VSPRINTF CONFIG_SYS_66MHZ CONFIG_SYS_8313ERDB_BROKEN_PMC CONFIG_SYS_83XX_DDR_USES_CS0 -CONFIG_SYS_8XX_XIN -CONFIG_SYS_8xx_CPUCLK_MAX -CONFIG_SYS_8xx_CPUCLK_MIN CONFIG_SYS_ACE_BASE CONFIG_SYS_ACE_BASE_PHYS_H CONFIG_SYS_ACE_BASE_PHYS_L @@ -2868,7 +2839,6 @@ CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR7_PRELIM CONFIG_SYS_BR8_PRELIM CONFIG_SYS_BR9_PRELIM -CONFIG_SYS_BRGCLK_PRESCALE CONFIG_SYS_BRIGHTNESS CONFIG_SYS_BUSCLK CONFIG_SYS_CACHELINE_SHIFT @@ -3329,7 +3299,6 @@ CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS CONFIG_SYS_DEFAULT_MBAR CONFIG_SYS_DEFAULT_VIDEO_MODE CONFIG_SYS_DEF_EEPROM_ADDR -CONFIG_SYS_DELAYED_ICACHE CONFIG_SYS_DER CONFIG_SYS_DEVICE_NULLDEV CONFIG_SYS_DFU_DATA_BUF_SIZE @@ -4122,7 +4091,6 @@ CONFIG_SYS_I2C_BUS_MAX CONFIG_SYS_I2C_CLK_OFFSET CONFIG_SYS_I2C_DAVINCI CONFIG_SYS_I2C_DIRECT_BUS -CONFIG_SYS_I2C_DPMEM_OFFSET CONFIG_SYS_I2C_DSPIC_2_ADDR CONFIG_SYS_I2C_DSPIC_ADDR CONFIG_SYS_I2C_DSPIC_IO_ADDR @@ -4285,7 +4253,6 @@ CONFIG_SYS_I2C_SPEED3 CONFIG_SYS_I2C_TCA642X_ADDR CONFIG_SYS_I2C_TCA642X_BUS_NUM CONFIG_SYS_I2C_TEGRA -CONFIG_SYS_I2C_UCODE_PATCH CONFIG_SYS_I2C_W83782G_ADDR CONFIG_SYS_I2C_ZYNQ CONFIG_SYS_I2C_ZYNQ_SLAVE @@ -4612,7 +4579,6 @@ CONFIG_SYS_MDIO_BASE_ADDR CONFIG_SYS_MDIO_PIN CONFIG_SYS_MDMRS_VAL CONFIG_SYS_MDREFR_VAL -CONFIG_SYS_MEASURE_CPUCLK CONFIG_SYS_MECR_VAL CONFIG_SYS_MEMAC_LITTLE_ENDIAN CONFIG_SYS_MEMORY_BASE @@ -5412,7 +5378,6 @@ CONFIG_SYS_POST_MEM_REGIONS CONFIG_SYS_POST_OCM CONFIG_SYS_POST_PREREL CONFIG_SYS_POST_RTC -CONFIG_SYS_POST_SPI CONFIG_SYS_POST_SPR CONFIG_SYS_POST_SYSMON CONFIG_SYS_POST_UART @@ -5434,7 +5399,6 @@ CONFIG_SYS_PSDMR CONFIG_SYS_PSDPAR CONFIG_SYS_PSRT CONFIG_SYS_PSSR_VAL -CONFIG_SYS_PTA_PER_CLK CONFIG_SYS_PTCPAR CONFIG_SYS_PTDPAR CONFIG_SYS_PTL2_BITS @@ -5493,12 +5457,10 @@ CONFIG_SYS_RIO_MEM_BUS CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_SIZE CONFIG_SYS_RIO_MEM_VIRT -CONFIG_SYS_RMDS CONFIG_SYS_RMR CONFIG_SYS_ROM_BASE CONFIG_SYS_ROOTPATH CONFIG_SYS_RSTC_RMR_VAL -CONFIG_SYS_RTCSC CONFIG_SYS_RTC_BUS_NUM CONFIG_SYS_RTC_CNT CONFIG_SYS_RTC_DS1337 @@ -5558,7 +5520,6 @@ CONFIG_SYS_SDIO_BASE0 CONFIG_SYS_SDIO_BASE1 CONFIG_SYS_SDIO_BASE2 CONFIG_SYS_SDIO_BASE3 -CONFIG_SYS_SDMR CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM0_CFG0 CONFIG_SYS_SDRAM0_CLKTR @@ -5673,7 +5634,6 @@ CONFIG_SYS_SDRC_MR_VAL5 CONFIG_SYS_SDRC_TR_VAL CONFIG_SYS_SDRC_TR_VAL1 CONFIG_SYS_SDRC_TR_VAL2 -CONFIG_SYS_SDSR CONFIG_SYS_SD_VOLTAGE CONFIG_SYS_SEC_MON_ADDR CONFIG_SYS_SEC_MON_OFFSET @@ -5712,14 +5672,10 @@ CONFIG_SYS_SMC0_MODE0_VAL CONFIG_SYS_SMC0_PULSE0_VAL CONFIG_SYS_SMC0_SETUP0_VAL CONFIG_SYS_SMC_CSR0_VAL -CONFIG_SYS_SMC_DPMEM_OFFSET CONFIG_SYS_SMC_RXBUFLEN -CONFIG_SYS_SMC_UCODE_PATCH CONFIG_SYS_SMI_BASE CONFIG_SYS_SPANSION_BASE CONFIG_SYS_SPANSION_BOOT -CONFIG_SYS_SPC1920_PLD_BASE -CONFIG_SYS_SPC1920_SMC1_CLK4 CONFIG_SYS_SPCR_OPT CONFIG_SYS_SPCR_TSEC1EP CONFIG_SYS_SPCR_TSEC2EP @@ -5741,7 +5697,6 @@ CONFIG_SYS_SPI_CLK CONFIG_SYS_SPI_CS_ACT CONFIG_SYS_SPI_CS_BASE CONFIG_SYS_SPI_CS_USED -CONFIG_SYS_SPI_DPMEM_OFFSET CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE @@ -5751,7 +5706,6 @@ CONFIG_SYS_SPI_KERNEL_OFFS CONFIG_SYS_SPI_MXC_WAIT CONFIG_SYS_SPI_RTC_DEVID CONFIG_SYS_SPI_ST_ENABLE_WP_PIN -CONFIG_SYS_SPI_UCODE_PATCH CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_SPI_WRITE_TOUT @@ -6052,10 +6006,6 @@ CONFIG_TQM860L CONFIG_TQM860M CONFIG_TQM862L CONFIG_TQM862M -CONFIG_TQM866M -CONFIG_TQM885D -CONFIG_TQM8xxL -CONFIG_TQM8xxM CONFIG_TRACE CONFIG_TRACE_BUFFER_SIZE CONFIG_TRACE_EARLY

There was for long time no activity in the 8260 area. We need to go further and convert to Kconfig, but it turned out, nobody is interested anymore in 8260, so remove it.

Signed-off-by: Heiko Schocher hs@denx.de

---

.travis.yml | 2 - README | 73 +- api/api_platform-powerpc.c | 2 +- arch/powerpc/Kconfig | 6 - arch/powerpc/cpu/mpc8260/Kconfig | 20 - arch/powerpc/cpu/mpc8260/Makefile | 13 - arch/powerpc/cpu/mpc8260/bedbug_603e.c | 236 ------ arch/powerpc/cpu/mpc8260/commproc.c | 174 ----- arch/powerpc/cpu/mpc8260/config.mk | 9 - arch/powerpc/cpu/mpc8260/cpu.c | 323 -------- arch/powerpc/cpu/mpc8260/cpu_init.c | 272 ------- arch/powerpc/cpu/mpc8260/ether_fcc.c | 1155 ---------------------------- arch/powerpc/cpu/mpc8260/ether_scc.c | 367 --------- arch/powerpc/cpu/mpc8260/interrupts.c | 255 ------ arch/powerpc/cpu/mpc8260/kgdb.S | 52 -- arch/powerpc/cpu/mpc8260/pci.c | 382 --------- arch/powerpc/cpu/mpc8260/serial_scc.c | 492 ------------ arch/powerpc/cpu/mpc8260/serial_smc.c | 461 ----------- arch/powerpc/cpu/mpc8260/speed.c | 228 ------ arch/powerpc/cpu/mpc8260/spi.c | 408 ---------- arch/powerpc/cpu/mpc8260/start.S | 901 ---------------------- arch/powerpc/cpu/mpc8260/traps.c | 248 ------ arch/powerpc/cpu/mpc8260/u-boot.lds | 74 -- arch/powerpc/cpu/mpc83xx/start.S | 2 +- arch/powerpc/include/asm/cpm_8260.h | 795 ------------------- arch/powerpc/include/asm/immap_8260.h | 604 --------------- arch/powerpc/include/asm/iopin_8260.h | 168 ---- arch/powerpc/include/asm/m8260_pci.h | 165 ---- arch/powerpc/include/asm/ppc.h | 5 - arch/powerpc/include/asm/processor.h | 3 - arch/powerpc/include/asm/status_led.h | 4 +- arch/powerpc/lib/Kconfig | 8 - arch/powerpc/lib/Makefile | 1 - arch/powerpc/lib/immap.c | 629 --------------- arch/powerpc/lib/kgdb.c | 52 -- board/keymile/km82xx/Kconfig | 12 - board/keymile/km82xx/MAINTAINERS | 7 - board/keymile/km82xx/Makefile | 8 - board/keymile/km82xx/km82xx.c | 463 ----------- cmd/bdinfo.c | 2 +- cmd/bedbug.c | 7 - common/board_f.c | 2 +- common/lynxkdi.c | 2 +- configs/mgcoge3ne_defconfig | 25 - configs/mgcoge_defconfig | 25 - doc/README.idma2intr | 10 - drivers/bootcount/bootcount.c | 5 - drivers/i2c/soft_i2c.c | 9 - drivers/pci/pci_indirect.c | 17 +- drivers/usb/gadget/gadget_chips.h | 9 - examples/standalone/Makefile | 1 - examples/standalone/mem_to_mem_idma2intr.c | 379 --------- include/asm-generic/u-boot.h | 2 +- include/configs/km82xx.h | 427 ---------- include/i2c.h | 4 +- include/mpc8260.h | 903 ---------------------- include/mpc8260_irq.h | 48 -- include/post.h | 4 - include/ppc_asm.tmpl | 26 +- post/drivers/memory.c | 7 - scripts/config_whitelist.txt | 75 -- 61 files changed, 17 insertions(+), 11051 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc8260/Kconfig delete mode 100644 arch/powerpc/cpu/mpc8260/Makefile delete mode 100644 arch/powerpc/cpu/mpc8260/bedbug_603e.c delete mode 100644 arch/powerpc/cpu/mpc8260/commproc.c delete mode 100644 arch/powerpc/cpu/mpc8260/config.mk delete mode 100644 arch/powerpc/cpu/mpc8260/cpu.c delete mode 100644 arch/powerpc/cpu/mpc8260/cpu_init.c delete mode 100644 arch/powerpc/cpu/mpc8260/ether_fcc.c delete mode 100644 arch/powerpc/cpu/mpc8260/ether_scc.c delete mode 100644 arch/powerpc/cpu/mpc8260/interrupts.c delete mode 100644 arch/powerpc/cpu/mpc8260/kgdb.S delete mode 100644 arch/powerpc/cpu/mpc8260/pci.c delete mode 100644 arch/powerpc/cpu/mpc8260/serial_scc.c delete mode 100644 arch/powerpc/cpu/mpc8260/serial_smc.c delete mode 100644 arch/powerpc/cpu/mpc8260/speed.c delete mode 100644 arch/powerpc/cpu/mpc8260/spi.c delete mode 100644 arch/powerpc/cpu/mpc8260/start.S delete mode 100644 arch/powerpc/cpu/mpc8260/traps.c delete mode 100644 arch/powerpc/cpu/mpc8260/u-boot.lds delete mode 100644 arch/powerpc/include/asm/cpm_8260.h delete mode 100644 arch/powerpc/include/asm/immap_8260.h delete mode 100644 arch/powerpc/include/asm/iopin_8260.h delete mode 100644 arch/powerpc/include/asm/m8260_pci.h delete mode 100644 arch/powerpc/lib/Kconfig delete mode 100644 arch/powerpc/lib/immap.c delete mode 100644 board/keymile/km82xx/Kconfig delete mode 100644 board/keymile/km82xx/MAINTAINERS delete mode 100644 board/keymile/km82xx/Makefile delete mode 100644 board/keymile/km82xx/km82xx.c delete mode 100644 configs/mgcoge3ne_defconfig delete mode 100644 configs/mgcoge_defconfig delete mode 100644 doc/README.idma2intr delete mode 100644 examples/standalone/mem_to_mem_idma2intr.c delete mode 100644 include/configs/km82xx.h delete mode 100644 include/mpc8260.h delete mode 100644 include/mpc8260_irq.h

diff --git a/.travis.yml b/.travis.yml index 8915284..3105a6f 100644 --- a/.travis.yml +++ b/.travis.yml @@ -200,8 +200,6 @@ matrix: - env: - BUILDMAN="mpc5xxx" - env: - - BUILDMAN="mpc8260" - - env: - BUILDMAN="mpc83xx" - env: - BUILDMAN="mpc85xx -x freescale" diff --git a/README b/README index 6355c79..6f2c0a2 100644 --- a/README +++ b/README @@ -700,14 +700,6 @@ The following options need to be configured: Select one of the baudrates listed in CONFIG_SYS_BAUDRATE_TABLE, see below.

-- Console Rx buffer length - With CONFIG_SYS_SMC_RXBUFLEN it is possible to define - the maximum receive buffer length for the SMC. - This option is actual only for 82xx possible. - If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE - must be defined, to setup the maximum idle timeout for - the SMC. - - Autoboot Command: CONFIG_BOOTCOMMAND Only needed when CONFIG_BOOTDELAY is enabled; @@ -937,11 +929,9 @@ The following options need to be configured: CONFIG_WATCHDOG If this variable is defined, it enables watchdog support for the SoC. There must be support in the SoC - specific code for a watchdog. For the 8260 - CPUs, the SIU Watchdog feature is enabled in the SYPCR - register. When supported for a specific SoC is - available, then no further board specific code should - be needed to use it. + specific code for a watchdog. When supported for a + specific SoC is available, then no further board specific + code should be needed to use it.

CONFIG_HW_WATCHDOG When using a watchdog circuitry external to the used @@ -2108,12 +2098,6 @@ The following options need to be configured:

eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)

- I2C_PORT - - (Only for MPC8260 CPU). The I/O port to use (the code - assumes both bits are on the same port). Valid values - are 0..3 for ports A..D. - I2C_ACTIVE

The code necessary to make the I2C data line active @@ -2402,7 +2386,7 @@ The following options need to be configured:

IVMS8, IVML24, SPD8xx, HERMES, IP860, RPXlite, LWMON, - FLAGADM, TQM8260 + FLAGADM

- Access to physical memory region (> 4GB) Some basic support is provided for operations on memory not @@ -3860,16 +3844,6 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface. set. If this value is set, it must be set to the same value as CONFIG_ENV_SIZE.

-- CONFIG_SYS_SPI_INIT_OFFSET - - Defines offset to the initial SPI buffer area in DPRAM. The - area is used at an early stage (ROM part) if the environment - is configured to reside in the SPI EEPROM: We need a 520 byte - scratch DPRAM area. It is used between the two initialization - calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems - to be a good choice since it makes it far enough from the - start of the data area as well as from the stack pointer. - Please note that the environment is read-only until the monitor has been relocated to RAM and a RAM copy of the environment has been created; also, when using EEPROM you will have to use getenv_f() @@ -3923,13 +3897,6 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_CACHELINE_SIZE: Cache Line Size of the CPU.

-- CONFIG_SYS_DEFAULT_IMMR: - Default address of the IMMR after system reset. - - Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU, - and RPXsuper) to be able to adjust the position of - the IMMR register after a reset. - - CONFIG_SYS_CCSRBAR_DEFAULT: Default (power-on reset) physical address of CCSR on Freescale PowerPC SOCs. @@ -3938,9 +3905,6 @@ Low Level (hardware related) configuration options: Virtual address of CCSR. On a 32-bit build, this is typically the same value as CONFIG_SYS_CCSRBAR_DEFAULT.

- CONFIG_SYS_DEFAULT_IMMR must also be set to this value, - for cross-platform code that uses that macro instead. - - CONFIG_SYS_CCSRBAR_PHYS: Physical address of CCSR. CCSR can be relocated to a new physical address, if desired. In this case, this macro should @@ -4016,8 +3980,6 @@ Low Level (hardware related) configuration options: sequences.

U-Boot uses the following memory types: - - MPC8260: IMMR (internal memory of the CPU) - - MPC824X: data cache - PPC4xx: data cache

- CONFIG_SYS_GBL_DATA_OFFSET: @@ -4069,27 +4031,6 @@ Low Level (hardware related) configuration options: CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM: Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)

-- CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K, - CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL: - Machine Mode Register and Memory Periodic Timer - Prescaler definitions (SDRAM timing) - -- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8260 only) - Offset of the bootmode word in DPRAM used by post - (Power On Self Tests). This definition overrides - #define'd default value in commproc.h resp. - cpm_8260.h. - -- CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB, - CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL, - CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS, - CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB, - CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START, - CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL, - CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE, - CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only) - Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set. - - CONFIG_PCI_DISABLE_PCIE: Disable PCI-Express on systems where it is supported but not required. @@ -5710,9 +5651,9 @@ configuration for CS0# this is a mirror of the on board Flash memory. To be able to re-map memory U-Boot then jumps to its link address. To be able to implement the initialization code in C, a (small!) initial stack is set up in the internal Dual Ported RAM (in case CPUs -which provide such a feature like MPC8xx or MPC8260), or in a locked -part of the data cache. After that, U-Boot initializes the CPU core, -the caches and the SIU. +which provide such a feature like), or in a locked part of the data +cache. After that, U-Boot initializes the CPU core, the caches and +the SIU.

Next, all (potentially) available memory banks are mapped using a preliminary mapping. For example, we put them on 512 MB boundaries diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c index 71fea5a..307a5f5 100644 --- a/api/api_platform-powerpc.c +++ b/api/api_platform-powerpc.c @@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si) si->clk_bus = gd->bus_clk; si->clk_cpu = gd->cpu_clk;

-#if defined(CONFIG_5xx) || defined(CONFIG_MPC8260) || \ +#if defined(CONFIG_5xx) || \ defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define bi_bar bi_immr_base #elif defined(CONFIG_MPC5xxx) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 671d2cc..75594c6 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -17,9 +17,6 @@ config 5xx config MPC5xxx bool "MPC5xxx"

-config MPC8260 - bool "MPC8260" - config MPC83xx bool "MPC83xx" select CREATE_ARCH_SYMLINK @@ -48,12 +45,9 @@ config 4xx

endchoice

-source "arch/powerpc/lib/Kconfig" - source "arch/powerpc/cpu/mpc512x/Kconfig" source "arch/powerpc/cpu/mpc5xx/Kconfig" source "arch/powerpc/cpu/mpc5xxx/Kconfig" -source "arch/powerpc/cpu/mpc8260/Kconfig" source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc86xx/Kconfig" diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig deleted file mode 100644 index 47bae55..0000000 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ /dev/null @@ -1,20 +0,0 @@ -menu "mpc8260 CPU" - depends on MPC8260 - -config SYS_CPU - default "mpc8260" - -choice - prompt "Target select" - optional - -config TARGET_KM82XX - bool "Support km82xx" - imply CMD_CRAMFS - imply FS_CRAMFS - -endchoice - -source "board/keymile/km82xx/Kconfig" - -endmenu diff --git a/arch/powerpc/cpu/mpc8260/Makefile b/arch/powerpc/cpu/mpc8260/Makefile deleted file mode 100644 index 72dd8ab..0000000 --- a/arch/powerpc/cpu/mpc8260/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -obj-y = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ - interrupts.o ether_fcc.o commproc.o \ - bedbug_603e.o pci.o spi.o kgdb.o - -obj-$(CONFIG_ETHER_ON_SCC) += ether_scc.o diff --git a/arch/powerpc/cpu/mpc8260/bedbug_603e.c b/arch/powerpc/cpu/mpc8260/bedbug_603e.c deleted file mode 100644 index 92f8957..0000000 --- a/arch/powerpc/cpu/mpc8260/bedbug_603e.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Bedbug Functions specific to the MPC603e core - */ - -#include <common.h> -#include <command.h> -#include <linux/ctype.h> -#include <bedbug/type.h> -#include <bedbug/bedbug.h> -#include <bedbug/regs.h> -#include <bedbug/ppc.h> - -#if defined(CONFIG_CMD_BEDBUG) \ - && (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260)) - -#define MAX_BREAK_POINTS 1 - -extern CPU_DEBUG_CTX bug_ctx; - -void bedbug603e_init __P((void)); -void bedbug603e_do_break __P((cmd_tbl_t*,int,int,char*const[])); -void bedbug603e_break_isr __P((struct pt_regs*)); -int bedbug603e_find_empty __P((void)); -int bedbug603e_set __P((int,unsigned long)); -int bedbug603e_clear __P((int)); - - -/* ====================================================================== - * Initialize the global bug_ctx structure for the processor. Clear all - * of the breakpoints. - * ====================================================================== */ - -void bedbug603e_init( void ) -{ - int i; - /* -------------------------------------------------- */ - - bug_ctx.hw_debug_enabled = 0; - bug_ctx.stopped = 0; - bug_ctx.current_bp = 0; - bug_ctx.regs = NULL; - - bug_ctx.do_break = bedbug603e_do_break; - bug_ctx.break_isr = bedbug603e_break_isr; - bug_ctx.find_empty = bedbug603e_find_empty; - bug_ctx.set = bedbug603e_set; - bug_ctx.clear = bedbug603e_clear; - - for( i = 1; i <= MAX_BREAK_POINTS; ++i ) - (*bug_ctx.clear)( i ); - - puts ("BEDBUG:ready\n"); - return; -} /* bedbug_init_breakpoints */ - - - -/* ====================================================================== - * Set/clear/show the hardware breakpoint for the 603e. The "off" - * string will disable a specific breakpoint. The "show" string will - * display the current breakpoints. Otherwise an address will set a - * breakpoint at that address. Setting a breakpoint uses the CPU-specific - * set routine which will assign a breakpoint number. - * ====================================================================== */ - -void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - long addr; /* Address to break at */ - int which_bp; /* Breakpoint number */ - /* -------------------------------------------------- */ - - if (argc < 2) { - cmd_usage(cmdtp); - return; - } - - /* Turn off a breakpoint */ - - if( strcmp( argv[ 1 ], "off" ) == 0 ) - { - if( bug_ctx.hw_debug_enabled == 0 ) - { - puts ( "No breakpoints enabled\n" ); - return; - } - - which_bp = simple_strtoul( argv[ 2 ], NULL, 10 ); - - if( bug_ctx.clear ) - (*bug_ctx.clear)( which_bp ); - - printf( "Breakpoint %d removed\n", which_bp ); - return; - } - - /* Show a list of breakpoints */ - - if( strcmp( argv[ 1 ], "show" ) == 0 ) - { - for( which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp ) - { - - addr = GET_IABR(); - - printf( "Breakpoint [%d]: ", which_bp ); - if( (addr & 0x00000002) == 0 ) - puts ( "NOT SET\n" ); - else - disppc( (unsigned char *)(addr & 0xFFFFFFFC), 0, 1, bedbug_puts, F_RADHEX ); - } - return; - } - - /* Set a breakpoint at the address */ - - if(!(( isdigit( argv[ 1 ][ 0 ] )) || - (( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) || - (( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' )))) { - cmd_usage(cmdtp); - return; - } - - addr = simple_strtoul( argv[ 1 ], NULL, 16 ); - - if(( bug_ctx.set ) && ( which_bp = (*bug_ctx.set)( 0, addr )) > 0 ) - { - printf( "Breakpoint [%d]: ", which_bp ); - disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); - } - - return; -} /* bedbug603e_do_break */ - - - -/* ====================================================================== - * Handle a breakpoint. Enter a mini main loop. Stay in the loop until - * the stopped flag in the debug context is cleared. - * ====================================================================== */ - -void bedbug603e_break_isr( struct pt_regs *regs ) -{ - unsigned long addr; /* Address stopped at */ - /* -------------------------------------------------- */ - - bug_ctx.current_bp = 1; - addr = GET_IABR() & 0xFFFFFFFC; - - bedbug_main_loop( addr, regs ); - return; -} /* bedbug603e_break_isr */ - - - -/* ====================================================================== - * See if the hardware breakpoint is available. - * ====================================================================== */ - -int bedbug603e_find_empty( void ) -{ - /* -------------------------------------------------- */ - - if( (GET_IABR() && 0x00000002) == 0 ) - return 1; - - return 0; -} /* bedbug603e_find_empty */ - - - -/* ====================================================================== - * Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint - * number, otherwise reassign the given breakpoint. If hardware debugging - * is not enabled, then turn it on via the MSR and DBCR0. Set the break - * address in the IABR register. - * ====================================================================== */ - -int bedbug603e_set( int which_bp, unsigned long addr ) -{ - /* -------------------------------------------------- */ - - if(( addr & 0x00000003 ) != 0 ) - { - puts ( "Breakpoints must be on a 32 bit boundary\n" ); - return 0; - } - - /* Only look if which_bp == 0, else use which_bp */ - if(( bug_ctx.find_empty ) && ( !which_bp ) && - ( which_bp = (*bug_ctx.find_empty)()) == 0 ) - { - puts ( "All breakpoints in use\n" ); - return 0; - } - - if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) - { - printf( "Invalid break point # %d\n", which_bp ); - return 0; - } - - if( ! bug_ctx.hw_debug_enabled ) - { - bug_ctx.hw_debug_enabled = 1; - } - - SET_IABR( addr | 0x00000002 ); - - return which_bp; -} /* bedbug603e_set */ - - - -/* ====================================================================== - * Disable a specific breakoint by setting the IABR register to zero. - * ====================================================================== */ - -int bedbug603e_clear( int which_bp ) -{ - /* -------------------------------------------------- */ - - if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) - { - printf( "Invalid break point # (%d)\n", which_bp ); - return -1; - } - - SET_IABR( 0 ); - - return 0; -} /* bedbug603e_clear */ - - -/* ====================================================================== */ -#endif diff --git a/arch/powerpc/cpu/mpc8260/commproc.c b/arch/powerpc/cpu/mpc8260/commproc.c deleted file mode 100644 index ff69881..0000000 --- a/arch/powerpc/cpu/mpc8260/commproc.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's - * copyright notice: - * - * General Purpose functions for the global management of the - * 8260 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) - * 2.3.99 Updates - * - * In addition to the individual control of the communication - * channels, there are a few functions that globally affect the - * communication processor. - * - * Buffer descriptors must be allocated from the dual ported memory - * space. The allocator for that is here. When the communication - * process is reset, we reclaim the memory available. There is - * currently no deallocator for this memory. - */ -#include <common.h> -#include <asm/cpm_8260.h> - -DECLARE_GLOBAL_DATA_PTR; - -void -m8260_cpm_reset(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile ulong count; - - /* Reclaim the DP memory for our use. - */ - gd->arch.dp_alloc_base = CPM_DATAONLY_BASE; - gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE; - - /* - * Reset CPM - */ - immr->im_cpm.cp_cpcr = CPM_CR_RST; - count = 0; - do { /* Spin until command processed */ - __asm__ __volatile__ ("eieio"); - } while ((immr->im_cpm.cp_cpcr & CPM_CR_FLG) && ++count < 1000000); -} - -/* Allocate some memory from the dual ported ram. - * To help protocols with object alignment restrictions, we do that - * if they ask. - */ -uint -m8260_cpm_dpalloc(uint size, uint align) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint retloc; - uint align_mask, off; - uint savebase; - - align_mask = align - 1; - savebase = gd->arch.dp_alloc_base; - - off = gd->arch.dp_alloc_base & align_mask; - if (off != 0) - gd->arch.dp_alloc_base += (align - off); - - if ((off = size & align_mask) != 0) - size += align - off; - - if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) { - gd->arch.dp_alloc_base = savebase; - panic("m8260_cpm_dpalloc: ran out of dual port ram!"); - } - - retloc = gd->arch.dp_alloc_base; - gd->arch.dp_alloc_base += size; - - memset((void *)&immr->im_dprambase[retloc], 0, size); - - return(retloc); -} - -/* We also own one page of host buffer space for the allocation of - * UART "fifos" and the like. - */ -uint -m8260_cpm_hostalloc(uint size, uint align) -{ - /* the host might not even have RAM yet - just use dual port RAM */ - return (m8260_cpm_dpalloc(size, align)); -} - -/* Set a baud rate generator. This needs lots of work. There are - * eight BRGs, which can be connected to the CPM channels or output - * as clocks. The BRGs are in two different block of internal - * memory mapped space. - * The baud rate clock is the system clock divided by something. - * It was set up long ago during the initial boot phase and is - * is given to us. - * Baud rate clocks are zero-based in the driver code (as that maps - * to port numbers). Documentation uses 1-based numbering. - */ -#define BRG_INT_CLK gd->arch.brg_clk -#define BRG_UART_CLK (BRG_INT_CLK / 16) - -/* This function is used by UARTs, or anything else that uses a 16x - * oversampled clock. - */ -void -m8260_cpm_setbrg(uint brg, uint rate) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile uint *bp; - uint cd = BRG_UART_CLK / rate; - - if ((BRG_UART_CLK % rate) < (rate / 2)) - cd--; - if (brg < 4) { - bp = (uint *)&immr->im_brgc1; - } - else { - bp = (uint *)&immr->im_brgc5; - brg -= 4; - } - bp += brg; - *bp = (cd << 1) | CPM_BRG_EN; -} - -/* This function is used to set high speed synchronous baud rate - * clocks. - */ -void -m8260_cpm_fastbrg(uint brg, uint rate, int div16) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile uint *bp; - - /* This is good enough to get SMCs running..... - */ - if (brg < 4) { - bp = (uint *)&immr->im_brgc1; - } - else { - bp = (uint *)&immr->im_brgc5; - brg -= 4; - } - bp += brg; - *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; - if (div16) - *bp |= CPM_BRG_DIV16; -} - -/* This function is used to set baud rate generators using an external - * clock source and 16x oversampling. - */ - -void -m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile uint *bp; - - if (brg < 4) { - bp = (uint *)&immr->im_brgc1; - } - else { - bp = (uint *)&immr->im_brgc5; - brg -= 4; - } - bp += brg; - *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; - if (pinsel == 0) - *bp |= CPM_BRG_EXTC_CLK3_9; - else - *bp |= CPM_BRG_EXTC_CLK5_15; -} diff --git a/arch/powerpc/cpu/mpc8260/config.mk b/arch/powerpc/cpu/mpc8260/config.mk deleted file mode 100644 index 6a1b6e3..0000000 --- a/arch/powerpc/cpu/mpc8260/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_CPM2 \ - -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc8260/cpu.c b/arch/powerpc/cpu/mpc8260/cpu.c deleted file mode 100644 index 7302b37..0000000 --- a/arch/powerpc/cpu/mpc8260/cpu.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x - * - * written or collected and sometimes rewritten by - * Magnus Damm damm@bitsmart.com - * - * modified by - * Wolfgang Denk wd@denx.de - * - * modified for 8260 by - * Murray Jensen Murray.Jensen@cmst.csiro.au - * - * added 8260 masks by - * Marius Groeger mag@sysgo.de - * - * added HiP7 (824x/827x/8280) processors support by - * Yuli Barcohen yuli@arabellasw.com - */ - -#include <common.h> -#include <watchdog.h> -#include <command.h> -#include <mpc8260.h> -#include <netdev.h> -#include <asm/processor.h> -#include <asm/cpm_8260.h> - -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_GET_CPU_STR_F) -extern int get_cpu_str_f (char *buf); -#endif - -int checkcpu (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - ulong clock = gd->cpu_clk; - uint pvr = get_pvr (); - uint immr, rev, m, k; - char buf[32]; - int ret; - - ret = prt_8260_rsr(); - if (ret) - return ret; - ret = prt_8260_clks(); - if (ret) - return ret; - puts ("CPU: "); - - switch (pvr) { - case PVR_8260: - case PVR_8260_HIP3: - k = 3; - break; - case PVR_8260_HIP4: - k = 4; - break; - case PVR_8260_HIP7R1: - case PVR_8260_HIP7RA: - case PVR_8260_HIP7: - k = 7; - break; - default: - return -1; /* whoops! not an MPC8260 */ - } - rev = pvr & 0xff; - - immr = immap->im_memctl.memc_immr; - if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR) - return -1; /* whoops! someone moved the IMMR */ - -#if defined(CONFIG_GET_CPU_STR_F) - get_cpu_str_f (buf); - printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev); -#else - printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev); -#endif - - /* - * the bottom 16 bits of the immr are the Part Number and Mask Number - * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the - * RISC Microcode Revision Number (13-10). - * For the 8260, Motorola doesn't include the Microcode Revision - * in the mask. - */ - m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK); - k = immap->im_dprambase16[PROFF_REVNUM / sizeof(u16)]; - - switch (m) { - case 0x0000: - puts ("0.2 2J24M"); - break; - case 0x0010: - puts ("A.0 K22A"); - break; - case 0x0011: - puts ("A.1 1K22A-XC"); - break; - case 0x0001: - puts ("B.1 1K23A"); - break; - case 0x0021: - puts ("B.2 2K23A-XC"); - break; - case 0x0023: - puts ("B.3 3K23A"); - break; - case 0x0024: - puts ("C.2 6K23A"); - break; - case 0x0060: - puts ("A.0(A) 2K25A"); - break; - case 0x0062: - puts ("B.1 4K25A"); - break; - case 0x0064: - puts ("C.0 5K25A"); - break; - case 0x0A00: - puts ("0.0 0K49M"); - break; - case 0x0A01: - puts ("0.1 1K49M"); - break; - case 0x0A10: - puts ("1.0 1K49M"); - break; - case 0x0C00: - puts ("0.0 0K50M"); - break; - case 0x0C10: - puts ("1.0 1K50M"); - break; - case 0x0D00: - puts ("0.0 0K50M"); - break; - case 0x0D10: - puts ("1.0 1K50M"); - break; - default: - printf ("unknown [immr=0x%04x,k=0x%04x]", m, k); - break; - } - - printf (") at %s MHz\n", strmhz (buf, clock)); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -/* configures a UPM by writing into the UPM RAM array */ -/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */ -/* NOTE: the physical address chosen must not overlap into any other area */ -/* mapped by the memory controller because bank 11 has the lowest priority */ - -void upmconfig (uint upm, uint * table, uint size) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */ - uint i; - - /* first set up bank 11 to reference the correct UPM at a dummy address */ - - memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */ - - switch (upm) { - - case UPMA: - memctl->memc_br11 = - ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA | - BRx_V; - memctl->memc_mamr = MxMR_OP_WARR; - break; - - case UPMB: - memctl->memc_br11 = - ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB | - BRx_V; - memctl->memc_mbmr = MxMR_OP_WARR; - break; - - case UPMC: - memctl->memc_br11 = - ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC | - BRx_V; - memctl->memc_mcmr = MxMR_OP_WARR; - break; - - default: - panic ("upmconfig passed invalid UPM number (%u)\n", upm); - break; - - } - - /* - * at this point, the dummy address is set up to access the selected UPM, - * the MAD pointer is zero, and the MxMR OP is set for writing to RAM - * - * now we simply load the mdr with each word and poke the dummy address. - * the MAD is incremented on each access. - */ - - for (i = 0; i < size; i++) { - memctl->memc_mdr = table[i]; - *dummy = 0; - } - - /* now kill bank 11 */ - memctl->memc_br11 = 0; -} - -/* ------------------------------------------------------------------------- */ - -#if !defined(CONFIG_HAVE_OWN_RESET) -int -do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong msr, addr; - - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */ - - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE - * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. - */ - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*)(void)) addr) (); - return 1; - -} -#endif /* CONFIG_HAVE_OWN_RESET */ - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * - */ -unsigned long get_tbclk (void) -{ - ulong tbclk; - - tbclk = (gd->bus_clk + 3L) / 4L; - - return (tbclk); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) -{ - int re_enable = disable_interrupts (); - - reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR); - if (re_enable) - enable_interrupts (); -} -#endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ -#ifdef CONFIG_OF_BOARD_SETUP -void ft_cpu_setup (void *blob, bd_t *bd) -{ - do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", - "clock-frequency", bd->bi_brgfreq, 1); - - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", OF_TBCLK, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(bd_t *bis) -{ -#if defined(CONFIG_ETHER_ON_FCC) - fec_initialize(bis); -#endif -#if defined(CONFIG_ETHER_ON_SCC) - mpc82xx_scc_enet_initialize(bis); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/mpc8260/cpu_init.c b/arch/powerpc/cpu/mpc8260/cpu_init.c deleted file mode 100644 index 55130f7..0000000 --- a/arch/powerpc/cpu/mpc8260/cpu_init.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8260.h> -#include <asm/cpm_8260.h> -#include <ioports.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -extern unsigned long board_get_cpu_clk_f (void); -#endif - -static void config_8260_ioports (volatile immap_t * immr) -{ - int portnum; - - for (portnum = 0; portnum < 4; portnum++) { - uint pmsk = 0, - ppar = 0, - psor = 0, - pdir = 0, - podr = 0, - pdat = 0; - iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; - iop_conf_t *eiopc = iopc + 32; - uint msk = 1; - - /* - * NOTE: - * index 0 refers to pin 31, - * index 31 refers to pin 0 - */ - while (iopc < eiopc) { - if (iopc->conf) { - pmsk |= msk; - if (iopc->ppar) - ppar |= msk; - if (iopc->psor) - psor |= msk; - if (iopc->pdir) - pdir |= msk; - if (iopc->podr) - podr |= msk; - if (iopc->pdat) - pdat |= msk; - } - - msk <<= 1; - iopc++; - } - - if (pmsk != 0) { - volatile ioport_t *iop = ioport_addr (immr, portnum); - uint tpmsk = ~pmsk; - - /* - * the (somewhat confused) paragraph at the - * bottom of page 35-5 warns that there might - * be "unknown behaviour" when programming - * PSORx and PDIRx, if PPARx = 1, so I - * decided this meant I had to disable the - * dedicated function first, and enable it - * last. - */ - iop->ppar &= tpmsk; - iop->psor = (iop->psor & tpmsk) | psor; - iop->podr = (iop->podr & tpmsk) | podr; - iop->pdat = (iop->pdat & tpmsk) | pdat; - iop->pdir = (iop->pdir & tpmsk) | pdir; - iop->ppar |= ppar; - } - } -} - -#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask)) -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f (volatile immap_t * immr) -{ - uint sccr; -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) - unsigned long cpu_clk; -#endif - volatile memctl8260_t *memctl = &immr->im_memctl; - extern void m8260_cpm_reset (void); - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - /* RSR - Reset Status Register - clear all status (5-4) */ - gd->arch.reset_status = immr->im_clkrst.car_rsr; - immr->im_clkrst.car_rsr = RSR_ALLBITS; - - /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */ - immr->im_clkrst.car_rmr = CONFIG_SYS_RMR; - - /* BCR - Bus Configuration Register (4-25) */ -#if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE) - if (immr->im_siu_conf.sc_bcr & BCR_EBM) { - immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010); - } else { - immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010); - } -#else - immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR; -#endif - - /* SIUMCR - contains debug pin configuration (4-31) */ -#if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH) - cpu_clk = board_get_cpu_clk_f (); - if (cpu_clk >= 100000000) { - immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000); - } else { - immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000); - } -#else - immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR; -#endif - - config_8260_ioports (immr); - - /* initialize time counter status and control register (4-40) */ - immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC; - - /* initialize the PIT (4-42) */ - immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; - - /* System clock control register (9-8) */ - sccr = immr->im_clkrst.car_sccr & - (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK); - immr->im_clkrst.car_sccr = sccr | - (CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) ); - - /* - * Memory Controller: - */ - - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ - -#if defined(CONFIG_SYS_OR0_REMAP) - memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; -#endif -#if defined(CONFIG_SYS_OR1_REMAP) - memctl->memc_or1 = CONFIG_SYS_OR1_REMAP; -#endif - - /* now restrict to preliminary range */ - /* the PS came from the HRCW, don't change it */ - memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CONFIG_SYS_BR0_PRELIM, BRx_PS_MSK); - memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; - -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) - memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; - memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) - memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM; - memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) - memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM; - memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR8_PRELIM) && defined(CONFIG_SYS_OR8_PRELIM) - memctl->memc_or8 = CONFIG_SYS_OR8_PRELIM; - memctl->memc_br8 = CONFIG_SYS_BR8_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR9_PRELIM) && defined(CONFIG_SYS_OR9_PRELIM) - memctl->memc_or9 = CONFIG_SYS_OR9_PRELIM; - memctl->memc_br9 = CONFIG_SYS_BR9_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR10_PRELIM) && defined(CONFIG_SYS_OR10_PRELIM) - memctl->memc_or10 = CONFIG_SYS_OR10_PRELIM; - memctl->memc_br10 = CONFIG_SYS_BR10_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR11_PRELIM) && defined(CONFIG_SYS_OR11_PRELIM) - memctl->memc_or11 = CONFIG_SYS_OR11_PRELIM; - memctl->memc_br11 = CONFIG_SYS_BR11_PRELIM; -#endif - - m8260_cpm_reset (); -} - -/* - * initialize higher level parts of CPU like time base and timers - */ -int cpu_init_r (void) -{ - volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base; - - immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; - - return (0); -} - -/* - * print out the reason for the reset - */ -int prt_8260_rsr (void) -{ - static struct { - ulong mask; - char *desc; - } bits[] = { - { - RSR_JTRS, "JTAG"}, { - RSR_CSRS, "Check Stop"}, { - RSR_SWRS, "Software Watchdog"}, { - RSR_BMRS, "Bus Monitor"}, { - RSR_ESRS, "External Soft"}, { - RSR_EHRS, "External Hard"} - }; - static int n = ARRAY_SIZE(bits); - ulong rsr = gd->arch.reset_status; - int i; - char *sep; - - puts (CPU_ID_STR " Reset Status:"); - - sep = " "; - for (i = 0; i < n; i++) - if (rsr & bits[i].mask) { - printf ("%s%s", sep, bits[i].desc); - sep = ", "; - } - - puts ("\n\n"); - return (0); -} diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c deleted file mode 100644 index 072eb76..0000000 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ /dev/null @@ -1,1155 +0,0 @@ -/* - * MPC8260 FCC Fast Ethernet - * - * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8260 FCC Fast Ethernet - * Basic ET HW initialization and packet RX/TX routines - * - * This code will not perform the IO port configuration. This should be - * done in the iop_conf_t structure specific for the board. - * - * TODO: - * add a PHY driver to do the negotiation - * reflect negotiation results in FPSMR - * look for ways to configure the board specific stuff elsewhere, eg. - * config_xxx.h or the board directory - */ - -#include <common.h> -#include <console.h> -#include <malloc.h> -#include <asm/cpm_8260.h> -#include <mpc8260.h> -#include <command.h> -#include <config.h> -#include <net.h> - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -#include <miiphy.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) - -static struct ether_fcc_info_s -{ - int ether_index; - int proff_enet; - ulong cpm_cr_enet_sblock; - ulong cpm_cr_enet_page; - ulong cmxfcr_mask; - ulong cmxfcr_value; -} - ether_fcc_info[] = -{ -#ifdef CONFIG_ETHER_ON_FCC1 -{ - 0, - PROFF_FCC1, - CPM_CR_FCC1_SBLOCK, - CPM_CR_FCC1_PAGE, - CONFIG_SYS_CMXFCR_MASK1, - CONFIG_SYS_CMXFCR_VALUE1 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC2 -{ - 1, - PROFF_FCC2, - CPM_CR_FCC2_SBLOCK, - CPM_CR_FCC2_PAGE, - CONFIG_SYS_CMXFCR_MASK2, - CONFIG_SYS_CMXFCR_VALUE2 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC3 -{ - 2, - PROFF_FCC3, - CPM_CR_FCC3_SBLOCK, - CPM_CR_FCC3_PAGE, - CONFIG_SYS_CMXFCR_MASK3, - CONFIG_SYS_CMXFCR_VALUE3 -}, -#endif -}; - -/*---------------------------------------------------------------------*/ - -/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ -#define PKT_MAXDMA_SIZE 1520 - -/* The FCC stores dest/src/type, data, and checksum for receive packets. */ -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 - -/* Maximum input buffer size. Must be a multiple of 32. */ -#define PKT_MAXBLR_SIZE 1536 - -#define TOUT_LOOP 1000000 - -#define TX_BUF_CNT 2 -#ifdef __GNUC__ -static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8))); -#else -#error "txbuf must be 64-bit aligned" -#endif - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FCC Ethernet Tx and Rx buffer descriptors. - * Provide for Double Buffering - * Note: PKTBUFSRX is defined in net.h - */ - -typedef volatile struct rtxbd { - cbd_t rxbd[PKTBUFSRX]; - cbd_t txbd[TX_BUF_CNT]; -} RTXBD; - -/* Good news: the FCC supports external BDs! */ -#ifdef __GNUC__ -static RTXBD rtx __attribute__ ((aligned(8))); -#else -#error "rtx must be 64-bit aligned" -#endif - -static int fec_send(struct eth_device *dev, void *packet, int length) -{ - int i; - int result = 0; - - if (length <= 0) { - printf("fec: bad packet size: %d\n", length); - goto out; - } - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - puts ("fec: tx buffer not ready\n"); - goto out; - } - } - - rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx.txbd[txIdx].cbd_datlen = length; - rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | - BD_ENET_TX_WRAP); - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - puts ("fec: tx error\n"); - goto out; - } - } - -#ifdef ET_DEBUG - printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc); -#endif - - /* return only status bits */ - result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; - -out: - return result; -} - -static int fec_recv(struct eth_device* dev) -{ - int length; - - for (;;) - { - if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - length = rtx.rxbd[rxIdx].cbd_datlen; - - if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { - printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); - } - else { - /* Pass the packet up to the protocol layers. */ - net_process_received_packet(net_rx_packets[rxIdx], length - 4); - } - - - /* Give the buffer back to the FCC. */ - rtx.rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } - else { - rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - - -static int fec_init(struct eth_device* dev, bd_t *bis) -{ - struct ether_fcc_info_s * info = dev->priv; - int i; - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8260_t *cp = &(immr->im_cpm); - fcc_enet_t *pram_ptr; - unsigned long mem_addr; - -#if 0 - mii_discover_phy(); -#endif - - /* 28.9 - (1-2): ioports have been set up already */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) | - info->cmxfcr_value; - - /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */ - immr->im_fcc[info->ether_index].fcc_gfmr = - FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - - /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */ - immr->im_fcc[info->ether_index].fcc_fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; - - /* 28.9 - (6): FDSR: Ethernet Syn */ - immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555; - - /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ - rxIdx = 0; - txIdx = 0; - - /* Setup Receiver Buffer Descriptors */ - for (i = 0; i < PKTBUFSRX; i++) - { - rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx.rxbd[i].cbd_datlen = 0; - rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i]; - } - rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* Setup Ethernet Transmitter Buffer Descriptors */ - for (i = 0; i < TX_BUF_CNT; i++) - { - rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); - rtx.txbd[i].cbd_datlen = 0; - rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; - } - rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* 28.9 - (7): initialise parameter ram */ - pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]); - - /* clear whole structure to make sure all reserved fields are zero */ - memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); - - /* - * common Parameter RAM area - * - * Allocate space in the reserved FCC area of DPRAM for the - * internal buffers. No one uses this space (yet), so we - * can do this. Later, we will add resource management for - * this area. - */ - mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); - pram_ptr->fen_genfcc.fcc_riptr = mem_addr; - pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; - /* - * Set maximum bytes per receive buffer. - * It must be a multiple of 32. - */ - pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; - pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | - CONFIG_SYS_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); - pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | - CONFIG_SYS_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); - - /* protocol-specific area */ - pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ - pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ - pram_ptr->fen_retlim = 15; /* Retry limit threshold */ - pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ - /* - * Set Ethernet station address. - * - * This is supplied in the board information structure, so we - * copy that into the controller. - * So, far we have only been given one Ethernet address. We make - * it unique by setting a few bits in the upper byte of the - * non-static part of the address. - */ -#define ea eth_get_ethaddr() - pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */ - /* pad pointer. use tiptr since we don't need a specific padding char */ - pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; - pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */ - pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */ - pram_ptr->fen_rfthr = 1; - pram_ptr->fen_rfcnt = 1; -#if 0 - printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n", - pram_ptr->fen_genfcc.fcc_rbase); - printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n", - pram_ptr->fen_genfcc.fcc_tbase); -#endif - - /* 28.9 - (8): clear out events in FCCE */ - immr->im_fcc[info->ether_index].fcc_fcce = ~0x0; - - /* 28.9 - (9): FCCM: mask all events */ - immr->im_fcc[info->ether_index].fcc_fccm = 0; - - /* 28.9 - (10-12): we don't use ethernet interrupts */ - - /* 28.9 - (13) - * - * Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page, - info->cpm_cr_enet_sblock, - 0x0c, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); - - /* 28.9 - (14): enable tx/rx in gfmr */ - immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - - return 1; -} - -static void fec_halt(struct eth_device* dev) -{ - struct ether_fcc_info_s * info = dev->priv; - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* write GFMR: disable tx/rx */ - immr->im_fcc[info->ether_index].fcc_gfmr &= - ~(FCC_GFMR_ENT | FCC_GFMR_ENR); -} - -int fec_initialize(bd_t *bis) -{ - struct eth_device* dev; - int i; - - for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) - { - dev = (struct eth_device*) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - sprintf(dev->name, "FCC%d", - ether_fcc_info[i].ether_index + 1); - dev->priv = &ether_fcc_info[i]; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; - - eth_register(dev); - -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ - && defined(CONFIG_BITBANGMII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - } - - return 1; -} - -#ifdef CONFIG_ETHER_LOOPBACK_TEST - -#define ELBT_BUFSZ 1024 /* must be multiple of 32 */ - -#define ELBT_CRCSZ 4 - -#define ELBT_NRXBD 4 /* must be at least 2 */ -#define ELBT_NTXBD 4 - -#define ELBT_MAXRXERR 32 -#define ELBT_MAXTXERR 32 - -#define ELBT_CLSWAIT 1000 /* msec to wait for further input frames */ - -typedef - struct { - uint off; - char *lab; - } -elbt_prdesc; - -typedef - struct { - uint _l, _f, m, bc, mc, lg, no, sh, cr, ov, cl; - uint badsrc, badtyp, badlen, badbit; - } -elbt_rxeacc; - -static elbt_prdesc rxeacc_descs[] = { - { offsetof(elbt_rxeacc, _l), "Not Last in Frame" }, - { offsetof(elbt_rxeacc, _f), "Not First in Frame" }, - { offsetof(elbt_rxeacc, m), "Address Miss" }, - { offsetof(elbt_rxeacc, bc), "Broadcast Address" }, - { offsetof(elbt_rxeacc, mc), "Multicast Address" }, - { offsetof(elbt_rxeacc, lg), "Frame Length Violation"}, - { offsetof(elbt_rxeacc, no), "Non-Octet Alignment" }, - { offsetof(elbt_rxeacc, sh), "Short Frame" }, - { offsetof(elbt_rxeacc, cr), "CRC Error" }, - { offsetof(elbt_rxeacc, ov), "Overrun" }, - { offsetof(elbt_rxeacc, cl), "Collision" }, - { offsetof(elbt_rxeacc, badsrc), "Bad Src Address" }, - { offsetof(elbt_rxeacc, badtyp), "Bad Frame Type" }, - { offsetof(elbt_rxeacc, badlen), "Bad Frame Length" }, - { offsetof(elbt_rxeacc, badbit), "Data Compare Errors" }, -}; -static int rxeacc_ndesc = ARRAY_SIZE(rxeacc_descs); - -typedef - struct { - uint def, hb, lc, rl, rc, un, csl; - } -elbt_txeacc; - -static elbt_prdesc txeacc_descs[] = { - { offsetof(elbt_txeacc, def), "Defer Indication" }, - { offsetof(elbt_txeacc, hb), "Heartbeat" }, - { offsetof(elbt_txeacc, lc), "Late Collision" }, - { offsetof(elbt_txeacc, rl), "Retransmission Limit" }, - { offsetof(elbt_txeacc, rc), "Retry Count" }, - { offsetof(elbt_txeacc, un), "Underrun" }, - { offsetof(elbt_txeacc, csl), "Carrier Sense Lost" }, -}; -static int txeacc_ndesc = ARRAY_SIZE(txeacc_descs); - -typedef - struct { - uchar rxbufs[ELBT_NRXBD][ELBT_BUFSZ]; - uchar txbufs[ELBT_NTXBD][ELBT_BUFSZ]; - cbd_t rxbd[ELBT_NRXBD]; - cbd_t txbd[ELBT_NTXBD]; - enum { Idle, Running, Closing, Closed } state; - int proff, page, sblock; - uint clstime, nsent, ntxerr, nrcvd, nrxerr; - ushort rxerrs[ELBT_MAXRXERR], txerrs[ELBT_MAXTXERR]; - elbt_rxeacc rxeacc; - elbt_txeacc txeacc; - } __attribute__ ((aligned(8))) -elbt_chan; - -static uchar patbytes[ELBT_NTXBD] = { - 0xff, 0xaa, 0x55, 0x00 -}; -static uint patwords[ELBT_NTXBD] = { - 0xffffffff, 0xaaaaaaaa, 0x55555555, 0x00000000 -}; - -#ifdef __GNUC__ -static elbt_chan elbt_chans[3] __attribute__ ((aligned(8))); -#else -#error "elbt_chans must be 64-bit aligned" -#endif - -#define CPM_CR_GRACEFUL_STOP_TX ((ushort)0x0005) - -static elbt_prdesc epram_descs[] = { - { offsetof(fcc_enet_t, fen_crcec), "CRC Errors" }, - { offsetof(fcc_enet_t, fen_alec), "Alignment Errors" }, - { offsetof(fcc_enet_t, fen_disfc), "Discarded Frames" }, - { offsetof(fcc_enet_t, fen_octc), "Octets" }, - { offsetof(fcc_enet_t, fen_colc), "Collisions" }, - { offsetof(fcc_enet_t, fen_broc), "Broadcast Frames" }, - { offsetof(fcc_enet_t, fen_mulc), "Multicast Frames" }, - { offsetof(fcc_enet_t, fen_uspc), "Undersize Frames" }, - { offsetof(fcc_enet_t, fen_frgc), "Fragments" }, - { offsetof(fcc_enet_t, fen_ospc), "Oversize Frames" }, - { offsetof(fcc_enet_t, fen_jbrc), "Jabbers" }, - { offsetof(fcc_enet_t, fen_p64c), "64 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p65c), "65-127 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p128c), "128-255 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p256c), "256-511 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"}, -}; -static int epram_ndesc = ARRAY_SIZE(epram_descs); - -/* - * given an elbt_prdesc array and an array of base addresses, print - * each prdesc down the screen with the values fetched from each - * base address across the screen - */ -static void -print_desc (elbt_prdesc descs[], int ndesc, uchar *bases[], int nbase) -{ - elbt_prdesc *dp = descs, *edp = dp + ndesc; - int i; - - printf ("%32s", ""); - - for (i = 0; i < nbase; i++) - printf (" Channel %d", i); - - putc ('\n'); - - while (dp < edp) { - - printf ("%-32s", dp->lab); - - for (i = 0; i < nbase; i++) { - uint val = *(uint *)(bases[i] + dp->off); - - printf (" %10u", val); - } - - putc ('\n'); - - dp++; - } -} - -/* - * return number of bits that are set in a value; value contains - * nbits (right-justified) bits. - */ -static uint __inline__ -nbs (uint value, uint nbits) -{ - uint cnt = 0; -#if 1 - uint pos = sizeof (uint) * 8; - - __asm__ __volatile__ ("\ - mtctr %2\n\ -1: rlwnm. %2,%1,%4,31,31\n\ - beq 2f\n\ - addi %0,%0,1\n\ -2: subi %4,%4,1\n\ - bdnz 1b" - : "=r"(cnt) - : "r"(value), "r"(nbits), "r"(cnt), "r"(pos) - : "ctr", "cc" ); -#else - uint mask = 1; - - do { - if (value & mask) - cnt++; - mask <<= 1; - } while (--nbits); -#endif - - return (cnt); -} - -static ulong -badbits (uchar *bp, int n, ulong pat) -{ - ulong *lp, cnt = 0; - int nl; - - while (n > 0 && ((ulong)bp & (sizeof (ulong) - 1)) != 0) { - uchar diff; - - diff = *bp++ ^ (uchar)pat; - - if (diff) - cnt += nbs ((ulong)diff, 8); - - n--; - } - - lp = (ulong *)bp; - nl = n / sizeof (ulong); - n -= nl * sizeof (ulong); - - while (nl > 0) { - ulong diff; - - diff = *lp++ ^ pat; - - if (diff) - cnt += nbs (diff, 32); - - nl--; - } - - bp = (uchar *)lp; - - while (n > 0) { - uchar diff; - - diff = *bp++ ^ (uchar)pat; - - if (diff) - cnt += nbs ((ulong)diff, 8); - - n--; - } - - return (cnt); -} - -static inline unsigned short -swap16 (unsigned short x) -{ - return (((x & 0xff) << 8) | ((x & 0xff00) >> 8)); -} - -/* broadcast is not an error - we send them like that */ -#define BD_ENET_RX_ERRS (BD_ENET_RX_STATS & ~BD_ENET_RX_BC) - -void -eth_loopback_test (void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8260_t *cp = &(immr->im_cpm); - int c, nclosed; - ulong runtime, nmsec; - uchar *bases[3]; - - puts ("FCC Ethernet External loopback test\n"); - - eth_getenv_enetaddr("ethaddr", net_ethaddr); - - /* - * global initialisations for all FCC channels - */ - - /* 28.9 - (1-2): ioports have been set up already */ - -#if defined(CONFIG_SACSng) - /* - * Attention: this is board-specific - * 1, FCC2 - */ -# define FCC_START_LOOP 1 -# define FCC_END_LOOP 1 - - /* - * Attention: this is board-specific - * - FCC2 Rx-CLK is CLK13 - * - FCC2 Tx-CLK is CLK14 - */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14; -#else -#error "eth_loopback_test not supported on your board" -#endif - - puts ("Initialise FCC channels:"); - - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) { - elbt_chan *ecp = &elbt_chans[c]; - volatile fcc_t *fcp = &immr->im_fcc[c]; - volatile fcc_enet_t *fpp; - int i; - ulong addr; - - /* - * initialise channel data - */ - - printf (" %d", c); - - memset ((void *)ecp, 0, sizeof (*ecp)); - - ecp->state = Idle; - - switch (c) { - - case 0: /* FCC1 */ - ecp->proff = PROFF_FCC1; - ecp->page = CPM_CR_FCC1_PAGE; - ecp->sblock = CPM_CR_FCC1_SBLOCK; - break; - - case 1: /* FCC2 */ - ecp->proff = PROFF_FCC2; - ecp->page = CPM_CR_FCC2_PAGE; - ecp->sblock = CPM_CR_FCC2_SBLOCK; - break; - - case 2: /* FCC3 */ - ecp->proff = PROFF_FCC3; - ecp->page = CPM_CR_FCC3_PAGE; - ecp->sblock = CPM_CR_FCC3_SBLOCK; - break; - } - - /* - * set up tx buffers and bds - */ - - for (i = 0; i < ELBT_NTXBD; i++) { - cbd_t *bdp = &ecp->txbd[i]; - uchar *bp = &ecp->txbufs[i][0]; - - bdp->cbd_bufaddr = (uint)bp; - /* room for crc */ - bdp->cbd_datlen = ELBT_BUFSZ - ELBT_CRCSZ; - bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \ - BD_ENET_TX_LAST | BD_ENET_TX_TC; - - memset((void *)bp, patbytes[i], ELBT_BUFSZ); - net_set_ether(bp, net_bcast_ethaddr, 0x8000); - } - ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* - * set up rx buffers and bds - */ - - for (i = 0; i < ELBT_NRXBD; i++) { - cbd_t *bdp = &ecp->rxbd[i]; - uchar *bp = &ecp->rxbufs[i][0]; - - bdp->cbd_bufaddr = (uint)bp; - bdp->cbd_datlen = 0; - bdp->cbd_sc = BD_ENET_RX_EMPTY; - - memset ((void *)bp, 0, ELBT_BUFSZ); - } - ecp->rxbd[ELBT_NRXBD - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * set up the FCC channel hardware - */ - - /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */ - fcp->fcc_gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - - /* 28.9 - (5): FPSMR: fd, enet CRC, Promis, RMON, Rx SHort */ - fcp->fcc_fpsmr = FCC_PSMR_FDE | FCC_PSMR_LPB | \ - FCC_PSMR_ENCRC | FCC_PSMR_PRO | \ - FCC_PSMR_MON | FCC_PSMR_RSH; - - /* 28.9 - (6): FDSR: Ethernet Syn */ - fcp->fcc_fdsr = 0xD555; - - /* 29.9 - (7): initialise parameter ram */ - fpp = (fcc_enet_t *)&(immr->im_dprambase[ecp->proff]); - - /* clear whole struct to make sure all resv fields are zero */ - memset ((void *)fpp, 0, sizeof (fcc_enet_t)); - - /* - * common Parameter RAM area - * - * Allocate space in the reserved FCC area of DPRAM for the - * internal buffers. No one uses this space (yet), so we - * can do this. Later, we will add resource management for - * this area. - */ - addr = CPM_FCC_SPECIAL_BASE + (c * 64); - fpp->fen_genfcc.fcc_riptr = addr; - fpp->fen_genfcc.fcc_tiptr = addr + 32; - - /* - * Set maximum bytes per receive buffer. - * It must be a multiple of 32. - * buffers are in 60x bus memory. - */ - fpp->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; - fpp->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24; - fpp->fen_genfcc.fcc_rbase = (unsigned int)(&ecp->rxbd[0]); - fpp->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24; - fpp->fen_genfcc.fcc_tbase = (unsigned int)(&ecp->txbd[0]); - - /* protocol-specific area */ - fpp->fen_cmask = 0xdebb20e3; /* CRC mask */ - fpp->fen_cpres = 0xffffffff; /* CRC preset */ - fpp->fen_retlim = 15; /* Retry limit threshold */ - fpp->fen_mflr = PKT_MAXBUF_SIZE;/* max frame length register */ - - /* - * Set Ethernet station address. - * - * This is supplied in the board information structure, so we - * copy that into the controller. - * So, far we have only been given one Ethernet address. We use - * the same address for all channels - */ - fpp->fen_paddrh = (net_ethaddr[5] << 8) + net_ethaddr[4]; - fpp->fen_paddrm = (net_ethaddr[3] << 8) + net_ethaddr[2]; - fpp->fen_paddrl = (net_ethaddr[1] << 8) + net_ethaddr[0]; - - fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */ - /* - * pad pointer. use tiptr since we don't need - * a specific padding char - */ - fpp->fen_padptr = fpp->fen_genfcc.fcc_tiptr; - fpp->fen_maxd1 = PKT_MAXDMA_SIZE; /* max DMA1 length */ - fpp->fen_maxd2 = PKT_MAXDMA_SIZE; /* max DMA2 length */ - fpp->fen_rfthr = 1; - fpp->fen_rfcnt = 1; - - /* 28.9 - (8): clear out events in FCCE */ - fcp->fcc_fcce = ~0x0; - - /* 28.9 - (9): FCCM: mask all events */ - fcp->fcc_fccm = 0; - - /* 28.9 - (10-12): we don't use ethernet interrupts */ - - /* 28.9 - (13) - * - * Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cp->cp_cpcr = mk_cr_cmd (ecp->page, ecp->sblock, \ - 0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); - } - - puts (" done\nStarting test... (Ctrl-C to Finish)\n"); - - /* - * Note: don't want serial output from here until the end of the - * test - the delays would probably stuff things up. - */ - - clear_ctrlc (); - runtime = get_timer (0); - - do { - nclosed = 0; - - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) { - volatile fcc_t *fcp = &immr->im_fcc[c]; - elbt_chan *ecp = &elbt_chans[c]; - int i; - - switch (ecp->state) { - - case Idle: - /* - * set the channel Running ... - */ - - /* 28.9 - (14): enable tx/rx in gfmr */ - fcp->fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - - ecp->state = Running; - break; - - case Running: - /* - * (while Running only) check for - * termination of the test - */ - - (void)ctrlc (); - - if (had_ctrlc ()) { - /* - * initiate a "graceful stop transmit" - * on the channel - */ - cp->cp_cpcr = mk_cr_cmd (ecp->page, \ - ecp->sblock, 0x0c, \ - CPM_CR_GRACEFUL_STOP_TX) | \ - CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); - - ecp->clstime = get_timer (0); - ecp->state = Closing; - } - /* fall through ... */ - - case Closing: - /* - * (while Running or Closing) poll the channel: - * - check for any non-READY tx buffers and - * make them ready - * - check for any non-EMPTY rx buffers and - * check that they were received correctly, - * adjust counters etc, then make empty - */ - - for (i = 0; i < ELBT_NTXBD; i++) { - cbd_t *bdp = &ecp->txbd[i]; - ushort sc = bdp->cbd_sc; - - if ((sc & BD_ENET_TX_READY) != 0) - continue; - - /* - * this frame has finished - * transmitting - */ - ecp->nsent++; - - if (sc & BD_ENET_TX_STATS) { - ulong n; - - /* - * we had an error on - * the transmission - */ - n = ecp->ntxerr++; - if (n < ELBT_MAXTXERR) - ecp->txerrs[n] = sc; - - if (sc & BD_ENET_TX_DEF) - ecp->txeacc.def++; - if (sc & BD_ENET_TX_HB) - ecp->txeacc.hb++; - if (sc & BD_ENET_TX_LC) - ecp->txeacc.lc++; - if (sc & BD_ENET_TX_RL) - ecp->txeacc.rl++; - if (sc & BD_ENET_TX_RCMASK) - ecp->txeacc.rc++; - if (sc & BD_ENET_TX_UN) - ecp->txeacc.un++; - if (sc & BD_ENET_TX_CSL) - ecp->txeacc.csl++; - - bdp->cbd_sc &= \ - ~BD_ENET_TX_STATS; - } - - if (ecp->state == Closing) - ecp->clstime = get_timer (0); - - /* make it ready again */ - bdp->cbd_sc |= BD_ENET_TX_READY; - } - - for (i = 0; i < ELBT_NRXBD; i++) { - cbd_t *bdp = &ecp->rxbd[i]; - ushort sc = bdp->cbd_sc, mask; - - if ((sc & BD_ENET_RX_EMPTY) != 0) - continue; - - /* we have a new frame in this buffer */ - ecp->nrcvd++; - - mask = BD_ENET_RX_LAST|BD_ENET_RX_FIRST; - if ((sc & mask) != mask) { - /* somethings wrong here ... */ - if (!(sc & BD_ENET_RX_LAST)) - ecp->rxeacc._l++; - if (!(sc & BD_ENET_RX_FIRST)) - ecp->rxeacc._f++; - } - - if (sc & BD_ENET_RX_ERRS) { - ulong n; - - /* - * we had some sort of error - * on the frame - */ - n = ecp->nrxerr++; - if (n < ELBT_MAXRXERR) - ecp->rxerrs[n] = sc; - - if (sc & BD_ENET_RX_MISS) - ecp->rxeacc.m++; - if (sc & BD_ENET_RX_BC) - ecp->rxeacc.bc++; - if (sc & BD_ENET_RX_MC) - ecp->rxeacc.mc++; - if (sc & BD_ENET_RX_LG) - ecp->rxeacc.lg++; - if (sc & BD_ENET_RX_NO) - ecp->rxeacc.no++; - if (sc & BD_ENET_RX_SH) - ecp->rxeacc.sh++; - if (sc & BD_ENET_RX_CR) - ecp->rxeacc.cr++; - if (sc & BD_ENET_RX_OV) - ecp->rxeacc.ov++; - if (sc & BD_ENET_RX_CL) - ecp->rxeacc.cl++; - - bdp->cbd_sc &= \ - ~BD_ENET_RX_ERRS; - } - else { - ushort datlen = bdp->cbd_datlen; - struct ethernet_hdr *ehp; - ushort prot; - int ours, tb, n, nbytes; - - ehp = (struct ethernet_hdr *) \ - &ecp->rxbufs[i][0]; - - ours = memcmp (ehp->et_src, \ - net_ethaddr, 6); - - prot = swap16 (ehp->et_protlen); - tb = prot & 0x8000; - n = prot & 0x7fff; - - nbytes = ELBT_BUFSZ - - ETHER_HDR_SIZE - - ELBT_CRCSZ; - - /* check the frame is correct */ - if (datlen != ELBT_BUFSZ) - ecp->rxeacc.badlen++; - else if (!ours) - ecp->rxeacc.badsrc++; - else if (!tb || n >= ELBT_NTXBD) - ecp->rxeacc.badtyp++; - else { - ulong patword = \ - patwords[n]; - uint nbb; - - nbb = badbits( - ((uchar *)&ehp) + - ETHER_HDR_SIZE, - nbytes, patword); - - ecp->rxeacc.badbit += \ - nbb; - } - } - - if (ecp->state == Closing) - ecp->clstime = get_timer (0); - - /* make it empty again */ - bdp->cbd_sc |= BD_ENET_RX_EMPTY; - } - - if (ecp->state != Closing) - break; - - /* - * (while Closing) check to see if - * waited long enough - */ - - if (get_timer (ecp->clstime) >= ELBT_CLSWAIT) { - /* write GFMR: disable tx/rx */ - fcp->fcc_gfmr &= \ - ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - ecp->state = Closed; - } - - break; - - case Closed: - nclosed++; - break; - } - } - - } while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1)); - - runtime = get_timer (runtime); - if (runtime <= ELBT_CLSWAIT) { - printf ("Whoops! somehow elapsed time (%ld) is wrong (<= %d)\n", - runtime, ELBT_CLSWAIT); - return; - } - nmsec = runtime - ELBT_CLSWAIT; - - printf ("Test Finished in %ldms (plus %dms close wait period)!\n\n", - nmsec, ELBT_CLSWAIT); - - /* - * now print stats - */ - - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) { - elbt_chan *ecp = &elbt_chans[c]; - uint rxpps, txpps, nerr; - - rxpps = (ecp->nrcvd * 1000) / nmsec; - txpps = (ecp->nsent * 1000) / nmsec; - - printf ("Channel %d: %d rcvd (%d pps, %d rxerrs), " - "%d sent (%d pps, %d txerrs)\n\n", c, - ecp->nrcvd, rxpps, ecp->nrxerr, - ecp->nsent, txpps, ecp->ntxerr); - - if ((nerr = ecp->nrxerr) > 0) { - ulong i; - - printf ("\tFirst %d rx errs:", nerr); - for (i = 0; i < nerr; i++) - printf (" %04x", ecp->rxerrs[i]); - putc ('\n'); - } - - if ((nerr = ecp->ntxerr) > 0) { - ulong i; - - printf ("\tFirst %d tx errs:", nerr); - for (i = 0; i < nerr; i++) - printf (" %04x", ecp->txerrs[i]); - putc ('\n'); - } - } - - puts ("Receive Error Counts:\n"); - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) - bases[c] = (uchar *)&elbt_chans[c].rxeacc; - print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3); - - puts ("\nTransmit Error Counts:\n"); - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) - bases[c] = (uchar *)&elbt_chans[c].txeacc; - print_desc (txeacc_descs, txeacc_ndesc, bases, 3); - - puts ("\nRMON(-like) Counters:\n"); - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) - bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff]; - print_desc (epram_descs, epram_ndesc, bases, 3); -} - -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - -#endif diff --git a/arch/powerpc/cpu/mpc8260/ether_scc.c b/arch/powerpc/cpu/mpc8260/ether_scc.c deleted file mode 100644 index fff8f2b..0000000 --- a/arch/powerpc/cpu/mpc8260/ether_scc.c +++ /dev/null @@ -1,367 +0,0 @@ -/* - * MPC8260 SCC Ethernet - * - * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright (c) 2001 - * Advent Networks, Inc. http://www.adventnetworks.com - * Jay Monkman jtm@smoothsmoothie.com - * - * Modified so that it plays nicely when more than one ETHERNET interface - * is in use a la ether_fcc.c. - * (C) Copyright 2008 - * DENX Software Engineerin GmbH - * Gary Jennejohn garyj@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/cpm_8260.h> -#include <mpc8260.h> -#include <malloc.h> -#include <net.h> -#include <command.h> -#include <config.h> - -#if (CONFIG_ETHER_INDEX == 1) -# define PROFF_ENET PROFF_SCC1 -# define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE -# define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK -# define CMXSCR_MASK (CMXSCR_SC1 |\ - CMXSCR_RS1CS_MSK |\ - CMXSCR_TS1CS_MSK) - -#elif (CONFIG_ETHER_INDEX == 2) -# define PROFF_ENET PROFF_SCC2 -# define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE -# define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK -# define CMXSCR_MASK (CMXSCR_SC2 |\ - CMXSCR_RS2CS_MSK |\ - CMXSCR_TS2CS_MSK) - -#elif (CONFIG_ETHER_INDEX == 3) -# define PROFF_ENET PROFF_SCC3 -# define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE -# define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK -# define CMXSCR_MASK (CMXSCR_SC3 |\ - CMXSCR_RS3CS_MSK |\ - CMXSCR_TS3CS_MSK) -#elif (CONFIG_ETHER_INDEX == 4) -# define PROFF_ENET PROFF_SCC4 -# define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE -# define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK -# define CMXSCR_MASK (CMXSCR_SC4 |\ - CMXSCR_RS4CS_MSK |\ - CMXSCR_TS4CS_MSK) - -#endif - - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#if !defined(CONFIG_SYS_SCC_TOUT_LOOP) - #define CONFIG_SYS_SCC_TOUT_LOOP 1000000 -#endif - -static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ]; - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * SCC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx; - - -static int sec_send(struct eth_device *dev, void *packet, int length) -{ - int i; - int result = 0; - - if (length <= 0) { - printf("scc: bad packet size: %d\n", length); - goto out; - } - - for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= CONFIG_SYS_SCC_TOUT_LOOP) { - puts ("scc: tx buffer not ready\n"); - goto out; - } - } - - rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | - BD_ENET_TX_WRAP); - - for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= CONFIG_SYS_SCC_TOUT_LOOP) { - puts ("scc: tx error\n"); - goto out; - } - } - - /* return only status bits */ - result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; - - out: - return result; -} - - -static int sec_rx(struct eth_device *dev) -{ - int length; - - for (;;) - { - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) - { - printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); - } - else - { - /* Pass the packet up to the protocol layers. */ - net_process_received_packet(net_rx_packets[rxIdx], length - 4); - } - - - /* Give the buffer back to the SCC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | - BD_ENET_RX_EMPTY); - rxIdx = 0; - } - else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - -/************************************************************** - * - * SCC Ethernet Initialization Routine - * - *************************************************************/ - -static int sec_init(struct eth_device *dev, bd_t *bis) -{ - int i; - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - scc_enet_t *pram_ptr; - uint dpaddr; - uchar ea[6]; - - rxIdx = 0; - txIdx = 0; - - /* - * Assign static pointer to BD area. - * Avoid exhausting DPRAM, which would cause a panic. - */ - if (rtx == NULL) { - dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16); - rtx = (RTXBD *)&immr->im_dprambase[dpaddr]; - } - - /* 24.21 - (1-3): ioports have been set up already */ - - /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) | - CONFIG_SYS_CMXSCR_VALUE); - - - /* 24.21 (6) write RBASE and TBASE to parameter RAM */ - pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]); - pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); - pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); - - pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */ - pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */ - - pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */ - - pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ - pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ - - - /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */ - while(immr->im_cpm.cp_cpcr & CPM_CR_FLG); - immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE, - CPM_CR_ENET_SBLOCK, - 0x0c, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - - /* 24.21 - (8-18): Set up parameter RAM */ - pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ - pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */ - pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ - - pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ - - pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ - - pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ - pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ - - pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ - pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ - - pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ - pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ - pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ - pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ - - eth_getenv_enetaddr("ethaddr", ea); - pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; - - pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ - - pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ - pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ - pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ - pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ - - pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ - pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ - pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ - - /* 24.21 - (19): Initialize RxBD */ - for (i = 0; i < PKTBUFSRX; i++) - { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i]; - } - - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* 24.21 - (20): Initialize TxBD */ - for (i = 0; i < TX_BUF_CNT; i++) - { - rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | - BD_ENET_TX_LAST | - BD_ENET_TX_TC); - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; - } - - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* 24.21 - (21): Write 0xffff to SCCE */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0); - - /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE | - SCCE_ENET_RXF | - SCCE_ENET_TXB); - - /* 24.21 - (23): we don't use ethernet interrupts */ - - /* 24.21 - (24): Clear GSMR_H to enable normal operations */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0; - - /* 24.21 - (25): Clear GSMR_L to enable normal operations */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI | - SCC_GSMRL_TPL_48 | - SCC_GSMRL_TPP_10 | - SCC_GSMRL_MODE_ENET); - - /* 24.21 - (26): Initialize DSR */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555; - - /* 24.21 - (27): Initialize PSMR2 - * - * Settings: - * CRC = 32-Bit CCITT - * NIB = Begin searching for SFD 22 bits after RENA - * FDE = Full Duplex Enable - * BRO = Reject broadcast packets - * PROMISCOUS = Catch all packets regardless of dest. MAC adress - */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC | - SCC_PSMR_NIB22 | -#if defined(CONFIG_SCC_ENET_FULL_DUPLEX) - SCC_PSMR_FDE | -#endif -#if defined(CONFIG_SCC_ENET_NO_BROADCAST) - SCC_PSMR_BRO | -#endif -#if defined(CONFIG_SCC_ENET_PROMISCOUS) - SCC_PSMR_PRO | -#endif - 0; - - /* 24.21 - (28): Write to GSMR_L to enable SCC */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | - SCC_GSMRL_ENT); - - return 0; -} - - -static void sec_halt(struct eth_device *dev) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR | - SCC_GSMRL_ENT); -} - -#if 0 -static void sec_restart(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | - SCC_GSMRL_ENT); -} -#endif - -int mpc82xx_scc_enet_initialize(bd_t *bis) -{ - struct eth_device *dev; - - dev = (struct eth_device *) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - strcpy(dev->name, "SCC"); - dev->init = sec_init; - dev->halt = sec_halt; - dev->send = sec_send; - dev->recv = sec_rx; - - eth_register(dev); - - return 1; -} diff --git a/arch/powerpc/cpu/mpc8260/interrupts.c b/arch/powerpc/cpu/mpc8260/interrupts.c deleted file mode 100644 index 41d2c04..0000000 --- a/arch/powerpc/cpu/mpc8260/interrupts.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00 - */ - -#include <common.h> -#include <command.h> -#include <mpc8260.h> -#include <mpc8260_irq.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -/****************************************************************************/ - -struct irq_action { - interrupt_handler_t *handler; - void *arg; - ulong count; -}; - -static struct irq_action irq_handlers[NR_IRQS]; - -static ulong ppc_cached_irq_mask[NR_MASK_WORDS]; - -/****************************************************************************/ -/* this section was ripped out of arch/powerpc/kernel/ppc8260_pic.c in the */ -/* Linux/PPC 2.4.x source. There was no copyright notice in that file. */ - -/* The 8260 internal interrupt controller. It is usually - * the only interrupt controller. - * There are two 32-bit registers (high/low) for up to 64 - * possible interrupts. - * - * Now, the fun starts.....Interrupt Numbers DO NOT MAP - * in a simple arithmetic fashion to mask or pending registers. - * That is, interrupt 4 does not map to bit position 4. - * We create two tables, indexed by vector number, to indicate - * which register to use and which bit in the register to use. - */ -static u_char irq_to_siureg[] = { - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u_char irq_to_siubit[] = { - 31, 16, 17, 18, 19, 20, 21, 22, - 23, 24, 25, 26, 27, 28, 29, 30, - 29, 30, 16, 17, 18, 19, 20, 21, - 22, 23, 24, 25, 26, 27, 28, 31, - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, - 15, 14, 13, 12, 11, 10, 9, 8, - 7, 6, 5, 4, 3, 2, 1, 0 -}; - -static void m8260_mask_irq (unsigned int irq_nr) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int bit, word; - volatile uint *simr; - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(immr->im_intctl.ic_simrh); - ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); - simr[word] = ppc_cached_irq_mask[word]; -} - -static void m8260_unmask_irq (unsigned int irq_nr) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int bit, word; - volatile uint *simr; - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(immr->im_intctl.ic_simrh); - ppc_cached_irq_mask[word] |= (1 << (31 - bit)); - simr[word] = ppc_cached_irq_mask[word]; -} - -static void m8260_mask_and_ack (unsigned int irq_nr) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int bit, word; - volatile uint *simr, *sipnr; - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(immr->im_intctl.ic_simrh); - sipnr = &(immr->im_intctl.ic_sipnrh); - ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); - simr[word] = ppc_cached_irq_mask[word]; - sipnr[word] = 1 << (31 - bit); -} - -static int m8260_get_irq (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int irq; - unsigned long bits; - - /* For MPC8260, read the SIVEC register and shift the bits down - * to get the irq number. */ - bits = immr->im_intctl.ic_sivec; - irq = bits >> 26; - return irq; -} - -/* end of code ripped out of arch/powerpc/kernel/ppc8260_pic.c */ -/****************************************************************************/ - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - *decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ; - - /* Initialize the default interrupt mapping priorities */ - immr->im_intctl.ic_sicr = 0; - immr->im_intctl.ic_siprr = 0x05309770; - immr->im_intctl.ic_scprrh = 0x05309770; - immr->im_intctl.ic_scprrl = 0x05309770; - - /* disable all interrupts and clear all pending bits */ - immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0; - immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0; - immr->im_intctl.ic_sipnrh = 0xffffffff; - immr->im_intctl.ic_sipnrl = 0xffffffff; - - return 0; -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void external_interrupt (struct pt_regs *regs) -{ - int irq, unmask = 1; - - irq = m8260_get_irq (regs); - - m8260_mask_and_ack (irq); - - enable_interrupts (); - - if (irq_handlers[irq].handler != NULL) - (*irq_handlers[irq].handler) (irq_handlers[irq].arg); - else { - printf ("\nBogus External Interrupt IRQ %d\n", irq); - /* - * turn off the bogus interrupt, otherwise it - * might repeat forever - */ - unmask = 0; - } - - if (unmask) - m8260_unmask_irq (irq); -} - -/****************************************************************************/ - -/* - * Install and free an interrupt handler. - */ - -void -irq_install_handler (int irq, interrupt_handler_t * handler, void *arg) -{ - if (irq < 0 || irq >= NR_IRQS) { - printf ("irq_install_handler: bad irq number %d\n", irq); - return; - } - - if (irq_handlers[irq].handler != NULL) - printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n", - (ulong) handler, (ulong) irq_handlers[irq].handler); - - irq_handlers[irq].handler = handler; - irq_handlers[irq].arg = arg; - - m8260_unmask_irq (irq); -} - -void irq_free_handler (int irq) -{ - if (irq < 0 || irq >= NR_IRQS) { - printf ("irq_free_handler: bad irq number %d\n", irq); - return; - } - - m8260_mask_irq (irq); - - irq_handlers[irq].handler = NULL; - irq_handlers[irq].arg = NULL; -} - -/****************************************************************************/ - -void timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} - -/****************************************************************************/ - -#if defined(CONFIG_CMD_IRQ) - -/* ripped this out of ppc4xx/interrupts.c */ - -/******************************************************************************* -* -* irqinfo - print information about PCI devices -* -*/ -void -do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[]) -{ - int irq, re_enable; - - re_enable = disable_interrupts (); - - puts ("\nInterrupt-Information:\n" - "Nr Routine Arg Count\n"); - - for (irq = 0; irq < 32; irq++) - if (irq_handlers[irq].handler != NULL) - printf ("%02d %08lx %08lx %ld\n", irq, - (ulong) irq_handlers[irq].handler, - (ulong) irq_handlers[irq].arg, - irq_handlers[irq].count); - - if (re_enable) - enable_interrupts (); -} - -#endif diff --git a/arch/powerpc/cpu/mpc8260/kgdb.S b/arch/powerpc/cpu/mpc8260/kgdb.S deleted file mode 100644 index bc9c628..0000000 --- a/arch/powerpc/cpu/mpc8260/kgdb.S +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2000 Murray Jensen Murray.Jensen@cmst.csiro.au - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <command.h> -#include <mpc8260.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#if defined(CONFIG_CMD_KGDB) - - /* - * cache flushing routines for kgdb - */ - - .globl kgdb_flush_cache_all -kgdb_flush_cache_all: - mfspr r3, HID0 - ori r3, r3, HID0_ICFI|HID0_DCI /* Invalidate All */ - SYNC - mtspr HID0, r3 - blr - - .globl kgdb_flush_cache_range -kgdb_flush_cache_range: - li r5,CONFIG_SYS_CACHELINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CONFIG_SYS_CACHELINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CONFIG_SYS_CACHELINE_SIZE - bdnz 2b - SYNC - blr - -#endif diff --git a/arch/powerpc/cpu/mpc8260/pci.c b/arch/powerpc/cpu/mpc8260/pci.c deleted file mode 100644 index 56f290c..0000000 --- a/arch/powerpc/cpu/mpc8260/pci.c +++ /dev/null @@ -1,382 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (c) 2005 MontaVista Software, Inc. - * Vitaly Bordug vbordug@ru.mvista.com - * Added support for PCI bridge on MPC8272ADS - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#ifdef CONFIG_PCI - -#include <pci.h> -#include <mpc8260.h> -#include <asm/m8260_pci.h> -#include <asm/io.h> -#ifdef CONFIG_OF_LIBFDT -#include <libfdt.h> -#include <fdt_support.h> -#endif - -/* - * Local->PCI map (from CPU) controlled by - * MPC826x master window - * - * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0 - * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1 - * - * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1) - * PCI Mem with prefetch - * - * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2) - * PCI Mem w/o prefetch - * - * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3) - * 32-bit PCI IO - * - * PCI->Local map (from PCI) - * MPC826x slave window controlled by - * - * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1) - * MPC826x local memory - */ - -/* - * Slave window that allows PCI masters to access MPC826x local memory. - * This window is set up using the first set of Inbound ATU registers - */ - -#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL -#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ -#else -#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL -#endif - -#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS -#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ -#else -#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS -#endif - -#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB -#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ - PICMR_PREFETCH_EN) -#else -#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB -#endif - -/* - * These are the windows that allow the CPU to access PCI address space. - * All three PCI master windows, which allow the CPU to access PCI - * prefetch, non prefetch, and IO space (see below), must all fit within - * these windows. - */ - -/* PCIBR0 */ -#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL -#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */ -#else -#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL -#endif - -#ifndef CONFIG_SYS_PCIMSK0_MASK -#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */ -#else -#define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK -#endif - -/* PCIBR1 */ -#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL -#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ -#else -#define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL -#endif - -#ifndef CONFIG_SYS_PCIMSK1_MASK -#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */ -#else -#define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK -#endif - -/* - * Master window that allows the CPU to access PCI Memory (prefetch). - * This window will be setup with the first set of Outbound ATU registers - * in the bridge. - */ - -#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL -#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ -#else -#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL -#endif - -#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS -#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ -#else -#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS -#endif - -#ifndef CONFIG_SYS_CPU_PCI_MEM_START -#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL -#else -#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START -#endif - -#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE -#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */ -#else -#define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE -#endif - -#ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB -#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN) -#else -#define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB -#endif - -/* - * Master window that allows the CPU to access PCI Memory (non-prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL -#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */ -#else -#define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL -#endif - -#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS -#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */ -#else -#define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS -#endif - -#ifndef CONFIG_SYS_CPU_PCI_MEMIO_START -#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL -#else -#define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START -#endif - -#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE -#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */ -#else -#define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE -#endif - -#ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB -#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) -#else -#define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB -#endif - -/* - * Master window that allows the CPU to access PCI IO space. - * This window will be setup with the third set of Outbound ATU registers - * in the bridge. - */ - -#ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL -#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */ -#else -#define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL -#endif - -#ifndef CONFIG_SYS_PCI_MSTR_IO_BUS -#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */ -#else -#define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS -#endif - -#ifndef CONFIG_SYS_CPU_PCI_IO_START -#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL -#else -#define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START -#endif - -#ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE -#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */ -#else -#define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE -#endif - -#ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB -#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO) -#else -#define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB -#endif - -/* PCI bus configuration registers. - */ - -#define PCI_CLASS_BRIDGE_CTLR 0x06 - - -static inline void pci_outl (u32 addr, u32 data) -{ - *(volatile u32 *) addr = cpu_to_le32 (data); -} - -void pci_mpc8250_init (struct pci_controller *hose) -{ - u16 tempShort; - - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - pci_dev_t host_devno = PCI_BDF (0, 0, 0); - - pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG, - CONFIG_SYS_IMMR + PCI_CFG_DATA_REG); - - /* - * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), - * and local bus for PCI (SIUMCR [LBPC]). - */ - immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & - ~SIUMCR_LBPC11 & - ~SIUMCR_CS10PC11 & - ~SIUMCR_LBPC11) | - SIUMCR_LBPC01 | - SIUMCR_CS10PC01 | - SIUMCR_APPC10; - - /* Make PCI lowest priority */ - /* Each 4 bits is a device bus request and the MS 4bits - is highest priority */ - /* Bus 4bit value - --- ---------- - CPM high 0b0000 - CPM middle 0b0001 - CPM low 0b0010 - PCI reguest 0b0011 - Reserved 0b0100 - Reserved 0b0101 - Internal Core 0b0110 - External Master 1 0b0111 - External Master 2 0b1000 - External Master 3 0b1001 - The rest are reserved */ - immap->im_siu_conf.sc_ppc_alrh = 0x61207893; - - /* Park bus on core while modifying PCI Bus accesses */ - immap->im_siu_conf.sc_ppc_acr = 0x6; - - /* - * Set up master windows that allow the CPU to access PCI space. These - * windows are set up using the two SIU PCIBR registers. - */ - immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK; - immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE; - - /* Release PCI RST (by default the PCI RST signal is held low) */ - immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN); - - /* give it some time */ - { - udelay (1000); - } - - /* - * Set up master window that allows the CPU to access PCI Memory (prefetch) - * space. This window is set up using the first set of Outbound ATU registers. - */ - immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */ - immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */ - immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */ - - /* - * Set up master window that allows the CPU to access PCI Memory (non-prefetch) - * space. This window is set up using the second set of Outbound ATU registers. - */ - immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */ - immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */ - immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */ - - /* - * Set up master window that allows the CPU to access PCI IO space. This window - * is set up using the third set of Outbound ATU registers. - */ - immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */ - immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */ - immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */ - - /* - * Set up slave window that allows PCI masters to access MPC826x local memory. - * This window is set up using the first set of Inbound ATU registers - */ - immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */ - immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */ - immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */ - - /* See above for description - puts PCI request as highest priority */ - immap->im_siu_conf.sc_ppc_alrh = 0x03124567; - - /* Park the bus on the PCI */ - immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; - - /* Host mode - specify the bridge as a host-PCI bridge */ - - pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE, - PCI_CLASS_BRIDGE_CTLR); - - /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */ - pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort); - pci_hose_write_config_word (hose, host_devno, PCI_COMMAND, - tempShort | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); - - /* do some bridge init, should be done on all 8260 based bridges */ - pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE, - 0x08); - pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER, - 0xF8); - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region (hose->regions + 0, - CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_BASE, - 0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region (hose->regions + 1, - PCI_MSTR_MEM_BUS, - PCI_MSTR_MEM_LOCAL, - PCI_MSTR_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (hose->regions + 2, - PCI_MSTR_IO_BUS, - PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose (hose); - /* Mask off master abort machine checks */ - immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP); - eieio (); - - hose->last_busno = pci_hose_scan (hose); - - - /* clear the error in the error status register */ - immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); - - /* unmask master abort machine checks */ - immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); -} - -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - do_fixup_by_prop_u32(blob, "device_type", "pci", 4, - "clock-frequency", gd->pci_clk, 1); -} -#endif - -#endif /* CONFIG_PCI */ diff --git a/arch/powerpc/cpu/mpc8260/serial_scc.c b/arch/powerpc/cpu/mpc8260/serial_scc.c deleted file mode 100644 index 8bfb3de..0000000 --- a/arch/powerpc/cpu/mpc8260/serial_scc.c +++ /dev/null @@ -1,492 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00. - */ - -/* - * Minimal serial functions needed to use one of the SCC ports - * as serial console interface. - */ - -#include <common.h> -#include <mpc8260.h> -#include <asm/cpm_8260.h> -#include <serial.h> -#include <linux/compiler.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CONS_ON_SCC) - -#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ - -#define SCC_INDEX 0 -#define PROFF_SCC PROFF_SCC1 -#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ - CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) -#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK - -#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */ - -#define SCC_INDEX 1 -#define PROFF_SCC PROFF_SCC2 -#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ - CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) -#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK - -#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */ - -#define SCC_INDEX 2 -#define PROFF_SCC PROFF_SCC3 -#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ - CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) -#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK - -#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */ - -#define SCC_INDEX 3 -#define PROFF_SCC PROFF_SCC4 -#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ - CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) -#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK - -#else - -#error "console not correctly defined" - -#endif - -static int mpc8260_scc_serial_init(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8260_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SCC */ - - sp = (scc_t *) &(im->im_scc[SCC_INDEX]); - up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; - - /* Disable transmitter/receiver. - */ - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* put the SCC channel into NMSI (non multiplexd serial interface) - * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). - */ - im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr&~CMXSCR_MASK)|CMXSCR_VALUE; - - /* Set up the baud rate generator. - */ - serial_setbrg (); - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = BD_SC_WRAP; - - /* Set up the uart parameters in the parameter ram. - */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); - up->scc_genscc.scc_rfcr = CPMFCR_EB; - up->scc_genscc.scc_tfcr = CPMFCR_EB; - up->scc_genscc.scc_mrblr = 1; - up->scc_maxidl = 0; - up->scc_brkcr = 1; - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; - up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Mask all interrupts and remove anything pending. - */ - sp->scc_sccm = 0; - sp->scc_scce = 0xffff; - - /* Set 8 bit FIFO, 16 bit oversampling and UART mode. - */ - sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ - sp->scc_gsmrl = \ - SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; - - /* Set CTS flow control, 1 stop bit, 8 bit character length, - * normal async UART mode, no parity - */ - sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL; - - /* execute the "Init Rx and Tx params" CP command. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; - - return (0); -} - -static void mpc8260_scc_serial_setbrg(void) -{ -#if defined(CONFIG_CONS_USE_EXTC) - m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate, - CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); -#else - m8260_cpm_setbrg(SCC_INDEX, gd->baudrate); -#endif -} - -static void mpc8260_scc_serial_putc(const char c) -{ - volatile scc_uart_t *up; - volatile cbd_t *tbdf; - volatile immap_t *im; - - if (c == '\n') - serial_putc ('\r'); - - im = (immap_t *)CONFIG_SYS_IMMR; - up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; - tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase]; - - /* Wait for last character to go. - */ - while (tbdf->cbd_sc & BD_SC_READY) - ; - - /* Load the character into the transmit buffer. - */ - *(volatile char *)tbdf->cbd_bufaddr = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -static int mpc8260_scc_serial_getc(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im; - unsigned char c; - - im = (immap_t *)CONFIG_SYS_IMMR; - up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; - rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; - - /* Wait for character to show up. - */ - while (rbdf->cbd_sc & BD_SC_EMPTY) - ; - - /* Grab the char and clear the buffer again. - */ - c = *(volatile unsigned char *)rbdf->cbd_bufaddr; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - -static int mpc8260_scc_serial_tstc(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im; - - im = (immap_t *)CONFIG_SYS_IMMR; - up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; - rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; - - return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); -} - -static struct serial_device mpc8260_scc_serial_drv = { - .name = "mpc8260_scc_uart", - .start = mpc8260_scc_serial_init, - .stop = NULL, - .setbrg = mpc8260_scc_serial_setbrg, - .putc = mpc8260_scc_serial_putc, - .puts = default_serial_puts, - .getc = mpc8260_scc_serial_getc, - .tstc = mpc8260_scc_serial_tstc, -}; - -void mpc8260_scc_serial_initialize(void) -{ - serial_register(&mpc8260_scc_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &mpc8260_scc_serial_drv; -} -#endif /* CONFIG_CONS_ON_SCC */ - -#if defined(CONFIG_KGDB_ON_SCC) - -#if defined(CONFIG_CONS_ON_SCC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX -#error Whoops! serial console and kgdb are on the same scc serial port -#endif - -#if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SCC1 */ - -#define KGDB_SCC_INDEX 0 -#define KGDB_PROFF_SCC PROFF_SCC1 -#define KGDB_CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ - CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) -#define KGDB_CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) -#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE -#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK - -#elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SCC2 */ - -#define KGDB_SCC_INDEX 1 -#define KGDB_PROFF_SCC PROFF_SCC2 -#define KGDB_CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ - CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) -#define KGDB_CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) -#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE -#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK - -#elif CONFIG_KGDB_INDEX == 3 /* KGDB Port on SCC3 */ - -#define KGDB_SCC_INDEX 2 -#define KGDB_PROFF_SCC PROFF_SCC3 -#define KGDB_CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ - CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) -#define KGDB_CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) -#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE -#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK - -#elif CONFIG_KGDB_INDEX == 4 /* KGDB Port on SCC4 */ - -#define KGDB_SCC_INDEX 3 -#define KGDB_PROFF_SCC PROFF_SCC4 -#define KGDB_CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ - CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) -#define KGDB_CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) -#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE -#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK - -#else - -#error "kgdb serial port not correctly defined" - -#endif - -void -kgdb_serial_init (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8260_t *cp = &(im->im_cpm); - uint dpaddr, speed = CONFIG_KGDB_BAUDRATE; - char *s, *e; - - if ((s = getenv("kgdbrate")) != NULL && *s != '\0') { - ulong rate = simple_strtoul(s, &e, 10); - if (e > s && *e == '\0') - speed = rate; - } - - /* initialize pointers to SCC */ - - sp = (scc_t *) &(im->im_scc[KGDB_SCC_INDEX]); - up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; - - /* Disable transmitter/receiver. - */ - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* put the SCC channel into NMSI (non multiplexd serial interface) - * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). - */ - im->im_cpmux.cmx_scr = \ - (im->im_cpmux.cmx_scr & ~KGDB_CMXSCR_MASK) | KGDB_CMXSCR_VALUE; - - /* Set up the baud rate generator. - */ -#if defined(CONFIG_KGDB_USE_EXTC) - m8260_cpm_extcbrg(KGDB_SCC_INDEX, speed, - CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL); -#else - m8260_cpm_setbrg(KGDB_SCC_INDEX, speed); -#endif - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = BD_SC_WRAP; - - /* Set up the uart parameters in the parameter ram. - */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); - up->scc_genscc.scc_rfcr = CPMFCR_EB; - up->scc_genscc.scc_tfcr = CPMFCR_EB; - up->scc_genscc.scc_mrblr = 1; - up->scc_maxidl = 0; - up->scc_brkcr = 1; - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; - up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Mask all interrupts and remove anything pending. - */ - sp->scc_sccm = 0; - sp->scc_scce = 0xffff; - - /* Set 8 bit FIFO, 16 bit oversampling and UART mode. - */ - sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ - sp->scc_gsmrl = \ - SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; - - /* Set CTS flow control, 1 stop bit, 8 bit character length, - * normal async UART mode, no parity - */ - sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL; - - /* execute the "Init Rx and Tx params" CP command. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SCC_PAGE, KGDB_CPM_CR_SCC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; - - printf("SCC%d at %dbps ", CONFIG_KGDB_INDEX, speed); -} - -void -putDebugChar(const char c) -{ - volatile scc_uart_t *up; - volatile cbd_t *tbdf; - volatile immap_t *im; - - if (c == '\n') - putDebugChar ('\r'); - - im = (immap_t *)CONFIG_SYS_IMMR; - up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; - tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase]; - - /* Wait for last character to go. - */ - while (tbdf->cbd_sc & BD_SC_READY) - ; - - /* Load the character into the transmit buffer. - */ - *(volatile char *)tbdf->cbd_bufaddr = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -void -putDebugStr (const char *s) -{ - while (*s) { - putDebugChar (*s++); - } -} - -int -getDebugChar(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im; - unsigned char c; - - im = (immap_t *)CONFIG_SYS_IMMR; - up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; - rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; - - /* Wait for character to show up. - */ - while (rbdf->cbd_sc & BD_SC_EMPTY) - ; - - /* Grab the char and clear the buffer again. - */ - c = *(volatile unsigned char *)rbdf->cbd_bufaddr; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - -void -kgdb_interruptible(int yes) -{ - return; -} - -#endif /* CONFIG_KGDB_ON_SCC */ diff --git a/arch/powerpc/cpu/mpc8260/serial_smc.c b/arch/powerpc/cpu/mpc8260/serial_smc.c deleted file mode 100644 index 594c5eb..0000000 --- a/arch/powerpc/cpu/mpc8260/serial_smc.c +++ /dev/null @@ -1,461 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with - * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the - * Linux/PPC sources (m8260_tty.c had no copyright info in it). - */ - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -#include <common.h> -#include <mpc8260.h> -#include <asm/cpm_8260.h> -#include <serial.h> -#include <linux/compiler.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CONS_ON_SMC) - -#if CONFIG_CONS_INDEX == 1 /* Console on SMC1 */ - -#define SMC_INDEX 0 -#define PROFF_SMC_BASE PROFF_SMC1_BASE -#define PROFF_SMC PROFF_SMC1 -#define CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE -#define CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK -#define CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK) -#define CMXSMR_VALUE CMXSMR_SMC1CS_BRG7 - -#elif CONFIG_CONS_INDEX == 2 /* Console on SMC2 */ - -#define SMC_INDEX 1 -#define PROFF_SMC_BASE PROFF_SMC2_BASE -#define PROFF_SMC PROFF_SMC2 -#define CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE -#define CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK -#define CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK) -#define CMXSMR_VALUE CMXSMR_SMC2CS_BRG8 - -#else - -#error "console not correctly defined" - -#endif - -#if !defined(CONFIG_SYS_SMC_RXBUFLEN) -#define CONFIG_SYS_SMC_RXBUFLEN 1 -#define CONFIG_SYS_MAXIDLE 0 -#else -#if !defined(CONFIG_SYS_MAXIDLE) -#error "you must define CONFIG_SYS_MAXIDLE" -#endif -#endif - -typedef volatile struct serialbuffer { - cbd_t rxbd; /* Rx BD */ - cbd_t txbd; /* Tx BD */ - uint rxindex; /* index for next character to read */ - volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */ - volatile uchar txbuf; /* tx buffers */ -} serialbuffer_t; - -/* map rs_table index to baud rate generator index */ -static unsigned char brg_map[] = { - 6, /* BRG7 for SMC1 */ - 7, /* BRG8 for SMC2 */ - 0, /* BRG1 for SCC1 */ - 1, /* BRG1 for SCC2 */ - 2, /* BRG1 for SCC3 */ - 3, /* BRG1 for SCC4 */ -}; - -static int mpc8260_smc_serial_init(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cpm8260_t *cp = &(im->im_cpm); - uint dpaddr; - volatile serialbuffer_t *rtx; - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(im->im_smc[SMC_INDEX]); - im->im_dprambase16[PROFF_SMC_BASE / sizeof(u16)] = PROFF_SMC; - up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC]; - - /* Disable transmitter/receiver. */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */ - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - /* allocate size of struct serialbuffer with bd rx/tx, - * buffer rx/tx and rx index - */ - dpaddr = m8260_cpm_dpalloc((sizeof(serialbuffer_t)), 16); - - rtx = (serialbuffer_t *)&im->im_dprambase[dpaddr]; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf; - rtx->rxbd.cbd_sc = 0; - - rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf; - rtx->txbd.cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = CPMFCR_EB; - up->smc_tfcr = CPMFCR_EB; - up->smc_brklen = 0; - up->smc_brkec = 0; - up->smc_brkcr = 0; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* put the SMC channel into NMSI (non multiplexd serial interface) - * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17). - */ - im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE; - - /* Set up the baud rate generator. */ - serial_setbrg (); - - /* Make the first buffer the only buffer. */ - rtx->txbd.cbd_sc |= BD_SC_WRAP; - rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* single/multi character receive. */ - up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN; - up->smc_maxidl = CONFIG_SYS_MAXIDLE; - rtx->rxindex = 0; - - /* Initialize Tx/Rx parameters. */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - return (0); -} - -static void mpc8260_smc_serial_setbrg(void) -{ -#if defined(CONFIG_CONS_USE_EXTC) - m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate, - CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); -#else - m8260_cpm_setbrg(brg_map[SMC_INDEX], gd->baudrate); -#endif -} - -static void mpc8260_smc_serial_putc(const char c) -{ - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile serialbuffer_t *rtx; - - if (c == '\n') - serial_putc ('\r'); - - up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); - - rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase]; - - /* Wait for last character to go. */ - while (rtx->txbd.cbd_sc & BD_SC_READY & BD_SC_READY) - ; - rtx->txbuf = c; - rtx->txbd.cbd_datlen = 1; - rtx->txbd.cbd_sc |= BD_SC_READY; -} - -static int mpc8260_smc_serial_getc(void) -{ - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile serialbuffer_t *rtx; - unsigned char c; - - up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); - - rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase]; - - /* Wait for character to show up. */ - while (rtx->rxbd.cbd_sc & BD_SC_EMPTY) - ; - - /* the characters are read one by one, - * use the rxindex to know the next char to deliver - */ - c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr + rtx->rxindex); - rtx->rxindex++; - - /* check if all char are readout, then make prepare for next receive */ - if (rtx->rxindex >= rtx->rxbd.cbd_datlen) { - rtx->rxindex = 0; - rtx->rxbd.cbd_sc |= BD_SC_EMPTY; - } - return(c); -} - -static int mpc8260_smc_serial_tstc(void) -{ - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile serialbuffer_t *rtx; - - up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); - rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase]; - - return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY); -} - -static struct serial_device mpc8260_smc_serial_drv = { - .name = "mpc8260_smc_uart", - .start = mpc8260_smc_serial_init, - .stop = NULL, - .setbrg = mpc8260_smc_serial_setbrg, - .putc = mpc8260_smc_serial_putc, - .puts = default_serial_puts, - .getc = mpc8260_smc_serial_getc, - .tstc = mpc8260_smc_serial_tstc, -}; - -void mpc8260_smc_serial_initialize(void) -{ - serial_register(&mpc8260_smc_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &mpc8260_smc_serial_drv; -} -#endif /* CONFIG_CONS_ON_SMC */ - -#if defined(CONFIG_KGDB_ON_SMC) - -#if defined(CONFIG_CONS_ON_SMC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX -#error Whoops! serial console and kgdb are on the same smc serial port -#endif - -#if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SMC1 */ - -#define KGDB_SMC_INDEX 0 -#define KGDB_PROFF_SMC_BASE PROFF_SMC1_BASE -#define KGDB_PROFF_SMC PROFF_SMC1 -#define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE -#define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK -#define KGDB_CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK) -#define KGDB_CMXSMR_VALUE CMXSMR_SMC1CS_BRG7 - -#elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SMC2 */ - -#define KGDB_SMC_INDEX 1 -#define KGDB_PROFF_SMC_BASE PROFF_SMC2_BASE -#define KGDB_PROFF_SMC PROFF_SMC2 -#define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE -#define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK -#define KGDB_CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK) -#define KGDB_CMXSMR_VALUE CMXSMR_SMC2CS_BRG8 - -#else - -#error "console not correctly defined" - -#endif - -void -kgdb_serial_init (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8260_t *cp = &(im->im_cpm); - uint dpaddr, speed = CONFIG_KGDB_BAUDRATE; - char *s, *e; - - if ((s = getenv("kgdbrate")) != NULL && *s != '\0') { - ulong rate = simple_strtoul(s, &e, 10); - if (e > s && *e == '\0') - speed = rate; - } - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]); - im->im_dprambase16[KGDB_PROFF_SMC_BASE / sizeof(u16)] = KGDB_PROFF_SMC; - up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC]; - - /* Disable transmitter/receiver. */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */ - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = CPMFCR_EB; - up->smc_tfcr = CPMFCR_EB; - up->smc_brklen = 0; - up->smc_brkec = 0; - up->smc_brkcr = 0; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* put the SMC channel into NMSI (non multiplexd serial interface) - * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17). - */ - im->im_cpmux.cmx_smr = - (im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE; - - /* Set up the baud rate generator. */ -#if defined(CONFIG_KGDB_USE_EXTC) - m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed, - CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL); -#else - m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed); -#endif - - /* Make the first buffer the only buffer. */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed); -} - -void -putDebugChar(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - if (c == '\n') - putDebugChar ('\r'); - - up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]); - - tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase]; - - /* Wait for last character to go. */ - buf = (char *)tbdf->cbd_bufaddr; - while (tbdf->cbd_sc & BD_SC_READY) - ; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -void -putDebugStr (const char *s) -{ - while (*s) { - putDebugChar (*s++); - } -} - -int -getDebugChar(void) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - unsigned char c; - - up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]); - - rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase]; - - /* Wait for character to show up. */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - while (rbdf->cbd_sc & BD_SC_EMPTY) - ; - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -void -kgdb_interruptible(int yes) -{ - return; -} - -#endif /* CONFIG_KGDB_ON_SMC */ diff --git a/arch/powerpc/cpu/mpc8260/speed.c b/arch/powerpc/cpu/mpc8260/speed.c deleted file mode 100644 index 0a06c48..0000000 --- a/arch/powerpc/cpu/mpc8260/speed.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8260.h> -#include <asm/processor.h> - -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -extern unsigned long board_get_cpu_clk_f (void); -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -/* Bus-to-Core Multiplier */ -#define _1x 2 -#define _1_5x 3 -#define _2x 4 -#define _2_5x 5 -#define _3x 6 -#define _3_5x 7 -#define _4x 8 -#define _4_5x 9 -#define _5x 10 -#define _5_5x 11 -#define _6x 12 -#define _6_5x 13 -#define _7x 14 -#define _7_5x 15 -#define _8x 16 -#define _byp -1 -#define _off -2 -#define _unk -3 - -typedef struct { - int b2c_mult; - int vco_div; - char *freq_60x; - char *freq_core; -} corecnf_t; - -/* - * this table based on "Errata to MPC8260 PowerQUICC II User's Manual", - * Rev. 1, 8/2000, page 10. - */ -corecnf_t corecnf_tab[] = { - { _1_5x, 4, " 33-100", " 33-100" }, /* 0x00 */ - { _1x, 4, " 50-150", " 50-150" }, /* 0x01 */ - { _1x, 8, " 25-75 ", " 25-75 " }, /* 0x02 */ - { _byp, -1, " ?-? ", " ?-? " }, /* 0x03 */ - { _2x, 2, " 50-150", "100-300" }, /* 0x04 */ - { _2x, 4, " 25-75 ", " 50-150" }, /* 0x05 */ - { _2_5x, 2, " 40-120", "100-240" }, /* 0x06 */ - { _4_5x, 2, " 22-65 ", "100-300" }, /* 0x07 */ - { _3x, 2, " 33-100", "100-300" }, /* 0x08 */ - { _5_5x, 2, " 18-55 ", "100-300" }, /* 0x09 */ - { _4x, 2, " 25-75 ", "100-300" }, /* 0x0A */ - { _5x, 2, " 20-60 ", "100-300" }, /* 0x0B */ - { _1_5x, 8, " 16-50 ", " 16-50 " }, /* 0x0C */ - { _6x, 2, " 16-50 ", "100-300" }, /* 0x0D */ - { _3_5x, 2, " 30-85 ", "100-300" }, /* 0x0E */ - { _off, -1, " ?-? ", " ?-? " }, /* 0x0F */ - { _3x, 4, " 16-50 ", " 50-150" }, /* 0x10 */ - { _2_5x, 4, " 20-60 ", " 50-120" }, /* 0x11 */ - { _6_5x, 2, " 15-46 ", "100-300" }, /* 0x12 */ - { _byp, -1, " ?-? ", " ?-? " }, /* 0x13 */ - { _7x, 2, " 14-43 ", "100-300" }, /* 0x14 */ - { _2x, 4, " 25-75 ", " 50-150" }, /* 0x15 */ - { _7_5x, 2, " 13-40 ", "100-300" }, /* 0x16 */ - { _4_5x, 2, " 22-65 ", "100-300" }, /* 0x17 */ - { _unk, -1, " ?-? ", " ?-? " }, /* 0x18 */ - { _5_5x, 2, " 18-55 ", "100-300" }, /* 0x19 */ - { _4x, 2, " 25-75 ", "100-300" }, /* 0x1A */ - { _5x, 2, " 20-60 ", "100-300" }, /* 0x1B */ - { _8x, 2, " 12-38 ", "100-300" }, /* 0x1C */ - { _6x, 2, " 16-50 ", "100-300" }, /* 0x1D */ - { _3_5x, 2, " 30-85 ", "100-300" }, /* 0x1E */ - { _off, -1, " ?-? ", " ?-? " }, /* 0x1F */ -}; - -/* ------------------------------------------------------------------------- */ - -/* - * - */ - -int get_clocks (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - ulong clkin; - ulong sccr, dfbrg; - ulong scmr, corecnf, plldf, pllmf; - corecnf_t *cp; - -#if !defined(CONFIG_8260_CLKIN) -#error clock measuring not implemented yet - define CONFIG_8260_CLKIN -#else -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) - clkin = board_get_cpu_clk_f (); -#else - clkin = CONFIG_8260_CLKIN; -#endif -#endif - - sccr = immap->im_clkrst.car_sccr; - dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; - - scmr = immap->im_clkrst.car_scmr; - corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; - cp = &corecnf_tab[corecnf]; - - /* HiP7, HiP7 Rev01, HiP7 RevA */ - if ((get_pvr () == PVR_8260_HIP7) || - (get_pvr () == PVR_8260_HIP7R1) || - (get_pvr () == PVR_8260_HIP7RA)) { - pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT; - gd->arch.vco_out = clkin * (pllmf + 1); - } else { /* HiP3, HiP4 */ - pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; - plldf = (scmr & SCMR_PLLDF) ? 1 : 0; - gd->arch.vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); - } - - gd->arch.cpm_clk = gd->arch.vco_out / 2; - gd->bus_clk = clkin; - gd->arch.scc_clk = gd->arch.vco_out / 4; - gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); - - if (cp->b2c_mult > 0) { - gd->cpu_clk = (clkin * cp->b2c_mult) / 2; - } else { - gd->cpu_clk = clkin; - } - -#ifdef CONFIG_PCI - gd->pci_clk = clkin; - - if (sccr & SCCR_PCI_MODE) { - uint pci_div; - uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT; - - if (sccr & SCCR_PCI_MODCK) { - pci_div = 2; - if (pcidf == 9) { - pci_div *= 5; - } else if (pcidf == 0xB) { - pci_div *= 6; - } else { - pci_div *= (pcidf + 1); - } - } else { - pci_div = pcidf + 1; - } - - gd->pci_clk = (gd->arch.cpm_clk * 2) / pci_div; - } -#endif - - return (0); -} - -int prt_8260_clks (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - ulong sccr, dfbrg; - ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf; - corecnf_t *cp; - - sccr = immap->im_clkrst.car_sccr; - dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; - - scmr = immap->im_clkrst.car_scmr; - corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; - busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; - cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; - plldf = (scmr & SCMR_PLLDF) ? 1 : 0; - pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; - pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT; - - cp = &corecnf_tab[corecnf]; - - puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult "); - - switch (cp->b2c_mult) { - case _byp: - puts ("BYPASS"); - break; - - case _off: - puts ("OFF"); - break; - - case _unk: - puts ("UNKNOWN"); - break; - - default: - printf ("%d%sx", - cp->b2c_mult / 2, - (cp->b2c_mult % 2) ? ".5" : ""); - break; - } - - printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n", - cp->vco_div, cp->freq_60x, cp->freq_core); - - printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, " - "plldf %ld, pllmf %ld, pcidf %ld\n", - dfbrg, corecnf, busdf, cpmdf, - plldf, pllmf, pcidf); - - printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n", - gd->arch.vco_out, gd->arch.scc_clk, gd->arch.brg_clk); - - printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n", - gd->cpu_clk, gd->arch.cpm_clk, gd->bus_clk); -#ifdef CONFIG_PCI - printf (" - pci_clk %10ld\n", gd->pci_clk); -#endif - putc ('\n'); - - return (0); -} diff --git a/arch/powerpc/cpu/mpc8260/spi.c b/arch/powerpc/cpu/mpc8260/spi.c deleted file mode 100644 index c7fb4e9..0000000 --- a/arch/powerpc/cpu/mpc8260/spi.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * nboppuri@trinetcommunication.com, - * pmpatel@trinetcommunication.com - * Copyright (c) 2001 Gerd Mennchen Gerd.Mennchen@icn.siemens.de - * Copyright (c) 2001-2003 Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8260 CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd@denx.de - * - */ - -#include <common.h> -#include <asm/cpm_8260.h> -#include <linux/ctype.h> -#include <malloc.h> -#include <post.h> -#include <net.h> - -#if defined(CONFIG_SPI) - -/* Warning: - * You cannot enable DEBUG for early system initalization, i. e. when - * this driver is used to read environment parameters like "baudrate" - * from EEPROM which are used to initialize the serial port which is - * needed to print the debug messages... - */ -#undef DEBUG - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - -/* --------------------------------------------------------------- - * Offset for initial SPI buffers in DPRAM: - * We need a 520 byte scratch DPRAM area to use at an early stage. - * It is used between the two initialization calls (spi_init_f() - * and spi_init_r()). - * The value 0x2000 makes it far enough from the start of the data - * area (as well as from the stack pointer). - * --------------------------------------------------------------- */ -#ifndef CONFIG_SYS_SPI_INIT_OFFSET -#define CONFIG_SYS_SPI_INIT_OFFSET 0x2000 -#endif - -#define CPM_SPI_BASE 0x100 - -#ifdef DEBUG - -#define DPRINT(a) printf a; -/* ----------------------------------------------- - * Helper functions to peek into tx and rx buffers - * ----------------------------------------------- */ -static const char * const hex_digit = "0123456789ABCDEF"; - -static char quickhex (int i) -{ - return hex_digit[i]; -} - -static void memdump (void *pv, int num) -{ - int i; - unsigned char *pc = (unsigned char *) pv; - - for (i = 0; i < num; i++) - printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); - printf ("\t"); - for (i = 0; i < num; i++) - printf ("%c", isprint (pc[i]) ? pc[i] : '.'); - printf ("\n"); -} -#else /* !DEBUG */ - -#define DPRINT(a) - -#endif /* DEBUG */ - -/* ------------------- - * Function prototypes - * ------------------- */ -void spi_init (void); - -ssize_t spi_read (uchar *, int, uchar *, int); -ssize_t spi_write (uchar *, int, uchar *, int); -ssize_t spi_xfer (size_t); - -/* ------------------- - * Variables - * ------------------- */ - -#define MAX_BUFFER 0x104 - -/* ---------------------------------------------------------------------- - * Initially we place the RX and TX buffers at a fixed location in DPRAM! - * ---------------------------------------------------------------------- */ -static uchar *rxbuf = - (uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase - [CONFIG_SYS_SPI_INIT_OFFSET]; -static uchar *txbuf = - (uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase - [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ -void spi_init_f (void) -{ - unsigned int dpaddr; - - volatile spi_t *spi; - volatile immap_t *immr; - volatile cpm8260_t *cp; - volatile cbd_t *tbdf, *rbdf; - - immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8260_t *) &immr->im_cpm; - - immr->im_dprambase16[PROFF_SPI_BASE / sizeof(u16)] = PROFF_SPI; - spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; - -/* 1 */ - /* ------------------------------------------------ - * Initialize Port D SPI pins - * (we are only in Master Mode !) - * ------------------------------------------------ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PPARD[16] = 1 [0x00008000] (SPIMISO) - * PPARD[17] = 1 [0x00004000] (SPIMOSI) - * PPARD[18] = 1 [0x00002000] (SPICLK) - * PPARD[12] = 0 [0x00080000] -> GPIO: (CS for ATC EEPROM) - * -------------------------------------------- */ - immr->im_ioport.iop_ppard |= 0x0000E000; /* set bits */ - immr->im_ioport.iop_ppard &= ~0x00080000; /* reset bit */ - - /* ---------------------------------------------- - * In/Out or per. Function 0/1 - * PDIRD[16] = 0 [0x00008000] -> PERI1: SPIMISO - * PDIRD[17] = 0 [0x00004000] -> PERI1: SPIMOSI - * PDIRD[18] = 0 [0x00002000] -> PERI1: SPICLK - * PDIRD[12] = 1 [0x00080000] -> GPIO OUT: CS for ATC EEPROM - * ---------------------------------------------- */ - immr->im_ioport.iop_pdird &= ~0x0000E000; - immr->im_ioport.iop_pdird |= 0x00080000; - - /* ---------------------------------------------- - * special option reg. - * PSORD[16] = 1 [0x00008000] -> SPIMISO - * PSORD[17] = 1 [0x00004000] -> SPIMOSI - * PSORD[18] = 1 [0x00002000] -> SPICLK - * ---------------------------------------------- */ - immr->im_ioport.iop_psord |= 0x0000E000; - - /* Initialize the parameter ram. - * We need to make sure many things are initialized to zero - */ - spi->spi_rstate = 0; - spi->spi_rdp = 0; - spi->spi_rbptr = 0; - spi->spi_rbc = 0; - spi->spi_rxtmp = 0; - spi->spi_tstate = 0; - spi->spi_tdp = 0; - spi->spi_tbptr = 0; - spi->spi_tbc = 0; - spi->spi_txtmp = 0; - - dpaddr = CPM_SPI_BASE; - -/* 3 */ - /* Set up the SPI parameters in the parameter ram */ - spi->spi_rbase = dpaddr; - spi->spi_tbase = dpaddr + sizeof (cbd_t); - - /***********IMPORTANT******************/ - - /* - * Setting transmit and receive buffer descriptor pointers - * initially to rbase and tbase. Only the microcode patches - * documentation talks about initializing this pointer. This - * is missing from the sample I2C driver. If you dont - * initialize these pointers, the kernel hangs. - */ - spi->spi_rbptr = spi->spi_rbase; - spi->spi_tbptr = spi->spi_tbase; - -/* 4 */ - /* Init SPI Tx + Rx Parameters */ - while (cp->cp_cpcr & CPM_CR_FLG) - ; - cp->cp_cpcr = mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG) - ; - -/* 6 */ - /* Set to big endian. */ - spi->spi_tfcr = CPMFCR_EB; - spi->spi_rfcr = CPMFCR_EB; - -/* 7 */ - /* Set maximum receive size. */ - spi->spi_mrblr = MAX_BUFFER; - -/* 8 + 9 */ - /* tx and rx buffer descriptors */ - tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; - rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; - - tbdf->cbd_sc &= ~BD_SC_READY; - rbdf->cbd_sc &= ~BD_SC_EMPTY; - - /* Set the bd's rx and tx buffer address pointers */ - rbdf->cbd_bufaddr = (ulong) rxbuf; - tbdf->cbd_bufaddr = (ulong) txbuf; - -/* 10 + 11 */ - immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */ - immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */ - - - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * - * return: --- - * - * *********************************************************************** */ -void spi_init_r (void) -{ - volatile spi_t *spi; - volatile immap_t *immr; - volatile cbd_t *tbdf, *rbdf; - - immr = (immap_t *) CONFIG_SYS_IMMR; - - spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; - - /* tx and rx buffer descriptors */ - tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; - rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; - - /* Allocate memory for RX and TX buffers */ - rxbuf = (uchar *) malloc (MAX_BUFFER); - txbuf = (uchar *) malloc (MAX_BUFFER); - - rbdf->cbd_bufaddr = (ulong) rxbuf; - tbdf->cbd_bufaddr = (ulong) txbuf; - - return; -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - *txbuf = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ - memcpy(alen + txbuf, buffer, len); - spi_xfer(alen + len); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - *txbuf = SPI_EEPROM_RDSR; /* read status */ - txbuf[1] = 0; - spi_xfer(2); - if (!(rxbuf[1] & 1)) { - break; - } - udelay(1000); - } - if (i >= 1000) { - printf ("*** spi_write: Time out while writing!\n"); - } - - return len; -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) -{ - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_READ; /* READ memory array */ - - /* - * There is a bug in 860T (?) that cuts the last byte of input - * if we're reading into DPRAM. The solution we choose here is - * to always read len+1 bytes (we have one extra byte at the - * end of the buffer). - */ - spi_xfer(alen + len + 1); - memcpy(buffer, alen + rxbuf, len); - - return len; -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer (size_t count) -{ - volatile immap_t *immr; - volatile spi_t *spi; - cbd_t *tbdf, *rbdf; - int tm; - - DPRINT (("*** spi_xfer entered ***\n")); - - immr = (immap_t *) CONFIG_SYS_IMMR; - - spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; - - tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; - rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; - - /* Board-specific: Set CS for device (ATC EEPROM) */ - immr->im_ioport.iop_pdatd &= ~0x00080000; - - /* Setting tx bd status and data length */ - tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP; - tbdf->cbd_datlen = count; - - DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", - tbdf->cbd_datlen)); - - /* Setting rx bd status and data length */ - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - rbdf->cbd_datlen = 0; /* rx length has no significance */ - - immr->im_spi.spi_spmode = SPMODE_REV | - SPMODE_MSTR | - SPMODE_EN | - SPMODE_LEN(8) | /* 8 Bits per char */ - SPMODE_PM(0x8) ; /* medium speed */ - immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */ - immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */ - - /* start spi transfer */ - DPRINT (("*** spi_xfer: Performing transfer ...\n")); - immr->im_spi.spi_spcom |= SPI_STR; /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm=0; tm<1000; ++tm) { - if (immr->im_spi.spi_spie & SPI_TXB) { /* Tx Buffer Empty */ - DPRINT (("*** spi_xfer: Tx buffer empty\n")); - break; - } - if ((tbdf->cbd_sc & BD_SC_READY) == 0) { - DPRINT (("*** spi_xfer: Tx BD done\n")); - break; - } - udelay (1000); - } - if (tm >= 1000) { - printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); - } - DPRINT (("*** spi_xfer: ... transfer ended\n")); - -#ifdef DEBUG - printf ("\nspi_xfer: txbuf after xfer\n"); - memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */ - printf ("spi_xfer: rxbuf after xfer\n"); - memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */ - printf ("\n"); -#endif - - /* Clear CS for device */ - immr->im_ioport.iop_pdatd |= 0x00080000; - - return count; -} -#endif /* CONFIG_SPI */ diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S deleted file mode 100644 index d255bde..0000000 --- a/arch/powerpc/cpu/mpc8260/start.S +++ /dev/null @@ -1,901 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek dmalek@jlc.net - * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> - * Copyright (C) 2000, 2001,2002 Wolfgang Denk wd@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards - */ -#include <asm-offsets.h> -#include <config.h> -#include <mpc8260.h> -#include <version.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> -#include <asm/u-boot.h> - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Floating Point enable, Machine Check and Recoverable Interr. */ -#ifdef DEBUG -#define MSR_KERNEL (MSR_FP|MSR_RI) -#else -#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) -#endif - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * Version string - must be in data segment because MPC8260 uses the first - * 256 bytes for the Hard Reset Configuration Word table (see below). - * Similarly, can't have the U-Boot Magic Number as the first thing in - * the image - don't know how this will affect the image tools, but I guess - * I'll find out soon - */ - .data - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - -/* - * Hard Reset Configuration Word (HRCW) table - * - * The Hard Reset Configuration Word (HRCW) sets a number of useful things - * such as whether there is an external memory controller, whether the - * PowerPC core is disabled (i.e. only the communications processor is - * active, accessed by another CPU on the bus), whether using external - * arbitration, external bus mode, boot port size, core initial prefix, - * internal space base, boot memory space, etc. - * - * These things dictate where the processor begins execution, where the - * boot ROM appears in memory, the memory controller setup when access - * boot ROM, etc. The HRCW is *extremely* important. - * - * The HRCW is read from the bus during reset. One CPU on the bus will - * be a hard reset configuration master, any others will be hard reset - * configuration slaves. The master reads eight HRCWs from flash during - * reset - the first it uses for itself, the other 7 it communicates to - * up to 7 configuration slaves by some complicated mechanism, which is - * not really important here. - * - * The configuration master performs 32 successive reads starting at address - * 0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8 - * bits is read, and always from byte lane D[0-7] (so that port size of the - * boot device does not matter). The first four reads form the 32 bit HRCW - * for the master itself. The second four reads form the HRCW for the first - * slave, and so on, up to seven slaves. The 32 bit HRCW is formed by - * concatenating the four bytes, with the first read placed in byte 0 (the - * most significant byte), and so on with the fourth read placed in byte 3 - * (the least significant byte). - */ -#define _HRCW_TABLE_ENTRY(w) \ - .fill 8,1,(((w)>>24)&0xff); \ - .fill 8,1,(((w)>>16)&0xff); \ - .fill 8,1,(((w)>> 8)&0xff); \ - .fill 8,1,(((w) )&0xff) - .text - .globl _hrcw_table -_hrcw_table: - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_MASTER) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE1) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE2) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE3) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE4) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE5) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE6) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE7) -/* - * After configuration, a system reset exception is executed using the - * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP] - * is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address - * is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value - * of MSR[IP] is determined by the CIP field in the HRCW. - * - * Other bits in the HRCW set up the Base Address and Port Size in BR0. - * This determines the location of the boot ROM (flash or EPROM) in the - * processor's address space at boot time. As long as the HRCW is set up - * so that we eventually end up executing the code below when the processor - * executes the reset exception, the actual values used should not matter. - * - * Once we have got here, the address mask in OR0 is cleared so that the - * bottom 32K of the boot ROM is effectively repeated all throughout the - * processor's address space, after which we can jump to the absolute - * address at which the boot ROM was linked at compile time, and proceed - * to initialise the memory controller without worrying if the rug will be - * pulled out from under us, so to speak (it will be fine as long as we - * configure BR0 with the same boot ROM link address). - */ - . = EXC_OFF_SYS_RESET - - .globl _start -_start: - mfmsr r5 /* save msr contents */ - -#if defined(CONFIG_SYS_DEFAULT_IMMR) - lis r3, CONFIG_SYS_IMMR@h - ori r3, r3, CONFIG_SYS_IMMR@l - lis r4, CONFIG_SYS_DEFAULT_IMMR@h - stw r3, 0x1A8(r4) -#endif /* CONFIG_SYS_DEFAULT_IMMR */ - - /* Initialise the MPC8260 processor core */ - /*--------------------------------------------------------------*/ - - bl init_8260_core - -#ifndef CONFIG_SYS_RAMBOOT - /* When booting from ROM (Flash or EPROM), clear the */ - /* Address Mask in OR0 so ROM appears everywhere */ - /*--------------------------------------------------------------*/ - - lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h - lwz r4, IM_OR0@l(r3) - li r5, 0x7fff - and r4, r4, r5 - stw r4, IM_OR0@l(r3) - - /* Calculate absolute address in FLASH and jump there */ - /*--------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_MONITOR_BASE@h - ori r3, r3, CONFIG_SYS_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: -#endif /* CONFIG_SYS_RAMBOOT */ - - /* initialize some things that are hard to access from C */ - /*--------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_IMMR@h /* set up stack in internal DPRAM */ - ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*--------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (in Flash)*/ - -#ifdef DEBUG - bl init_debug /* set up debugging stuff */ -#endif - - bl board_init_f /* run 1st part of board init code (in Flash)*/ - - /* NOTREACHED - board_init_f() does not return */ - -/* - * Vector Table - */ - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) -#ifdef DEBUG - . = 0x1300 - /* - * This exception occurs when the program counter matches the - * Instruction Address Breakpoint Register (IABR). - * - * I want the cpu to halt if this occurs so I can hunt around - * with the debugger and look at things. - * - * When DEBUG is defined, both machine check enable (in the MSR) - * and checkstop reset enable (in the reset mode register) are - * turned off and so a checkstop condition will result in the cpu - * halting. - * - * I force the cpu into a checkstop condition by putting an illegal - * instruction here (at least this is the theory). - * - * well - that didnt work, so just do an infinite loop! - */ -1: b 1b -#else - STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) -#endif - STD_EXCEPTION(0x1400, SMI, UnknownException) - - STD_EXCEPTION(0x1500, Trap_15, UnknownException) - STD_EXCEPTION(0x1600, Trap_16, UnknownException) - STD_EXCEPTION(0x1700, Trap_17, UnknownException) - STD_EXCEPTION(0x1800, Trap_18, UnknownException) - STD_EXCEPTION(0x1900, Trap_19, UnknownException) - STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) - STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) - STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) - STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) - STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) - STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) - STD_EXCEPTION(0x2000, Trap_20, UnknownException) - STD_EXCEPTION(0x2100, Trap_21, UnknownException) - STD_EXCEPTION(0x2200, Trap_22, UnknownException) - STD_EXCEPTION(0x2300, Trap_23, UnknownException) - STD_EXCEPTION(0x2400, Trap_24, UnknownException) - STD_EXCEPTION(0x2500, Trap_25, UnknownException) - STD_EXCEPTION(0x2600, Trap_26, UnknownException) - STD_EXCEPTION(0x2700, Trap_27, UnknownException) - STD_EXCEPTION(0x2800, Trap_28, UnknownException) - STD_EXCEPTION(0x2900, Trap_29, UnknownException) - STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) - STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) - STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) - STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) - STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) - STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - . = 0x3000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* - * This code initialises the MPC8260 processor core - * (conforms to PowerPC 603e spec) - * Note: expects original MSR contents to be in r5. - */ - - .globl init_8260_core -init_8260_core: - - /* Initialize machine status; enable machine check interrupt */ - /*--------------------------------------------------------------*/ - - li r3, MSR_KERNEL /* Set ME and RI flags */ - rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ -#ifdef DEBUG - rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ -#endif - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - /* Initialise the SYPCR early, and reset the watchdog (if req) */ - /*--------------------------------------------------------------*/ - - lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h - lis r4, CONFIG_SYS_SYPCR@h - ori r4, r4, CONFIG_SYS_SYPCR@l - stw r4, IM_SYPCR@l(r3) -#if defined(CONFIG_WATCHDOG) - li r4, 21868 /* = 0x556c */ - sth r4, IM_SWSR@l(r3) - li r4, -21959 /* = 0xaa39 */ - sth r4, IM_SWSR@l(r3) -#endif /* CONFIG_WATCHDOG */ - - /* Initialize the Hardware Implementation-dependent Registers */ - /* HID0 also contains cache control */ - /*--------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_HID0_INIT@h - ori r3, r3, CONFIG_SYS_HID0_INIT@l - SYNC - mtspr HID0, r3 - - lis r3, CONFIG_SYS_HID0_FINAL@h - ori r3, r3, CONFIG_SYS_HID0_FINAL@l - SYNC - mtspr HID0, r3 - - lis r3, CONFIG_SYS_HID2@h - ori r3, r3, CONFIG_SYS_HID2@l - mtspr HID2, r3 - - /* clear all BAT's */ - /*--------------------------------------------------------------*/ - - li r0, 0 - mtspr DBAT0U, r0 - mtspr DBAT0L, r0 - mtspr DBAT1U, r0 - mtspr DBAT1L, r0 - mtspr DBAT2U, r0 - mtspr DBAT2L, r0 - mtspr DBAT3U, r0 - mtspr DBAT3L, r0 - mtspr IBAT0U, r0 - mtspr IBAT0L, r0 - mtspr IBAT1U, r0 - mtspr IBAT1L, r0 - mtspr IBAT2U, r0 - mtspr IBAT2L, r0 - mtspr IBAT3U, r0 - mtspr IBAT3L, r0 - SYNC - - /* invalidate all tlb's */ - /* */ - /* From the 603e User Manual: "The 603e provides the ability to */ - /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */ - /* instruction invalidates the TLB entry indexed by the EA, and */ - /* operates on both the instruction and data TLBs simultaneously*/ - /* invalidating four TLB entries (both sets in each TLB). The */ - /* index corresponds to bits 15-19 of the EA. To invalidate all */ - /* entries within both TLBs, 32 tlbie instructions should be */ - /* issued, incrementing this field by one each time." */ - /* */ - /* "Note that the tlbia instruction is not implemented on the */ - /* 603e." */ - /* */ - /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */ - /* incrementing by 0x1000 each time. The code below is sort of */ - /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */ - /* */ - /*--------------------------------------------------------------*/ - - li r3, 32 - mtctr r3 - li r3, 0 -1: tlbie r3 - addi r3, r3, 0x1000 - bdnz 1b - SYNC - - /* Done! */ - /*--------------------------------------------------------------*/ - - blr - -#ifdef DEBUG - -/* - * initialise things related to debugging. - * - * must be called after the global offset table (GOT) is initialised - * (GET_GOT) and after cpu_init_f() has executed. - */ - - .globl init_debug -init_debug: - - lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h - - /* Quick and dirty hack to enable the RAM and copy the */ - /* vectors so that we can take exceptions. */ - /*--------------------------------------------------------------*/ - /* write Memory Refresh Prescaler */ - li r4, CONFIG_SYS_MPTPR - sth r4, IM_MPTPR@l(r3) - /* write 60x Refresh Timer */ - li r4, CONFIG_SYS_PSRT - stb r4, IM_PSRT@l(r3) - /* init the 60x SDRAM Mode Register */ - lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@h - ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@l - stw r4, IM_PSDMR@l(r3) - /* write Precharge All Banks command */ - lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@h - ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@l - stw r4, IM_PSDMR@l(r3) - stb r0, 0(0) - /* write eight CBR Refresh commands */ - lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@h - ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@l - stw r4, IM_PSDMR@l(r3) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - /* write Mode Register Write command */ - lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@h - ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@l - stw r4, IM_PSDMR@l(r3) - stb r0, 0(0) - /* write Normal Operation command and enable Refresh */ - lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h - ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l - stw r4, IM_PSDMR@l(r3) - stb r0, 0(0) - /* RAM should now be operational */ - -#define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4) - mflr r3 - GET_GOT - mtlr r3 - lwz r3, GOT(_end_of_vectors) - rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */ - lis r5, VEC_WRD_CNT@h - ori r5, r5, VEC_WRD_CNT@l - mtctr r5 -1: - lwzu r5, -4(r3) - stwu r5, -4(r4) - bdnz 1b - - /* Load the Instruction Address Breakpoint Register (IABR). */ - /* */ - /* The address to load is stored in the first word of dual port */ - /* ram and should be preserved while the power is on, so you */ - /* can plug addresses into that location then reset the cpu and */ - /* this code will load that address into the IABR after the */ - /* reset. */ - /* */ - /* When the program counter matches the contents of the IABR, */ - /* an exception is generated (before the instruction at that */ - /* location completes). The vector for this exception is 0x1300 */ - /*--------------------------------------------------------------*/ - lis r3, CONFIG_SYS_IMMR@h - lwz r3, 0(r3) - mtspr IABR, r3 - - /* Set the entire dual port RAM (where the initial stack */ - /* resides) to a known value - makes it easier to see where */ - /* the stack has been written */ - /*--------------------------------------------------------------*/ - lis r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@h - ori r3, r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@l - li r4, ((CONFIG_SYS_INIT_SP_OFFSET - 4) / 4) - mtctr r4 - lis r4, 0xdeadbeaf@h - ori r4, r4, 0xdeadbeaf@l -1: - stwu r4, -4(r3) - bdnz 1b - - /* Done! */ - /*--------------------------------------------------------------*/ - - blr -#endif - -/* Cache functions. - * - * Note: requires that all cache bits in - * HID0 are in the low half word. - */ - .globl icache_enable -icache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_ICE - lis r4, 0 - ori r4, r4, HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_disable -icache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_ICE|HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31 - blr - - .globl dcache_enable -dcache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_DCE - lis r4, 0 - ori r4, r4, HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_disable -dcache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_DCE|HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3, r5 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mfspr r7,HID0 /* don't do dcbst if dcache is disabled */ - rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31 - cmpwi r7,0 - beq 9f - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ -9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ - rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31 - cmpwi r7,0 - beq 7f - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - cmpwi r0,0 - add r0,r0,r11 - stw r4,0(r3) - beq- 5f - stw r0,0(r4) -5: bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mfmsr r3 /* now that the vectors have */ - lis r7, MSR_IP@h /* relocated into low memory */ - ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ - andc r3, r3, r7 /* (if it was on) */ - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - - mtlr r4 /* restore link register */ - blr diff --git a/arch/powerpc/cpu/mpc8260/traps.c b/arch/powerpc/cpu/mpc8260/traps.c deleted file mode 100644 index cbcf533..0000000 --- a/arch/powerpc/cpu/mpc8260/traps.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * linux/arch/powerpc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include <common.h> -#include <command.h> -#include <kgdb.h> -#include <asm/processor.h> -#include <asm/m8260_pci.h> - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x02000000 - -/* - * Trap & Exception support - */ - -static void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - puts ("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - putc ('\n'); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - putc ('\n'); -} - -void show_regs(struct pt_regs *regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - putc ('\n'); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) { - putc ('\n'); - } - } -} - - -static void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -#ifdef CONFIG_PCI -void dump_pci (void) -{ - - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - printf ("PCI: err status %x err mask %x err ctrl %x\n", - le32_to_cpu (immap->im_pci.pci_esr), - le32_to_cpu (immap->im_pci.pci_emr), - le32_to_cpu (immap->im_pci.pci_ecr)); - printf (" error address %x error data %x ctrl %x\n", - le32_to_cpu (immap->im_pci.pci_eacr), - le32_to_cpu (immap->im_pci.pci_edcr), - le32_to_cpu (immap->im_pci.pci_eccr)); - -} -#endif - -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ -#ifdef CONFIG_PCI - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; -#ifdef DEBUG - dump_pci(); -#endif - /* clear the error in the error status register */ - if(immap->im_pci.pci_esr & cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) { - immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP); - return; - } -#endif - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - puts ("Machine check in kernel mode.\n" - "Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - puts ("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - puts ("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - puts ("Data parity signal\n"); - break; - case (0x80000000>>15): - puts ("Address parity signal\n"); - break; - default: - puts ("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); -#ifdef CONFIG_PCI - dump_pci(); -#endif - panic("machine check"); -} - -void AlignmentException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void ProgramCheckException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void SoftEmuException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void UnknownException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -#if defined(CONFIG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -void DebugException(struct pt_regs *regs) -{ - - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,"ax"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,"a"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds deleted file mode 100644 index 469fc29..0000000 --- a/arch/powerpc/cpu/mpc8260/u-boot.lds +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - arch/powerpc/cpu/mpc8260/start.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index ff31289..2fed4a1 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -140,7 +140,7 @@ ppcDWload:

#ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined -#endif /* CONFIG_SYS_DEFAULT_IMMR */ +#endif /* CONFIG_DEFAULT_IMMR */ #ifndef CONFIG_SYS_IMMR #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR #endif /* CONFIG_SYS_IMMR */ diff --git a/arch/powerpc/include/asm/cpm_8260.h b/arch/powerpc/include/asm/cpm_8260.h deleted file mode 100644 index 4f78186..0000000 --- a/arch/powerpc/include/asm/cpm_8260.h +++ /dev/null @@ -1,795 +0,0 @@ -/* - * MPC8260 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * - * This file contains structures and information for the communication - * processor channels found in the dual port RAM or parameter RAM. - * All CPM control and status is available through the MPC8260 internal - * memory map. See immap.h for details. - */ -#ifndef __CPM_82XX__ -#define __CPM_82XX__ - -#include <asm/immap_8260.h> - -/* CPM Command register. -*/ -#define CPM_CR_RST ((uint)0x80000000) -#define CPM_CR_PAGE ((uint)0x7c000000) -#define CPM_CR_SBLOCK ((uint)0x03e00000) -#define CPM_CR_FLG ((uint)0x00010000) -#define CPM_CR_MCN ((uint)0x00003fc0) -#define CPM_CR_OPCODE ((uint)0x0000000f) - -/* Device sub-block and page codes. -*/ -#define CPM_CR_SCC1_SBLOCK (0x04) -#define CPM_CR_SCC2_SBLOCK (0x05) -#define CPM_CR_SCC3_SBLOCK (0x06) -#define CPM_CR_SCC4_SBLOCK (0x07) -#define CPM_CR_SMC1_SBLOCK (0x08) -#define CPM_CR_SMC2_SBLOCK (0x09) -#define CPM_CR_SPI_SBLOCK (0x0a) -#define CPM_CR_I2C_SBLOCK (0x0b) -#define CPM_CR_TIMER_SBLOCK (0x0f) -#define CPM_CR_RAND_SBLOCK (0x0e) -#define CPM_CR_FCC1_SBLOCK (0x10) -#define CPM_CR_FCC2_SBLOCK (0x11) -#define CPM_CR_FCC3_SBLOCK (0x12) -#define CPM_CR_IDMA1_SBLOCK (0x14) -#define CPM_CR_IDMA2_SBLOCK (0x15) -#define CPM_CR_IDMA3_SBLOCK (0x16) -#define CPM_CR_IDMA4_SBLOCK (0x17) -#define CPM_CR_MCC1_SBLOCK (0x1c) - -#define CPM_CR_SCC1_PAGE (0x00) -#define CPM_CR_SCC2_PAGE (0x01) -#define CPM_CR_SCC3_PAGE (0x02) -#define CPM_CR_SCC4_PAGE (0x03) -#define CPM_CR_SMC1_PAGE (0x07) -#define CPM_CR_SMC2_PAGE (0x08) -#define CPM_CR_SPI_PAGE (0x09) -#define CPM_CR_I2C_PAGE (0x0a) -#define CPM_CR_TIMER_PAGE (0x0a) -#define CPM_CR_RAND_PAGE (0x0a) -#define CPM_CR_FCC1_PAGE (0x04) -#define CPM_CR_FCC2_PAGE (0x05) -#define CPM_CR_FCC3_PAGE (0x06) -#define CPM_CR_IDMA1_PAGE (0x07) -#define CPM_CR_IDMA2_PAGE (0x08) -#define CPM_CR_IDMA3_PAGE (0x09) -#define CPM_CR_IDMA4_PAGE (0x0a) -#define CPM_CR_MCC1_PAGE (0x07) -#define CPM_CR_MCC2_PAGE (0x08) - -/* Some opcodes (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_SET_GADDR ((ushort)0x0008) - -#define mk_cr_cmd(PG, SBC, MCN, OP) \ - ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) - -/* Dual Port RAM addresses. The first 16K is available for almost - * any CPM use, so we put the BDs there. The first 128 bytes are - * used for SMC1 and SMC2 parameter RAM, so we start allocating - * BDs above that. All of this must change when we start - * downloading RAM microcode. - */ -#define CPM_DATAONLY_BASE ((uint)128) -#define CPM_DP_NOSPACE ((uint)0x7fffffff) -#ifndef CONFIG_MPC8272_FAMILY -#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) -#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) -#else /* 8247/48/71/72 */ -#define CPM_DATAONLY_SIZE ((uint)(4 * 1024) - CPM_DATAONLY_BASE) -#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) -#endif /* !CONFIG_MPC8272_FAMILY */ - -/* The number of pages of host memory we allocate for CPM. This is - * done early in kernel initialization to get physically contiguous - * pages. - */ -#define NUM_CPM_HOST_PAGES 2 - - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -extern cpm8260_t *cpmp; /* Pointer to comm processor */ -uint m8260_cpm_dpalloc(uint size, uint align); -uint m8260_cpm_hostalloc(uint size, uint align); -void m8260_cpm_setbrg(uint brg, uint rate); -void m8260_cpm_fastbrg(uint brg, uint rate, int div16); -void m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel); - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ - -/* Function code bits, usually generic to devices. -*/ -#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ -#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ -#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ -#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ -#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ - -/* Parameter RAM offsets from the base. -*/ -#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR -#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */ -#else -#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR -#endif - -#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR -#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) -#else -#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR -#endif - -#define PROFF_SCC1 ((uint)0x8000) -#define PROFF_SCC2 ((uint)0x8100) -#define PROFF_SCC3 ((uint)0x8200) -#define PROFF_SCC4 ((uint)0x8300) -#define PROFF_FCC1 ((uint)0x8400) -#define PROFF_FCC2 ((uint)0x8500) -#define PROFF_FCC3 ((uint)0x8600) -#define PROFF_MCC1 ((uint)0x8700) -#define PROFF_SMC1_BASE ((uint)0x87fc) -#define PROFF_IDMA1_BASE ((uint)0x87fe) -#define PROFF_MCC2 ((uint)0x8800) -#define PROFF_SMC2_BASE ((uint)0x88fc) -#define PROFF_IDMA2_BASE ((uint)0x88fe) -#define PROFF_SPI_BASE ((uint)0x89fc) -#define PROFF_IDMA3_BASE ((uint)0x89fe) -#define PROFF_TIMERS ((uint)0x8ae0) -#define PROFF_REVNUM ((uint)0x8af0) -#define PROFF_RAND ((uint)0x8af8) -#define PROFF_I2C_BASE ((uint)0x8afc) -#define PROFF_IDMA4_BASE ((uint)0x8afe) - -/* The SMCs are relocated to any of the first eight DPRAM pages. - * We will fix these at the first locations of DPRAM, until we - * get some microcode patches :-). - * The parameter ram space for the SMCs is fifty-some bytes, and - * they are required to start on a 64 byte boundary. - */ -#define PROFF_SMC1 (0) -#define PROFF_SMC2 (64) -#define PROFF_SPI ((16*1024) - 128) - -/* Define enough so I can at least use the serial port as a UART. - */ -typedef struct smc_uart { - ushort smc_rbase; /* Rx Buffer descriptor base address */ - ushort smc_tbase; /* Tx Buffer descriptor base address */ - u_char smc_rfcr; /* Rx function code */ - u_char smc_tfcr; /* Tx function code */ - ushort smc_mrblr; /* Max receive buffer length */ - uint smc_rstate; /* Internal */ - uint smc_idp; /* Internal */ - ushort smc_rbptr; /* Internal */ - ushort smc_ibc; /* Internal */ - uint smc_rxtmp; /* Internal */ - uint smc_tstate; /* Internal */ - uint smc_tdp; /* Internal */ - ushort smc_tbptr; /* Internal */ - ushort smc_tbc; /* Internal */ - uint smc_txtmp; /* Internal */ - ushort smc_maxidl; /* Maximum idle characters */ - ushort smc_tmpidl; /* Temporary idle counter */ - ushort smc_brklen; /* Last received break length */ - ushort smc_brkec; /* rcv'd break condition counter */ - ushort smc_brkcr; /* xmt break count register */ - ushort smc_rmask; /* Temporary bit mask */ - uint smc_stmp; /* SDMA Temp */ -} smc_uart_t; - -/* SMC uart mode register (Internal memory map). -*/ -#define SMCMR_REN ((ushort)0x0001) -#define SMCMR_TEN ((ushort)0x0002) -#define SMCMR_DM ((ushort)0x000c) -#define SMCMR_SM_GCI ((ushort)0x0000) -#define SMCMR_SM_UART ((ushort)0x0020) -#define SMCMR_SM_TRANS ((ushort)0x0030) -#define SMCMR_SM_MASK ((ushort)0x0030) -#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ -#define SMCMR_REVD SMCMR_PM_EVEN -#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ -#define SMCMR_BS SMCMR_PEN -#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ -#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ -#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) - -/* SMC Event and Mask register. -*/ -#define SMCM_TXE ((unsigned char)0x10) -#define SMCM_BSY ((unsigned char)0x04) -#define SMCM_TX ((unsigned char)0x02) -#define SMCM_RX ((unsigned char)0x01) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - -/* CPM Ethernet through SCC1. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PSMR) as used by Ethernet. -*/ -#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. - * Common to SCC and FCC. - */ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. - * Common to SCC and FCC. - */ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - uint scc_res1; /* Reserved */ - uint scc_res2; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PSMR when used as a UART. -*/ -#define SCU_PSMR_FLC ((ushort)0x8000) -#define SCU_PSMR_SL ((ushort)0x4000) -#define SCU_PSMR_CL ((ushort)0x3000) -#define SCU_PSMR_UM ((ushort)0x0c00) -#define SCU_PSMR_FRZ ((ushort)0x0200) -#define SCU_PSMR_RZS ((ushort)0x0100) -#define SCU_PSMR_SYN ((ushort)0x0080) -#define SCU_PSMR_DRT ((ushort)0x0040) -#define SCU_PSMR_PEN ((ushort)0x0010) -#define SCU_PSMR_RPM ((ushort)0x000c) -#define SCU_PSMR_REVP ((ushort)0x0008) -#define SCU_PSMR_TPM ((ushort)0x0003) -#define SCU_PSMR_TEVP ((ushort)0x0003) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - -/* SCC as HDLC controller - taken from commproc.h - */ -typedef struct scc_hdlc { - sccp_t sh_genscc; - /* - * HDLC specific parameter RAM - */ - uchar res[4]; /* reserved */ - ulong sh_cmask; /* CRC constant */ - ulong sh_cpres; /* CRC preset */ - ushort sh_disfc; /* discarded frame counter */ - ushort sh_crcec; /* CRC error counter */ - ushort sh_abtsc; /* abort sequence counter */ - ushort sh_nmarc; /* nonmatching address rx cnt */ - ushort sh_retrc; /* frame retransmission cnt */ - ushort sh_mflr; /* maximum frame length reg */ - ushort sh_maxcnt; /* maximum length counter */ - ushort sh_rfthr; /* received frames threshold */ - ushort sh_rfcnt; /* received frames count */ - ushort sh_hmask; /* user defined frm addr mask */ - ushort sh_haddr1; /* user defined frm address 1 */ - ushort sh_haddr2; /* user defined frm address 2 */ - ushort sh_haddr3; /* user defined frm address 3 */ - ushort sh_haddr4; /* user defined frm address 4 */ - ushort tmp; /* temp */ - ushort tmp_mb; /* temp */ -} scc_hdlc_t; - -/* How about some FCCs..... -*/ -#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) -#define FCC_GFMR_DIAG_LE ((uint)0x40000000) -#define FCC_GFMR_DIAG_AE ((uint)0x80000000) -#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) -#define FCC_GFMR_TCI ((uint)0x20000000) -#define FCC_GFMR_TRX ((uint)0x10000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_CDP ((uint)0x04000000) -#define FCC_GFMR_CTSP ((uint)0x02000000) -#define FCC_GFMR_CDS ((uint)0x01000000) -#define FCC_GFMR_CTSS ((uint)0x00800000) -#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) -#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) -#define FCC_GFMR_SYNL_8 ((uint)0x00008000) -#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) -#define FCC_GFMR_RTSM ((uint)0x00002000) -#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) -#define FCC_GFMR_REVD ((uint)0x00000400) -#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) -#define FCC_GFMR_TCRC_16 ((uint)0x00000000) -#define FCC_GFMR_TCRC_32 ((uint)0x00000080) -#define FCC_GFMR_ENR ((uint)0x00000020) -#define FCC_GFMR_ENT ((uint)0x00000010) -#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) -#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) -#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) - -/* Generic FCC parameter ram. -*/ -typedef struct fcc_param { - ushort fcc_riptr; /* Rx Internal temp pointer */ - ushort fcc_tiptr; /* Tx Internal temp pointer */ - ushort fcc_res1; - ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ - uint fcc_rstate; /* Upper byte is Func code, must be set */ - uint fcc_rbase; /* Receive BD base */ - ushort fcc_rbdstat; /* RxBD status */ - ushort fcc_rbdlen; /* RxBD down counter */ - uint fcc_rdptr; /* RxBD internal data pointer */ - uint fcc_tstate; /* Upper byte is Func code, must be set */ - uint fcc_tbase; /* Transmit BD base */ - ushort fcc_tbdstat; /* TxBD status */ - ushort fcc_tbdlen; /* TxBD down counter */ - uint fcc_tdptr; /* TxBD internal data pointer */ - uint fcc_rbptr; /* Rx BD Internal buf pointer */ - uint fcc_tbptr; /* Tx BD Internal buf pointer */ - uint fcc_rcrc; /* Rx temp CRC */ - uint fcc_res2; - uint fcc_tcrc; /* Tx temp CRC */ -} fccp_t; - - -/* Ethernet controller through FCC. -*/ -typedef struct fcc_enet { - fccp_t fen_genfcc; - uint fen_statbuf; /* Internal status buffer */ - uint fen_camptr; /* CAM address */ - uint fen_cmask; /* Constant mask for CRC */ - uint fen_cpres; /* Preset CRC */ - uint fen_crcec; /* CRC Error counter */ - uint fen_alec; /* alignment error counter */ - uint fen_disfc; /* discard frame counter */ - ushort fen_retlim; /* Retry limit */ - ushort fen_retcnt; /* Retry counter */ - ushort fen_pper; /* Persistence */ - ushort fen_boffcnt; /* backoff counter */ - uint fen_gaddrh; /* Group address filter, high 32-bits */ - uint fen_gaddrl; /* Group address filter, low 32-bits */ - ushort fen_tfcstat; /* out of sequence TxBD */ - ushort fen_tfclen; - uint fen_tfcptr; - ushort fen_mflr; /* Maximum frame length (1518) */ - ushort fen_paddrh; /* MAC address */ - ushort fen_paddrm; - ushort fen_paddrl; - ushort fen_ibdcount; /* Internal BD counter */ - ushort fen_idbstart; /* Internal BD start pointer */ - ushort fen_ibdend; /* Internal BD end pointer */ - ushort fen_txlen; /* Internal Tx frame length counter */ - uint fen_ibdbase[8]; /* Internal use */ - uint fen_iaddrh; /* Individual address filter */ - uint fen_iaddrl; - ushort fen_minflr; /* Minimum frame length (64) */ - ushort fen_taddrh; /* Filter transfer MAC address */ - ushort fen_taddrm; - ushort fen_taddrl; - ushort fen_padptr; /* Pointer to pad byte buffer */ - ushort fen_cftype; /* control frame type */ - ushort fen_cfrange; /* control frame range */ - ushort fen_maxb; /* maximum BD count */ - ushort fen_maxd1; /* Max DMA1 length (1520) */ - ushort fen_maxd2; /* Max DMA2 length (1520) */ - ushort fen_maxd; /* internal max DMA count */ - ushort fen_dmacnt; /* internal DMA counter */ - uint fen_octc; /* Total octect counter */ - uint fen_colc; /* Total collision counter */ - uint fen_broc; /* Total broadcast packet counter */ - uint fen_mulc; /* Total multicast packet count */ - uint fen_uspc; /* Total packets < 64 bytes */ - uint fen_frgc; /* Total packets < 64 bytes with errors */ - uint fen_ospc; /* Total packets > 1518 */ - uint fen_jbrc; /* Total packets > 1518 with errors */ - uint fen_p64c; /* Total packets == 64 bytes */ - uint fen_p65c; /* Total packets 64 < bytes <= 127 */ - uint fen_p128c; /* Total packets 127 < bytes <= 255 */ - uint fen_p256c; /* Total packets 256 < bytes <= 511 */ - uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ - uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ - uint fen_cambuf; /* Internal CAM buffer poiner */ - ushort fen_rfthr; /* Received frames threshold */ - ushort fen_rfcnt; /* Received frames count */ -} fcc_enet_t; - -/* FCC Event/Mask register as used by Ethernet. -*/ -#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ -#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ -#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ -#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* FCC Mode Register (FPSMR) as used by Ethernet. -*/ -#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ -#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ -#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ -#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ -#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ -#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ -#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ -#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ -#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ -#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ -#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ -#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ -#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ -#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ - -/* IIC parameter RAM. -*/ -typedef struct iic { - ushort iic_rbase; /* Rx Buffer descriptor base address */ - ushort iic_tbase; /* Tx Buffer descriptor base address */ - u_char iic_rfcr; /* Rx function code */ - u_char iic_tfcr; /* Tx function code */ - ushort iic_mrblr; /* Max receive buffer length */ - uint iic_rstate; /* Internal */ - uint iic_rdp; /* Internal */ - ushort iic_rbptr; /* Internal */ - ushort iic_rbc; /* Internal */ - uint iic_rxtmp; /* Internal */ - uint iic_tstate; /* Internal */ - uint iic_tdp; /* Internal */ - ushort iic_tbptr; /* Internal */ - ushort iic_tbc; /* Internal */ - uint iic_txtmp; /* Internal */ -} iic_t; - -/* SPI parameter RAM. -*/ -typedef struct spi { - ushort spi_rbase; /* Rx Buffer descriptor base address */ - ushort spi_tbase; /* Tx Buffer descriptor base address */ - u_char spi_rfcr; /* Rx function code */ - u_char spi_tfcr; /* Tx function code */ - ushort spi_mrblr; /* Max receive buffer length */ - uint spi_rstate; /* Internal */ - uint spi_rdp; /* Internal */ - ushort spi_rbptr; /* Internal */ - ushort spi_rbc; /* Internal */ - uint spi_rxtmp; /* Internal */ - uint spi_tstate; /* Internal */ - uint spi_tdp; /* Internal */ - ushort spi_tbptr; /* Internal */ - ushort spi_tbc; /* Internal */ - uint spi_txtmp; /* Internal */ - uint spi_res; /* Tx temp. */ - uint spi_res1[4]; /* SDMA temp. */ -} spi_t; - -/* SPI Mode register. -*/ -#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ -#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ -#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ -#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ -#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ -#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ -#define SPMODE_EN ((ushort)0x0100) /* Enable */ -#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ -#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ - -#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) -#define SPMODE_PM(x) ((x) &0xF) - -/* SPI Event/Mask register. -*/ -#define SPI_EMASK 0x37 /* Event Mask */ -#define SPI_MME 0x20 /* Multi-Master Error */ -#define SPI_TXE 0x10 /* Transmit Error */ -#define SPI_BSY 0x04 /* Busy */ -#define SPI_TXB 0x02 /* Tx Buffer Empty */ -#define SPI_RXB 0x01 /* RX Buffer full/closed */ - -#define SPI_STR 0x80 /* SPCOM: Start transmit */ - -#define SPI_EB ((u_char)0x10) /* big endian byte order */ - -#define BD_IIC_START ((ushort)0x0400) - -#endif /* __CPM_82XX__ */ diff --git a/arch/powerpc/include/asm/immap_8260.h b/arch/powerpc/include/asm/immap_8260.h deleted file mode 100644 index c7021a7..0000000 --- a/arch/powerpc/include/asm/immap_8260.h +++ /dev/null @@ -1,604 +0,0 @@ -/* - * MPC8260 Internal Memory Map - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * - * The Internal Memory Map of the 8260. I don't know how generic - * this will be, as I don't have any knowledge of the subsequent - * parts at this time. I copied this from the 8xx_immap.h. - */ -#ifndef __IMMAP_82XX__ -#define __IMMAP_82XX__ - -/* System configuration registers. -*/ -typedef struct sys_conf { - uint sc_siumcr; - uint sc_sypcr; - char res1[6]; - ushort sc_swsr; - char res2[20]; - uint sc_bcr; - u_char sc_ppc_acr; - char res3[3]; - uint sc_ppc_alrh; - uint sc_ppc_alrl; - u_char sc_lcl_acr; - char res4[3]; - uint sc_lcl_alrh; - uint sc_lcl_alrl; - uint sc_tescr1; - uint sc_tescr2; - uint sc_ltescr1; - uint sc_ltescr2; - uint sc_pdtea; - u_char sc_pdtem; - char res5[3]; - uint sc_ldtea; - u_char sc_ldtem; - char res6[163]; -} sysconf8260_t; - - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - uint memc_br0; - uint memc_or0; - uint memc_br1; - uint memc_or1; - uint memc_br2; - uint memc_or2; - uint memc_br3; - uint memc_or3; - uint memc_br4; - uint memc_or4; - uint memc_br5; - uint memc_or5; - uint memc_br6; - uint memc_or6; - uint memc_br7; - uint memc_or7; - uint memc_br8; - uint memc_or8; - uint memc_br9; - uint memc_or9; - uint memc_br10; - uint memc_or10; - uint memc_br11; - uint memc_or11; - char res1[8]; - uint memc_mar; - char res2[4]; - uint memc_mamr; - uint memc_mbmr; - uint memc_mcmr; - char res3[8]; - ushort memc_mptpr; - char res4[2]; - uint memc_mdr; - char res5[4]; - uint memc_psdmr; - uint memc_lsdmr; - u_char memc_purt; - char res6[3]; - u_char memc_psrt; - char res7[3]; - u_char memc_lurt; - char res8[3]; - u_char memc_lsrt; - char res9[3]; - uint memc_immr; - uint memc_pcibr0; - uint memc_pcibr1; - char res10[16]; - uint memc_pcimsk0; - uint memc_pcimsk1; - char res11[52]; -} memctl8260_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - char res1[32]; - ushort sit_tmcntsc; - char res2[2]; - uint sit_tmcnt; - char res3[4]; - uint sit_tmcntal; - char res4[16]; - ushort sit_piscr; - char res5[2]; - uint sit_pitc; - uint sit_pitr; - char res6[94]; - char res7[390]; -} sit8260_t; - -/* PCI - */ -typedef struct pci_config { - uint pci_omisr; - uint pci_ominr; - char res1[8]; - uint pci_ifqpr; - uint pci_ofqpr; - char res2[8]; - uint pci_imr0; - uint pci_imr1; - uint pci_omr0; - uint pci_omr1; - uint pci_odr; - char res3[4]; - uint pci_idr; - char res4[20]; - uint pci_imisr; - uint pci_imimr; - char res5[24]; - uint pci_ifhpr; - char res5_2[4]; - uint pci_iftpr; - char res6[4]; - uint pci_iphpr; - char res6_2[4]; - uint pci_iptpr; - char res7[4]; - uint pci_ofhpr; - char res7_2[4]; - uint pci_oftpr; - char res8[4]; - uint pci_ophpr; - char res8_2[4]; - uint pci_optpr; - char res9[8]; - uint pci_mucr; - char res10[8]; - uint pci_qbar; - char res11[12]; - uint pci_dmamr0; - uint pci_dmasr0; - uint pci_dmacdar0; - char res12[4]; - uint pci_dmasar0; - char res13[4]; - uint pci_dmadar0; - char res14[4]; - uint pci_dmabcr0; - uint pci_dmandar0; - char res15[88]; - uint pci_dmamr1; - uint pci_dmasr1; - uint pci_dmacdar1; - char res16[4]; - uint pci_dmasar1; - char res17[4]; - uint pci_dmadar1; - char res18[4]; - uint pci_dmabcr1; - uint pci_dmandar1; - char res19[88]; - uint pci_dmamr2; - uint pci_dmasr2; - uint pci_dmacdar2; - char res20[4]; - uint pci_dmasar2; - char res21[4]; - uint pci_dmadar2; - char res22[4]; - uint pci_dmabcr2; - uint pci_dmandar2; - char res23[88]; - uint pci_dmamr3; - uint pci_dmasr3; - uint pci_dmacdar3; - char res24[4]; - uint pci_dmasar3; - char res25[4]; - uint pci_dmadar3; - char res26[4]; - uint pci_dmabcr3; - uint pci_dmandar3; - char res27[344]; - uint pci_potar0; - char res28[4]; - uint pci_pobar0; - char res29[4]; - uint pci_pocmr0; - char res30[4]; - uint pci_potar1; - char res31[4]; - uint pci_pobar1; - char res32[4]; - uint pci_pocmr1; - char res33[4]; - uint pci_potar2; - char res34[4]; - uint pci_pobar2; - char res35[4]; - uint pci_pocmr2; - char res36[52]; - uint pci_ptcr; - uint pci_gpcr; - uint pci_gcr; - uint pci_esr; - uint pci_emr; - uint pci_ecr; - uint pci_eacr; - char res37[4]; - uint pci_edcr; - char res38[4]; - uint pci_eccr; - char res39[44]; - uint pci_pitar1; - char res40[4]; - uint pci_pibar1; - char res41[4]; - uint pci_picmr1; - char res42[4]; - uint pci_pitar0; - char res43[4]; - uint pci_pibar0; - char res44[4]; - uint pci_picmr0; - char res45[4]; - uint pci_cfg_addr; - uint pci_cfg_data; - uint pci_int_ack; - char res46[756]; -}pci8260_t; -#define PISCR_PIRQ_MASK ((ushort)0xff00) -#define PISCR_PS ((ushort)0x0080) -#define PISCR_PIE ((ushort)0x0004) -#define PISCR_PTF ((ushort)0x0002) -#define PISCR_PTE ((ushort)0x0001) - -/* Interrupt Controller. -*/ -typedef struct interrupt_controller { - ushort ic_sicr; - char res1[2]; - uint ic_sivec; - uint ic_sipnrh; - uint ic_sipnrl; - uint ic_siprr; - uint ic_scprrh; - uint ic_scprrl; - uint ic_simrh; - uint ic_simrl; - uint ic_siexr; - char res2[88]; -} intctl8260_t; - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - uint car_sccr; - char res1[4]; - uint car_scmr; - char res2[4]; - uint car_rsr; - uint car_rmr; - char res[104]; -} car8260_t; - -/* Input/Output Port control/status registers. - * Names consistent with processor manual, although they are different - * from the original 8xx names....... - */ -typedef struct io_port { - uint iop_pdira; - uint iop_ppara; - uint iop_psora; - uint iop_podra; - uint iop_pdata; - char res1[12]; - uint iop_pdirb; - uint iop_pparb; - uint iop_psorb; - uint iop_podrb; - uint iop_pdatb; - char res2[12]; - uint iop_pdirc; - uint iop_pparc; - uint iop_psorc; - uint iop_podrc; - uint iop_pdatc; - char res3[12]; - uint iop_pdird; - uint iop_ppard; - uint iop_psord; - uint iop_podrd; - uint iop_pdatd; - char res4[12]; -} iop8260_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - u_char cpmt_tgcr1; - char res1[3]; - u_char cpmt_tgcr2; - char res2[11]; - ushort cpmt_tmr1; - ushort cpmt_tmr2; - ushort cpmt_trr1; - ushort cpmt_trr2; - ushort cpmt_tcr1; - ushort cpmt_tcr2; - ushort cpmt_tcn1; - ushort cpmt_tcn2; - ushort cpmt_tmr3; - ushort cpmt_tmr4; - ushort cpmt_trr3; - ushort cpmt_trr4; - ushort cpmt_tcr3; - ushort cpmt_tcr4; - ushort cpmt_tcn3; - ushort cpmt_tcn4; - ushort cpmt_ter1; - ushort cpmt_ter2; - ushort cpmt_ter3; - ushort cpmt_ter4; - char res3[584]; -} cpmtimer8260_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - char res0[24]; - u_char sdma_sdsr; - char res1[3]; - u_char sdma_sdmr; - char res2[3]; - u_char sdma_idsr1; - char res3[3]; - u_char sdma_idmr1; - char res4[3]; - u_char sdma_idsr2; - char res5[3]; - u_char sdma_idmr2; - char res6[3]; - u_char sdma_idsr3; - char res7[3]; - u_char sdma_idmr3; - char res8[3]; - u_char sdma_idsr4; - char res9[3]; - u_char sdma_idmr4; - char res10[707]; -} sdma8260_t; - -/* Fast controllers -*/ -typedef struct fcc { - uint fcc_gfmr; - uint fcc_fpsmr; - ushort fcc_ftodr; - char res1[2]; - ushort fcc_fdsr; - char res2[2]; - ushort fcc_fcce; - char res3[2]; - ushort fcc_fccm; - char res4[2]; - u_char fcc_fccs; - char res5[3]; - u_char fcc_ftirr_phy[4]; -} fcc_t; - -/* Fast controllers continued - */ -typedef struct fcc_c { - uint fcc_firper; - uint fcc_firer; - uint fcc_firsr_hi; - uint fcc_firsr_lo; - u_char fcc_gfemr; - char res1[15]; -} fcc_c_t; - -/* TC Layer - */ -typedef struct tclayer { - ushort tc_tcmode; - ushort tc_cdsmr; - ushort tc_tcer; - ushort tc_rcc; - ushort tc_tcmr; - ushort tc_fcc; - ushort tc_ccc; - ushort tc_icc; - ushort tc_tcc; - ushort tc_ecc; - char res1[12]; -} tclayer_t; - -/* I2C -*/ -typedef struct i2c { - u_char i2c_i2mod; - char res1[3]; - u_char i2c_i2add; - char res2[3]; - u_char i2c_i2brg; - char res3[3]; - u_char i2c_i2com; - char res4[3]; - u_char i2c_i2cer; - char res5[3]; - u_char i2c_i2cmr; - char res6[331]; -} i2c8260_t; - -typedef struct scc { /* Serial communication channels */ - uint scc_gsmrl; - uint scc_gsmrh; - ushort scc_psmr; - char res1[2]; - ushort scc_todr; - ushort scc_dsr; - ushort scc_scce; - char res2[2]; - ushort scc_sccm; - char res3; - u_char scc_sccs; - char res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - char res1[2]; - ushort smc_smcmr; - char res2[2]; - u_char smc_smce; - char res3[3]; - u_char smc_smcm; - char res4[5]; -} smc_t; - -/* Serial Peripheral Interface. -*/ -typedef struct im_spi { - ushort spi_spmode; - char res1[4]; - u_char spi_spie; - char res2[3]; - u_char spi_spim; - char res3[2]; - u_char spi_spcom; - char res4[82]; -} im_spi_t; - -/* CPM Mux. -*/ -typedef struct cpmux { - u_char cmx_si1cr; - char res1; - u_char cmx_si2cr; - char res2; - uint cmx_fcr; - uint cmx_scr; - u_char cmx_smr; - char res3; - ushort cmx_uar; - char res4[16]; -} cpmux_t; - -/* SIRAM control -*/ -typedef struct siram { - ushort si_amr; - ushort si_bmr; - ushort si_cmr; - ushort si_dmr; - u_char si_gmr; - char res1; - u_char si_cmdr; - char res2; - u_char si_str; - char res3; - ushort si_rsr; -} siramctl_t; - -typedef struct mcc { - ushort mcc_mcce; - char res1[2]; - ushort mcc_mccm; - char res2[2]; - u_char mcc_mccf; - char res3[7]; -} mcc_t; - -typedef struct comm_proc { - uint cp_cpcr; - uint cp_rccr; - char res1[14]; - ushort cp_rter; - char res2[2]; - ushort cp_rtmr; - ushort cp_rtscr; - char res3[2]; - uint cp_rtsr; - char res4[12]; -} cpm8260_t; - -/* ...and the whole thing wrapped up.... -*/ -typedef struct immap { - /* Some references are into the unique and known dpram spaces, - * others are from the generic base. - */ - union { - struct { - u_char im_dpram1[16 * 1024]; - char res1[16 * 1024]; - u_char im_dpram2[4 * 1024]; - char res2[8 * 1024]; - u_char im_dpram3[4 * 1024]; - char res3[16 * 1024]; - }; - u8 im_dprambase[64 * 1024]; - u16 im_dprambase16[32 * 1024]; - }; - - sysconf8260_t im_siu_conf; /* SIU Configuration */ - memctl8260_t im_memctl; /* Memory Controller */ - sit8260_t im_sit; /* System Integration Timers */ - pci8260_t im_pci; /* PCI Configuration */ - intctl8260_t im_intctl; /* Interrupt Controller */ - car8260_t im_clkrst; /* Clocks and reset */ - iop8260_t im_ioport; /* IO Port control/status */ - cpmtimer8260_t im_cpmtimer; /* CPM timers */ - sdma8260_t im_sdma; /* SDMA control/status */ - - fcc_t im_fcc[3]; /* Three FCCs */ - - char res4[32]; - fcc_c_t im_fcc_c[3]; /* Continued FCCs */ - char res4a[32]; - - tclayer_t im_tclayer[8]; /* Eight TCLayers */ - ushort tc_tcgsr; - ushort tc_tcger; - - /* First set of baud rate generators. - */ - char res4b[236]; - uint im_brgc5; - uint im_brgc6; - uint im_brgc7; - uint im_brgc8; - - char res5[608]; - - i2c8260_t im_i2c; /* I2C control/status */ - cpm8260_t im_cpm; /* Communication processor */ - - /* Second set of baud rate generators. - */ - uint im_brgc1; - uint im_brgc2; - uint im_brgc3; - uint im_brgc4; - - scc_t im_scc[4]; /* Four SCCs */ - smc_t im_smc[2]; /* Couple of SMCs */ - im_spi_t im_spi; /* A SPI */ - cpmux_t im_cpmux; /* CPM clock route mux */ - siramctl_t im_siramctl1; /* First SI RAM Control */ - mcc_t im_mcc1; /* First MCC */ - siramctl_t im_siramctl2; /* Second SI RAM Control */ - mcc_t im_mcc2; /* Second MCC */ - - char res6[1184]; - - ushort im_si1txram[256]; - char res7[512]; - ushort im_si1rxram[256]; - char res8[512]; - ushort im_si2txram[256]; - char res9[512]; - ushort im_si2rxram[256]; - char res10[512]; - char res11[4096]; -} immap_t; - -#endif /* __IMMAP_82XX__ */ diff --git a/arch/powerpc/include/asm/iopin_8260.h b/arch/powerpc/include/asm/iopin_8260.h deleted file mode 100644 index 617584d..0000000 --- a/arch/powerpc/include/asm/iopin_8260.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * MPC8260 I/O port pin manipulation functions - */ - -#ifndef _ASM_IOPIN_8260_H_ -#define _ASM_IOPIN_8260_H_ - -#include <linux/types.h> -#include <asm/immap_8260.h> - -#ifdef __KERNEL__ - -typedef - struct { - u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ - u_char pin:5; /* port pin (0-31) */ - u_char flag:1; /* for whatever */ - } -iopin_t; - -#define IOPIN_PORTA 0 -#define IOPIN_PORTB 1 -#define IOPIN_PORTC 2 -#define IOPIN_PORTD 3 - -static __inline__ void -iopin_set_high(iopin_t *iopin) -{ - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; - datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -static __inline__ void -iopin_set_low(iopin_t *iopin) -{ - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; - datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -static __inline__ uint -iopin_is_high(iopin_t *iopin) -{ - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; - return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -static __inline__ uint -iopin_is_low(iopin_t *iopin) -{ - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; - return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -static __inline__ void -iopin_set_out(iopin_t *iopin) -{ - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; - dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -static __inline__ void -iopin_set_in(iopin_t *iopin) -{ - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; - dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -static __inline__ uint -iopin_is_out(iopin_t *iopin) -{ - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; - return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -static __inline__ uint -iopin_is_in(iopin_t *iopin) -{ - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; - return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -static __inline__ void -iopin_set_odr(iopin_t *iopin) -{ - volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; - odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -static __inline__ void -iopin_set_act(iopin_t *iopin) -{ - volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; - odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -static __inline__ uint -iopin_is_odr(iopin_t *iopin) -{ - volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; - return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -static __inline__ uint -iopin_is_act(iopin_t *iopin) -{ - volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; - return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -static __inline__ void -iopin_set_ded(iopin_t *iopin) -{ - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; - parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -static __inline__ void -iopin_set_gen(iopin_t *iopin) -{ - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; - parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -static __inline__ uint -iopin_is_ded(iopin_t *iopin) -{ - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; - return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -static __inline__ uint -iopin_is_gen(iopin_t *iopin) -{ - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; - return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -static __inline__ void -iopin_set_opt2(iopin_t *iopin) -{ - volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; - sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -static __inline__ void -iopin_set_opt1(iopin_t *iopin) -{ - volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; - sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -static __inline__ uint -iopin_is_opt2(iopin_t *iopin) -{ - volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; - return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -static __inline__ uint -iopin_is_opt1(iopin_t *iopin) -{ - volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; - return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IOPIN_8260_H_ */ diff --git a/arch/powerpc/include/asm/m8260_pci.h b/arch/powerpc/include/asm/m8260_pci.h deleted file mode 100644 index 6daca4f..0000000 --- a/arch/powerpc/include/asm/m8260_pci.h +++ /dev/null @@ -1,165 +0,0 @@ -#ifndef _PPC_KERNEL_M8260_PCI_H -#define _PPC_KERNEL_M8260_PCI_H - -#define M8265_PCIBR0 0x101ac -#define M8265_PCIBR1 0x101b0 -#define M8265_PCIMSK0 0x101c4 -#define M8265_PCIMSK1 0x101c8 - -/* Bit definitions for PCIBR registers */ - -#define PCIBR_ENABLE 0x00000001 - -/* Bit definitions for PCIMSK registers */ - -#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */ -#define PCIMSK_64KB 0xFFFF0000 -#define PCIMSK_128KB 0xFFFE0000 -#define PCIMSK_256KB 0xFFFC0000 -#define PCIMSK_512KB 0xFFF80000 -#define PCIMSK_1MB 0xFFF00000 -#define PCIMSK_2MB 0xFFE00000 -#define PCIMSK_4MB 0xFFC00000 -#define PCIMSK_8MB 0xFF800000 -#define PCIMSK_16MB 0xFF000000 -#define PCIMSK_32MB 0xFE000000 -#define PCIMSK_64MB 0xFC000000 -#define PCIMSK_128MB 0xF8000000 -#define PCIMSK_256MB 0xF0000000 -#define PCIMSK_512MB 0xE0000000 -#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */ - - -#define M826X_SCCR_PCI_MODE_EN 0x100 - - -/* - * Outbound ATU registers (3 sets). These registers control how 60x bus (local) - * addresses are translated to PCI addresses when the MPC826x is a PCI bus - * master (initiator). - */ - -#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ -#define POTAR_REG1 0x10818 -#define POTAR_REG2 0x10830 - -#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ -#define POBAR_REG1 0x10820 -#define POBAR_REG2 0x10838 - -#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ -#define POCMR_REG1 0x10828 -#define POCMR_REG2 0x10840 - -/* Bit definitions for POMCR registers */ - -#define POCMR_MASK_4KB 0x000FFFFF -#define POCMR_MASK_8KB 0x000FFFFE -#define POCMR_MASK_16KB 0x000FFFFC -#define POCMR_MASK_32KB 0x000FFFF8 -#define POCMR_MASK_64KB 0x000FFFF0 -#define POCMR_MASK_128KB 0x000FFFE0 -#define POCMR_MASK_256KB 0x000FFFC0 -#define POCMR_MASK_512KB 0x000FFF80 -#define POCMR_MASK_1MB 0x000FFF00 -#define POCMR_MASK_2MB 0x000FFE00 -#define POCMR_MASK_4MB 0x000FFC00 -#define POCMR_MASK_8MB 0x000FF800 -#define POCMR_MASK_16MB 0x000FF000 -#define POCMR_MASK_32MB 0x000FE000 -#define POCMR_MASK_64MB 0x000FC000 -#define POCMR_MASK_128MB 0x000F8000 -#define POCMR_MASK_256MB 0x000F0000 -#define POCMR_MASK_512MB 0x000E0000 -#define POCMR_MASK_1GB 0x000C0000 - -#define POCMR_ENABLE 0x80000000 -#define POCMR_PCI_IO 0x40000000 -#define POCMR_PREFETCH_EN 0x20000000 - -/* Soft PCI reset */ - -#define PCI_GCR_REG 0x10880 - -/* Bit definitions for PCI_GCR registers */ - -#define PCIGCR_PCI_BUS_EN 0x1 - -/* - * Inbound ATU registers (2 sets). These registers control how PCI addresses - * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target. - */ - -#define PITAR_REG1 0x108D0 -#define PIBAR_REG1 0x108D8 -#define PICMR_REG1 0x108E0 -#define PITAR_REG0 0x108E8 -#define PIBAR_REG0 0x108F0 -#define PICMR_REG0 0x108F8 - -/* Bit definitions for PCI Inbound Comparison Mask registers */ - -#define PICMR_MASK_4KB 0x000FFFFF -#define PICMR_MASK_8KB 0x000FFFFE -#define PICMR_MASK_16KB 0x000FFFFC -#define PICMR_MASK_32KB 0x000FFFF8 -#define PICMR_MASK_64KB 0x000FFFF0 -#define PICMR_MASK_128KB 0x000FFFE0 -#define PICMR_MASK_256KB 0x000FFFC0 -#define PICMR_MASK_512KB 0x000FFF80 -#define PICMR_MASK_1MB 0x000FFF00 -#define PICMR_MASK_2MB 0x000FFE00 -#define PICMR_MASK_4MB 0x000FFC00 -#define PICMR_MASK_8MB 0x000FF800 -#define PICMR_MASK_16MB 0x000FF000 -#define PICMR_MASK_32MB 0x000FE000 -#define PICMR_MASK_64MB 0x000FC000 -#define PICMR_MASK_128MB 0x000F8000 -#define PICMR_MASK_256MB 0x000F0000 -#define PICMR_MASK_512MB 0x000E0000 -#define PICMR_MASK_1GB 0x000C0000 - -#define PICMR_ENABLE 0x80000000 -#define PICMR_NO_SNOOP_EN 0x40000000 -#define PICMR_PREFETCH_EN 0x20000000 - -/* PCI error Registers */ - -#define PCI_ERROR_STATUS_REG 0x10884 -#define PCI_ERROR_MASK_REG 0x10888 -#define PCI_ERROR_CONTROL_REG 0x1088C -#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 -#define PCI_ERROR_DATA_CAPTURE_REG 0x10898 -#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 - -/* PCI error Register bit defines */ - -#define PCI_ERROR_PCI_ADDR_PAR 0x00000001 -#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 -#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 -#define PCI_ERROR_PCI_NO_RSP 0x00000008 -#define PCI_ERROR_PCI_TAR_ABT 0x00000010 -#define PCI_ERROR_PCI_SERR 0x00000020 -#define PCI_ERROR_PCI_PERR_RD 0x00000040 -#define PCI_ERROR_PCI_PERR_WR 0x00000080 -#define PCI_ERROR_I2O_OFQO 0x00000100 -#define PCI_ERROR_I2O_IPQO 0x00000200 -#define PCI_ERROR_IRA 0x00000400 -#define PCI_ERROR_NMI 0x00000800 -#define PCI_ERROR_I2O_DBMC 0x00001000 - -/* - * Register pair used to generate configuration cycles on the PCI bus - * and access the MPC826x's own PCI configuration registers. - */ - -#define PCI_CFG_ADDR_REG 0x10900 -#define PCI_CFG_DATA_REG 0x10904 - -/* Bus parking decides where the bus control sits when idle */ -/* If modifying memory controllers for PCI park on the core */ - -#define PPC_ACR_BUS_PARK_CORE 0x6 -#define PPC_ACR_BUS_PARK_PCI 0x3 - -#endif /* _PPC_KERNEL_M8260_PCI_H */ diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h index 8abe727..f23ed3e 100644 --- a/arch/powerpc/include/asm/ppc.h +++ b/arch/powerpc/include/asm/ppc.h @@ -19,11 +19,6 @@ #include <mpc5xxx.h> #elif defined(CONFIG_MPC512X) #include <asm/immap_512x.h> -#elif defined(CONFIG_MPC8260) -#if defined(CONFIG_MPC8247) || defined(CONFIG_MPC8272) -#define CONFIG_MPC8272_FAMILY 1 -#endif -#include <asm/immap_8260.h> #endif #ifdef CONFIG_MPC86xx #include <mpc86xx.h> diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index aaabae0..6549a09 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1364,9 +1364,6 @@ int prt_8260_clks(void); #if defined(CONFIG_WALNUT) #define _machine _MACH_walnut #define have_of 0 -#elif defined(CONFIG_MPC8260) -#define _machine _MACH_8260 -#define have_of 0 #else #error "Machine not defined correctly" #endif diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h index c151b54..2767c05 100644 --- a/arch/powerpc/include/asm/status_led.h +++ b/arch/powerpc/include/asm/status_led.h @@ -9,9 +9,7 @@

/* if not overridden */ #ifndef CONFIG_LED_STATUS_BOARD_SPECIFIC -# if defined(CONFIG_MPC8260) -# include <mpc8260.h> -# elif defined(CONFIG_5xx) +# if defined(CONFIG_5xx) # include <mpc5xx.h> # else # error CPU specific Status LED header file missing. diff --git a/arch/powerpc/lib/Kconfig b/arch/powerpc/lib/Kconfig deleted file mode 100644 index 987cec9..0000000 --- a/arch/powerpc/lib/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -config CMD_IMMAP - bool "Enable various commands to dump IMMR information" - help - This enables various commands such as: - - siuinfo - print System Interface Unit (SIU) registers - memcinfo - print Memory Controller registers - sitinfo - print System Integration Timers (SIT) registers diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 5e55385..4dd6b56 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_BAT_RW) += bat_rw.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += extable.o -obj-$(CONFIG_CMD_IMMAP) += immap.o obj-y += interrupts.o obj-$(CONFIG_CMD_KGDB) += kgdb.o obj-y += stack.o diff --git a/arch/powerpc/lib/immap.c b/arch/powerpc/lib/immap.c deleted file mode 100644 index 85527a1..0000000 --- a/arch/powerpc/lib/immap.c +++ /dev/null @@ -1,629 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8xx/MPC8260 Internal Memory Map Functions - */ - -#include <common.h> -#include <command.h> - -#if defined(CONFIG_MPC8260) - -#include <asm/immap_8260.h> -#include <asm/cpm_8260.h> -#include <asm/iopin_8260.h> - -DECLARE_GLOBAL_DATA_PTR; - -static void -unimplemented ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf ("Sorry, but the '%s' command has not been implemented\n", - cmdtp->name); -} - -int -do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#if defined(CONFIG_MPC8260) - volatile sysconf8260_t *sc = &immap->im_siu_conf; -#endif - - printf ("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr); -#if defined(CONFIG_MPC8260) - printf ("BCR = %08x\n", sc->sc_bcr); - printf ("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n", - sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl); - printf ("L_ACR = %02x L_ALRH= %08x L_ALRL= %08x\n", - sc->sc_lcl_acr, sc->sc_lcl_alrh, sc->sc_lcl_alrl); - printf ("PTESR1= %08x PTESR2= %08x\n", sc->sc_tescr1, sc->sc_tescr2); - printf ("LTESR1= %08x LTESR2= %08x\n", sc->sc_ltescr1, sc->sc_ltescr2); - printf ("PDTEA = %08x PDTEM = %02x\n", sc->sc_pdtea, sc->sc_pdtem); - printf ("LDTEA = %08x LDTEM = %02x\n", sc->sc_ldtea, sc->sc_ldtem); -#endif - return 0; -} - -int -do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#if defined(CONFIG_MPC8260) - volatile memctl8260_t *memctl = &immap->im_memctl; - int nbanks = 12; -#endif - volatile uint *p = &memctl->memc_br0; - int i; - - for (i = 0; i < nbanks; i++, p += 2) { - if (i < 10) { - printf ("BR%d = %08x OR%d = %08x\n", - i, p[0], i, p[1]); - } else { - printf ("BR%d = %08x OR%d = %08x\n", - i, p[0], i, p[1]); - } - } - - printf ("MAR = %08x", memctl->memc_mar); -#if defined(CONFIG_MPC8260) - putc ('\n'); -#endif - printf ("MAMR = %08x MBMR = %08x", - memctl->memc_mamr, memctl->memc_mbmr); -#if defined(CONFIG_MPC8260) - printf (" MCMR = %08x\n", memctl->memc_mcmr); -#endif - printf ("MPTPR = %04x MDR = %08x\n", - memctl->memc_mptpr, memctl->memc_mdr); -#if defined(CONFIG_MPC8260) - printf ("PSDMR = %08x LSDMR = %08x\n", - memctl->memc_psdmr, memctl->memc_lsdmr); - printf ("PURT = %02x PSRT = %02x\n", - memctl->memc_purt, memctl->memc_psrt); - printf ("LURT = %02x LSRT = %02x\n", - memctl->memc_lurt, memctl->memc_lsrt); - printf ("IMMR = %08x\n", memctl->memc_immr); -#endif - return 0; -} - -int -do_sitinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -#ifdef CONFIG_MPC8260 -int -do_icinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} -#endif - -int -do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#if defined(CONFIG_MPC8260) - volatile car8260_t *car = &immap->im_clkrst; -#endif - -#if defined(CONFIG_MPC8260) - printf ("SCCR = %08x\n", car->car_sccr); - printf ("SCMR = %08x\n", car->car_scmr); - printf ("RSR = %08x\n", car->car_rsr); - printf ("RMR = %08x\n", car->car_rmr); -#endif - return 0; -} - -static int counter; - -static void -header(void) -{ - char *data = "\ - -------------------------------- --------------------------------\ - 00000000001111111111222222222233 00000000001111111111222222222233\ - 01234567890123456789012345678901 01234567890123456789012345678901\ - -------------------------------- --------------------------------\ - "; - int i; - - if (counter % 2) - putc('\n'); - counter = 0; - - for (i = 0; i < 4; i++, data += 79) - printf("%.79s\n", data); -} - -static void binary (char *label, uint value, int nbits) -{ - uint mask = 1 << (nbits - 1); - int i, second = (counter++ % 2); - - if (second) - putc (' '); - puts (label); - for (i = 32 + 1; i != nbits; i--) - putc (' '); - - while (mask != 0) { - if (value & mask) - putc ('1'); - else - putc ('0'); - mask >>= 1; - } - - if (second) - putc ('\n'); -} - -#if defined(CONFIG_MPC8260) -#define PA_NBITS 32 -#define PA_NB_ODR 32 -#define PB_NBITS 28 -#define PB_NB_ODR 28 -#define PC_NBITS 32 -#define PD_NBITS 28 -#endif - -int -do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#if defined(CONFIG_MPC8260) - volatile iop8260_t *iop = &immap->im_ioport; - volatile uint *l, *r; -#endif - volatile uint *R; - - counter = 0; - header (); - - /* - * Ports A & B - */ - -#if defined(CONFIG_MPC8260) - l = &iop->iop_pdira; - R = &iop->iop_pdirb; -#endif - binary ("PA_DIR", *l++, PA_NBITS); - binary ("PB_DIR", *R++, PB_NBITS); - binary ("PA_PAR", *l++, PA_NBITS); - binary ("PB_PAR", *R++, PB_NBITS); -#if defined(CONFIG_MPC8260) - binary ("PA_SOR", *l++, PA_NBITS); - binary ("PB_SOR", *R++, PB_NBITS); -#endif - binary ("PA_ODR", *l++, PA_NB_ODR); - binary ("PB_ODR", *R++, PB_NB_ODR); - binary ("PA_DAT", *l++, PA_NBITS); - binary ("PB_DAT", *R++, PB_NBITS); - - header (); - - /* - * Ports C & D - */ - -#if defined(CONFIG_MPC8260) - l = &iop->iop_pdirc; - r = &iop->iop_pdird; -#endif - binary ("PC_DIR", *l++, PC_NBITS); - binary ("PD_DIR", *r++, PD_NBITS); - binary ("PC_PAR", *l++, PC_NBITS); - binary ("PD_PAR", *r++, PD_NBITS); -#if defined(CONFIG_MPC8260) - binary ("PC_SOR", *l++, PC_NBITS); - binary ("PD_SOR", *r++, PD_NBITS); - binary ("PC_ODR", *l++, PC_NBITS); - binary ("PD_ODR", *r++, PD_NBITS); -#endif - binary ("PC_DAT", *l++, PC_NBITS); - binary ("PD_DAT", *r++, PD_NBITS); - - header (); - return 0; -} - -/* - * set the io pins - * this needs a clean up for smaller tighter code - * use *uint and set the address based on cmd + port - */ -int -do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - uint rcode = 0; - iopin_t iopin; - static uint port = 0; - static uint pin = 0; - static uint value = 0; - static enum { - DIR, - PAR, - SOR, - ODR, - DAT, - } cmd = DAT; - - if (argc != 5) { - puts ("iopset PORT PIN CMD VALUE\n"); - return 1; - } - port = argv[1][0] - 'A'; - if (port > 3) - port -= 0x20; - if (port > 3) - rcode = 1; - pin = simple_strtol (argv[2], NULL, 10); - if (pin > 31) - rcode = 1; - - - switch (argv[3][0]) { - case 'd': - if (argv[3][1] == 'a') - cmd = DAT; - else if (argv[3][1] == 'i') - cmd = DIR; - else - rcode = 1; - break; - case 'p': - cmd = PAR; - break; - case 'o': - cmd = ODR; - break; - case 's': - cmd = SOR; - break; - default: - printf ("iopset: unknown command %s\n", argv[3]); - rcode = 1; - } - if (argv[4][0] == '1') - value = 1; - else if (argv[4][0] == '0') - value = 0; - else - rcode = 1; - if (rcode == 0) { - iopin.port = port; - iopin.pin = pin; - iopin.flag = 0; - switch (cmd) { - case DIR: - if (value) - iopin_set_out (&iopin); - else - iopin_set_in (&iopin); - break; - case PAR: - if (value) - iopin_set_ded (&iopin); - else - iopin_set_gen (&iopin); - break; - case SOR: - if (value) - iopin_set_opt2 (&iopin); - else - iopin_set_opt1 (&iopin); - break; - case ODR: - if (value) - iopin_set_odr (&iopin); - else - iopin_set_act (&iopin); - break; - case DAT: - if (value) - iopin_set_high (&iopin); - else - iopin_set_low (&iopin); - break; - } - - } - return rcode; -} - -int -do_dmainfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -int -do_fccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -static void prbrg (int n, uint val) -{ - uint extc = (val >> 14) & 3; - uint cd = (val & CPM_BRG_CD_MASK) >> 1; - uint div16 = (val & CPM_BRG_DIV16) != 0; - -#if defined(CONFIG_MPC8260) - ulong clock = gd->arch.brg_clk; -#endif - - printf ("BRG%d:", n); - - if (val & CPM_BRG_RST) - puts (" RESET"); - else - puts (" "); - - if (val & CPM_BRG_EN) - puts (" ENABLED"); - else - puts (" DISABLED"); - - printf (" EXTC=%d", extc); - - if (val & CPM_BRG_ATB) - puts (" ATB"); - else - puts (" "); - - printf (" DIVIDER=%4d", cd); - if (extc == 0 && cd != 0) { - uint baudrate; - - if (div16) - baudrate = (clock / 16) / (cd + 1); - else - baudrate = clock / (cd + 1); - - printf ("=%6d bps", baudrate); - } else { - puts (" "); - } - - if (val & CPM_BRG_DIV16) - puts (" DIV16"); - else - puts (" "); - - putc ('\n'); -} - -int -do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#if defined(CONFIG_MPC8260) - volatile uint *p = &immap->im_brgc1; -#endif - int i = 1; - - while (i <= 4) - prbrg (i++, *p++); - -#if defined(CONFIG_MPC8260) - p = &immap->im_brgc5; - while (i <= 8) - prbrg (i++, *p++); -#endif - return 0; -} - -int -do_i2cinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#if defined(CONFIG_MPC8260) - volatile i2c8260_t *i2c = &immap->im_i2c; - volatile iic_t *iip; - uint dpaddr; - - dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)]; - if (dpaddr == 0) - iip = NULL; - else - iip = (iic_t *) & immap->im_dprambase[dpaddr]; -#endif - - printf ("I2MOD = %02x I2ADD = %02x\n", i2c->i2c_i2mod, i2c->i2c_i2add); - printf ("I2BRG = %02x I2COM = %02x\n", i2c->i2c_i2brg, i2c->i2c_i2com); - printf ("I2CER = %02x I2CMR = %02x\n", i2c->i2c_i2cer, i2c->i2c_i2cmr); - - if (iip == NULL) - puts ("i2c parameter ram not allocated\n"); - else { - printf ("RBASE = %08x TBASE = %08x\n", - iip->iic_rbase, iip->iic_tbase); - printf ("RFCR = %02x TFCR = %02x\n", - iip->iic_rfcr, iip->iic_tfcr); - printf ("MRBLR = %04x\n", iip->iic_mrblr); - printf ("RSTATE= %08x RDP = %08x\n", - iip->iic_rstate, iip->iic_rdp); - printf ("RBPTR = %04x RBC = %04x\n", - iip->iic_rbptr, iip->iic_rbc); - printf ("RXTMP = %08x\n", iip->iic_rxtmp); - printf ("TSTATE= %08x TDP = %08x\n", - iip->iic_tstate, iip->iic_tdp); - printf ("TBPTR = %04x TBC = %04x\n", - iip->iic_tbptr, iip->iic_tbc); - printf ("TXTMP = %08x\n", iip->iic_txtmp); - } - return 0; -} - -int -do_sccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -int -do_smcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -int -do_spiinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -int -do_muxinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -int -do_siinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -int -do_mccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -/***************************************************/ - -U_BOOT_CMD( - siuinfo, 1, 1, do_siuinfo, - "print System Interface Unit (SIU) registers", - "" -); - -U_BOOT_CMD( - memcinfo, 1, 1, do_memcinfo, - "print Memory Controller registers", - "" -); - -U_BOOT_CMD( - sitinfo, 1, 1, do_sitinfo, - "print System Integration Timers (SIT) registers", - "" -); - -#ifdef CONFIG_MPC8260 -U_BOOT_CMD( - icinfo, 1, 1, do_icinfo, - "print Interrupt Controller registers", - "" -); -#endif - -U_BOOT_CMD( - carinfo, 1, 1, do_carinfo, - "print Clocks and Reset registers", - "" -); - -U_BOOT_CMD( - iopinfo, 1, 1, do_iopinfo, - "print I/O Port registers", - "" -); - -U_BOOT_CMD( - iopset, 5, 0, do_iopset, - "set I/O Port registers", - "PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1" -); - -U_BOOT_CMD( - dmainfo, 1, 1, do_dmainfo, - "print SDMA/IDMA registers", - "" -); - -U_BOOT_CMD( - fccinfo, 1, 1, do_fccinfo, - "print FCC registers", - "" -); - -U_BOOT_CMD( - brginfo, 1, 1, do_brginfo, - "print Baud Rate Generator (BRG) registers", - "" -); - -U_BOOT_CMD( - i2cinfo, 1, 1, do_i2cinfo, - "print I2C registers", - "" -); - -U_BOOT_CMD( - sccinfo, 1, 1, do_sccinfo, - "print SCC registers", - "" -); - -U_BOOT_CMD( - smcinfo, 1, 1, do_smcinfo, - "print SMC registers", - "" -); - -U_BOOT_CMD( - spiinfo, 1, 1, do_spiinfo, - "print Serial Peripheral Interface (SPI) registers", - "" -); - -U_BOOT_CMD( - muxinfo, 1, 1, do_muxinfo, - "print CPM Multiplexing registers", - "" -); - -U_BOOT_CMD( - siinfo, 1, 1, do_siinfo, - "print Serial Interface (SI) registers", - "" -); - -U_BOOT_CMD( - mccinfo, 1, 1, do_mccinfo, - "print MCC registers", - "" -); - -#endif diff --git a/arch/powerpc/lib/kgdb.c b/arch/powerpc/lib/kgdb.c index 01a7708..88c2af2 100644 --- a/arch/powerpc/lib/kgdb.c +++ b/arch/powerpc/lib/kgdb.c @@ -159,20 +159,6 @@ kgdb_trap(struct pt_regs *regs)

#define SPACE_REQUIRED ((32*4)+(32*8)+(6*4))

-#ifdef CONFIG_MPC8260 -/* store floating double indexed */ -#define STFDI(n,p) __asm__ __volatile__ ("stfd " #n ",%0" : "=o"(p[2*n])) -/* store floating double multiple */ -#define STFDM(p) { STFDI( 0,p); STFDI( 1,p); STFDI( 2,p); STFDI( 3,p); \ - STFDI( 4,p); STFDI( 5,p); STFDI( 6,p); STFDI( 7,p); \ - STFDI( 8,p); STFDI( 9,p); STFDI(10,p); STFDI(11,p); \ - STFDI(12,p); STFDI(13,p); STFDI(14,p); STFDI(15,p); \ - STFDI(16,p); STFDI(17,p); STFDI(18,p); STFDI(19,p); \ - STFDI(20,p); STFDI(21,p); STFDI(22,p); STFDI(23,p); \ - STFDI(24,p); STFDI(25,p); STFDI(26,p); STFDI(27,p); \ - STFDI(28,p); STFDI(29,p); STFDI(30,p); STFDI(31,p); } -#endif - int kgdb_getregs(struct pt_regs *regs, char *buf, int max) { @@ -190,15 +176,10 @@ kgdb_getregs(struct pt_regs *regs, char *buf, int max) *ptr++ = regs->gpr[i];

/* Floating Point Regs */ -#ifdef CONFIG_MPC8260 - STFDM(ptr); - ptr += 32*2; -#else for (i = 0; i < 32; i++) { *ptr++ = 0; *ptr++ = 0; } -#endif

/* pc, msr, cr, lr, ctr, xer, (mq is unused) */ *ptr++ = regs->nip; @@ -212,23 +193,6 @@ kgdb_getregs(struct pt_regs *regs, char *buf, int max) }

/* set the value of the CPU registers */ - -#ifdef CONFIG_MPC8260 -/* load floating double */ -#define LFD(n,v) __asm__ __volatile__ ("lfd " #n ",%0" :: "o"(v)) -/* load floating double indexed */ -#define LFDI(n,p) __asm__ __volatile__ ("lfd " #n ",%0" :: "o"((p)[2*n])) -/* load floating double multiple */ -#define LFDM(p) { LFDI( 0,p); LFDI( 1,p); LFDI( 2,p); LFDI( 3,p); \ - LFDI( 4,p); LFDI( 5,p); LFDI( 6,p); LFDI( 7,p); \ - LFDI( 8,p); LFDI( 9,p); LFDI(10,p); LFDI(11,p); \ - LFDI(12,p); LFDI(13,p); LFDI(14,p); LFDI(15,p); \ - LFDI(16,p); LFDI(17,p); LFDI(18,p); LFDI(19,p); \ - LFDI(20,p); LFDI(21,p); LFDI(22,p); LFDI(23,p); \ - LFDI(24,p); LFDI(25,p); LFDI(26,p); LFDI(27,p); \ - LFDI(28,p); LFDI(29,p); LFDI(30,p); LFDI(31,p); } -#endif - void kgdb_putreg(struct pt_regs *regs, int regno, char *buf, int length) { @@ -251,19 +215,6 @@ kgdb_putreg(struct pt_regs *regs, int regno, char *buf, int length) if (regno >= 0 && regno < 32) regs->gpr[regno] = *ptr; else switch (regno) { - -#ifdef CONFIG_MPC8260 -#define caseF(n) \ - case (n) + 32: LFD(n, *ptr); break; - -caseF( 0) caseF( 1) caseF( 2) caseF( 3) caseF( 4) caseF( 5) caseF( 6) caseF( 7) -caseF( 8) caseF( 9) caseF(10) caseF(11) caseF(12) caseF(13) caseF(14) caseF(15) -caseF(16) caseF(17) caseF(18) caseF(19) caseF(20) caseF(21) caseF(22) caseF(23) -caseF(24) caseF(25) caseF(26) caseF(27) caseF(28) caseF(29) caseF(30) caseF(31) - -#undef caseF -#endif - case 64: regs->nip = *ptr; break; case 65: regs->msr = *ptr; break; case 66: regs->ccr = *ptr; break; @@ -298,9 +249,6 @@ kgdb_putregs(struct pt_regs *regs, char *buf, int length) regs->gpr[i] = *ptr++;

/* Floating Point Regs */ -#ifdef CONFIG_MPC8260 - LFDM(ptr); -#endif ptr += 32*2;

/* pc, msr, cr, lr, ctr, xer, (mq is unused) */ diff --git a/board/keymile/km82xx/Kconfig b/board/keymile/km82xx/Kconfig deleted file mode 100644 index c9a093c..0000000 --- a/board/keymile/km82xx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KM82XX - -config SYS_BOARD - default "km82xx" - -config SYS_VENDOR - default "keymile" - -config SYS_CONFIG_NAME - default "km82xx" - -endif diff --git a/board/keymile/km82xx/MAINTAINERS b/board/keymile/km82xx/MAINTAINERS deleted file mode 100644 index 50e06b2..0000000 --- a/board/keymile/km82xx/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -KM82XX BOARD -M: Holger Brunck holger.brunck@keymile.com -S: Maintained -F: board/keymile/km82xx/ -F: include/configs/km82xx.h -F: configs/mgcoge_defconfig -F: configs/mgcoge3ne_defconfig diff --git a/board/keymile/km82xx/Makefile b/board/keymile/km82xx/Makefile deleted file mode 100644 index 20f193a..0000000 --- a/board/keymile/km82xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := km82xx.o ../common/common.o ../common/ivm.o diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c deleted file mode 100644 index f5a98b3..0000000 --- a/board/keymile/km82xx/km82xx.c +++ /dev/null @@ -1,463 +0,0 @@ -/* - * (C) Copyright 2007 - 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8260.h> -#include <ioports.h> -#include <malloc.h> -#include <asm/io.h> - -#include <libfdt.h> -#include <i2c.h> -#include "../common/common.h" - -DECLARE_GLOBAL_DATA_PTR; - -static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PA31 */ - { 0, 0, 0, 0, 0, 0 }, /* PA30 */ - { 0, 0, 0, 0, 0, 0 }, /* PA29 */ - { 0, 0, 0, 0, 0, 0 }, /* PA28 */ - { 0, 0, 0, 0, 0, 0 }, /* PA27 */ - { 0, 0, 0, 0, 0, 0 }, /* PA26 */ - { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - { 0, 0, 0, 0, 0, 0 }, /* PA21 */ - { 0, 0, 0, 0, 0, 0 }, /* PA20 */ - { 0, 0, 0, 0, 0, 0 }, /* PA19 */ - { 0, 0, 0, 0, 0, 0 }, /* PA18 */ - { 0, 0, 0, 0, 0, 0 }, /* PA17 */ - { 0, 0, 0, 0, 0, 0 }, /* PA16 */ - { 0, 0, 0, 0, 0, 0 }, /* PA15 */ - { 0, 0, 0, 0, 0, 0 }, /* PA14 */ - { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - { 1, 1, 0, 1, 0, 0 }, /* PA9 SMC2 TxD */ - { 1, 1, 0, 0, 0, 0 }, /* PA8 SMC2 RxD */ - { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PB31 */ - { 0, 0, 0, 0, 0, 0 }, /* PB30 */ - { 0, 0, 0, 0, 0, 0 }, /* PB29 */ - { 0, 0, 0, 0, 0, 0 }, /* PB28 */ - { 0, 0, 0, 0, 0, 0 }, /* PB27 */ - { 0, 0, 0, 0, 0, 0 }, /* PB26 */ - { 0, 0, 0, 0, 0, 0 }, /* PB25 */ - { 0, 0, 0, 0, 0, 0 }, /* PB24 */ - { 0, 0, 0, 0, 0, 0 }, /* PB23 */ - { 0, 0, 0, 0, 0, 0 }, /* PB22 */ - { 0, 0, 0, 0, 0, 0 }, /* PB21 */ - { 0, 0, 0, 0, 0, 0 }, /* PB20 */ - { 0, 0, 0, 0, 0, 0 }, /* PB19 */ - { 0, 0, 0, 0, 0, 0 }, /* PB18 */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - { 1, 1, 0, 0, 0, 0 }, /* PC25 RxClk */ - { 1, 1, 0, 0, 0, 0 }, /* PC24 TxClk */ - { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - { 0, 0, 0, 0, 0, 0 }, /* PC21 */ - { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - { 0, 0, 0, 0, 0, 0 }, /* PC18 */ - { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - { 1, 1, 0, 0, 0, 0 }, /* PC9 SCC4: CTS */ - { 1, 1, 0, 0, 0, 0 }, /* PC8 SCC4: CD */ - { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PD31 */ - { 0, 0, 0, 0, 0, 0 }, /* PD30 */ - { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - { 1, 1, 0, 0, 0, 0 }, /* PD22 SCC4: RXD */ - { 1, 1, 0, 1, 0, 0 }, /* PD21 SCC4: TXD */ - { 1, 1, 0, 1, 0, 0 }, /* PD20 SCC4: RTS */ - { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - { 0, 0, 0, 0, 0, 0 }, /* PD16 */ - { 1, 0, 0, 0, 1, 1 }, /* PD15 */ - { 1, 0, 0, 1, 1, 1 }, /* PD14 */ - { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -/* - * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init(memctl8260_t *memctl, ulong sdmr, - ulong orx, uchar *base) -{ - uchar c = 0xff; - ulong maxsize, size; - int i; - - /* - * We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff))/* / 2*/; - - out_be32(&memctl->memc_or1, orx); - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address - * CONFIG_SYS_SDRAM_BASE. - */ - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA); - out_8(base, c); - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR); - for (i = 0; i < 8; i++) - out_8(base, c); - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW); - /* setting MR on address lines */ - out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c); - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN); - out_8(base, c); - - size = get_ram_size((long *)base, maxsize); - out_be32(&memctl->memc_or1, orx | ~(size - 1)); - - return size; -} - -#ifdef CONFIG_SYS_SDRAM_LIST - -/* - * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM - * configurations therein (should be from high to lower) to find the - * one actually matching the current configuration. - * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are - * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST - * (defined as the initialization value for the array of struct sdram_conf_s) - * will then be ORed with such base values. - */ - -struct sdram_conf_s { - ulong size; - int or1; - int psdmr; -}; - -static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST; - -static long probe_sdram(memctl8260_t *memctl) -{ - int n = 0; - long psize = 0; - - for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) { - psize = try_init(memctl, - CONFIG_SYS_PSDMR | sdram_conf[n].psdmr, - CONFIG_SYS_OR1 | sdram_conf[n].or1, - (uchar *) CONFIG_SYS_SDRAM_BASE); - debug("Probing %ld bytes returned %ld\n", - sdram_conf[n].size, psize); - if (psize == sdram_conf[n].size) - break; - } - return psize; -} - -#else /* CONFIG_SYS_SDRAM_LIST */ - -static long probe_sdram(memctl8260_t *memctl) -{ - return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1, - (uchar *) CONFIG_SYS_SDRAM_BASE); -} -#endif /* CONFIG_SYS_SDRAM_LIST */ - - -int dram_init(void) -{ - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - memctl8260_t *memctl = &immap->im_memctl; - - long psize; - - out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT); - out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); - - /* 60x SDRAM setup: - */ - psize = probe_sdram(memctl); - - icache_enable(); - - gd->ram_size = psize; - - return 0; -} - -int checkboard(void) -{ -#if defined(CONFIG_MGCOGE) - puts("Board: Keymile mgcoge"); -#else - puts("Board: Keymile mgcoge3ne"); -#endif - if (ethernet_present()) - puts(" with PIGGY."); - puts("\n"); - return 0; -} - -int last_stage_init(void) -{ - struct bfticu_iomap *base = - (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE; - u8 dip_switch; - - dip_switch = in_8(&base->mswitch); - dip_switch &= BFTICU_DIPSWITCH_MASK; - /* dip switch 'full reset' or 'db erase' or 'Local mgmt IP' or any */ - if (dip_switch != 0) { - /* start bootloader */ - puts("DIP: Enabled\n"); - setenv("actual_bank", "0"); - } - set_km_env(); - return 0; -} - -#ifdef CONFIG_MGCOGE3NE -static void set_pin(int state, unsigned long mask, int port); - -/* - * For mgcoge3ne boards, the mgcoge3un control is controlled from - * a GPIO line on the PPC CPU. If bobcatreset is set the line - * will toggle once what forces the mgocge3un part to restart - * immediately. - */ -static void handle_mgcoge3un_reset(void) -{ - char *bobcatreset = getenv("bobcatreset"); - if (bobcatreset) { - if (strcmp(bobcatreset, "true") == 0) { - puts("Forcing bobcat reset\n"); - set_pin(0, 0x00000004, 3); /* clear PD29 (reset arm) */ - udelay(1000); - set_pin(1, 0x00000004, 3); - } else - set_pin(1, 0x00000004, 3); /* don't reset arm */ - } -} -#endif - -int ethernet_present(void) -{ - struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; - - return in_8(&base->bprth) & PIGGY_PRESENT; -} - -/* - * Early board initalization. - */ -int board_early_init_r(void) -{ - struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; - - /* setup the UPIOx */ - /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */ - out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED)); - /* SCC4 enable, halfduplex, FCC1 powerdown */ - out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA | - H_OPORTS_FCC1_PW_DWN)); - -#ifdef CONFIG_MGCOGE3NE - handle_mgcoge3un_reset(); -#endif - return 0; -} - -int misc_init_r(void) -{ - ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); - return 0; -} - -int hush_init_var(void) -{ - ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); - return 0; -} - -#define SDA_MASK 0x00010000 -#define SCL_MASK 0x00020000 - -static void set_pin(int state, unsigned long mask, int port) -{ - ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port); - - if (state) - setbits_be32(&iop->pdat, mask); - else - clrbits_be32(&iop->pdat, mask); - - setbits_be32(&iop->pdir, mask); -} - -static int get_pin(unsigned long mask, int port) -{ - ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port); - - clrbits_be32(&iop->pdir, mask); - return 0 != (in_be32(&iop->pdat) & mask); -} - -void set_sda(int state) -{ - set_pin(state, SDA_MASK, 3); -} - -void set_scl(int state) -{ - set_pin(state, SCL_MASK, 3); -} - -int get_sda(void) -{ - return get_pin(SDA_MASK, 3); -} - -int get_scl(void) -{ - return get_pin(SCL_MASK, 3); -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} - -#if defined(CONFIG_MGCOGE3NE) -int get_testpin(void) -{ - /* Testpin is Port C pin 29 - enable = low */ - int testpin = !get_pin(0x00000004, 2); - return testpin; -} -#endif diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 484a853..81967ff 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -184,7 +184,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_num("sramstart", bd->bi_sramstart); print_num("sramsize", bd->bi_sramsize); #if defined(CONFIG_5xx) || \ - defined(CONFIG_MPC8260) || defined(CONFIG_E500) + defined(CONFIG_E500) print_num("immr_base", bd->bi_immr_base); #endif print_num("bootflags", bd->bi_bootflags); diff --git a/cmd/bedbug.c b/cmd/bedbug.c index 14663dc..3206757 100644 --- a/cmd/bedbug.c +++ b/cmd/bedbug.c @@ -54,13 +54,6 @@ void bedbug_init (void) bedbug405_init (); #endif

-#if defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260) - /* Processors that are 603e core based */ - void bedbug603e_init (void); - - bedbug603e_init (); -#endif - return; } /* bedbug_init */

diff --git a/common/board_f.c b/common/board_f.c index a3f8704..b02ca37 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -547,7 +547,7 @@ static int setup_board_part1(void) bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ #endif

-#if defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ +#if defined(CONFIG_5xx) || \ defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ #endif diff --git a/common/lynxkdi.c b/common/lynxkdi.c index 22ad384..9856015 100644 --- a/common/lynxkdi.c +++ b/common/lynxkdi.c @@ -22,7 +22,7 @@

DECLARE_GLOBAL_DATA_PTR;

-#if defined(CONFIG_MPC8260) || defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) void lynxkdi_boot(image_header_t *hdr) { void (*lynxkdi)(void) = (void(*)(void))image_get_ep(hdr); diff --git a/configs/mgcoge3ne_defconfig b/configs/mgcoge3ne_defconfig deleted file mode 100644 index 58d6656..0000000 --- a/configs/mgcoge3ne_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_CMD_IMMAP=y -CONFIG_TARGET_KM82XX=y -CONFIG_FIT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="MGCOGE3NE" -CONFIG_VERSION_VARIABLE=y -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_UBI=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/mgcoge_defconfig b/configs/mgcoge_defconfig deleted file mode 100644 index c4f39b3..0000000 --- a/configs/mgcoge_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_CMD_IMMAP=y -CONFIG_TARGET_KM82XX=y -CONFIG_FIT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="MGCOGE" -CONFIG_VERSION_VARIABLE=y -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_UBI=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/doc/README.idma2intr b/doc/README.idma2intr deleted file mode 100644 index 1828b51..0000000 --- a/doc/README.idma2intr +++ /dev/null @@ -1,10 +0,0 @@ -(C) 2003 Arun Dharankar ADharankar@ATTBI.Com - -Attached is an IDMA example code for MPC8260/PPCBoot. I had tried to -search around and could not find any for implementing IDMA, so -implemented one. Its not coded in the best way, but works. - -Also, I was able to test the IDMA specific code under Linux also -(with modifications). My requirement was to implement it for -CompactFlash implemented in memory mode, and it works for it under -PPCBoot and Linux. diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c index f922cfb..f1425cb 100644 --- a/drivers/bootcount/bootcount.c +++ b/drivers/bootcount/bootcount.c @@ -24,11 +24,6 @@ #define CONFIG_SYS_BOOTCOUNT_SINGLEWORD #endif /* defined(CONFIG_MPC512X) */

-#if defined(CONFIG_MPC8260) -#include <asm/cpm_8260.h> -#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR) -#endif /* defined(CONFIG_MPC8260) */ - #if defined(CONFIG_QE) #include <linux/immap_qe.h> #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \ diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 9380a04..de3758d 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -17,10 +17,6 @@ */

#include <common.h> -#ifdef CONFIG_MPC8260 /* only valid for MPC8260 */ -#include <ioports.h> -#include <asm/io.h> -#endif #if defined(CONFIG_AVR32) #include <asm/arch/portmux.h> #endif @@ -94,12 +90,7 @@ DECLARE_GLOBAL_DATA_PTR;

#ifndef I2C_SOFT_DECLARATIONS -# if defined(CONFIG_MPC8260) -# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = \ - ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); -# else # define I2C_SOFT_DECLARATIONS -# endif #endif

#if !defined(CONFIG_SYS_I2C_SOFT_SPEED) diff --git a/drivers/pci/pci_indirect.c b/drivers/pci/pci_indirect.c index aee0bd6..efa13a2 100644 --- a/drivers/pci/pci_indirect.c +++ b/drivers/pci/pci_indirect.c @@ -17,22 +17,7 @@ #define cfg_read(val, addr, type, op) *val = op((type)(addr)) #define cfg_write(val, addr, type, op) op((type *)(addr), (val))

-#if defined(CONFIG_MPC8260) -#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ -static int \ -indirect_##rw##_config_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, type val) \ -{ \ - u32 b, d,f; \ - b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ - b = b - hose->first_busno; \ - dev = PCI_BDF(b, d, f); \ - out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ - sync(); \ - cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ - return 0; \ -} -#elif defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ static int \ indirect_##rw##_config_##size(struct pci_controller *hose, \ diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index 0e3ba94..f320708 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -125,13 +125,6 @@ #define gadget_is_musbhdrc(g) 0 #endif

-/* from Montavista kernel (?) */ -#ifdef CONFIG_USB_GADGET_MPC8272 -#define gadget_is_mpc8272(g) (!strcmp("mpc8272_udc", (g)->name)) -#else -#define gadget_is_mpc8272(g) 0 -#endif - #ifdef CONFIG_USB_GADGET_M66592 #define gadget_is_m66592(g) (!strcmp("m66592_udc", (g)->name)) #else @@ -209,8 +202,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x14; else if (gadget_is_musbhdrc(gadget)) return 0x15; - else if (gadget_is_mpc8272(gadget)) - return 0x16; else if (gadget_is_atmel_usba(gadget)) return 0x17; else if (gadget_is_fsl_usb2(gadget)) diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 4c25f6f..810d285 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -10,7 +10,6 @@ extra-$(CONFIG_SMC91111) += smc91111_eeprom extra-$(CONFIG_SMC911X) += smc911x_eeprom extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2 extra-$(CONFIG_MPC5xxx) += interrupt -extra-$(CONFIG_MPC8260) += mem_to_mem_idma2intr extra-$(CONFIG_PPC) += sched

# diff --git a/examples/standalone/mem_to_mem_idma2intr.c b/examples/standalone/mem_to_mem_idma2intr.c deleted file mode 100644 index ce6e6c4..0000000 --- a/examples/standalone/mem_to_mem_idma2intr.c +++ /dev/null @@ -1,379 +0,0 @@ -/* The dpalloc function used and implemented in this file was derieved - * from PPCBoot/U-Boot file "arch/powerpc/cpu/mpc8260/commproc.c". - */ - -/* Author: Arun Dharankar ADharankar@ATTBI.Com - * This example is meant to only demonstrate how the IDMA could be used. - */ - -/* - * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's - * copyright notice: - * - * General Purpose functions for the global management of the - * 8260 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) - * 2.3.99 Updates - * - * In addition to the individual control of the communication - * channels, there are a few functions that globally affect the - * communication processor. - * - * Buffer descriptors must be allocated from the dual ported memory - * space. The allocator for that is here. When the communication - * process is reset, we reclaim the memory available. There is - * currently no deallocator for this memory. - */ - - -#include <common.h> -#include <console.h> -#include <exports.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define STANDALONE - -#ifndef STANDALONE /* Linked into/Part of PPCBoot */ -#include <command.h> -#include <watchdog.h> -#else /* Standalone app of PPCBoot */ -#define WATCHDOG_RESET() { \ - *(ushort *)(CONFIG_SYS_IMMR + 0x1000E) = 0x556c; \ - *(ushort *)(CONFIG_SYS_IMMR + 0x1000E) = 0xaa39; \ - } -#endif /* STANDALONE */ - -static int debug = 1; - -#define DEBUG(fmt, args...) { \ - if(debug != 0) { \ - printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__); \ - printf(fmt, ##args); \ - } \ -} - -#define CPM_CR_IDMA1_SBLOCK (0x14) -#define CPM_CR_IDMA2_SBLOCK (0x15) -#define CPM_CR_IDMA3_SBLOCK (0x16) -#define CPM_CR_IDMA4_SBLOCK (0x17) -#define CPM_CR_IDMA1_PAGE (0x07) -#define CPM_CR_IDMA2_PAGE (0x08) -#define CPM_CR_IDMA3_PAGE (0x09) -#define CPM_CR_IDMA4_PAGE (0x0a) -#define PROFF_IDMA1_BASE ((uint)0x87fe) -#define PROFF_IDMA2_BASE ((uint)0x88fe) -#define PROFF_IDMA3_BASE ((uint)0x89fe) -#define PROFF_IDMA4_BASE ((uint)0x8afe) - -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_FLG ((ushort)0x0001) - -#define mk_cr_cmd(PG, SBC, MCN, OP) \ - ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) - - -#pragma pack(1) -typedef struct ibdbits { - unsigned b_valid:1; - unsigned b_resv1:1; - unsigned b_wrap:1; - unsigned b_interrupt:1; - unsigned b_last:1; - unsigned b_resv2:1; - unsigned b_cm:1; - unsigned b_resv3:2; - unsigned b_sdn:1; - unsigned b_ddn:1; - unsigned b_dgbl:1; - unsigned b_dbo:2; - unsigned b_resv4:1; - unsigned b_ddtb:1; - unsigned b_resv5:2; - unsigned b_sgbl:1; - unsigned b_sbo:2; - unsigned b_resv6:1; - unsigned b_sdtb:1; - unsigned b_resv7:9; -} ibdbits_t; - -#pragma pack(1) -typedef union ibdbitsu { - ibdbits_t b; - uint i; -} ibdbitsu_t; - -#pragma pack(1) -typedef struct idma_buf_desc { - ibdbitsu_t ibd_bits; /* Status and Control */ - uint ibd_datlen; /* Data length in buffer */ - uint ibd_sbuf; /* Source buffer addr in host mem */ - uint ibd_dbuf; /* Destination buffer addr in host mem */ -} ibd_t; - - -#pragma pack(1) -typedef struct dcmbits { - unsigned b_fb:1; - unsigned b_lp:1; - unsigned b_resv1:3; - unsigned b_tc2:1; - unsigned b_resv2:1; - unsigned b_wrap:3; - unsigned b_sinc:1; - unsigned b_dinc:1; - unsigned b_erm:1; - unsigned b_dt:1; - unsigned b_sd:2; -} dcmbits_t; - -#pragma pack(1) -typedef union dcmbitsu { - dcmbits_t b; - ushort i; -} dcmbitsu_t; - -#pragma pack(1) -typedef struct pram_idma { - ushort pi_ibase; - dcmbitsu_t pi_dcmbits; - ushort pi_ibdptr; - ushort pi_dprbuf; - ushort pi_bufinv; /* internal to CPM */ - ushort pi_ssmax; - ushort pi_dprinptr; /* internal to CPM */ - ushort pi_sts; - ushort pi_dproutptr; /* internal to CPM */ - ushort pi_seob; - ushort pi_deob; - ushort pi_dts; - ushort pi_retadd; - ushort pi_resv1; /* internal to CPM */ - uint pi_bdcnt; - uint pi_sptr; - uint pi_dptr; - uint pi_istate; -} pram_idma_t; - - -volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -volatile ibd_t *bdf; -volatile pram_idma_t *piptr; - -volatile int dmadone; -volatile int *dmadonep = &dmadone; -void dmadone_handler (void *); - -int idma_init (void); -void idma_start (int, int, int, uint, uint, int); -uint dpalloc (uint, uint); - - -uint dpinit_done = 0; - - -#ifdef STANDALONE -int ctrlc (void) -{ - if (tstc()) { - switch (getc ()) { - case 0x03: /* ^C - Control C */ - return 1; - default: - break; - } - } - return 0; -} -int memcmp(const void * cs,const void * ct,size_t count) -{ - const unsigned char *su1, *su2; - int res = 0; - for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) - if ((res = *su1 - *su2) != 0) - break; - return res; -} -#endif /* STANDALONE */ - -#ifdef STANDALONE -int mem_to_mem_idma2intr (int argc, char * const argv[]) -#else -int do_idma (bd_t * bd, int argc, char * const argv[]) -#endif /* STANDALONE */ -{ - int i; - - app_startup(argv); - dpinit_done = 0; - - idma_init (); - - DEBUG ("Installing dma handler\n"); - install_hdlr (7, dmadone_handler, (void *) bdf); - - memset ((void *) 0x100000, 'a', 512); - memset ((void *) 0x200000, 'b', 512); - - for (i = 0; i < 32; i++) { - printf ("Startin IDMA, iteration=%d\n", i); - idma_start (1, 1, 512, 0x100000, 0x200000, 3); - } - - DEBUG ("Uninstalling dma handler\n"); - free_hdlr (7); - - return 0; -} - -void -idma_start (int sinc, int dinc, int sz, uint sbuf, uint dbuf, int ttype) -{ - /* ttype is for M-M, M-P, P-M or P-P: not used for now */ - - piptr->pi_istate = 0; /* manual says: clear it before every START_IDMA */ - piptr->pi_dcmbits.b.b_resv1 = 0; - - if (sinc == 1) - piptr->pi_dcmbits.b.b_sinc = 1; - else - piptr->pi_dcmbits.b.b_sinc = 0; - - if (dinc == 1) - piptr->pi_dcmbits.b.b_dinc = 1; - else - piptr->pi_dcmbits.b.b_dinc = 0; - - piptr->pi_dcmbits.b.b_erm = 0; - piptr->pi_dcmbits.b.b_sd = 0x00; /* M-M */ - - bdf->ibd_sbuf = sbuf; - bdf->ibd_dbuf = dbuf; - bdf->ibd_bits.b.b_cm = 0; - bdf->ibd_bits.b.b_interrupt = 1; - bdf->ibd_bits.b.b_wrap = 1; - bdf->ibd_bits.b.b_last = 1; - bdf->ibd_bits.b.b_sdn = 0; - bdf->ibd_bits.b.b_ddn = 0; - bdf->ibd_bits.b.b_dgbl = 0; - bdf->ibd_bits.b.b_ddtb = 0; - bdf->ibd_bits.b.b_sgbl = 0; - bdf->ibd_bits.b.b_sdtb = 0; - bdf->ibd_bits.b.b_dbo = 1; - bdf->ibd_bits.b.b_sbo = 1; - bdf->ibd_bits.b.b_valid = 1; - bdf->ibd_datlen = 512; - - *dmadonep = 0; - - immap->im_sdma.sdma_idmr2 = (uchar) 0xf; - - immap->im_cpm.cp_cpcr = mk_cr_cmd (CPM_CR_IDMA2_PAGE, - CPM_CR_IDMA2_SBLOCK, 0x0, - 0x9) | 0x00010000; - - while (*dmadonep != 1) { - if (ctrlc ()) { - DEBUG ("\nInterrupted waiting for DMA interrupt.\n"); - goto done; - } - printf ("Waiting for DMA interrupt (dmadone=%d b_valid = %d)...\n", - dmadone, bdf->ibd_bits.b.b_valid); - udelay (1000000); - } - printf ("DMA complete notification received!\n"); - - done: - DEBUG ("memcmp(0x%08x, 0x%08x, 512) = %d\n", - sbuf, dbuf, memcmp ((void *) sbuf, (void *) dbuf, 512)); - - return; -} - -#define MAX_INT_BUFSZ 64 -#define DCM_WRAP 0 /* MUST be consistant with MAX_INT_BUFSZ */ - -int idma_init (void) -{ - uint memaddr; - - immap->im_cpm.cp_rccr &= ~0x00F3FFFF; - immap->im_cpm.cp_rccr |= 0x00A00A00; - - memaddr = dpalloc (sizeof (pram_idma_t), 64); - - *(volatile u16 *)&immap->im_dprambase16 - [PROFF_IDMA2_BASE / sizeof(u16)] = memaddr; - piptr = (volatile pram_idma_t *) ((uint) (immap) + memaddr); - - piptr->pi_resv1 = 0; /* manual says: clear it */ - piptr->pi_dcmbits.b.b_fb = 0; - piptr->pi_dcmbits.b.b_lp = 1; - piptr->pi_dcmbits.b.b_erm = 0; - piptr->pi_dcmbits.b.b_dt = 0; - - memaddr = (uint) dpalloc (sizeof (ibd_t), 64); - piptr->pi_ibase = piptr->pi_ibdptr = (volatile short) memaddr; - bdf = (volatile ibd_t *) ((uint) (immap) + memaddr); - bdf->ibd_bits.b.b_valid = 0; - - memaddr = (uint) dpalloc (64, 64); - piptr->pi_dprbuf = (volatile ushort) memaddr; - piptr->pi_dcmbits.b.b_wrap = 4; - piptr->pi_ssmax = 32; - - piptr->pi_sts = piptr->pi_ssmax; - piptr->pi_dts = piptr->pi_ssmax; - - return 1; -} - -void dmadone_handler (void *arg) -{ - immap->im_sdma.sdma_idmr2 = (uchar) 0x0; - - *dmadonep = 1; - - return; -} - - -static uint dpbase = 0; - -uint dpalloc (uint size, uint align) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - uint retloc; - uint align_mask, off; - uint savebase; - - /* Pointer to initial global data area */ - - if (dpinit_done == 0) { - dpbase = gd->arch.dp_alloc_base; - dpinit_done = 1; - } - - align_mask = align - 1; - savebase = dpbase; - - if ((off = (dpbase & align_mask)) != 0) - dpbase += (align - off); - - if ((off = size & align_mask) != 0) - size += align - off; - - if ((dpbase + size) >= gd->arch.dp_alloc_top) { - dpbase = savebase; - printf ("dpalloc: ran out of dual port ram!"); - return 0; - } - - retloc = dpbase; - dpbase += size; - - memset ((void *) &immr->im_dprambase[retloc], 0, size); - - return (retloc); -} diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 4374c2e..a779713 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -41,7 +41,7 @@ typedef struct bd_info { unsigned long bi_dsp_freq; /* dsp core frequency */ unsigned long bi_ddr_freq; /* ddr frequency */ #endif -#if defined(CONFIG_5xx) || defined(CONFIG_MPC8260) \ +#if defined(CONFIG_5xx) \ || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h deleted file mode 100644 index 09c3aa9..0000000 --- a/include/configs/km82xx.h +++ /dev/null @@ -1,427 +0,0 @@ -/* - * (C) Copyright 2007-2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8247 -/* MGCOGE */ -#if defined(CONFIG_MGCOGE) -#define CONFIG_HOSTNAME mgcoge -#define CONFIG_KM_BOARD_EXTRA_ENV "" - -/* MGCOGE3NE */ -#elif defined(CONFIG_MGCOGE3NE) -#define CONFIG_HOSTNAME mgcoge3ne -#define CONFIG_KM_82XX -#define CONFIG_KM_BOARD_EXTRA_ENV "bobcatreset=true\0" - -#else -#error ("Board unsupported") -#endif - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_MISC_INIT_R - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 32 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -/* MGCOGE */ -#if defined(CONFIG_MGCOGE) -#define CONFIG_SYS_MAX_FLASH_BANKS 3 -/* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#define CONFIG_SYS_FLASH_BASE_1 0x50000000 -#define CONFIG_SYS_FLASH_SIZE_1 32 -#define CONFIG_SYS_FLASH_BASE_2 0x52000000 -#define CONFIG_SYS_FLASH_SIZE_2 32 - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE_1, \ - CONFIG_SYS_FLASH_BASE_2 } -#define MTDIDS_DEFAULT "nor3=app" - -/* - * Bank 1 - 60x bus SDRAM - */ -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ - -/* SDRAM initialization values -*/ - -#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \ - ORxS_SDAM_MSK) |\ - ORxS_BPD_8 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR ( \ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* MGCOGE3NE */ -#elif defined(CONFIG_MGCOGE3NE) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* - * max num of sects on one - * chip - */ - -#define CONFIG_SYS_FLASH_BASE_1 0x50000000 -#define CONFIG_SYS_FLASH_SIZE_1 128 - -#define CONFIG_SYS_FLASH_SIZE_2 0 /* dummy value to calc SYS_OR5 */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE_1 } - -#define MTDIDS_DEFAULT "nor2=app" - -/* - * Bank 1 - 60x bus SDRAM - * mgcoge3ne has 256MB - * mgcoge2ne has 128MB - */ -#define SDRAM_MAX_SIZE 0x10000000 /* max. 256 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512 << 20) /* less than 512 MB */ - -#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \ - ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_NUMR_13 |\ - ORxS_IBID) - -#define CONFIG_SYS_PSDMR ( \ - PSDMR_PBI |\ - PSDMR_RFEN |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -#define CONFIG_SYS_SDRAM_LIST { \ - { .size = 256 << 20, \ - .or1 = ORxS_ROWST_PBI1_A4, \ - .psdmr = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6, \ - }, \ - { .size = 128 << 20, \ - .or1 = ORxS_ROWST_PBI1_A5, \ - .psdmr = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7, \ - }, \ -} -#endif /* defined(CONFIG_MGCOGE3NE) */ - -/* include further common stuff for all keymile 82xx boards */ -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ -#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ -#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#define CONFIG_ETHER_INDEX 4 -#define CONFIG_HAS_ETH0 -#define CONFIG_SYS_SCC_TOUT_LOOP 10000000 - -#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif - -#define BOOTFLASH_START 0xFE000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyCPM0" - -#define MTDPARTS_DEFAULT "mtdparts=" \ - "app:" \ - "768k(u-boot)," \ - "128k(env)," \ - "128k(envred)," \ - "3072k(free)," \ - "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")" - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_BOARD_EXTRA_ENV \ - CONFIG_KM_DEF_ENV \ - "unlock=yes\0" \ - "newenv=" \ - "prot off 0xFE0C0000 +0x40000 && " \ - "era 0xFE0C0000 +0x40000\0" \ - "arch=ppc_82xx\0" \ - "" - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (768 << 10) - -#define CONFIG_ENV_IS_IN_FLASH - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_NUM_I2C_BUSES 3 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SPEED CONFIG_SYS_I2C_SOFT_SPEED -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9542, 0x70, 0} } }, \ - {0, {{I2C_MUX_PCA9542, 0x70, 1} } } } - -#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ -#define CONFIG_KM_I2C_ABORT - -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) do { \ - if (bit) \ - iop->pdat |= 0x00010000; \ - else \ - iop->pdat &= ~0x00010000; \ - } while (0) -#define I2C_SCL(bit) do { \ - if (bit) \ - iop->pdat |= 0x00020000; \ - else \ - iop->pdat &= ~0x00020000; \ - } while (0) -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#ifndef __ASSEMBLY__ -void set_sda(int state); -void set_scl(int state); -int get_sda(void); -int get_scl(void); -#endif - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -#define CONFIG_SYS_IMMR 0xF0000000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CONFIG_SYS_HRCW_MASTER 0x0604b211 - -/* No slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SIUMCR 0x4020c200 -#define CONFIG_SYS_SYPCR 0xFFFFFF83 -#define CONFIG_SYS_BCR 0x10000000 -#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) - -/* - *----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR 0 - -/* - *----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/* - *----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/* - *----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 8 bit FLASH - * 1 60x SDRAM 32 bit SDRAM - * 3 60x GPCM 8 bit GPIO/PIGGY - * 5 60x GPCM 16 bit CFG-Flash - * - */ -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -#define CONFIG_SYS_MPTPR 0x1800 - -/* - *----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 -#define CONFIG_SYS_PSRT 0x0e - -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 - -/* - * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values - */ -#define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\ - BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_3_CLK | ORxG_TRLX) - -/* - * BFTICU board FPGA on CS4 initialization values - */ -#define CONFIG_SYS_FPGA_BASE 0x40000000 -#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ - -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\ - BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_3_CLK | ORxG_TRLX) - -/* - * CFG-Flash on CS5 initialization values - */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ - BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \ - CONFIG_SYS_FLASH_SIZE_2) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK | ORxG_TRLX) - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" - -#endif /* __CONFIG_H */ diff --git a/include/i2c.h b/include/i2c.h index fe3dca0..695cb76 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -660,9 +660,7 @@ extern struct i2c_bus_hose i2c_bus[]; #endif

#ifndef I2C_SOFT_DECLARATIONS -# if defined(CONFIG_MPC8260) -# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); -# elif (defined(CONFIG_AT91RM9200) || \ +# if (defined(CONFIG_AT91RM9200) || \ defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ defined(CONFIG_AT91SAM9263)) # define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; diff --git a/include/mpc8260.h b/include/mpc8260.h deleted file mode 100644 index 75f1b0c..0000000 --- a/include/mpc8260.h +++ /dev/null @@ -1,903 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mpc8260.h - * - * MPC8255 / MPC8260 specific definitions - */ - -#ifndef __MPC8260_H__ -#define __MPC8260_H__ - -#ifdef CONFIG_MPC8255 -#define CPU_ID_STR "MPC8255" -#endif -#ifndef CPU_ID_STR -#if defined(CONFIG_MPC8272_FAMILY) -#ifdef CONFIG_MPC8247 -#define CPU_ID_STR "MPC8247" -#else -#define CPU_ID_STR "MPC8272" -#endif -#else -#define CPU_ID_STR "MPC8260" -#endif -#endif /* !CPU_ID_STR */ - -/*----------------------------------------------------------------------- - * Exception offsets (PowerPC standard) - */ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET EXC_OFF_SYS_RESET - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration Register 4-25 - */ -#define BCR_EBM 0x80000000 /* External Bus Mode */ -#define BCR_APD_MSK 0x70000000 /* Address Phase Delay Mask */ -#define BCR_L2C 0x08000000 /* Secondary Cache Controller */ -#define BCR_L2D_MSK 0x07000000 /* L2 Cache Hit Delay Mask */ -#define BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */ -#define BCR_EAV 0x00400000 /* Enable Address Visibility */ -#define BCR_ETM 0x00080000 /* Compatibility Mode Enable */ -#define BCR_LETM 0x00040000 /* LocalBus Compatibility Mode Enable*/ -#define BCR_EPAR 0x00020000 /* Even Parity */ -#define BCR_LEPAR 0x00010000 /* Local Bus Even Parity */ -#define BCR_NPQM0 0x00008000 /* Non PowerQUICC-II Master 0 */ -#define BCR_NPQM1 0x00004000 /* Non PowerQUICC-II Master 1 */ -#define BCR_NPQM2 0x00002000 /* Non PowerQUICC-II Master 2 */ -#define BCR_EXDD 0x00000400 /* External Master Delay Disable*/ -#define BCR_ISPS 0x00000010 /* Internal Space Port Size */ - - -/*----------------------------------------------------------------------- - * PPC_ACR - 60x Bus Arbiter Configuration Register 4-28 - */ -#define PPC_ACR_DBGD 0x20 /* Data Bus Grant Delay */ -#define PPC_ACR_EARB 0x10 /* External Arbitration */ -#define PPC_ACR_PRKM_MSK 0x0f /* Parking Master */ - -#define PPC_ACR_PRKM_CPMH 0x00 /* CPM high request level */ -#define PPC_ACR_PRKM_CPMM 0x01 /* CPM middle request level */ -#define PPC_ACR_PRKM_CPML 0x02 /* CPM low request level */ -#define PPC_ACR_PRKM_CORE 0x06 /* Internal Core */ -#define PPC_ACR_PRKM_EXT1 0x07 /* External Master 1 */ -#define PPC_ACR_PRKM_EXT2 0x08 /* External Master 2 */ -#define PPC_ACR_PRKM_EXT3 0x09 /* External Master 3 */ - -/*----------------------------------------------------------------------- - * PPC_ALRH/PPC_ALRL - 60x Bus Arbitration-Level Registers 4-28 - */ -#define PPC_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */ -#define PPC_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */ -#define PPC_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */ -#define PPC_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */ -#define PPC_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */ -#define PPC_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */ -#define PPC_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */ -#define PPC_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */ -#define PPC_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */ -#define PPC_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */ -#define PPC_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */ -#define PPC_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */ -#define PPC_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */ -#define PPC_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */ -#define PPC_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */ -#define PPC_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */ - -/*----------------------------------------------------------------------- - * LCL_ACR - Local Bus Arbiter Configuration Register 4-29 - */ -#define LCL_ACR_DBGD 0x20 /* Data Bus Grant Delay */ -#define LCL_ACR_PRKM_MSK 0x0f /* Parking Master */ - -#define LCL_ACR_PRKM_CPMH 0x00 /* CPM high request level */ -#define LCL_ACR_PRKM_CPMM 0x01 /* CPM middle request level */ -#define LCL_ACR_PRKM_CPML 0x02 /* CPM low request level */ -#define LCL_ACR_PRKM_HOST 0x03 /* Host Bridge */ - -/*----------------------------------------------------------------------- - * LCL_ALRH/LCL_ALRL - Local Bus Arbitration Level Registers 4-30 - */ -#define LCL_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */ -#define LCL_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */ -#define LCL_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */ -#define LCL_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */ -#define LCL_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */ -#define LCL_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */ -#define LCL_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */ -#define LCL_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */ -#define LCL_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */ -#define LCL_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */ -#define LCL_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */ -#define LCL_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */ -#define LCL_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */ -#define LCL_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */ -#define LCL_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */ -#define LCL_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration Register 4-31 - */ -#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */ -#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */ -#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */ -#define SIUMCR_CDIS 0x10000000 /* Core Disable */ -#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/ -#define SIUMCR_DPPC01 0x04000000 /* - " - */ -#define SIUMCR_DPPC10 0x08000000 /* - " - */ -#define SIUMCR_DPPC11 0x0c000000 /* - " - */ -#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ -#define SIUMCR_L2CPC01 0x01000000 /* - " - */ -#define SIUMCR_L2CPC10 0x02000000 /* - " - */ -#define SIUMCR_L2CPC11 0x03000000 /* - " - */ -#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */ -#define SIUMCR_LBPC01 0x00400000 /* - " - */ -#define SIUMCR_LBPC10 0x00800000 /* - " - */ -#define SIUMCR_LBPC11 0x00c00000 /* - " - */ -#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/ -#define SIUMCR_APPC01 0x00100000 /* - " - */ -#define SIUMCR_APPC10 0x00200000 /* - " - */ -#define SIUMCR_APPC11 0x00300000 /* - " - */ -#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */ -#define SIUMCR_CS10PC01 0x00040000 /* - " - */ -#define SIUMCR_CS10PC10 0x00080000 /* - " - */ -#define SIUMCR_CS10PC11 0x000c0000 /* - " - */ -#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */ -#define SIUMCR_BCTLC01 0x00010000 /* - " - */ -#define SIUMCR_BCTLC10 0x00020000 /* - " - */ -#define SIUMCR_BCTLC11 0x00030000 /* - " - */ -#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */ -#define SIUMCR_MMR01 0x00004000 /* - " - */ -#define SIUMCR_MMR10 0x00008000 /* - " - */ -#define SIUMCR_MMR11 0x0000c000 /* - " - */ -#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/ -#define SIUMCR_ABE 0x00000400 /* Address output buffer impedance*/ - -/*----------------------------------------------------------------------- - * IMMR - Internal Memory Map Register 4-34 - */ -#define IMMR_ISB_MSK 0xfffe0000 /* Internal Space base */ -#define IMMR_PARTNUM_MSK 0x0000ff00 /* Part number */ -#define IMMR_MASKNUM_MSK 0x000000ff /* Mask number */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control Register 4-35 - */ -#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count*/ -#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */ -#define SYPCR_PBME 0x00000080 /* 60x Bus Monitor Enable */ -#define SYPCR_LBME 0x00000040 /* Local Bus Monitor Enable */ -#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ -#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select*/ -#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control Register 4-40 - */ -#define TMCNTSC_SEC 0x0080 /* Once Per Second Interrupt */ -#define TMCNTSC_ALR 0x0040 /* Alarm Interrupt */ -#define TMCNTSC_SIE 0x0008 /* Second Interrupt Enable */ -#define TMCNTSC_ALE 0x0004 /* Alarm Interrupt Enable */ -#define TMCNTSC_TCF 0x0002 /* Time Counter Frequency */ -#define TMCNTSC_TCE 0x0001 /* Time Counter Enable */ - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control Register 4-42 - */ -#if 0 /* already defined in asm/immap_8260.h */ -#define PISCR_PS 0x0080 /* Periodic Interrupt Status */ -#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */ -#define PISCR_PTF 0x0002 /* Periodic Timer Frequency */ -#define PISCR_PTE 0x0001 /* Periodic Timer Enable */ -#endif - -/*----------------------------------------------------------------------- - * RSR - Reset Status Register 5-4 - */ -#define RSR_JTRS 0x00000020 /* JTAG Reset Status */ -#define RSR_CSRS 0x00000010 /* Check Stop Reset Status */ -#define RSR_SWRS 0x00000008 /* Software Watchdog Reset Status*/ -#define RSR_BMRS 0x00000004 /* Bus Monitor Reset Status */ -#define RSR_ESRS 0x00000002 /* External Soft Reset Status */ -#define RSR_EHRS 0x00000001 /* External Hard Reset Status */ - -#define RSR_ALLBITS (RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS) - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - */ -#define RMR_CSRE 0x00000001 /* Checkstop Reset Enable */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Word 5-8 - */ -#define HRCW_EARB 0x80000000 /* External Arbitration */ -#define HRCW_EXMC 0x40000000 /* External Memory Controller */ -#define HRCW_CDIS 0x20000000 /* Core Disable */ -#define HRCW_EBM 0x10000000 /* External Bus Mode */ -#define HRCW_BPS00 0x00000000 /* Boot Port Size */ -#define HRCW_BPS01 0x04000000 /* - " - */ -#define HRCW_BPS10 0x08000000 /* - " - */ -#define HRCW_BPS11 0x0c000000 /* - " - */ -#define HRCW_CIP 0x02000000 /* Core Initial Prefix */ -#define HRCW_ISPS 0x01000000 /* Internal Space Port Size */ -#define HRCW_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ -#define HRCW_L2CPC01 0x00400000 /* - " - */ -#define HRCW_L2CPC10 0x00800000 /* - " - */ -#define HRCW_L2CPC11 0x00c00000 /* - " - */ -#define HRCW_DPPC00 0x00000000 /* Data Parity Pin Configuration*/ -#define HRCW_DPPC01 0x00100000 /* - " - */ -#define HRCW_DPPC10 0x00200000 /* - " - */ -#define HRCW_DPPC11 0x00300000 /* - " - */ -#define HRCW_reserved1 0x00080000 /* reserved */ -#define HRCW_ISB000 0x00000000 /* Initial Internal Space Base */ -#define HRCW_ISB001 0x00010000 /* - " - */ -#define HRCW_ISB010 0x00020000 /* - " - */ -#define HRCW_ISB011 0x00030000 /* - " - */ -#define HRCW_ISB100 0x00040000 /* - " - */ -#define HRCW_ISB101 0x00050000 /* - " - */ -#define HRCW_ISB110 0x00060000 /* - " - */ -#define HRCW_ISB111 0x00070000 /* - " - */ -#define HRCW_BMS 0x00008000 /* Boot Memory Space */ -#define HRCW_BBD 0x00004000 /* Bus Busy Disable */ -#define HRCW_MMR00 0x00000000 /* Mask Masters Requests */ -#define HRCW_MMR01 0x00001000 /* - " - */ -#define HRCW_MMR10 0x00002000 /* - " - */ -#define HRCW_MMR11 0x00003000 /* - " - */ -#define HRCW_LBPC00 0x00000000 /* Local Bus Pin Configuration */ -#define HRCW_LBPC01 0x00000400 /* - " - */ -#define HRCW_LBPC10 0x00000800 /* - " - */ -#define HRCW_LBPC11 0x00000c00 /* - " - */ -#define HRCW_APPC00 0x00000000 /* Address Parity Pin Configuration*/ -#define HRCW_APPC01 0x00000100 /* - " - */ -#define HRCW_APPC10 0x00000200 /* - " - */ -#define HRCW_APPC11 0x00000300 /* - " - */ -#define HRCW_CS10PC00 0x00000000 /* CS10 Pin Configuration */ -#define HRCW_CS10PC01 0x00000040 /* - " - */ -#define HRCW_CS10PC10 0x00000080 /* - " - */ -#define HRCW_CS10PC11 0x000000c0 /* - " - */ -#define HRCW_MODCK_H0000 0x00000000 /* High-order bits of MODCK Bus */ -#define HRCW_MODCK_H0001 0x00000001 /* - " - */ -#define HRCW_MODCK_H0010 0x00000002 /* - " - */ -#define HRCW_MODCK_H0011 0x00000003 /* - " - */ -#define HRCW_MODCK_H0100 0x00000004 /* - " - */ -#define HRCW_MODCK_H0101 0x00000005 /* - " - */ -#define HRCW_MODCK_H0110 0x00000006 /* - " - */ -#define HRCW_MODCK_H0111 0x00000007 /* - " - */ -#define HRCW_MODCK_H1000 0x00000008 /* - " - */ -#define HRCW_MODCK_H1001 0x00000009 /* - " - */ -#define HRCW_MODCK_H1010 0x0000000a /* - " - */ -#define HRCW_MODCK_H1011 0x0000000b /* - " - */ -#define HRCW_MODCK_H1100 0x0000000c /* - " - */ -#define HRCW_MODCK_H1101 0x0000000d /* - " - */ -#define HRCW_MODCK_H1110 0x0000000e /* - " - */ -#define HRCW_MODCK_H1111 0x0000000f /* - " - */ - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control Register 9-8 - */ -#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */ -#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */ -#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ -#define SCCR_PCIDF_SHIFT 3 -#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ -#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */ -#define SCCR_DFBRG_SHIFT 0 - -#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ -#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/ -#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ -#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 128 */ - -/*----------------------------------------------------------------------- - * SCMR - System Clock Mode Register 9-9 - */ -#define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */ -#define SCMR_CORECNF_SHIFT 24 -#define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */ -#define SCMR_BUSDF_SHIFT 20 -#define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */ -#define SCMR_CPMDF_SHIFT 16 -#define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */ -#define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/ -#define SCMR_PLLMF_MSKH7 0x0000000f /* for HiP7 processors */ -#define SCMR_PLLMF_SHIFT 0 - - -/*----------------------------------------------------------------------- - * MxMR - Machine A/B/C Mode Registers 10-13 - */ -#define MxMR_BSEL 0x80000000 /* Bus Select */ -#define MxMR_RFEN 0x40000000 /* Refresh Enable */ -#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */ -#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */ -#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */ -#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */ -#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */ -#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */ -#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */ -#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */ -#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */ - -#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ -#define MxMR_OP_WARR 0x10000000 /* Write to Array */ -#define MxMR_OP_RARR 0x20000000 /* Read from Array */ -#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */ - -#define MxMR_AMx_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */ -#define MxMR_AMx_TYPE_1 0x01000000 /* Addess Multiplexing Type 1 */ -#define MxMR_AMx_TYPE_2 0x02000000 /* Addess Multiplexing Type 2 */ -#define MxMR_AMx_TYPE_3 0x03000000 /* Addess Multiplexing Type 3 */ -#define MxMR_AMx_TYPE_4 0x04000000 /* Addess Multiplexing Type 4 */ -#define MxMR_AMx_TYPE_5 0x05000000 /* Addess Multiplexing Type 5 */ - -#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */ -#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ -#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */ -#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */ - -#define MxMR_G0CLx_A12 0x00000000 /* General Line 0 : A12 */ -#define MxMR_G0CLx_A11 0x00080000 /* General Line 0 : A11 */ -#define MxMR_G0CLx_A10 0x00100000 /* General Line 0 : A10 */ -#define MxMR_G0CLx_A9 0x00180000 /* General Line 0 : A9 */ -#define MxMR_G0CLx_A8 0x00200000 /* General Line 0 : A8 */ -#define MxMR_G0CLx_A7 0x00280000 /* General Line 0 : A7 */ -#define MxMR_G0CLx_A6 0x00300000 /* General Line 0 : A6 */ -#define MxMR_G0CLx_A5 0x00380000 /* General Line 0 : A5 */ - -#define MxMR_RLFx_1X 0x00004000 /* Read Loop is executed 1 time */ -#define MxMR_RLFx_2X 0x00008000 /* Read Loop is executed 2 times*/ -#define MxMR_RLFx_3X 0x0000c000 /* Read Loop is executed 3 times*/ -#define MxMR_RLFx_4X 0x00010000 /* Read Loop is executed 4 times*/ -#define MxMR_RLFx_5X 0x00014000 /* Read Loop is executed 5 times*/ -#define MxMR_RLFx_6X 0x00018000 /* Read Loop is executed 6 times*/ -#define MxMR_RLFx_7X 0x0001c000 /* Read Loop is executed 7 times*/ -#define MxMR_RLFx_8X 0x00020000 /* Read Loop is executed 8 times*/ -#define MxMR_RLFx_9X 0x00024000 /* Read Loop is executed 9 times*/ -#define MxMR_RLFx_10X 0x00028000 /* Read Loop is executed 10 times*/ -#define MxMR_RLFx_11X 0x0002c000 /* Read Loop is executed 11 times*/ -#define MxMR_RLFx_12X 0x00030000 /* Read Loop is executed 12 times*/ -#define MxMR_RLFx_13X 0x00034000 /* Read Loop is executed 13 times*/ -#define MxMR_RLFx_14X 0x00038000 /* Read Loop is executed 14 times*/ -#define MxMR_RLFx_15X 0x0003c000 /* Read Loop is executed 15 times*/ -#define MxMR_RLFx_16X 0x00000000 /* Read Loop is executed 16 times*/ - -#define MxMR_WLFx_1X 0x00000400 /* Write Loop is executed 1 time*/ -#define MxMR_WLFx_2X 0x00000800 /* Write Loop is executed 2 times*/ -#define MxMR_WLFx_3X 0x00000c00 /* Write Loop is executed 3 times*/ -#define MxMR_WLFx_4X 0x00001000 /* Write Loop is executed 4 times*/ -#define MxMR_WLFx_5X 0x00001400 /* Write Loop is executed 5 times*/ -#define MxMR_WLFx_6X 0x00001800 /* Write Loop is executed 6 times*/ -#define MxMR_WLFx_7X 0x00001c00 /* Write Loop is executed 7 times*/ -#define MxMR_WLFx_8X 0x00002000 /* Write Loop is executed 8 times*/ -#define MxMR_WLFx_9X 0x00002400 /* Write Loop is executed 9 times*/ -#define MxMR_WLFx_10X 0x00002800 /* Write Loop is executed 10 times*/ -#define MxMR_WLFx_11X 0x00002c00 /* Write Loop is executed 11 times*/ -#define MxMR_WLFx_12X 0x00003000 /* Write Loop is executed 12 times*/ -#define MxMR_WLFx_13X 0x00003400 /* Write Loop is executed 13 times*/ -#define MxMR_WLFx_14X 0x00003800 /* Write Loop is executed 14 times*/ -#define MxMR_WLFx_15X 0x00003c00 /* Write Loop is executed 15 times*/ -#define MxMR_WLFx_16X 0x00000000 /* Write Loop is executed 16 times*/ - -#define MxMR_TLFx_1X 0x00000040 /* Timer Loop is executed 1 time*/ -#define MxMR_TLFx_2X 0x00000080 /* Timer Loop is executed 2 times*/ -#define MxMR_TLFx_3X 0x000000c0 /* Timer Loop is executed 3 times*/ -#define MxMR_TLFx_4X 0x00000100 /* Timer Loop is executed 4 times*/ -#define MxMR_TLFx_5X 0x00000140 /* Timer Loop is executed 5 times*/ -#define MxMR_TLFx_6X 0x00000180 /* Timer Loop is executed 6 times*/ -#define MxMR_TLFx_7X 0x000001c0 /* Timer Loop is executed 7 times*/ -#define MxMR_TLFx_8X 0x00000200 /* Timer Loop is executed 8 times*/ -#define MxMR_TLFx_9X 0x00000240 /* Timer Loop is executed 9 times*/ -#define MxMR_TLFx_10X 0x00000280 /* Timer Loop is executed 10 times*/ -#define MxMR_TLFx_11X 0x000002c0 /* Timer Loop is executed 11 times*/ -#define MxMR_TLFx_12X 0x00000300 /* Timer Loop is executed 12 times*/ -#define MxMR_TLFx_13X 0x00000340 /* Timer Loop is executed 13 times*/ -#define MxMR_TLFx_14X 0x00000380 /* Timer Loop is executed 14 times*/ -#define MxMR_TLFx_15X 0x000003c0 /* Timer Loop is executed 15 times*/ -#define MxMR_TLFx_16X 0x00000000 /* Timer Loop is executed 16 times*/ - - -/*----------------------------------------------------------------------- - * BRx - Memory Controller: Base Register 10-14 - */ -#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */ -#define BRx_PS_MSK 0x00001800 /* Port Size Mask */ -#define BRx_DECC_MSK 0x00000600 /* Data Error Correct+Check Mask*/ -#define BRx_WP 0x00000100 /* Write Protect */ -#define BRx_MS_MSK 0x000000e0 /* Machine Select Mask */ -#define BRx_EMEMC 0x00000010 /* External MEMC Enable */ -#define BRx_ATOM_MSK 0x0000000c /* Atomic Operation Mask */ -#define BRx_DR 0x00000002 /* Data Pipelining */ -#define BRx_V 0x00000001 /* Bank Valid */ - -#define BRx_PS_64 0x00000000 /* 64 bit port size (60x bus only)*/ -#define BRx_PS_8 0x00000800 /* 8 bit port size */ -#define BRx_PS_16 0x00001000 /* 16 bit port size */ -#define BRx_PS_32 0x00001800 /* 32 bit port size */ - -#define BRx_DECC_NONE 0x00000000 /* Data Errors Checking Disabled*/ -#define BRx_DECC_NORMAL 0x00000200 /* Normal Parity Checking */ -#define BRx_DECC_RMWPC 0x00000400 /* Read-Modify-Write Parity Checking*/ -#define BRx_DECC_ECC 0x00000600 /* ECC Correction and Checking */ - -#define BRx_MS_GPCM_P 0x00000000 /* G.P.C.M. 60x Bus Machine Select*/ -#define BRx_MS_GPCM_L 0x00000020 /* G.P.C.M. Local Bus Machine Select*/ -#define BRx_MS_SDRAM_P 0x00000040 /* SDRAM 60x Bus Machine Select */ -#define BRx_MS_SDRAM_L 0x00000060 /* SDRAM Local Bus Machine Select*/ -#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ -#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */ -#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */ - -#define BRx_ATOM_RAWA 0x00000004 /* Read-After-Write-Atomic */ -#define BRx_ATOM_WARA 0x00000008 /* Write-After-Read-Atomic */ - -/*----------------------------------------------------------------------- - * ORx - Memory Controller: Option Register - SDRAM Mode 10-16 - */ -#define ORxS_SDAM_MSK 0xfff00000 /* SDRAM Address Mask Mask */ -#define ORxS_LSDAM_MSK 0x000f8000 /* Lower SDRAM Address Mask Mask*/ -#define ORxS_BPD_MSK 0x00006000 /* Banks Per Device Mask */ -#define ORxS_ROWST_MSK 0x00001e00 /* Row Start Address Bit Mask */ -#define ORxS_NUMR_MSK 0x000001c0 /* Number of Row Addr Lines Mask*/ -#define ORxS_PMSEL 0x00000020 /* Page Mode Select */ -#define ORxS_IBID 0x00000010 /* Internal Bank Interleaving Disable*/ - -#define ORxS_BPD_2 0x00000000 /* 2 Banks Per Device */ -#define ORxS_BPD_4 0x00002000 /* 4 Banks Per Device */ -#define ORxS_BPD_8 0x00004000 /* 8 Banks Per Device */ - -/* ROWST values for xSDMR[PBI] = 0 */ -#define ORxS_ROWST_PBI0_A7 0x00000400 /* Row Start Address Bit is A7 */ -#define ORxS_ROWST_PBI0_A8 0x00000800 /* Row Start Address Bit is A8 */ -#define ORxS_ROWST_PBI0_A9 0x00000c00 /* Row Start Address Bit is A9 */ -#define ORxS_ROWST_PBI0_A10 0x00001000 /* Row Start Address Bit is A10 */ -#define ORxS_ROWST_PBI0_A11 0x00001400 /* Row Start Address Bit is A11 */ -#define ORxS_ROWST_PBI0_A12 0x00001800 /* Row Start Address Bit is A12 */ -#define ORxS_ROWST_PBI0_A13 0x00001c00 /* Row Start Address Bit is A13 */ - -/* ROWST values for xSDMR[PBI] = 1 */ -#define ORxS_ROWST_PBI1_A0 0x00000000 /* Row Start Address Bit is A0 */ -#define ORxS_ROWST_PBI1_A1 0x00000200 /* Row Start Address Bit is A1 */ -#define ORxS_ROWST_PBI1_A2 0x00000400 /* Row Start Address Bit is A2 */ -#define ORxS_ROWST_PBI1_A3 0x00000600 /* Row Start Address Bit is A3 */ -#define ORxS_ROWST_PBI1_A4 0x00000800 /* Row Start Address Bit is A4 */ -#define ORxS_ROWST_PBI1_A5 0x00000a00 /* Row Start Address Bit is A5 */ -#define ORxS_ROWST_PBI1_A6 0x00000c00 /* Row Start Address Bit is A6 */ -#define ORxS_ROWST_PBI1_A7 0x00000e00 /* Row Start Address Bit is A7 */ -#define ORxS_ROWST_PBI1_A8 0x00001000 /* Row Start Address Bit is A8 */ -#define ORxS_ROWST_PBI1_A9 0x00001200 /* Row Start Address Bit is A9 */ -#define ORxS_ROWST_PBI1_A10 0x00001400 /* Row Start Address Bit is A10 */ -#define ORxS_ROWST_PBI1_A11 0x00001600 /* Row Start Address Bit is A11 */ -#define ORxS_ROWST_PBI1_A12 0x00001800 /* Row Start Address Bit is A12 */ - -#define ORxS_NUMR_9 0x00000000 /* 9 Row Address Lines */ -#define ORxS_NUMR_10 0x00000040 /* 10 Row Address Lines */ -#define ORxS_NUMR_11 0x00000080 /* 11 Row Address Lines */ -#define ORxS_NUMR_12 0x000000c0 /* 12 Row Address Lines */ -#define ORxS_NUMR_13 0x00000100 /* 13 Row Address Lines */ -#define ORxS_NUMR_14 0x00000140 /* 14 Row Address Lines */ -#define ORxS_NUMR_15 0x00000180 /* 15 Row Address Lines */ -#define ORxS_NUMR_16 0x000001c0 /* 16 Row Address Lines */ - -/* helper to determine the AM for a given size (SDRAM mode) */ -#define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ - -/*----------------------------------------------------------------------- - * ORx - Memory Controller: Option Register - GPCM Mode 10-18 - */ -#define ORxG_AM_MSK 0xffff8000 /* Address Mask Mask */ -#define ORxG_BCTLD 0x00001000 /* Data Buffer Control Disable */ -#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */ -#define ORxG_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask*/ -#define ORxG_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ -#define ORxG_SETA 0x00000008 /* External Access Termination */ -#define ORxG_TRLX 0x00000004 /* Timing Relaxed */ -#define ORxG_EHTR 0x00000002 /* Extended Hold Time on Read */ - -#define ORxG_ACS_DIV1 0x00000000 /* CS is output at the same time*/ -#define ORxG_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later*/ -#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/ - -#define ORxG_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ -#define ORxG_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ -#define ORxG_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ -#define ORxG_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ -#define ORxG_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ -#define ORxG_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ -#define ORxG_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ -#define ORxG_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ -#define ORxG_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ -#define ORxG_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ -#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ -#define ORxG_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */ -#define ORxG_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */ -#define ORxG_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */ -#define ORxG_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */ -#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ - -/*----------------------------------------------------------------------- - * ORx - Memory Controller: Option Register - UPM Mode 10-20 - */ -#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */ -#define ORxU_BCTLD 0x00001000 /* Data Buffer Control Disable */ -#define ORxU_BI 0x00000100 /* Burst Inhibit */ -#define ORxU_EHTR_MSK 0x00000006 /* Extended Hold Time on Read Mask*/ - -#define ORxU_EHTR_NORM 0x00000000 /* Normal Timing */ -#define ORxU_EHTR_1IDLE 0x00000002 /* One Idle Clock Cycle Inserted*/ -#define ORxU_EHTR_4IDLE 0x00000004 /* Four Idle Clock Cycles Inserted*/ -#define ORxU_EHTR_8IDLE 0x00000006 /* Eight Idle Clock Cycles Inserted*/ - - -/* helpers to convert values into an OR address mask (GPCM mode) */ -#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ -#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) - - -/*----------------------------------------------------------------------- - * PSDMR - 60x SDRAM Mode Register 10-21 - */ -#define PSDMR_PBI 0x80000000 /* Page-based Interleaving */ -#define PSDMR_RFEN 0x40000000 /* Refresh Enable */ -#define PSDMR_OP_MSK 0x38000000 /* SDRAM Operation Mask */ -#define PSDMR_SDAM_MSK 0x07000000 /* SDRAM Address Multiplex Mask */ -#define PSDMR_BSMA_MSK 0x00e00000 /* Bank Select Muxd Addr Line Mask*/ -#define PSDMR_SDA10_MSK 0x001c0000 /* A10 Control Mask */ -#define PSDMR_RFRC_MSK 0x00038000 /* Refresh Recovery Mask */ -#define PSDMR_PRETOACT_MSK 0x00007000 /* Precharge to Activate Intvl Mask*/ -#define PSDMR_ACTTORW_MSK 0x00000e00 /* Activate to Read/Write Intvl Mask*/ -#define PSDMR_BL 0x00000100 /* Burst Length */ -#define PSDMR_LDOTOPRE_MSK 0x000000c0 /* Last Data Out to Precharge Mask*/ -#define PSDMR_WRC_MSK 0x00000030 /* Write Recovery Time Mask */ -#define PSDMR_EAMUX 0x00000008 /* External Address Multiplexing*/ -#define PSDMR_BUFCMD 0x00000004 /* SDRAM ctl lines asrtd for 2 cycles*/ -#define PSDMR_CL_MSK 0x00000003 /* CAS Latency Mask */ - -#define PSDMR_OP_NORM 0x00000000 /* Normal Operation */ -#define PSDMR_OP_CBRR 0x08000000 /* CBR Refresh */ -#define PSDMR_OP_SELFR 0x10000000 /* Self Refresh */ -#define PSDMR_OP_MRW 0x18000000 /* Mode Register Write */ -#define PSDMR_OP_PREB 0x20000000 /* Precharge Bank */ -#define PSDMR_OP_PREA 0x28000000 /* Precharge All Banks */ -#define PSDMR_OP_ACTB 0x30000000 /* Activate Bank */ -#define PSDMR_OP_RW 0x38000000 /* Read/Write */ - -#define PSDMR_SDAM_A13_IS_A5 0x00000000 /* SDRAM Address Multiplex A13 is A5 */ -#define PSDMR_SDAM_A14_IS_A5 0x01000000 /* SDRAM Address Multiplex A14 is A5 */ -#define PSDMR_SDAM_A15_IS_A5 0x02000000 /* SDRAM Address Multiplex A15 is A5 */ -#define PSDMR_SDAM_A16_IS_A5 0x03000000 /* SDRAM Address Multiplex A16 is A5 */ -#define PSDMR_SDAM_A17_IS_A5 0x04000000 /* SDRAM Address Multiplex A17 is A5 */ -#define PSDMR_SDAM_A18_IS_A5 0x05000000 /* SDRAM Address Multiplex A18 is A5 */ - -#define PSDMR_BSMA_A12_A14 0x00000000 /* A12 - A14 */ -#define PSDMR_BSMA_A13_A15 0x00200000 /* A13 - A15 */ -#define PSDMR_BSMA_A14_A16 0x00400000 /* A14 - A16 */ -#define PSDMR_BSMA_A15_A17 0x00600000 /* A15 - A17 */ -#define PSDMR_BSMA_A16_A18 0x00800000 /* A16 - A18 */ -#define PSDMR_BSMA_A17_A19 0x00a00000 /* A17 - A19 */ -#define PSDMR_BSMA_A18_A20 0x00c00000 /* A18 - A20 */ -#define PSDMR_BSMA_A19_A21 0x00e00000 /* A19 - A21 */ - -/* SDA10 values for xSDMR[PBI] = 0 */ -#define PSDMR_SDA10_PBI0_A12 0x00000000 /* "A10" Control is A12 */ -#define PSDMR_SDA10_PBI0_A11 0x00040000 /* "A10" Control is A11 */ -#define PSDMR_SDA10_PBI0_A10 0x00080000 /* "A10" Control is A10 */ -#define PSDMR_SDA10_PBI0_A9 0x000c0000 /* "A10" Control is A9 */ -#define PSDMR_SDA10_PBI0_A8 0x00100000 /* "A10" Control is A8 */ -#define PSDMR_SDA10_PBI0_A7 0x00140000 /* "A10" Control is A7 */ -#define PSDMR_SDA10_PBI0_A6 0x00180000 /* "A10" Control is A6 */ -#define PSDMR_SDA10_PBI0_A5 0x001c0000 /* "A10" Control is A5 */ - -/* SDA10 values for xSDMR[PBI] = 1 */ -#define PSDMR_SDA10_PBI1_A10 0x00000000 /* "A10" Control is A10 */ -#define PSDMR_SDA10_PBI1_A9 0x00040000 /* "A10" Control is A9 */ -#define PSDMR_SDA10_PBI1_A8 0x00080000 /* "A10" Control is A8 */ -#define PSDMR_SDA10_PBI1_A7 0x000c0000 /* "A10" Control is A7 */ -#define PSDMR_SDA10_PBI1_A6 0x00100000 /* "A10" Control is A6 */ -#define PSDMR_SDA10_PBI1_A5 0x00140000 /* "A10" Control is A5 */ -#define PSDMR_SDA10_PBI1_A4 0x00180000 /* "A10" Control is A4 */ -#define PSDMR_SDA10_PBI1_A3 0x001c0000 /* "A10" Control is A3 */ - -#define PSDMR_RFRC_3_CLK 0x00008000 /* 3 Clocks */ -#define PSDMR_RFRC_4_CLK 0x00010000 /* 4 Clocks */ -#define PSDMR_RFRC_5_CLK 0x00018000 /* 5 Clocks */ -#define PSDMR_RFRC_6_CLK 0x00020000 /* 6 Clocks */ -#define PSDMR_RFRC_7_CLK 0x00028000 /* 7 Clocks */ -#define PSDMR_RFRC_8_CLK 0x00030000 /* 8 Clocks */ -#define PSDMR_RFRC_16_CLK 0x00038000 /* 16 Clocks */ - -#define PSDMR_PRETOACT_8W 0x00000000 /* 8 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_1W 0x00001000 /* 1 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_2W 0x00002000 /* 2 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_3W 0x00003000 /* 3 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_4W 0x00004000 /* 4 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_5W 0x00005000 /* 5 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_6W 0x00006000 /* 6 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_7W 0x00007000 /* 7 Clock-cycle Wait States */ - -#define PSDMR_ACTTORW_8W 0x00000000 /* 8 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_1W 0x00000200 /* 1 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_2W 0x00000400 /* 2 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_3W 0x00000600 /* 3 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_4W 0x00000800 /* 4 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_5W 0x00000a00 /* 5 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_6W 0x00000c00 /* 6 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_7W 0x00000e00 /* 7 Clock-cycle Wait States */ - -#define PSDMR_LDOTOPRE_0C 0x00000000 /* 0 Clock Cycles */ -#define PSDMR_LDOTOPRE_1C 0x00000040 /* 1 Clock Cycles */ -#define PSDMR_LDOTOPRE_2C 0x00000080 /* 2 Clock Cycles */ - -#define PSDMR_WRC_4C 0x00000000 /* 4 Clock Cycles */ -#define PSDMR_WRC_1C 0x00000010 /* 1 Clock Cycles */ -#define PSDMR_WRC_2C 0x00000020 /* 2 Clock Cycles */ -#define PSDMR_WRC_3C 0x00000030 /* 3 Clock Cycles */ - -#define PSDMR_CL_1 0x00000001 /* CAS Latency = 1 */ -#define PSDMR_CL_2 0x00000002 /* CAS Latency = 2 */ -#define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */ - -/*----------------------------------------------------------------------- - * LSDMR - Local Bus SDRAM Mode Register 10-24 - */ - -/* - * No definitions here - the LSDMR has the same fields as the PSDMR. - */ - -/*----------------------------------------------------------------------- - * MPTPR - Memory Refresh Timer Prescaler Register 10-32 - * See User's Manual Errata for the changed definition (matches the - * 8xx now). The wrong prescaler definition causes excessive refreshes - * (typically "divide by 2" when "divide by 32" is intended) which will - * cause unnecessary memory subsystem slowdown. - */ -#define MPTPR_PTP_MSK 0xff00 /* Periodic Timers Prescaler Mask */ -#define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */ -#define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */ -#define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */ -#define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */ -#define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */ -#define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */ - - -/*----------------------------------------------------------------------- - * TGCR1/TGCR2 - Timer Global Configuration Registers 17-4 - */ -#define TGCR1_CAS2 0x80 /* Cascade Timer 1 and 2 */ -#define TGCR1_STP2 0x20 /* Stop timer 2 */ -#define TGCR1_RST2 0x10 /* Reset timer 2 */ -#define TGCR1_GM1 0x08 /* Gate Mode for Pin 1 */ -#define TGCR1_STP1 0x02 /* Stop timer 1 */ -#define TGCR1_RST1 0x01 /* Reset timer 1 */ -#define TGCR2_CAS4 0x80 /* Cascade Timer 3 and 4 */ -#define TGCR2_STP4 0x20 /* Stop timer 4 */ -#define TGCR2_RST4 0x10 /* Reset timer 4 */ -#define TGCR2_GM2 0x08 /* Gate Mode for Pin 2 */ -#define TGCR2_STP3 0x02 /* Stop timer 3 */ -#define TGCR2_RST3 0x01 /* Reset timer 3 */ - - -/*----------------------------------------------------------------------- - * TMR1-TMR4 - Timer Mode Registers 17-6 - */ -#define TMRx_PS_MSK 0xff00 /* Prescaler Value */ -#define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/ -#define TMRx_OM 0x0020 /* Output Mode */ -#define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/ -#define TMRx_FRR 0x0008 /* Free Run/Restart */ -#define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */ -#define TMRx_GE 0x0001 /* Gate Enable */ - -#define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/ -#define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */ -#define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */ -#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */ - -#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ -#define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/ -#define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/ -#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */ - - -/*----------------------------------------------------------------------- - * CMXFCR - CMX FCC Clock Route Register 15-12 - */ -#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ -#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ -#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ -#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ -#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ -#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ -#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ -#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ -#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ - -#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ -#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ -#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ -#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ -#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ -#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ -#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ -#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ - -#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ -#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ -#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ -#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ -#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ -#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ -#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ -#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ - -#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ -#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ -#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ -#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ -#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ -#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ -#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ -#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ - -#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ -#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ -#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ -#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ -#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ -#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ -#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ -#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ - -#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ -#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ -#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ -#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ -#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ -#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ -#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ -#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ - -#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ -#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ -#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ -#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ -#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ -#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ -#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ -#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ - -/*----------------------------------------------------------------------- - * CMXSCR - CMX SCC Clock Route Register 15-14 - */ -#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ -#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ -#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ -#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ -#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ -#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ -#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ -#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ -#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ -#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ -#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ -#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ -#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ -#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ -#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ -#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ - -#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ -#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ -#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ -#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ -#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ -#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ -#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ -#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ -#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ -#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ -#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ -#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ -#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ -#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ -#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ -#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ -#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ -#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ -#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ -#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ -#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ -#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ -#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ -#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ -#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ -#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ -#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ -#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ -#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ -#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ -#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ -#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ -#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ -#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ -#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ -#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ -#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ -#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ -#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ -#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ -#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ -#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ -#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ - -#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ -#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ -#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ -#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ -#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ -#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ -#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ -#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ -#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ -#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ -#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ -#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ -#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ -#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ -#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ - -/*----------------------------------------------------------------------- - * CMXSMR - CMX SMC Clock Route Register 15-17 - */ -#define CMXSMR_SMC1 0x80 /* SMC1 Connection */ -#define CMXSMR_SMC1CS_MSK 0x30 /* SMC1 Clock Source */ -#define CMXSMR_SMC2 0x08 /* SMC2 Connection */ -#define CMXSMR_SMC2CS_MSK 0x03 /* SMC2 Clock Source */ - -#define CMXSMR_SMC1CS_BRG1 0x00 /* SMC1 Tx and Rx Clocks are BRG1 */ -#define CMXSMR_SMC1CS_BRG7 0x10 /* SMC1 Tx and Rx Clocks are BRG7 */ -#define CMXSMR_SMC1CS_CLK7 0x20 /* SMC1 Tx and Rx Clocks are CLK7 */ -#define CMXSMR_SMC1CS_CLK9 0x30 /* SMC1 Tx and Rx Clocks are CLK9 */ - -#define CMXSMR_SMC2CS_BRG2 0x00 /* SMC2 Tx and Rx Clocks are BRG2 */ -#define CMXSMR_SMC2CS_BRG8 0x01 /* SMC2 Tx and Rx Clocks are BRG8 */ -#define CMXSMR_SMC2CS_CLK19 0x02 /* SMC2 Tx and Rx Clocks are CLK19 */ -#define CMXSMR_SMC2CS_CLK20 0x03 /* SMC2 Tx and Rx Clocks are CLK20 */ - -/*----------------------------------------------------------------------- - * miscellaneous - */ - -#define UPMA 1 -#define UPMB 2 -#define UPMC 3 - -#if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG) -static __inline__ void -reset_8260_watchdog(volatile immap_t *immr) -{ - immr->im_siu_conf.sc_swsr = 0x556c; - immr->im_siu_conf.sc_swsr = 0xaa39; -} -#endif /* !__ASSEMBLY && CONFIG_WATCHDOG */ - -#endif /* __MPC8260_H__ */ diff --git a/include/mpc8260_irq.h b/include/mpc8260_irq.h deleted file mode 100644 index 9bee9a3..0000000 --- a/include/mpc8260_irq.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef _MPC8260_IRQ_H -#define _MPC8260_IRQ_H - -/****************************************************************************/ -/* most of this was ripped out of include/asm-ppc/irq.h from the Linux/PPC */ -/* source. There was no copyright information in the file. */ - -/* - * this is the # irq's for all ppc arch's (pmac/chrp/prep) - * so it is the max of them all - * - * [let's just worry about 8260 for now - mjj] - */ -#define NR_IRQS 64 - -/* The 8260 has an internal interrupt controller with a maximum of - * 64 IRQs. We will use NR_IRQs from above since it is large enough. - * Don't be confused by the 8260 documentation where they list an - * "interrupt number" and "interrupt vector". We are only interested - * in the interrupt vector. There are "reserved" holes where the - * vector number increases, but the interrupt number in the table does not. - * (Document errata updates have fixed this...make sure you have up to - * date processor documentation -- Dan). - */ -#define NR_SIU_INTS 64 - -/* There are many more than these, we will add them as we need them. -*/ -#define SIU_INT_SMC1 ((uint)0x04) -#define SIU_INT_SMC2 ((uint)0x05) -#define SIU_INT_IRQ1 ((uint)0x13) -#define SIU_INT_IRQ2 ((uint)0x14) -#define SIU_INT_IRQ3 ((uint)0x15) -#define SIU_INT_IRQ4 ((uint)0x16) -#define SIU_INT_IRQ5 ((uint)0x17) -#define SIU_INT_IRQ6 ((uint)0x18) -#define SIU_INT_IRQ7 ((uint)0x19) -#define SIU_INT_FCC1 ((uint)0x20) -#define SIU_INT_FCC2 ((uint)0x21) -#define SIU_INT_FCC3 ((uint)0x22) -#define SIU_INT_SCC1 ((uint)0x28) -#define SIU_INT_SCC2 ((uint)0x29) -#define SIU_INT_SCC3 ((uint)0x2a) -#define SIU_INT_SCC4 ((uint)0x2b) - -#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) - -#endif /* _MPC8260_IRQ_H */ diff --git a/include/post.h b/include/post.h index d5b4062..8bee125 100644 --- a/include/post.h +++ b/include/post.h @@ -29,10 +29,6 @@ #define _POST_WORD_ADDR \ (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

-#elif defined(CONFIG_MPC8260) -#include <asm/cpm_8260.h> -#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) - #elif defined(CONFIG_MPC8360) #include <linux/immap_qe.h> #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 8288433..53141b1 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -93,31 +93,7 @@ #define EID 81 #endif /* CONFIG_5xx */

-#if defined(CONFIG_MPC8260) - -#define HID2 1011 - -#define HID0_IFEM (1<<7) - -#define HID0_ICE_BITPOS 16 -#define HID0_DCE_BITPOS 17 - -#define IM_REGBASE 0x10000 -#define IM_SYPCR (IM_REGBASE+0x0004) -#define IM_SWSR (IM_REGBASE+0x000e) -#define IM_BR0 (IM_REGBASE+0x0100) -#define IM_OR0 (IM_REGBASE+0x0104) -#define IM_BR1 (IM_REGBASE+0x0108) -#define IM_OR1 (IM_REGBASE+0x010c) -#define IM_BR2 (IM_REGBASE+0x0110) -#define IM_OR2 (IM_REGBASE+0x0114) -#define IM_MPTPR (IM_REGBASE+0x0184) -#define IM_PSDMR (IM_REGBASE+0x0190) -#define IM_PSRT (IM_REGBASE+0x019c) -#define IM_IMMR (IM_REGBASE+0x01a8) -#define IM_SCCR (IM_REGBASE+0x0c80) - -#elif defined(CONFIG_MPC5xxx) +#if defined(CONFIG_MPC5xxx)

#define HID0_ICE_BITPOS 16 #define HID0_DCE_BITPOS 17 diff --git a/post/drivers/memory.c b/post/drivers/memory.c index 89725fa..b410502 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -170,14 +170,7 @@ DECLARE_GLOBAL_DATA_PTR; */ static void move64(const unsigned long long *src, unsigned long long *dest) { -#if defined(CONFIG_MPC8260) - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0" ); /* Clobbers fr0 */ - return; -#else *dest = *src; -#endif }

/* diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 9619ff4..abe464d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -35,7 +35,6 @@ CONFIG_5xx_CONS_SCI2 CONFIG_5xx_GCLK_FREQ CONFIG_64BIT_PHYS_ADDR CONFIG_66 -CONFIG_8260_CLKIN CONFIG_8349_CLKIN CONFIG_83XX CONFIG_83XX_CLKIN @@ -435,7 +434,6 @@ CONFIG_CONS_EXTC_PINSEL CONFIG_CONS_EXTC_RATE CONFIG_CONS_NONE CONFIG_CONS_ON_SCC -CONFIG_CONS_ON_SMC CONFIG_CONS_SCIF0 CONFIG_CONS_SCIF1 CONFIG_CONS_SCIF2 @@ -795,13 +793,11 @@ CONFIG_ETH2ADDR CONFIG_ETHADDR CONFIG_ETHBASE CONFIG_ETHER_INDEX -CONFIG_ETHER_LOOPBACK_TEST CONFIG_ETHER_NONE CONFIG_ETHER_ON_FCC CONFIG_ETHER_ON_FCC1 CONFIG_ETHER_ON_FCC2 CONFIG_ETHER_ON_FCC3 -CONFIG_ETHER_ON_SCC CONFIG_ETHPRIME CONFIG_ETH_BUFSIZE CONFIG_ETH_RXSIZE @@ -1072,7 +1068,6 @@ CONFIG_HAS_FSL_MPH_USB CONFIG_HAS_FSL_XHCI_USB CONFIG_HAS_POST CONFIG_HAVE_ACPI_RESUME -CONFIG_HAVE_OWN_RESET CONFIG_HCLK_FREQ CONFIG_HDBOOT CONFIG_HDMI_ENCODER_I2C_ADDR @@ -1357,11 +1352,6 @@ CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_KEYSTONE_RBL_NAND CONFIG_KEY_REVOCATION CONFIG_KGDB_BAUDRATE -CONFIG_KGDB_EXTC_PINSEL -CONFIG_KGDB_EXTC_RATE -CONFIG_KGDB_INDEX -CONFIG_KGDB_ON_SCC -CONFIG_KGDB_ON_SMC CONFIG_KGDB_SER_INDEX CONFIG_KILAUEA CONFIG_KIRKWOOD_EGIGA_INIT @@ -1381,7 +1371,6 @@ CONFIG_KMSUPX5 CONFIG_KMTEGR1 CONFIG_KMTEPR2 CONFIG_KMVECT1 -CONFIG_KM_82XX CONFIG_KM_BOARD_EXTRA_ENV CONFIG_KM_BOARD_NAME CONFIG_KM_COGE5UN @@ -1672,9 +1661,6 @@ CONFIG_MPC555 CONFIG_MPC5xxx_FEC CONFIG_MPC5xxx_FEC_MII10 CONFIG_MPC5xxx_FEC_MII100 -CONFIG_MPC8247 -CONFIG_MPC8255 -CONFIG_MPC8272_FAMILY CONFIG_MPC8308 CONFIG_MPC8308RDB CONFIG_MPC8308_P1M @@ -2771,9 +2757,6 @@ CONFIG_SYS_AUXCORE_BOOTDATA CONFIG_SYS_BARGSIZE CONFIG_SYS_BASE_BAUD CONFIG_SYS_BAUDRATE_TABLE -CONFIG_SYS_BCR -CONFIG_SYS_BCR_60x -CONFIG_SYS_BCR_SINGLE CONFIG_SYS_BCSR CONFIG_SYS_BCSR3_PCIE CONFIG_SYS_BCSR5_PCI66EN @@ -2824,8 +2807,6 @@ CONFIG_SYS_BOOT_RAMDISK_HIGH CONFIG_SYS_BR0_64M CONFIG_SYS_BR0_8M CONFIG_SYS_BR0_PRELIM -CONFIG_SYS_BR10_PRELIM -CONFIG_SYS_BR11_PRELIM CONFIG_SYS_BR1_PRELIM CONFIG_SYS_BR2_PRELIM CONFIG_SYS_BR3_CAN @@ -2837,8 +2818,6 @@ CONFIG_SYS_BR6_64M CONFIG_SYS_BR6_8M CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR7_PRELIM -CONFIG_SYS_BR8_PRELIM -CONFIG_SYS_BR9_PRELIM CONFIG_SYS_BRIGHTNESS CONFIG_SYS_BUSCLK CONFIG_SYS_CACHELINE_SHIFT @@ -2898,7 +2877,6 @@ CONFIG_SYS_CMXFCR_MASK3 CONFIG_SYS_CMXFCR_VALUE1 CONFIG_SYS_CMXFCR_VALUE2 CONFIG_SYS_CMXFCR_VALUE3 -CONFIG_SYS_CMXSCR_VALUE CONFIG_SYS_CORE_SRAM CONFIG_SYS_CORE_SRAM_SIZE CONFIG_SYS_CORTEX_R4 @@ -2925,14 +2903,10 @@ CONFIG_SYS_CPLD_SIZE CONFIG_SYS_CPMFCR_RAMTYPE CONFIG_SYS_CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_INTERRUPT -CONFIG_SYS_CPM_POST_WORD_ADDR CONFIG_SYS_CPRI CONFIG_SYS_CPRI_CLK CONFIG_SYS_CPUSPEED CONFIG_SYS_CPU_CLK -CONFIG_SYS_CPU_PCI_IO_START -CONFIG_SYS_CPU_PCI_MEMIO_START -CONFIG_SYS_CPU_PCI_MEM_START CONFIG_SYS_CS0_BASE CONFIG_SYS_CS0_CFG CONFIG_SYS_CS0_CTRL @@ -3294,7 +3268,6 @@ CONFIG_SYS_DEBUG CONFIG_SYS_DEBUG_SERVER_FW_ADDR CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR CONFIG_SYS_DECREMENT_PATTERNS -CONFIG_SYS_DEFAULT_IMMR CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS CONFIG_SYS_DEFAULT_MBAR CONFIG_SYS_DEFAULT_VIDEO_MODE @@ -4052,14 +4025,6 @@ CONFIG_SYS_HOSTNAME CONFIG_SYS_HRCW_HIGH CONFIG_SYS_HRCW_HIGH_BASE CONFIG_SYS_HRCW_LOW -CONFIG_SYS_HRCW_MASTER -CONFIG_SYS_HRCW_SLAVE1 -CONFIG_SYS_HRCW_SLAVE2 -CONFIG_SYS_HRCW_SLAVE3 -CONFIG_SYS_HRCW_SLAVE4 -CONFIG_SYS_HRCW_SLAVE5 -CONFIG_SYS_HRCW_SLAVE6 -CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HSDRAMC CONFIG_SYS_HWINFO_MAGIC CONFIG_SYS_HWINFO_OFFSET @@ -4501,7 +4466,6 @@ CONFIG_SYS_MATRIX_EBI0CSA_VAL CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_MCFG_REMAP CONFIG_SYS_MAXARGS -CONFIG_SYS_MAXIDLE CONFIG_SYS_MAX_DATAFLASH_BANKS CONFIG_SYS_MAX_DDR_BAT_SIZE CONFIG_SYS_MAX_DOC_DEVICE @@ -4716,13 +4680,6 @@ CONFIG_SYS_MPC8xxx_PIC_ADDR CONFIG_SYS_MPC92469AC CONFIG_SYS_MPEG_BASE CONFIG_SYS_MPEG_SIZE -CONFIG_SYS_MPTPR -CONFIG_SYS_MPTPR_1BK_2K -CONFIG_SYS_MPTPR_1BK_4K -CONFIG_SYS_MPTPR_1BK_8K -CONFIG_SYS_MPTPR_2BK_2K -CONFIG_SYS_MPTPR_2BK_4K -CONFIG_SYS_MPTPR_2BK_8K CONFIG_SYS_MRAM_BASE CONFIG_SYS_MRAM_SIZE CONFIG_SYS_MRS_OFFS @@ -4938,8 +4895,6 @@ CONFIG_SYS_OR0_8M CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_REMAP CONFIG_SYS_OR1 -CONFIG_SYS_OR10_PRELIM -CONFIG_SYS_OR11_PRELIM CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR2_PRELIM @@ -4953,8 +4908,6 @@ CONFIG_SYS_OR6_64M CONFIG_SYS_OR6_8M CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR7_PRELIM -CONFIG_SYS_OR8_PRELIM -CONFIG_SYS_OR9_PRELIM CONFIG_SYS_OR_TIMING_FLASH CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ CONFIG_SYS_OR_TIMING_MRAM @@ -5177,8 +5130,6 @@ CONFIG_SYS_PCIE_MMAP_SIZE CONFIG_SYS_PCIE_NR_PORTS CONFIG_SYS_PCIE_PHYS CONFIG_SYS_PCIE_VIRT -CONFIG_SYS_PCIMSK0_MASK -CONFIG_SYS_PCIMSK1_MASK CONFIG_SYS_PCISPEED_66 CONFIG_SYS_PCI_64BIT CONFIG_SYS_PCI_BAR0 @@ -5222,17 +5173,6 @@ CONFIG_SYS_PCI_MEM_SIZE CONFIG_SYS_PCI_MMIO_BASE CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_SIZE -CONFIG_SYS_PCI_MSTR0_LOCAL -CONFIG_SYS_PCI_MSTR1_LOCAL -CONFIG_SYS_PCI_MSTR_IO_BUS -CONFIG_SYS_PCI_MSTR_IO_LOCAL -CONFIG_SYS_PCI_MSTR_IO_SIZE -CONFIG_SYS_PCI_MSTR_MEMIO_BUS -CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL -CONFIG_SYS_PCI_MSTR_MEMIO_SIZE -CONFIG_SYS_PCI_MSTR_MEM_BUS -CONFIG_SYS_PCI_MSTR_MEM_LOCAL -CONFIG_SYS_PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_NR_INBOUND_WIN CONFIG_SYS_PCI_PHYS CONFIG_SYS_PCI_PTM1LA @@ -5305,7 +5245,6 @@ CONFIG_SYS_PHYS_ADDR_HIGH CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_PIB_BASE CONFIG_SYS_PIB_WINDOW_SIZE -CONFIG_SYS_PICMR0_MASK_ATTRIB CONFIG_SYS_PIOC_ASR_VAL CONFIG_SYS_PIOC_BSR_VAL CONFIG_SYS_PIOC_PDR_VAL @@ -5343,9 +5282,6 @@ CONFIG_SYS_PMAN CONFIG_SYS_PMC_BASE CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PME_CLK -CONFIG_SYS_POCMR0_MASK_ATTRIB -CONFIG_SYS_POCMR1_MASK_ATTRIB -CONFIG_SYS_POCMR2_MASK_ATTRIB CONFIG_SYS_PORTTC CONFIG_SYS_POST_BSPEC1 CONFIG_SYS_POST_BSPEC2 @@ -5395,9 +5331,7 @@ CONFIG_SYS_PSC1 CONFIG_SYS_PSC3 CONFIG_SYS_PSC4 CONFIG_SYS_PSC6 -CONFIG_SYS_PSDMR CONFIG_SYS_PSDPAR -CONFIG_SYS_PSRT CONFIG_SYS_PSSR_VAL CONFIG_SYS_PTCPAR CONFIG_SYS_PTDPAR @@ -5440,7 +5374,6 @@ CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C2_SPEED CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_RCAR_I2C3_SPEED -CONFIG_SYS_RCCR CONFIG_SYS_RCWH_PCIHOST CONFIG_SYS_READ_SPD CONFIG_SYS_REDUNDAND_ENVIRONMENT @@ -5457,7 +5390,6 @@ CONFIG_SYS_RIO_MEM_BUS CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_SIZE CONFIG_SYS_RIO_MEM_VIRT -CONFIG_SYS_RMR CONFIG_SYS_ROM_BASE CONFIG_SYS_ROOTPATH CONFIG_SYS_RSTC_RMR_VAL @@ -5497,7 +5429,6 @@ CONFIG_SYS_SCCR_TSEC2ON CONFIG_SYS_SCCR_TSECCM CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_USBMPHCM -CONFIG_SYS_SCC_TOUT_LOOP CONFIG_SYS_SCR CONFIG_SYS_SCRATCH_VA CONFIG_SYS_SCSI_MAXDEVICE @@ -5663,8 +5594,6 @@ CONFIG_SYS_SICRL CONFIG_SYS_SIL1178_I2C CONFIG_SYS_SIMULATE_SPD_EEPROM CONFIG_SYS_SIUMCR -CONFIG_SYS_SIUMCR_HIGH -CONFIG_SYS_SIUMCR_LOW CONFIG_SYS_SJA1000_BASE CONFIG_SYS_SMALL_FLASH CONFIG_SYS_SMC0_CYCLE0_VAL @@ -5672,7 +5601,6 @@ CONFIG_SYS_SMC0_MODE0_VAL CONFIG_SYS_SMC0_PULSE0_VAL CONFIG_SYS_SMC0_SETUP0_VAL CONFIG_SYS_SMC_CSR0_VAL -CONFIG_SYS_SMC_RXBUFLEN CONFIG_SYS_SMI_BASE CONFIG_SYS_SPANSION_BASE CONFIG_SYS_SPANSION_BOOT @@ -5701,7 +5629,6 @@ CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE CONFIG_SYS_SPI_FLASH_U_BOOT_START -CONFIG_SYS_SPI_INIT_OFFSET CONFIG_SYS_SPI_KERNEL_OFFS CONFIG_SYS_SPI_MXC_WAIT CONFIG_SYS_SPI_RTC_DEVID @@ -5766,7 +5693,6 @@ CONFIG_SYS_TIMER_COUNTS_DOWN CONFIG_SYS_TIMER_PRESCALER CONFIG_SYS_TIMER_RATE CONFIG_SYS_TLB_FOR_BOOT_FLASH -CONFIG_SYS_TMCNTSC CONFIG_SYS_TMPVIRT CONFIG_SYS_TMRINTR_MASK CONFIG_SYS_TMRINTR_NO @@ -6175,7 +6101,6 @@ CONFIG_USB_GADGET_GOKU CONFIG_USB_GADGET_IMX CONFIG_USB_GADGET_M66592 CONFIG_USB_GADGET_MASS_STORAGE -CONFIG_USB_GADGET_MPC8272 CONFIG_USB_GADGET_MQ11XX CONFIG_USB_GADGET_MUSBHSFC CONFIG_USB_GADGET_N9604

There was for long time no activity in the 5xx area. We need to go further and convert to Kconfig, but it turned out, nobody is interested anymore in 5xx, so remove it.

Signed-off-by: Heiko Schocher hs@denx.de

--- Compiling without errors on travis: https://travis-ci.org/hsdenx/u-boot-test/builds/240293627

README | 12 - api/api_platform-powerpc.c | 3 +- arch/powerpc/Kconfig | 4 - arch/powerpc/cpu/mpc5xx/Kconfig | 18 - arch/powerpc/cpu/mpc5xx/Makefile | 20 -- arch/powerpc/cpu/mpc5xx/config.mk | 8 - arch/powerpc/cpu/mpc5xx/cpu.c | 156 --------- arch/powerpc/cpu/mpc5xx/cpu_init.c | 108 ------ arch/powerpc/cpu/mpc5xx/interrupts.c | 192 ----------- arch/powerpc/cpu/mpc5xx/serial.c | 168 ---------- arch/powerpc/cpu/mpc5xx/speed.c | 52 --- arch/powerpc/cpu/mpc5xx/spi.c | 396 ---------------------- arch/powerpc/cpu/mpc5xx/start.S | 541 ------------------------------ arch/powerpc/cpu/mpc5xx/traps.c | 211 ------------ arch/powerpc/cpu/mpc5xx/u-boot.lds | 86 ----- arch/powerpc/include/asm/5xx_immap.h | 424 ----------------------- arch/powerpc/include/asm/ppc.h | 7 +- arch/powerpc/include/asm/status_led.h | 73 ---- arch/powerpc/lib/time.c | 11 - board/mpl/common/common_util.c | 53 +-- board/mpl/pati/Kconfig | 15 - board/mpl/pati/MAINTAINERS | 6 - board/mpl/pati/Makefile | 9 - board/mpl/pati/cmd_pati.c | 433 ------------------------ board/mpl/pati/pati.c | 610 ---------------------------------- board/mpl/pati/pati.h | 423 ----------------------- board/mpl/pati/pci_eeprom.h | 90 ----- board/mpl/pati/plx9056.h | 95 ------ cmd/bdinfo.c | 3 +- cmd/reginfo.c | 37 --- common/board_f.c | 3 +- configs/PATI_defconfig | 28 -- doc/README.mpc5xx | 48 --- include/asm-generic/u-boot.h | 3 +- include/configs/PATI.h | 245 -------------- include/mpc5xx.h | 173 ---------- include/ppc_asm.tmpl | 12 - include/watchdog.h | 5 - scripts/config_whitelist.txt | 18 - 39 files changed, 7 insertions(+), 4792 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc5xx/Kconfig delete mode 100644 arch/powerpc/cpu/mpc5xx/Makefile delete mode 100644 arch/powerpc/cpu/mpc5xx/config.mk delete mode 100644 arch/powerpc/cpu/mpc5xx/cpu.c delete mode 100644 arch/powerpc/cpu/mpc5xx/cpu_init.c delete mode 100644 arch/powerpc/cpu/mpc5xx/interrupts.c delete mode 100644 arch/powerpc/cpu/mpc5xx/serial.c delete mode 100644 arch/powerpc/cpu/mpc5xx/speed.c delete mode 100644 arch/powerpc/cpu/mpc5xx/spi.c delete mode 100644 arch/powerpc/cpu/mpc5xx/start.S delete mode 100644 arch/powerpc/cpu/mpc5xx/traps.c delete mode 100644 arch/powerpc/cpu/mpc5xx/u-boot.lds delete mode 100644 arch/powerpc/include/asm/5xx_immap.h delete mode 100644 arch/powerpc/include/asm/status_led.h delete mode 100644 board/mpl/pati/Kconfig delete mode 100644 board/mpl/pati/MAINTAINERS delete mode 100644 board/mpl/pati/Makefile delete mode 100644 board/mpl/pati/cmd_pati.c delete mode 100644 board/mpl/pati/pati.c delete mode 100644 board/mpl/pati/pati.h delete mode 100644 board/mpl/pati/pci_eeprom.h delete mode 100644 board/mpl/pati/plx9056.h delete mode 100644 configs/PATI_defconfig delete mode 100644 doc/README.mpc5xx delete mode 100644 include/configs/PATI.h delete mode 100644 include/mpc5xx.h

diff --git a/README b/README index 6f2c0a2..c7baa69 100644 --- a/README +++ b/README @@ -4000,16 +4000,6 @@ Low Level (hardware related) configuration options: point to an otherwise UNUSED address space between the top of RAM and the start of the PCI space.

-- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6) - -- CONFIG_SYS_SYPCR: System Protection Control (11-9) - -- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26) - -- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31) - -- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30) - - CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)

- CONFIG_SYS_OR_TIMING_SDRAM: @@ -4018,8 +4008,6 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_MAMR_PTA: periodic timer for refresh

-- CONFIG_SYS_DER: Debug Event Register (37-47) - - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM, CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM, diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c index 307a5f5..7d54ea7 100644 --- a/api/api_platform-powerpc.c +++ b/api/api_platform-powerpc.c @@ -30,8 +30,7 @@ int platform_sys_info(struct sys_info *si) si->clk_bus = gd->bus_clk; si->clk_cpu = gd->cpu_clk;

-#if defined(CONFIG_5xx) || \ - defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define bi_bar bi_immr_base #elif defined(CONFIG_MPC5xxx) #define bi_bar bi_mbar_base diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 75594c6..c0345ac 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -11,9 +11,6 @@ choice config MPC512X bool "MPC512X"

-config 5xx - bool "MPC5xx" - config MPC5xxx bool "MPC5xxx"

@@ -46,7 +43,6 @@ config 4xx endchoice

source "arch/powerpc/cpu/mpc512x/Kconfig" -source "arch/powerpc/cpu/mpc5xx/Kconfig" source "arch/powerpc/cpu/mpc5xxx/Kconfig" source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" diff --git a/arch/powerpc/cpu/mpc5xx/Kconfig b/arch/powerpc/cpu/mpc5xx/Kconfig deleted file mode 100644 index d81bfd2..0000000 --- a/arch/powerpc/cpu/mpc5xx/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -menu "mpc5xx CPU" - depends on 5xx - -config SYS_CPU - default "mpc5xx" - -choice - prompt "Target select" - optional - -config TARGET_PATI - bool "Support PATI" - -endchoice - -source "board/mpl/pati/Kconfig" - -endmenu diff --git a/arch/powerpc/cpu/mpc5xx/Makefile b/arch/powerpc/cpu/mpc5xx/Makefile deleted file mode 100644 index 7b8826a..0000000 --- a/arch/powerpc/cpu/mpc5xx/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2003 -# Martin Winistoerfer, martinwinistoerfer@gmx.ch. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# File: arch/powerpc/cpu/mpc5xx/Makefile -# -# Discription: Makefile to build mpc5xx cpu configuration. -# Will include top config.mk which itselfs -# uses the definitions made in arch/powerpc/cpu/mpc5xx/config.mk -# - -extra-y = start.o -obj-y = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o diff --git a/arch/powerpc/cpu/mpc5xx/config.mk b/arch/powerpc/cpu/mpc5xx/config.mk deleted file mode 100644 index dd2ec37..0000000 --- a/arch/powerpc/cpu/mpc5xx/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003 -# Martin Winistoerfer, martinwinistoerfer@gmx.ch. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mpowerpc -msoft-float diff --git a/arch/powerpc/cpu/mpc5xx/cpu.c b/arch/powerpc/cpu/mpc5xx/cpu.c deleted file mode 100644 index cfcf633..0000000 --- a/arch/powerpc/cpu/mpc5xx/cpu.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: cpu.c - * - * Discription: Some cpu specific function for watchdog, - * cpu version test, clock setting ... - * - */ - - -#include <common.h> -#include <watchdog.h> -#include <command.h> -#include <mpc5xx.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if (defined(CONFIG_MPC555)) -# define ID_STR "MPC555/556" - -/* - * Check version of cpu with Processor Version Register (PVR) - */ -static int check_cpu_version (long clock, uint pvr, uint immr) -{ - char buf[32]; - /* The highest 16 bits should be 0x0002 for a MPC555/556 */ - if ((pvr >> 16) == 0x0002) { - printf (" " ID_STR " Version %x", (pvr >> 16)); - printf (" at %s MHz:", strmhz (buf, clock)); - } else { - printf ("Not supported cpu version"); - return -1; - } - return 0; -} -#endif /* CONFIG_MPC555 */ - - -/* - * Check version of mpc5xx - */ -int checkcpu (void) -{ - ulong clock = gd->cpu_clk; - uint immr = get_immr (0); /* Return full IMMR contents */ - uint pvr = get_pvr (); /* Retrieve PVR register */ - - puts ("CPU: "); - - return check_cpu_version (clock, pvr, immr); -} - -/* - * Called by macro WATCHDOG_RESET - */ -#if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) -{ - int re_enable = disable_interrupts (); - - reset_5xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); - if (re_enable) - enable_interrupts (); -} - -/* - * Will clear software reset - */ -void reset_5xx_watchdog (volatile immap_t * immr) -{ - /* Use the MPC5xx Internal Watchdog */ - immr->im_siu_conf.sc_swsr = 0x556c; /* Prevent SW time-out */ - immr->im_siu_conf.sc_swsr = 0xaa39; -} - -#endif /* CONFIG_WATCHDOG */ - - -/* - * Get timebase clock frequency - */ -unsigned long get_tbclk (void) -{ - volatile immap_t *immr = (volatile immap_t *) CONFIG_SYS_IMMR; - ulong oscclk, factor; - - if (immr->im_clkrst.car_sccr & SCCR_TBS) { - return (gd->cpu_clk / 16); - } - - factor = (((CONFIG_SYS_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1; - - oscclk = gd->cpu_clk / factor; - - if ((immr->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { - return (oscclk / 4); - } - return (oscclk / 16); -} - -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} - -/* - * Reset board - */ -int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ -#if defined(CONFIG_PATI) - volatile ulong *addr = (ulong *) CONFIG_SYS_RESET_ADDRESS; - *addr = 1; -#else - ulong addr; - - /* Interrupts off, enable reset */ - __asm__ volatile (" mtspr 81, %r0 \n\t" - " mfmsr %r3 \n\t" - " rlwinm %r31,%r3,0,25,23\n\t" - " mtmsr %r31 \n\t"); - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. - * "(ulong)-1" used to be a good choice for many systems... - */ - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*) (void)) addr) (); -#endif /* #if defined(CONFIG_PATI) */ - return 1; -} diff --git a/arch/powerpc/cpu/mpc5xx/cpu_init.c b/arch/powerpc/cpu/mpc5xx/cpu_init.c deleted file mode 100644 index 5bae39f..0000000 --- a/arch/powerpc/cpu/mpc5xx/cpu_init.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: cpu_init.c - * - * Discription: Contains initialisation functions to setup - * the cpu properly - * - */ - -#include <common.h> -#include <mpc5xx.h> -#include <watchdog.h> - -/* - * Setup essential cpu registers to run - */ -void cpu_init_f (volatile immap_t * immr) -{ - volatile memctl5xx_t *memctl = &immr->im_memctl; - ulong reg; - - /* SYPCR - contains watchdog control. This will enable watchdog */ - /* if CONFIG_WATCHDOG is set */ - immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR; - -#if defined(CONFIG_WATCHDOG) - reset_5xx_watchdog (immr); -#endif - - /* SIUMCR - contains debug pin configuration */ - immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; - - /* Initialize timebase. Unlock TBSCRK */ - immr->im_sitk.sitk_tbscrk = KAPWR_KEY; - immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR; - - /* Full IMB bus speed */ - immr->im_uimb.uimb_umcr = CONFIG_SYS_UMCR; - - /* Time base and decrementer will be enables (TBE) */ - /* in timer_init() in time.c called from board_init_f(). */ - - /* Initialize the PIT. Unlock PISCRK */ - immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; - -#if !defined(CONFIG_PATI) - /* PATI sest PLL in start.S */ - /* PLL (CPU clock) settings */ - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - - /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to - * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, - * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the currentMF - * field value. - */ -#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0) - reg = CONFIG_SYS_PLPRCR; /* reset control bits */ -#else - reg = immr->im_clkrst.car_plprcr; - reg &= PLPRCR_MF_MSK; /* isolate MF field */ - reg |= CONFIG_SYS_PLPRCR; /* reset control bits */ -#endif - immr->im_clkrst.car_plprcr = reg; - -#endif /* !defined(CONFIG_PATI) */ - - /* System integration timers. CONFIG_SYS_MASK has EBDF configuration */ - immr->im_clkrstk.cark_sccrk = KAPWR_KEY; - reg = immr->im_clkrst.car_sccr; - reg &= SCCR_MASK; - reg |= CONFIG_SYS_SCCR; - immr->im_clkrst.car_sccr = reg; - - /* Memory Controller */ - memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; - memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; - -#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; -#endif - -} - -/* - * Initialize higher level parts of cpu - */ -int cpu_init_r (void) -{ - /* Nothing to do at the moment */ - return (0); -} diff --git a/arch/powerpc/cpu/mpc5xx/interrupts.c b/arch/powerpc/cpu/mpc5xx/interrupts.c deleted file mode 100644 index 35dddf5..0000000 --- a/arch/powerpc/cpu/mpc5xx/interrupts.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * (C) Copyright 2000-2002 Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: interrupt.c - * - * Discription: Contains interrupt routines needed by U-Boot - * - */ - -#include <common.h> -#include <command.h> -#include <mpc5xx.h> -#include <asm/processor.h> - -#if defined(CONFIG_PATI) -/* PATI uses IRQs for PCI doorbell */ -#undef NR_IRQS -#define NR_IRQS 16 -#endif - -struct interrupt_action { - interrupt_handler_t *handler; - void *arg; - int count; -}; - -static struct interrupt_action irq_vecs[NR_IRQS]; - -/* - * Initialise interrupts - */ - -int interrupt_init_cpu (ulong *decrementer_count) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int vec; - - /* Decrementer used here for status led */ - *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; - - /* Disable all interrupts */ - immr->im_siu_conf.sc_simask = 0; - for (vec=0; vec<NR_IRQS; vec++) { - irq_vecs[vec].handler = NULL; - irq_vecs[vec].arg = NULL; - irq_vecs[vec].count = 0; - } - - return (0); -} - -/* - * Handle external interrupts - */ -void external_interrupt (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int irq; - ulong simask, newmask; - ulong vec, v_bit; - - /* - * read the SIVEC register and shift the bits down - * to get the irq number - */ - vec = immr->im_siu_conf.sc_sivec; - irq = vec >> 26; - v_bit = 0x80000000UL >> irq; - - /* - * Read Interrupt Mask Register and Mask Interrupts - */ - simask = immr->im_siu_conf.sc_simask; - newmask = simask & (~(0xFFFF0000 >> irq)); - immr->im_siu_conf.sc_simask = newmask; - - if (!(irq & 0x1)) { /* External Interrupt ? */ - ulong siel; - - /* - * Read Interrupt Edge/Level Register - */ - siel = immr->im_siu_conf.sc_siel; - - if (siel & v_bit) { /* edge triggered interrupt ? */ - /* - * Rewrite SIPEND Register to clear interrupt - */ - immr->im_siu_conf.sc_sipend = v_bit; - } - } - - if (irq_vecs[irq].handler != NULL) { - irq_vecs[irq].handler (irq_vecs[irq].arg); - } else { - printf ("\nBogus External Interrupt IRQ %d Vector %ld\n", - irq, vec); - /* turn off the bogus interrupt to avoid it from now */ - simask &= ~v_bit; - } - /* - * Re-Enable old Interrupt Mask - */ - immr->im_siu_conf.sc_simask = simask; -} - -/* - * Install and free an interrupt handler - */ -void irq_install_handler (int vec, interrupt_handler_t * handler, - void *arg) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - /* SIU interrupt */ - if (irq_vecs[vec].handler != NULL) { - printf ("SIU interrupt %d 0x%x\n", - vec, - (uint) handler); - } - irq_vecs[vec].handler = handler; - irq_vecs[vec].arg = arg; - immr->im_siu_conf.sc_simask |= 1 << (31 - vec); -#if 0 - printf ("Install SIU interrupt for vector %d ==> %p\n", - vec, handler); -#endif -} - -void irq_free_handler (int vec) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - /* SIU interrupt */ -#if 0 - printf ("Free CPM interrupt for vector %d\n", - vec); -#endif - immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec)); - irq_vecs[vec].handler = NULL; - irq_vecs[vec].arg = NULL; -} - -/* - * Timer interrupt - gets called when bit 0 of DEC changes from - * 0. Decrementer is enabled with bit TBE in TBSCR. - */ -void timer_interrupt_cpu (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - -#if 0 - printf ("*** Timer Interrupt *** "); -#endif - /* Reset Timer Status Bit and Timers Interrupt Status */ - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - __asm__ ("nop"); - immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST; - - return; -} - -#if defined(CONFIG_CMD_IRQ) -/******************************************************************************* - * - * irqinfo - print information about IRQs - * - */ -int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int vec; - - printf ("\nInterrupt-Information:\n"); - printf ("Nr Routine Arg Count\n"); - - for (vec=0; vec<NR_IRQS; vec++) { - if (irq_vecs[vec].handler != NULL) { - printf ("%02d %08lx %08lx %d\n", - vec, - (ulong)irq_vecs[vec].handler, - (ulong)irq_vecs[vec].arg, - irq_vecs[vec].count); - } - } - return 0; -} - - -#endif diff --git a/arch/powerpc/cpu/mpc5xx/serial.c b/arch/powerpc/cpu/mpc5xx/serial.c deleted file mode 100644 index a2a8d94..0000000 --- a/arch/powerpc/cpu/mpc5xx/serial.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: serial.c - * - * Discription: Serial interface driver for SCI1 and SCI2. - * Since this code will be called from ROM use - * only non-static local variables. - * - */ - -#include <common.h> -#include <watchdog.h> -#include <command.h> -#include <mpc5xx.h> -#include <serial.h> -#include <linux/compiler.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Local functions - */ - -static int ready_to_send(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile short status; - - do { -#if defined(CONFIG_5xx_CONS_SCI1) - status = immr->im_qsmcm.qsmcm_sc1sr; -#else - status = immr->im_qsmcm.qsmcm_sc2sr; -#endif - -#if defined(CONFIG_WATCHDOG) - reset_5xx_watchdog (immr); -#endif - } while ((status & SCI_TDRE) == 0); - return 1; - -} - -/* - * Minimal global serial functions needed to use one of the SCI modules. - */ - -static int mpc5xx_serial_init(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - serial_setbrg(); - -#if defined(CONFIG_5xx_CONS_SCI1) - /* 10-Bit, 1 start bit, 8 data bit, no parity, 1 stop bit */ - immr->im_qsmcm.qsmcm_scc1r1 = SCI_M_10; - immr->im_qsmcm.qsmcm_scc1r1 = SCI_TE | SCI_RE; -#else - immr->im_qsmcm.qsmcm_scc2r1 = SCI_M_10; - immr->im_qsmcm.qsmcm_scc2r1 = SCI_TE | SCI_RE; -#endif - return 0; -} - -static void mpc5xx_serial_putc(const char c) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* Test for completition */ - if(ready_to_send()) { -#if defined(CONFIG_5xx_CONS_SCI1) - immr->im_qsmcm.qsmcm_sc1dr = (short)c; -#else - immr->im_qsmcm.qsmcm_sc2dr = (short)c; -#endif - if(c == '\n') { - if(ready_to_send()); -#if defined(CONFIG_5xx_CONS_SCI1) - immr->im_qsmcm.qsmcm_sc1dr = (short)'\r'; -#else - immr->im_qsmcm.qsmcm_sc2dr = (short)'\r'; -#endif - } - } -} - -static int mpc5xx_serial_getc(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile short status; - unsigned char tmp; - - /* New data ? */ - do { -#if defined(CONFIG_5xx_CONS_SCI1) - status = immr->im_qsmcm.qsmcm_sc1sr; -#else - status = immr->im_qsmcm.qsmcm_sc2sr; -#endif - -#if defined(CONFIG_WATCHDOG) - reset_5xx_watchdog (immr); -#endif - } while ((status & SCI_RDRF) == 0); - - /* Read data */ -#if defined(CONFIG_5xx_CONS_SCI1) - tmp = (unsigned char)(immr->im_qsmcm.qsmcm_sc1dr & SCI_SCXDR_MK); -#else - tmp = (unsigned char)( immr->im_qsmcm.qsmcm_sc2dr & SCI_SCXDR_MK); -#endif - return tmp; -} - -static int mpc5xx_serial_tstc(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - short status; - - /* New data character ? */ -#if defined(CONFIG_5xx_CONS_SCI1) - status = immr->im_qsmcm.qsmcm_sc1sr; -#else - status = immr->im_qsmcm.qsmcm_sc2sr; -#endif - return (status & SCI_RDRF); -} - -static void mpc5xx_serial_setbrg(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - short scxbr; - - /* Set baudrate */ - scxbr = (gd->cpu_clk / (32 * gd->baudrate)); -#if defined(CONFIG_5xx_CONS_SCI1) - immr->im_qsmcm.qsmcm_scc1r0 = (scxbr & SCI_SCXBR_MK); -#else - immr->im_qsmcm.qsmcm_scc2r0 = (scxbr & SCI_SCXBR_MK); -#endif -} - -static struct serial_device mpc5xx_serial_drv = { - .name = "mpc5xx_serial", - .start = mpc5xx_serial_init, - .stop = NULL, - .setbrg = mpc5xx_serial_setbrg, - .putc = mpc5xx_serial_putc, - .puts = default_serial_puts, - .getc = mpc5xx_serial_getc, - .tstc = mpc5xx_serial_tstc, -}; - -void mpc5xx_serial_initialize(void) -{ - serial_register(&mpc5xx_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &mpc5xx_serial_drv; -} diff --git a/arch/powerpc/cpu/mpc5xx/speed.c b/arch/powerpc/cpu/mpc5xx/speed.c deleted file mode 100644 index 24b9026..0000000 --- a/arch/powerpc/cpu/mpc5xx/speed.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: speed.c - * - * Discription: Provides cpu speed calculation - * - */ - -#include <common.h> -#include <mpc5xx.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Get cpu and bus clock - */ -int get_clocks (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - -#ifndef CONFIG_5xx_GCLK_FREQ - uint divf = (immr->im_clkrst.car_plprcr & PLPRCR_DIVF_MSK); - uint mf = ((immr->im_clkrst.car_plprcr & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT); - ulong vcoout; - - vcoout = (CONFIG_SYS_OSC_CLK / (divf + 1)) * (mf + 1) * 2; - if(immr->im_clkrst.car_plprcr & PLPRCR_CSRC_MSK) { - gd->cpu_clk = vcoout / (2^(((immr->im_clkrst.car_sccr & SCCR_DFNL_MSK) >> SCCR_DFNL_SHIFT) + 1)); - } else { - gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK)); - } - -#else /* CONFIG_5xx_GCLK_FREQ */ - gd->bus_clk = CONFIG_5xx_GCLK_FREQ; -#endif /* CONFIG_5xx_GCLK_FREQ */ - - if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) { - /* No Bus Divider active */ - gd->bus_clk = gd->cpu_clk; - } else { - /* CLKOUT is GCLK / 2 */ - gd->bus_clk = gd->cpu_clk / 2; - } - return (0); -} diff --git a/arch/powerpc/cpu/mpc5xx/spi.c b/arch/powerpc/cpu/mpc5xx/spi.c deleted file mode 100644 index ef8b55f..0000000 --- a/arch/powerpc/cpu/mpc5xx/spi.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * nboppuri@trinetcommunication.com, - * pmpatel@trinetcommunication.com - * Copyright (c) 2001 Gerd Mennchen Gerd.Mennchen@icn.siemens.de - * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC5xx CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd@denx.de - * - * Ported to MPC5xx - * Copyright (c) 2003 Denis Peter, MPL AG Switzerland, d.petr@mpl.ch. - */ - -#include <common.h> -#include <mpc5xx.h> -#include <asm/5xx_immap.h> -#include <linux/ctype.h> -#include <malloc.h> -#include <post.h> -#include <net.h> - -#if defined(CONFIG_SPI) - -#undef DEBUG - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - - -#ifdef DEBUG - -#define DPRINT(a) printf a; -/* ----------------------------------------------- - * Helper functions to peek into tx and rx buffers - * ----------------------------------------------- */ -static const char * const hex_digit = "0123456789ABCDEF"; - -static char quickhex (int i) -{ - return hex_digit[i]; -} - -static void memdump (void *pv, int num) -{ - int i; - unsigned char *pc = (unsigned char *) pv; - - for (i = 0; i < num; i++) - printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); - printf ("\t"); - for (i = 0; i < num; i++) - printf ("%c", isprint (pc[i]) ? pc[i] : '.'); - printf ("\n"); -} -#else /* !DEBUG */ - -#define DPRINT(a) - -#endif /* DEBUG */ - -/* ------------------- - * Function prototypes - * ------------------- */ -void spi_init (void); - -ssize_t spi_read (uchar *, int, uchar *, int); -ssize_t spi_write (uchar *, int, uchar *, int); -ssize_t spi_xfer (size_t); - - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ - -void spi_init_f (void) -{ - int i; - - volatile immap_t *immr; - volatile qsmcm5xx_t *qsmcm; - - immr = (immap_t *) CONFIG_SYS_IMMR; - qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; - - qsmcm->qsmcm_qsmcr = 0; /* all accesses enabled */ - qsmcm->qsmcm_qspi_il = 0; /* lowest IRQ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PQSPAR[00] = 0 reserved - * PQSPAR[01] = 1 [0x4000] -> PERI: (SPICS3) - * PQSPAR[02] = 0 [0x0000] -> GPIO - * PQSPAR[03] = 0 [0x0000] -> GPIO - * PQSPAR[04] = 1 [0x0800] -> PERI: (SPICS0) - * PQSPAR[05] = 0 reseved - * PQSPAR[06] = 1 [0x0200] -> PERI: (SPIMOSI) - * PQSPAR[07] = 1 [0x0100] -> PERI: (SPIMISO) - * -------------------------------------------- */ - qsmcm->qsmcm_pqspar = 0x3 | (CONFIG_SYS_SPI_CS_USED << 3); - - /* -------------------------------------------- - * DDRQS[00] = 0 reserved - * DDRQS[01] = 1 [0x0040] -> SPICS3 Output - * DDRQS[02] = 0 [0x0000] -> GPIO Output - * DDRQS[03] = 0 [0x0000] -> GPIO Output - * DDRQS[04] = 1 [0x0008] -> SPICS0 Output - * DDRQS[05] = 1 [0x0004] -> SPICLK Output - * DDRQS[06] = 1 [0x0002] -> SPIMOSI Output - * DDRQS[07] = 0 [0x0001] -> SPIMISO Input - * -------------------------------------------- */ - qsmcm->qsmcm_ddrqs = 0x7E; - /* -------------------------------------------- - * Base state for used SPI CS pins, if base = 0 active must be 1 - * PORTQS[00] = 0 reserved - * PORTQS[01] = 0 reserved - * PORTQS[02] = 0 reserved - * PORTQS[03] = 0 reserved - * PORTQS[04] = 0 [0x0000] RxD2 - * PORTQS[05] = 1 [0x0400] TxD2 - * PORTQS[06] = 0 [0x0000] RxD1 - * PORTQS[07] = 1 [0x0100] TxD1 - * PORTQS[08] = 0 reserved - * PORTQS[09] = 0 [0x0000] -> SPICS3 Base Output - * PORTQS[10] = 0 [0x0000] -> SPICS2 Base Output - * PORTQS[11] = 0 [0x0000] -> SPICS1 Base Output - * PORTQS[12] = 0 [0x0000] -> SPICS0 Base Output - * PORTQS[13] = 0 [0x0004] -> SPICLK Output - * PORTQS[14] = 0 [0x0002] -> SPIMOSI Output - * PORTQS[15] = 0 [0x0001] -> SPIMISO Input - * -------------------------------------------- */ - qsmcm->qsmcm_portqs |= (CONFIG_SYS_SPI_CS_BASE << 3); - /* -------------------------------------------- - * Controll Register 0 - * SPCR0[00] = 1 (0x8000) Master - * SPCR0[01] = 0 (0x0000) Wired-Or - * SPCR0[2..5] = (0x2000) Bits per transfer (default 8) - * SPCR0[06] = 0 (0x0000) Normal polarity - * SPCR0[07] = 0 (0x0000) Normal Clock Phase - * SPCR0[08..15] = 14 1.4MHz - */ - qsmcm->qsmcm_spcr0=0xA00E; - /* -------------------------------------------- - * Controll Register 1 - * SPCR1[00] = 0 (0x0000) QSPI enabled - * SPCR1[1..7] = (0x7F00) Delay before Transfer - * SPCR1[8..15] = (0x0000) Delay After transfer (204.8usec@40MHz) - */ - qsmcm->qsmcm_spcr1=0x7F00; - /* -------------------------------------------- - * Controll Register 2 - * SPCR2[00] = 0 (0x0000) SPI IRQs Disabeld - * SPCR2[01] = 0 (0x0000) No Wrap around - * SPCR2[02] = 0 (0x0000) Wrap to 0 - * SPCR2[3..7] = (0x0000) End Queue pointer = 0 - * SPCR2[8..10] = 0 (0x0000) reserved - * SPCR2[11..15] = 0 (0x0000) NewQueue Address = 0 - */ - qsmcm->qsmcm_spcr2=0x0000; - /* -------------------------------------------- - * Controll Register 3 - * SPCR3[00..04] = 0 (0x0000) reserved - * SPCR3[05] = 0 (0x0000) Feedback disabled - * SPCR3[06] = 0 (0x0000) IRQ on HALTA & MODF disabled - * SPCR3[07] = 0 (0x0000) Not halted - */ - qsmcm->qsmcm_spcr3=0x00; - /* -------------------------------------------- - * SPSR (Controll Register 3) Read only/ reset Flags 08,09,10 - * SPCR3[08] = 1 (0x80) QSPI finished - * SPCR3[09] = 1 (0x40) Mode Fault Flag - * SPCR3[10] = 1 (0x20) HALTA - * SPCR3[11..15] = 0 (0x0000) Last executed command - */ - qsmcm->qsmcm_spsr=0xE0; - /*------------------------------------------- - * Setup RAM - */ - for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; - } - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * Dummy, all initializations have been done in spi_init_r - * *********************************************************************** */ -void spi_init_r (void) -{ - return; - -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int i,dlen; - volatile immap_t *immr; - volatile qsmcm5xx_t *qsmcm; - - immr = (immap_t *) CONFIG_SYS_IMMR; - qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; - for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; - } - qsmcm->qsmcm_tranram[0] = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - i=0; - qsmcm->qsmcm_tranram[i++] = SPI_EEPROM_WRITE; /* WRITE memory array */ - qsmcm->qsmcm_tranram[i++] = addr[0]; - qsmcm->qsmcm_tranram[i++] = addr[1]; - - for(dlen=0;dlen<len;dlen++) { - qsmcm->qsmcm_tranram[i+dlen] = buffer[dlen]; /* WRITE memory array */ - } - /* transmit it */ - spi_xfer(i+dlen); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - qsmcm->qsmcm_tranram[0] = SPI_EEPROM_RDSR; /* read status */ - qsmcm->qsmcm_tranram[1] = 0; - spi_xfer(2); - if (!(qsmcm->qsmcm_recram[1] & 1)) { - break; - } - udelay(1000); - } - if (i >= 1000) { - printf ("*** spi_write: Time out while writing!\n"); - } - return len; -} - -#define TRANSFER_LEN 16 - -ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int index,i,newlen; - uchar newaddr[2]; - int curraddr; - - curraddr=(addr[alen-2]<<8)+addr[alen-1]; - i=len; - index=0; - do { - newaddr[1]=(curraddr & 0xff); - newaddr[0]=((curraddr>>8) & 0xff); - if(i>TRANSFER_LEN) { - newlen=TRANSFER_LEN; - i-=TRANSFER_LEN; - } - else { - newlen=i; - i=0; - } - short_spi_write (newaddr, 2, &buffer[index], newlen); - index+=newlen; - curraddr+=newlen; - }while(i); - return (len); -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - volatile immap_t *immr; - volatile qsmcm5xx_t *qsmcm; - - immr = (immap_t *) CONFIG_SYS_IMMR; - qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; - - for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; - } - i=0; - qsmcm->qsmcm_tranram[i++] = (SPI_EEPROM_READ); /* READ memory array */ - qsmcm->qsmcm_tranram[i++] = addr[0] & 0xff; - qsmcm->qsmcm_tranram[i++] = addr[1] & 0xff; - spi_xfer(3 + len); - for(i=0;i<len;i++) { - *buffer++=(char)qsmcm->qsmcm_recram[i+3]; - } - return len; -} - -ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) -{ - int index,i,newlen; - uchar newaddr[2]; - int curraddr; - - curraddr=(addr[alen-2]<<8)+addr[alen-1]; - i=len; - index=0; - do { - newaddr[1]=(curraddr & 0xff); - newaddr[0]=((curraddr>>8) & 0xff); - if(i>TRANSFER_LEN) { - newlen=TRANSFER_LEN; - i-=TRANSFER_LEN; - } - else { - newlen=i; - i=0; - } - short_spi_read (newaddr, 2, &buffer[index], newlen); - index+=newlen; - curraddr+=newlen; - }while(i); - return (len); -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer (size_t count) -{ - volatile immap_t *immr; - volatile qsmcm5xx_t *qsmcm; - int i; - int tm; - ushort status; - immr = (immap_t *) CONFIG_SYS_IMMR; - qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; - DPRINT (("*** spi_xfer entered count %d***\n",count)); - - /* Set CS for device */ - for(i=0;i<(count-1);i++) - qsmcm->qsmcm_comdram[i] = 0x80 | CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ - - qsmcm->qsmcm_comdram[i] = CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ - qsmcm->qsmcm_spcr2=((count-1)&0x1F)<<8; - - DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", count)); - - qsmcm->qsmcm_spsr=0xE0; /* clear all flags */ - - /* start spi transfer */ - DPRINT (("*** spi_xfer: Performing transfer ...\n")); - qsmcm->qsmcm_spcr1 |= 0x8000; /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm=0; tm<1000; ++tm) { - status=qsmcm->qsmcm_spcr1; - if((status & 0x8000)==0) - break; - udelay (1000); - } - if (tm >= 1000) { - printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); - } -#ifdef DEBUG - printf ("\nspi_xfer: txbuf after xfer\n"); - memdump ((void *) qsmcm->qsmcm_tranram, 32); /* dump of txbuf before transmit */ - printf ("spi_xfer: rxbuf after xfer\n"); - memdump ((void *) qsmcm->qsmcm_recram, 32); /* dump of rxbuf after transmit */ - printf ("\nspi_xfer: commbuf after xfer\n"); - memdump ((void *) qsmcm->qsmcm_comdram, 32); /* dump of txbuf before transmit */ - printf ("\n"); -#endif - - return count; -} - -#endif /* CONFIG_SPI */ diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S deleted file mode 100644 index 6b196de..0000000 --- a/arch/powerpc/cpu/mpc5xx/start.S +++ /dev/null @@ -1,541 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek dmalek@jlc.net - * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> - * Copyright (C) 2000, 2001, 2002 Wolfgang Denk wd@denx.de - * Copyright (C) 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: start.S - * - * Discription: startup code - * - */ - -#include <asm-offsets.h> -#include <config.h> -#include <mpc5xx.h> -#include <version.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/processor.h> -#include <asm/u-boot.h> - -/* We don't have a MMU. -*/ -#undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */ - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - mfspr r3, 638 - li r4, CONFIG_SYS_ISB /* Set ISB bit */ - or r3, r3, r4 - mtspr 638, r3 - - /* Initialize machine status; enable machine check interrupt */ - /*----------------------------------------------------------------------*/ - li r3, MSR_KERNEL /* Set ME, RI flags */ - mtmsr r3 - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - /* Initialize debug port registers */ - /*----------------------------------------------------------------------*/ - xor r0, r0, r0 /* Clear R0 */ - mtspr LCTRL1, r0 /* Initialize debug port regs */ - mtspr LCTRL2, r0 - mtspr COUNTA, r0 - mtspr COUNTB, r0 - -#if defined(CONFIG_PATI) - /* the external flash access on PATI fails if programming the PLL to 40MHz. - * Copy the PLL programming code to the internal RAM and execute it - *----------------------------------------------------------------------*/ - lis r3, CONFIG_SYS_MONITOR_BASE@h - ori r3, r3, CONFIG_SYS_MONITOR_BASE@l - addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET - - lis r4, CONFIG_SYS_INIT_RAM_ADDR@h - ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l - mtlr r4 - addis r5,0,0x0 - ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2) - mtctr r5 - addi r3, r3, -4 - addi r4, r4, -4 -0: - lwzu r0,4(r3) - stwu r0,4(r4) - bdnz 0b /* copy loop */ - blrl -#endif - - /* - * Calculate absolute address in FLASH and jump there - *----------------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_MONITOR_BASE@h - ori r3, r3, CONFIG_SYS_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: - - /* Initialize some SPRs that are hard to access from C */ - /*----------------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_IMMR@h /* Pass IMMR as arg1 to C routine */ - lis r2, CONFIG_SYS_INIT_SP_ADDR@h - ori r1, r2, CONFIG_SYS_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */ - /* Note: R0 is still 0 here */ - stwu r0, -4(r1) /* Clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* - * Disable serialized ifetch and show cycles - * (i.e. set processor to normal mode) for maximum - * performance. - */ - - li r2, 0x0007 - mtspr ICTRL, r2 - - /* Set up debug mode entry */ - - lis r2, CONFIG_SYS_DER@h - ori r2, r2, CONFIG_SYS_DER@l - mtspr DER, r2 - - /* Let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*----------------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - - bl board_init_f /* run 1st part of board init code (from Flash) */ - - /* NOTREACHED - board_init_f() does not return */ - - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - /* FPU on MPC5xx available. We will use it later. - */ - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - /* On the MPC8xx, this is a software emulation interrupt. It occurs - * for all unimplemented and illegal instructions. - */ - STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) - - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) - STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException) - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - - . = 0x2000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - - -/* - * unsigned int get_immr (unsigned int mask) - * - * return (mask ? (IMMR & mask) : IMMR); - */ - .globl get_immr -get_immr: - mr r4,r3 /* save mask */ - mfspr r3, IMMR /* IMMR */ - cmpwi 0,r4,0 /* mask != 0 ? */ - beq 4f - and r3,r3,r4 /* IMMR & mask */ -4: - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer in SRAM */ - mr r9, r4 /* Save copy of global data pointer in SRAM */ - mr r10, r5 /* Save copy of monitor destination Address in SRAM */ - - GET_GOT - mr r3, r5 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* the the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 4f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -4: sync - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - cmpwi r0,0 - add r0,r0,r11 - stw r4,0(r3) - beq- 5f - stw r0,0(r4) -5: bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end) - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mtlr r4 /* restore link register */ - blr - -#if defined(CONFIG_PATI) -/* Program the PLL */ -pll_prog_code_start: - lis r4, (CONFIG_SYS_IMMR + 0x002fc384)@h - ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l - lis r3, (0x55ccaa33)@h - ori r3, r3, (0x55ccaa33)@l - stw r3, 0(r4) - lis r4, (CONFIG_SYS_IMMR + 0x002fc284)@h - ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l - lis r3, CONFIG_SYS_PLPRCR@h - ori r3, r3, CONFIG_SYS_PLPRCR@l - stw r3, 0(r4) - addis r3,0,0x0 - ori r3,r3,0xA000 - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - blr -pll_prog_code_end: - nop - blr -#endif diff --git a/arch/powerpc/cpu/mpc5xx/traps.c b/arch/powerpc/cpu/mpc5xx/traps.c deleted file mode 100644 index 6f31d81..0000000 --- a/arch/powerpc/cpu/mpc5xx/traps.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * linux/arch/powerpc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include <common.h> -#include <command.h> -#include <kgdb.h> -#include <asm/processor.h> - -#if defined(CONFIG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x0001000 - - -/* - * Print stack backtrace - */ -static void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -/* - * Print current registers - */ -void show_regs(struct pt_regs *regs) -{ - int i; - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -/* - * General exception handler routine - */ -static void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -/* - * Machine check exception handler routine - */ -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -/* - * Alignment exception handler routine - */ -void AlignmentException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -/* - * Program check exception handler routine - */ -void ProgramCheckException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -/* - * Software emulation exception handler routine - */ -void SoftEmuException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -/* - * Unknown exception handler routine - */ -void UnknownException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -/* - * Debug exception handler routine - */ -void DebugException(struct pt_regs *regs) -{ - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds deleted file mode 100644 index 6a53571..0000000 --- a/arch/powerpc/cpu/mpc5xx/u-boot.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2001-2010 Wolfgang Denk, DENX Software Engineering, wd@denx.de - * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc5xx/start.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); - . = env_start; - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } -} diff --git a/arch/powerpc/include/asm/5xx_immap.h b/arch/powerpc/include/asm/5xx_immap.h deleted file mode 100644 index 0a333c2..0000000 --- a/arch/powerpc/include/asm/5xx_immap.h +++ /dev/null @@ -1,424 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: 5xx_immap.h - * - * Discription: MPC555 Internal Memory Map - * - */ - -#ifndef __IMMAP_5XX__ -#define __IMMAP_5XX__ - -/* System Configuration Registers. -*/ -typedef struct sys_conf { - uint sc_siumcr; - uint sc_sypcr; - char res1[6]; - ushort sc_swsr; - uint sc_sipend; - uint sc_simask; - uint sc_siel; - uint sc_sivec; - uint sc_tesr; - uint sc_sgpiodt1; - uint sc_sgpiodt2; - uint sc_sgpiocr; - uint sc_emcr; - uint sc_res1aa; - uint sc_res1ab; - uint sc_pdmcr; - char res3[192]; -} sysconf5xx_t; - - -/* Memory Controller Registers. -*/ -typedef struct mem_ctlr { - uint memc_br0; - uint memc_or0; - uint memc_br1; - uint memc_or1; - uint memc_br2; - uint memc_or2; - uint memc_br3; - uint memc_or3; - char res1[32]; - uint memc_dmbr; - uint memc_dmor; - char res2[48]; - ushort memc_mstat; - ushort memc_res4a; - char res3[132]; -} memctl5xx_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - ushort sit_tbscr; - char res1[2]; - uint sit_tbref0; - uint sit_tbref1; - char res2[20]; - ushort sit_rtcsc; - char res3[2]; - uint sit_rtc; - uint sit_rtsec; - uint sit_rtcal; - char res4[16]; - ushort sit_piscr; - char res5[2]; - uint sit_pitc; - uint sit_pitr; - char res6[52]; -} sit5xx_t; - -/* Clocks and Reset -*/ -typedef struct clk_and_reset { - uint car_sccr; - uint car_plprcr; - ushort car_rsr; - ushort car_res7a; - ushort car_colir; - ushort car_res7b; - ushort car_vsrmcr; - ushort car_res7c; - char res1[108]; - -} car5xx_t; - -#define TBSCR_TBE ((ushort)0x0001) - -/* System Integration Timer Keys -*/ -typedef struct sitk { - uint sitk_tbscrk; - uint sitk_tbref0k; - uint sitk_tbref1k; - uint sitk_tbk; - char res1[16]; - uint sitk_rtcsck; - uint sitk_rtck; - uint sitk_rtseck; - uint sitk_rtcalk; - char res2[16]; - uint sitk_piscrk; - uint sitk_pitck; - char res3[56]; -} sitk5xx_t; - -/* Clocks and Reset Keys. -*/ -typedef struct cark { - uint cark_sccrk; - uint cark_plprcrk; - uint cark_rsrk; - char res1[1140]; -} cark8xx_t; - -/* The key to unlock registers maintained by keep-alive power. -*/ -#define KAPWR_KEY ((unsigned int)0x55ccaa33) - -/* Flash Configuration -*/ -typedef struct fl { - uint fl_cmfmcr; - uint fl_cmftst; - uint fl_cmfctl; - char res1[52]; -} fl5xx_t; - -/* Dpram Control -*/ -typedef struct dprc { - ushort dprc_dptmcr; - ushort dprc_ramtst; - ushort dprc_rambar; - ushort dprc_misrh; - ushort dprc_misrl; - ushort dprc_miscnt; -} dprc5xx_t; - -/* Time Processor Unit -*/ -typedef struct tpu { - ushort tpu_tpumcr; - ushort tpu_tcr; - ushort tpu_dscr; - ushort tpu_dssr; - ushort tpu_ticr; - ushort tpu_cier; - ushort tpu_cfsr0; - ushort tpu_cfsr1; - ushort tpu_cfsr2; - ushort tpu_cfsr3; - ushort tpu_hsqr0; - ushort tpu_hsqr1; - ushort tpu_hsrr0; - ushort tpu_hsrr1; - ushort tpu_cpr0; - ushort tpu_cpr1; - ushort tpu_cisr; - ushort tpu_lr; - ushort tpu_sglr; - ushort tpu_dcnr; - ushort tpu_tpumcr2; - ushort tpu_tpumcr3; - ushort tpu_isdr; - ushort tpu_iscr; - char res1[208]; - char tpu[16][16]; - char res2[512]; -} tpu5xx_t; - -/* QADC -*/ -typedef struct qadc { - ushort qadc_64mcr; - ushort qadc_64test; - ushort qadc_64int; - u_char qadc_portqa; - u_char qadc_portqb; - ushort qadc_ddrqa; - ushort qadc_qacr0; - ushort qadc_qacr1; - ushort qadc_qacr2; - ushort qadc_qasr0; - ushort qadc_qasr1; - char res1[492]; - /* command convertion word table */ - ushort qadc_ccw[64]; - /* result word table, unsigned right justified */ - ushort qadc_rjurr[64]; - /* result word table, signed left justified */ - ushort qadc_ljsrr[64]; - /* result word table, unsigned left justified */ - ushort qadc_ljurr[64]; -} qadc5xx_t; - -/* QSMCM -*/ -typedef struct qsmcm { - ushort qsmcm_qsmcr; - ushort qsmcm_qtest; - ushort qsmcm_qdsci_il; - ushort qsmcm_qspi_il; - ushort qsmcm_scc1r0; - ushort qsmcm_scc1r1; - ushort qsmcm_sc1sr; - ushort qsmcm_sc1dr; - char res1[2]; - char res2[2]; - ushort qsmcm_portqs; - u_char qsmcm_pqspar; - u_char qsmcm_ddrqs; - ushort qsmcm_spcr0; - ushort qsmcm_spcr1; - ushort qsmcm_spcr2; - u_char qsmcm_spcr3; - u_char qsmcm_spsr; - ushort qsmcm_scc2r0; - ushort qsmcm_scc2r1; - ushort qsmcm_sc2sr; - ushort qsmcm_sc2dr; - ushort qsmcm_qsci1cr; - ushort qsmcm_qsci1sr; - ushort qsmcm_sctq[16]; - ushort qsmcm_scrq[16]; - char res3[212]; - ushort qsmcm_recram[32]; - ushort qsmcm_tranram[32]; - u_char qsmcm_comdram[32]; - char res[3616]; -} qsmcm5xx_t; - - -/* MIOS -*/ - -typedef struct mios { - ushort mios_mpwmsm0perr; /* mpwmsm0 */ - ushort mios_mpwmsm0pulr; - ushort mios_mpwmsm0cntr; - ushort mios_mpwmsm0scr; - ushort mios_mpwmsm1perr; /* mpwmsm1 */ - ushort mios_mpwmsm1pulr; - ushort mios_mpwmsm1cntr; - ushort mios_mpwmsm1scr; - ushort mios_mpwmsm2perr; /* mpwmsm2 */ - ushort mios_mpwmsm2pulr; - ushort mios_mpwmsm2cntr; - ushort mios_mpwmsm2scr; - ushort mios_mpwmsm3perr; /* mpwmsm3 */ - ushort mios_mpwmsm3pulr; - ushort mios_mpwmsm3cntr; - ushort mios_mpwmsm3scr; - char res1[16]; - ushort mios_mmcsm6cnt; /* mmcsm6 */ - ushort mios_mmcsm6mlr; - ushort mios_mmcsm6scrd, mmcsm6scr; - char res2[32]; - ushort mios_mdasm11ar; /* mdasm11 */ - ushort mios_mdasm11br; - ushort mios_mdasm11scrd, mdasm11scr; - ushort mios_mdasm12ar; /* mdasm12 */ - ushort mios_mdasm12br; - ushort mios_mdasm12scrd, mdasm12scr; - ushort mios_mdasm13ar; /* mdasm13 */ - ushort mios_mdasm13br; - ushort mios_mdasm13scrd, mdasm13scr; - ushort mios_mdasm14ar; /* mdasm14 */ - ushort mios_mdasm14br; - ushort mios_mdasm14scrd, mdasm14scr; - ushort mios_mdasm15ar; /* mdasm15 */ - ushort mios_mdasm15br; - ushort mios_mdasm15scrd, mdasm15scr; - ushort mios_mpwmsm16perr; /* mpwmsm16 */ - ushort mios_mpwmsm16pulr; - ushort mios_mpwmsm16cntr; - ushort mios_mpwmsm16scr; - ushort mios_mpwmsm17perr; /* mpwmsm17 */ - ushort mios_mpwmsm17pulr; - ushort mios_mpwmsm17cntr; - ushort mios_mpwmsm17scr; - ushort mios_mpwmsm18perr; /* mpwmsm18 */ - ushort mios_mpwmsm18pulr; - ushort mios_mpwmsm18cntr; - ushort mios_mpwmsm18scr; - ushort mios_mpwmsm19perr; /* mpwmsm19 */ - ushort mios_mpwmsm19pulr; - ushort mios_mpwmsm19cntr; - ushort mios_mpwmsm19scr; - char res3[16]; - ushort mios_mmcsm22cnt; /* mmcsm22 */ - ushort mios_mmcsm22mlr; - ushort mios_mmcsm22scrd, mmcsm22scr; - char res4[32]; - ushort mios_mdasm27ar; /* mdasm27 */ - ushort mios_mdasm27br; - ushort mios_mdasm27scrd, mdasm27scr; - ushort mios_mdasm28ar; /*mdasm28 */ - ushort mios_mdasm28br; - ushort mios_mdasm28scrd, mdasm28scr; - ushort mios_mdasm29ar; /* mdasm29 */ - ushort mios_mdasm29br; - ushort mios_mdasm29scrd, mdasm29scr; - ushort mios_mdasm30ar; /* mdasm30 */ - ushort mios_mdasm30br; - ushort mios_mdasm30scrd, mdasm30scr; - ushort mios_mdasm31ar; /* mdasm31 */ - ushort mios_mdasm31br; - ushort mios_mdasm31scrd, mdasm31scr; - ushort mios_mpiosm32dr; - ushort mios_mpiosm32ddr; - char res5[1788]; - ushort mios_mios1tpcr; - char mios_res13[2]; - ushort mios_mios1vnr; - ushort mios_mios1mcr; - char res6[12]; - ushort mios_res42z; - ushort mios_mcpsmscr; - char res7[1000]; - ushort mios_mios1sr0; - char res12[2]; - ushort mios_mios1er0; - ushort mios_mios1rpr0; - char res8[40]; - ushort mios_mios1lvl0; - char res9[14]; - ushort mios_mios1sr1; - char res10[2]; - ushort mios_mios1er1; - ushort mios_mios1rpr1; - char res11[40]; - ushort mios_mios1lvl1; - char res13[1038]; -} mios5xx_t; - -/* Toucan Module -*/ -typedef struct tcan { - ushort tcan_tcnmcr; - ushort tcan_cantcr; - ushort tcan_canicr; - u_char tcan_canctrl0; - u_char tcan_canctrl1; - u_char tcan_presdiv; - u_char tcan_canctrl2; - ushort tcan_timer; - char res1[4]; - ushort tcan_rxgmskhi; - ushort tcan_rxgmsklo; - ushort tcan_rx14mskhi; - ushort tcan_rx14msklo; - ushort tcan_rx15mskhi; - ushort tcan_rx15msklo; - char res2[4]; - ushort tcan_estat; - ushort tcan_imask; - ushort tcan_iflag; - u_char tcan_rxectr; - u_char tcan_txectr; - char res3[88]; - struct { - ushort scr; - ushort id_high; - ushort id_low; - u_char data[8]; - char res4[2]; - } tcan_mbuff[16]; - char res5[640]; -} tcan5xx_t; - -/* UIMB -*/ -typedef struct uimb { - uint uimb_umcr; - char res1[12]; - uint uimb_utstcreg; - char res2[12]; - uint uimb_uipend; -} uimb5xx_t; - - -/* Internal Memory Map MPC555 -*/ -typedef struct immap { - char res1[262144]; /* CMF Flash A 256 Kbytes */ - char res2[196608]; /* CMF Flash B 192 Kbytes */ - char res3[2670592]; /* Reserved for Flash */ - sysconf5xx_t im_siu_conf; /* SIU Configuration */ - memctl5xx_t im_memctl; /* Memory Controller */ - sit5xx_t im_sit; /* System Integration Timers */ - car5xx_t im_clkrst; /* Clocks and Reset */ - sitk5xx_t im_sitk; /* System Integration Timer Keys*/ - cark8xx_t im_clkrstk; /* Clocks and Resert Keys */ - fl5xx_t im_fla; /* Flash Module A */ - fl5xx_t im_flb; /* Flash Module B */ - char res4[14208]; /* Reserved for SIU */ - dprc5xx_t im_dprc; /* Dpram Control Register */ - char res5[8180]; /* Reserved */ - char dptram[6144]; /* Dptram */ - char res6[2048]; /* Reserved */ - tpu5xx_t im_tpua; /* Time Proessing Unit A */ - tpu5xx_t im_tpub; /* Time Processing Unit B */ - qadc5xx_t im_qadca; /* QADC A */ - qadc5xx_t im_qadcb; /* QADC B */ - qsmcm5xx_t im_qsmcm; /* SCI and SPI */ - mios5xx_t im_mios; /* MIOS */ - tcan5xx_t im_tcana; /* Toucan A */ - tcan5xx_t im_tcanb; /* Toucan B */ - char res7[1792]; /* Reserved */ - uimb5xx_t im_uimb; /* UIMB */ -} immap_t; - -#endif /* __IMMAP_5XX__ */ diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h index f23ed3e..f5e9334 100644 --- a/arch/powerpc/include/asm/ppc.h +++ b/arch/powerpc/include/asm/ppc.h @@ -13,9 +13,7 @@

#ifndef __ASSEMBLY__

-#if defined(CONFIG_5xx) -#include <asm/5xx_immap.h> -#elif defined(CONFIG_MPC5xxx) +#if defined(CONFIG_MPC5xxx) #include <mpc5xxx.h> #elif defined(CONFIG_MPC512X) #include <asm/immap_512x.h> @@ -45,9 +43,6 @@ #include <asm/arch/immap_lsch2.h> #endif

-#if defined(CONFIG_5xx) -uint get_immr(uint); -#endif #if defined(CONFIG_MPC5xxx) uint get_svr(void); #endif diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h deleted file mode 100644 index 2767c05..0000000 --- a/arch/powerpc/include/asm/status_led.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * asm/status_led.h - * - * MPC8xx/MPC8260/MPC5xx based status led support functions - */ - -#ifndef __ASM_STATUS_LED_H__ -#define __ASM_STATUS_LED_H__ - -/* if not overridden */ -#ifndef CONFIG_LED_STATUS_BOARD_SPECIFIC -# if defined(CONFIG_5xx) -# include <mpc5xx.h> -# else -# error CPU specific Status LED header file missing. -#endif - -/* led_id_t is unsigned long mask */ -typedef unsigned long led_id_t; - -static inline void __led_init (led_id_t mask, int state) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - -#ifdef STATUS_LED_PAR - immr->STATUS_LED_PAR &= ~mask; -#endif -#ifdef STATUS_LED_ODR - immr->STATUS_LED_ODR &= ~mask; -#endif - -#if (STATUS_LED_ACTIVE == 0) - if (state == CONFIG_LED_STATUS_ON) - immr->STATUS_LED_DAT &= ~mask; - else - immr->STATUS_LED_DAT |= mask; -#else - if (state == CONFIG_LED_STATUS_ON) - immr->STATUS_LED_DAT |= mask; - else - immr->STATUS_LED_DAT &= ~mask; -#endif -#ifdef STATUS_LED_DIR - immr->STATUS_LED_DIR |= mask; -#endif -} - -static inline void __led_toggle (led_id_t mask) -{ - ((immap_t *) CONFIG_SYS_IMMR)->STATUS_LED_DAT ^= mask; -} - -static inline void __led_set (led_id_t mask, int state) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - -#if (STATUS_LED_ACTIVE == 0) - if (state == CONFIG_LED_STATUS_ON) - immr->STATUS_LED_DAT &= ~mask; - else - immr->STATUS_LED_DAT |= mask; -#else - if (state == CONFIG_LED_STATUS_ON) - immr->STATUS_LED_DAT |= mask; - else - immr->STATUS_LED_DAT &= ~mask; -#endif - -} - -#endif - -#endif /* __ASM_STATUS_LED_H__ */ diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c index c1a0a69..3a5ad4d 100644 --- a/arch/powerpc/lib/time.c +++ b/arch/powerpc/lib/time.c @@ -64,21 +64,10 @@ int timer_init(void) { unsigned long temp;

-#if defined(CONFIG_5xx) - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* unlock */ - immap->im_sitk.sitk_tbk = KAPWR_KEY; -#endif - /* reset */ asm volatile("li %0,0 ; mttbu %0 ; mttbl %0;" : "=&r"(temp) );

-#if defined(CONFIG_5xx) - /* enable */ - immap->im_sit.sit_tbscr |= TBSCR_TBE; -#endif return (0); } /* ------------------------------------------------------------------------- */ diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 5ea5a51..31636b3 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -28,10 +28,6 @@

DECLARE_GLOBAL_DATA_PTR;

-#if defined(CONFIG_PATI) -#define FIRM_START 0xFFF00000 -#endif - extern int mem_test(ulong start, ulong ramsize, int quiet);

#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */ @@ -189,11 +185,8 @@ mpl_prg(uchar *src, ulong size) ulong start; flash_info_t *info = &flash_info[0]; int i, rc; -#if defined(CONFIG_PATI) - int start_sect; -#endif -#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \ - || defined(CONFIG_TARGET_MIP405T) || defined(CONFIG_PATI) +#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) || \ + defined(CONFIG_TARGET_MIP405T) char *copystr = (char *)src; ulong *magic = (ulong *)src;

@@ -219,7 +212,6 @@ mpl_prg(uchar *src, ulong size) printf("Wrong Firmware Image: %s\n", &copystr[i]); return -1; } -#if !defined(CONFIG_PATI) start = 0 - size;

/* unprotect sectors used by u-boot */ @@ -241,38 +233,6 @@ mpl_prg(uchar *src, ulong size) flash_perror(rc); return (1); } - -#else /* #if !defined(CONFIG_PATI) */ - start = FIRM_START; - start_sect = -1; - - /* search start sector */ - for (i = info->sector_count-1; i > 0; i--) - if (start >= info->start[i]) - break; - - start_sect = i; - - for (i = info->sector_count-1; i > 0; i--) - if ((start + size) >= info->start[i]) - break; - - /* unprotect sectors used by u-boot */ - flash_protect(FLAG_PROTECT_CLEAR, - start, - start + size, - info); - - /* now erase flash */ - printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n", - start, start + size, start_sect, i, - info->start[start_sect], info->start[i]); - if ((rc = flash_erase (info, start_sect, i)) != 0) { - puts ("ERROR "); - flash_perror (rc); - return (1); - } -#endif /* defined(CONFIG_PATI) */ #endif printf("flash erased, programming from 0x%lx 0x%lx Bytes\n", (ulong)src, size); @@ -380,7 +340,6 @@ mpl_prg_image(uchar *ld_addr) return(rc); }

-#if !defined(CONFIG_PATI) void get_backup_values(backup_t *buf) { i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t)); @@ -541,17 +500,13 @@ void check_env(void) } }

-#endif /* #if !defined(CONFIG_PATI) */ - int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong ld_addr; int result; -#if !defined(CONFIG_PATI) ulong size = IMAGE_SIZE; ulong src = MULTI_PURPOSE_SOCKET_ADDR; backup_t back; -#endif

if (strcmp(argv[1], "flash") == 0) { @@ -587,15 +542,12 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) result=mpl_prg_image((uchar *)ld_addr); return result; } -#if !defined(CONFIG_PATI) if (strcmp(argv[2], "mps") == 0) { puts("\nupdating bootloader image from MPS\n"); result=mpl_prg((uchar *)src,size); return result; } -#endif /* #if !defined(CONFIG_PATI) */ } -#if !defined(CONFIG_PATI) if (strcmp(argv[1], "clearenvvalues") == 0) { if (strcmp(argv[2], "yes") == 0) @@ -618,7 +570,6 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) set_backup_values(1); return 0; } -#endif return cmd_usage(cmdtp); }

diff --git a/board/mpl/pati/Kconfig b/board/mpl/pati/Kconfig deleted file mode 100644 index 0eeaf70..0000000 --- a/board/mpl/pati/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_PATI - -config SYS_BOARD - default "pati" - -config SYS_VENDOR - default "mpl" - -config SYS_CONFIG_NAME - default "PATI" - -config ISO_STRING - string - default "MEV-10084-001" -endif diff --git a/board/mpl/pati/MAINTAINERS b/board/mpl/pati/MAINTAINERS deleted file mode 100644 index 19ad05d..0000000 --- a/board/mpl/pati/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PATI BOARD -#M: - -S: Maintained -F: board/mpl/pati/ -F: include/configs/PATI.h -F: configs/PATI_defconfig diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile deleted file mode 100644 index 9822082..0000000 --- a/board/mpl/pati/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := pati.o cmd_pati.o \ - ../common/common_util.o diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c deleted file mode 100644 index fcae5e0..0000000 --- a/board/mpl/pati/cmd_pati.c +++ /dev/null @@ -1,433 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Adapted for PATI - */ - -#include <common.h> -#include <command.h> -#define PLX9056_LOC -#include "plx9056.h" -#include "pati.h" -#include "pci_eeprom.h" - -extern void show_pld_regs(void); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - -extern void user_led0(int led_on); -extern void user_led1(int led_on); - -/* ------------------------------------------------------------------------- */ -#if defined(CONFIG_SYS_PCI_CON_DEVICE) -extern void pci_con_disc(void); -extern void pci_con_connect(void); -#endif - -/****************************************************************************** - * Eeprom Support - ******************************************************************************/ -unsigned long get32(unsigned long addr) -{ - unsigned long *p=(unsigned long *)addr; - return *p; -} - -void set32(unsigned long addr,unsigned long data) -{ - unsigned long *p=(unsigned long *)addr; - *p=data; -} - -#define PCICFG_GET_REG(x) (get32((x) + PCI_CONFIG_BASE)) -#define PCICFG_SET_REG(x,y) (set32((x) + PCI_CONFIG_BASE,(y))) - - -/****************************************************************************** - * reload_pci_eeprom - ******************************************************************************/ - -static void reload_pci_eeprom(void) -{ - unsigned long reg; - /* Set Bit 29 and clear it again */ - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - udelay(1); - /* set it*/ - reg|=(1<<29); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - /* EECLK @ 33MHz = 125kHz - * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec - * use 20msec - */ - udelay(20000); /* wait 20ms */ - reg &= ~(1<<29); /* set it low */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ -} - -/****************************************************************************** - * clock_pci_eeprom - ******************************************************************************/ - -static void clock_pci_eeprom(void) -{ - unsigned long reg; - /* clock is low, data is valid */ - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - udelay(1); - /* set clck high */ - reg|=(1<<24); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ - reg &= ~(1<<24); /* set clock low */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ -} - -/****************************************************************************** - * send_pci_eeprom_cmd - ******************************************************************************/ -static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len) -{ - unsigned long reg; - int i; - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Clear all EEPROM bits */ - reg &= ~(0xF << 24); - /* Toggle EEPROM's Chip select to get it out of Shift Register Mode */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ - /* Enable EEPROM Chip Select */ - reg |= (1 << 25); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - /* Send EEPROM command - one bit at a time */ - for (i = (int)(len-1); i >= 0; i--) { - /* Check if current bit is 0 or 1 */ - if (cmd & (1 << i)) - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26))); - else - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - clock_pci_eeprom(); - } -} - -/****************************************************************************** - * write_pci_eeprom_offs - ******************************************************************************/ -static void write_pci_eeprom_offs(unsigned short offset, unsigned short value) -{ - unsigned long reg; - int bitpos, cmdshft, cmdlen, timeout; - /* we're using the Eeprom 93CS66 */ - cmdshft = 2; - cmdlen = EE66_CMD_LEN; - /* Send Write_Enable command to EEPROM */ - send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen); - /* Send EEPROM Write command and offset to EEPROM */ - send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen); - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Clear all EEPROM bits */ - reg &= ~(0xF << 24); - /* Make sure EEDO Input is disabled for some PLX chips */ - reg &= ~(1 << 31); - /* Enable EEPROM Chip Select */ - reg |= (1 << 25); - /* Write 16-bit value to EEPROM - one bit at a time */ - for (bitpos = 15; bitpos >= 0; bitpos--) { - /* Get bit value and shift into result */ - if (value & (1 << bitpos)) - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26))); - else - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg ); - clock_pci_eeprom(); - } /* for */ - /* Deselect Chip */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25)); - /* Re-select Chip */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25)); - /* A small delay is needed to let EEPROM complete */ - timeout = 0; - do { - udelay(10); - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - timeout++; - } while (((reg & (1 << 27)) == 0) && timeout < 20000); - /* Send Write_Disable command to EEPROM */ - send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen); - /* Clear Chip Select and all other EEPROM bits */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); -} - - -/****************************************************************************** - * read_pci_eeprom_offs - ******************************************************************************/ -static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue) -{ - unsigned long reg; - int bitpos, cmdshft, cmdlen; - /* we're using the Eeprom 93CS66 */ - cmdshft = 2; - cmdlen = EE66_CMD_LEN; - /* Send EEPROM read command and offset to EEPROM */ - send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen); - /* Set EEPROM write output bit */ - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Set EEDO Input enable */ - reg |= (1 << 31); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26)); - /* Get 16-bit value from EEPROM - one bit at a time */ - for (bitpos = 0; bitpos < 16; bitpos++) { - clock_pci_eeprom(); - udelay(10); - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Get bit value and shift into result */ - if (reg & (1 << 27)) - *pvalue = (unsigned short)((*pvalue << 1) | 1); - else - *pvalue = (unsigned short)(*pvalue << 1); - } - /* Clear EEDO Input enable */ - reg &= ~(1 << 31); - /* Clear Chip Select and all other EEPROM bits */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); -} - - -/****************************************************************************** - * EEPROM read/writes -******************************************************************************/ - -#undef EEPROM_DBG -static int pati_pci_eeprom_erase(void) -{ - int i; - printf("Erasing EEPROM "); - for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) { - write_pci_eeprom_offs(i,0xffff); - if((i%0x10)) - printf("."); - } - printf("\nDone\n"); - return 0; -} - -static int pati_pci_eeprom_prg(void) -{ - int i; - i=0; - printf("Programming EEPROM "); - while(pati_eeprom[i].offset<0xffff) { - write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value); - #ifdef EEPROM_DBG - printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value); - #else - if((i%0x10)) - printf("."); - #endif - i++; - } - printf("\nDone\n"); - return 0; -} - -static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size) -{ - int i; - unsigned short value; - unsigned short *buffer =(unsigned short *)addr; - if((offset + size) > PATI_EEPROM_LAST_OFFSET) { - size = PATI_EEPROM_LAST_OFFSET - offset; - } - printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2); - for( i = offset; i< (offset + size); i+=2) { - value = *buffer++; - write_pci_eeprom_offs(i,value); - #ifdef EEPROM_DBG - printf("0x%04X: 0x%04X\n",i, value); - #else - if((i%0x10)) - printf("."); - #endif - } - printf("\nDone\n"); - return 0; -} - -static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size) -{ - int i; - unsigned short value = 0; - unsigned short *buffer =(unsigned short *)addr; - if((offset + size) > PATI_EEPROM_LAST_OFFSET) { - size = PATI_EEPROM_LAST_OFFSET - offset; - } - printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2); - for( i = offset; i< (offset + size); i+=2) { - read_pci_eeprom_offs(i,&value); - *buffer++=value; - #ifdef EEPROM_DBG - printf("0x%04X: 0x%04X\n",i, value); - #else - if((i%0x10)) - printf("."); - #endif - } - printf("\nDone\n"); - return 0; -} - -/****************************************************************************** - * PCI Bridge Registers Dump -*******************************************************************************/ -static void display_pci_regs(void) -{ - printf(" PCI9056_SPACE0_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE)); - printf(" PCI9056_SPACE0_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP)); - printf(" PCI9056_LOCAL_DMA_ARBIT %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT)); - printf(" PCI9056_ENDIAN_DESC %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC)); - printf(" PCI9056_EXP_ROM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE)); - printf(" PCI9056_EXP_ROM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP)); - printf(" PCI9056_SPACE0_ROM_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC)); - printf(" PCI9056_DM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE)); - printf(" PCI9056_DM_MEM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE)); - printf(" PCI9056_DM_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE)); - printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP)); - printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG)); - printf(" PCI9056_SPACE1_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE)); - printf(" PCI9056_SPACE1_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP)); - printf(" PCI9056_SPACE1_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC)); - printf(" PCI9056_DM_DAC %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC)); - printf(" PCI9056_MAILBOX0 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0)); - printf(" PCI9056_MAILBOX1 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1)); - printf(" PCI9056_MAILBOX2 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2)); - printf(" PCI9056_MAILBOX3 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3)); - printf(" PCI9056_MAILBOX4 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4)); - printf(" PCI9056_MAILBOX5 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5)); - printf(" PCI9056_MAILBOX6 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6)); - printf(" PCI9056_MAILBOX7 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7)); - printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL)); - printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL)); - printf(" PCI9056_INT_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT)); - printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT)); - printf(" PCI9056_PERM_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID)); - printf(" PCI9056_REVISION_ID %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID)); - printf(" \n"); - printf(" PCI9056_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID)); - printf(" PCI9056_COMMAND %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND)); - printf(" PCI9056_REVISION %08lX\n",PCICFG_GET_REG(PCI9056_REVISION)); - printf(" PCI9056_CACHE_SIZE %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE)); - printf(" PCI9056_RTR_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE)); - printf(" PCI9056_RTR_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE)); - printf(" PCI9056_LOCAL_BASE0 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0)); - printf(" PCI9056_LOCAL_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1)); - printf(" PCI9056_UNUSED_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1)); - printf(" PCI9056_UNUSED_BASE2 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2)); - printf(" PCI9056_CIS_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR)); - printf(" PCI9056_SUB_ID %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID)); - printf(" PCI9056_EXP_ROM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE)); - printf(" PCI9056_CAP_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR)); - printf(" PCI9056_INT_LINE %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE)); - printf(" PCI9056_PM_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID)); - printf(" PCI9056_PM_CSR %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR)); - printf(" PCI9056_HS_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID)); - printf(" PCI9056_VPD_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID)); - printf(" PCI9056_VPD_DATA %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA)); -} - - -int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (strcmp(argv[1], "info") == 0) - { - show_pld_regs(); - return 0; - } - if (strcmp(argv[1], "pci") == 0) - { - display_pci_regs(); - return 0; - } - if (strcmp(argv[1], "led") == 0) - { - int led_nr,led_on; - led_nr = (int)simple_strtoul(argv[2], NULL, 10); - led_on = (int)simple_strtoul(argv[3], NULL, 10); - if(!led_nr) - user_led0(led_on); - else - user_led1(led_on); - return 0; - } -#if defined(CONFIG_SYS_PCI_CON_DEVICE) - if (strcmp(argv[1], "con") == 0) { - pci_con_connect(); - return 0; - } - if (strcmp(argv[1], "disc") == 0) { - pci_con_disc(); - return 0; - } -#endif - if (strcmp(argv[1], "eeprom") == 0) { - unsigned long addr; - int size, offset; - offset = 0; - size = PATI_EEPROM_LAST_OFFSET; - if(argc>2) { - if(argc>3) { - addr = simple_strtoul(argv[3], NULL, 16); - if(argc>4) - offset = (int) simple_strtoul(argv[4], NULL, 16); - if(argc>5) - size = (int) simple_strtoul(argv[5], NULL, 16); - if (strcmp(argv[2], "read") == 0) { - return (pati_pci_eeprom_read(offset, addr, size)); - } - if (strcmp(argv[2], "write") == 0) { - return (pati_pci_eeprom_write(offset, addr, size)); - } - } - if (strcmp(argv[2], "prg") == 0) { - return (pati_pci_eeprom_prg()); - } - if (strcmp(argv[2], "era") == 0) { - return (pati_pci_eeprom_erase()); - } - if (strcmp(argv[2], "reload") == 0) { - reload_pci_eeprom(); - return 0; - } - - - } - } - - return (do_mplcommon(cmdtp, flag, argc, argv)); -} - -U_BOOT_CMD( - pati, 8, 1, do_pati, - "PATI specific Cmds", - "info - displays board information\n" - "pati pci - displays PCI registers\n" - "pati led <nr> <on> \n" - " - switch LED <nr> <on>\n" - "pati flash mem [SrcAddr]\n" - " - updates U-Boot with image in memory\n" - "pati eeprom <cmd> - PCI EEPROM sub-system\n" - " read <addr> <offset> <size>\n" - " - read PCI EEPROM to <addr> from <offset> <size> words\n" - " write <addr> <offset> <size>\n" - " - write PCI EEPROM from <addr> to <offset> <size> words\n" - " prg - programm PCI EEPROM with default values\n" - " era - erase PCI EEPROM (write all word to 0xffff)\n" - " reload- Reload PCI Bridge with EEPROM Values\n" - " NOTE: <addr> must start on word boundary\n" - " <offset> and <size> must be even byte values" -); - -/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c deleted file mode 100644 index 1288f74..0000000 --- a/board/mpl/pati/pati.c +++ /dev/null @@ -1,610 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * Atapted for PATI - * Denis Peter, d.peter@mpl.ch - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*********************************************************************************** - * Bits for the SDRAM controller - * ----------------------------- - * - * CAL: CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on - * the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM - * controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3). - * RCD: RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default) - * tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns. - * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns. - * If set to 1 tWR must be equal or less 50ns. - * RP: Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less - * 25ns. If set to 1 tRP must be equal or less 50ns. - * RC: Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal - * or less 75ns. If set to 1 tRC must be equal or less 100ns. - * LMR: Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM - * is the Load Mode Register Command. - * IIP: Init in progress. Set to 1 for starting the init sequence - * (Precharge All). As long this bit is set, the Precharge All is still in progress. - * After command has completed, wait at least for 8 refresh (200usec) before proceed. - **********************************************************************************/ - -#include <common.h> -#include <console.h> -#include <mpc5xx.h> -#include <stdio_dev.h> -#include <pci_ids.h> -#define PLX9056_LOC -#include "plx9056.h" -#include "pati.h" - -#if defined(__APPLE__) -/* Leading underscore on symbols */ -# define SYM_CHAR "_" -#else /* No leading character on symbols */ -# define SYM_CHAR -#endif - -#undef SDRAM_DEBUG -/* - * Macros to generate global absolutes. - */ -#define GEN_SYMNAME(str) SYM_CHAR #str -#define GEN_VALUE(str) #str -#define GEN_ABS(name, value) \ - asm (".globl " GEN_SYMNAME(name)); \ - asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) - - -DECLARE_GLOBAL_DATA_PTR; - -/************************************************************************ - * Early debug routines - */ -void write_hex (unsigned char i) -{ - char cc; - - cc = i >> 4; - cc &= 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); - cc = i & 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); -} - -#if defined(SDRAM_DEBUG) - -void write_4hex (unsigned long val) -{ - write_hex ((unsigned char) (val >> 24)); - write_hex ((unsigned char) (val >> 16)); - write_hex ((unsigned char) (val >> 8)); - write_hex ((unsigned char) val); -} - -#endif - -unsigned long in32(unsigned long addr) -{ - unsigned long *p=(unsigned long *)addr; - return *p; -} - -void out32(unsigned long addr,unsigned long data) -{ - unsigned long *p=(unsigned long *)addr; - *p=data; -} - -typedef struct { - unsigned short boardtype; /* Board revision and Population Options */ - unsigned char cal; /* cas Latency 0:CAL=2 1:CAL=3 */ - unsigned char rcd; /* ras to cas delay 0:<25ns 1:<50ns*/ - unsigned char wrec; /* write recovery 0:<25ns 1:<50ns */ - unsigned char pr; /* Precharge Command Time 0:<25ns 1:<50ns */ - unsigned char rc; /* Auto Refresh to Active Time 0:<75ns 1:<100ns */ - unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */ -} sdram_t; - -const sdram_t sdram_table[] = { - { 0x0000, /* PATI Rev A, 16MByte -1 Board */ - 1, /* Case Latenty = 3 */ - 0, /* ras to cas delay 0 (20ns) */ - 0, /* write recovery 0:<25ns 1:<50ns*/ - 0, /* Precharge Command Time 0 (20ns) */ - 0, /* Auto Refresh to Active Time 0 (68) */ - 2 /* log binary => Size 2 = 16MByte, 1=8 */ - }, - { 0xffff, /* terminator */ - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff } -}; - - -extern int mem_test (unsigned long start, unsigned long ramsize, int quiet); - -/* - * Get RAM size. - */ -int dram_init(void) -{ - unsigned char board_rev; - unsigned long reg; - unsigned long lmr; - int i,timeout; - -#if defined(SDRAM_DEBUG) - reg=in32(PLD_CONFIG_BASE+PLD_PART_ID); - puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg)); - puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg)); - puts("\nSDRAM part 0x"); write_4hex(SDRAM_PART(reg)); - puts(" Vers 0x"); write_4hex(SDRAM_ID(reg)); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - puts("\nBoard rev. 0x"); write_4hex(SYSCNTR_BREV(reg)); - putc('\n'); -#endif - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - board_rev=(unsigned char)(SYSCNTR_BREV(reg)); - i=0; - while(1) { - if(sdram_table[i].boardtype==0xffff) { - puts("ERROR, found no table for Board 0x"); - write_hex(board_rev); - while(1); - } - if(sdram_table[i].boardtype==(unsigned char)board_rev) - break; - i++; - } - /* Set CAL, RCD, WREQ, PR and RC Bits */ -#if defined(SDRAM_DEBUG) - puts("Set CAL, RCD, WREQ, PR and RC Bits\n"); -#endif - /* mask bits */ - reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) | - SET_REG_BIT(1,SDRAM_PR) | SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR) | - SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0)); - /* set bits */ - reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) | - SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) | - SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) | - SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) | - SET_REG_BIT(sdram_table[i].rc,SDRAM_RC)); - - out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg); - /* step 2 set IIP */ -#if defined(SDRAM_DEBUG) - puts("step 2 set IIP\n"); -#endif - /* step 2 set IIP */ - reg |= SET_REG_BIT(1,SDRAM_IIP); - timeout=0; - while (timeout!=0xffff) { - __asm__ volatile("eieio"); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - if((reg & SET_REG_BIT(1,SDRAM_IIP))==0) - break; - timeout++; - udelay(1); - } - /* wait for at least 8 refresh */ - udelay(1000); - /* set LMR */ - reg |= SET_REG_BIT(1,SDRAM_LMR); - out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg); - __asm__ volatile("eieio"); - lmr=0x00000002; /* sequential burst 4 data */ - if(sdram_table[i].cal==1) - lmr|=0x00000030; /* cal = 3 */ - else - lmr|=0000000020; /* cal = 2 */ - /* rest standard operation programmed write burst length */ - /* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */ - lmr<<=2; - in32(CONFIG_SYS_SDRAM_BASE + lmr); - /* ok, we're done, set SDRAM size to log2 value of 4MByte*/ - gd->ram_size = 0x400000 << sdram_table[i].sz; - - return 0; -} - - -void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp) -{ - unsigned long reg; - reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE); - reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) | - SET_REG_BIT(1,SYSCNTR_FL_VPP) | - SET_REG_BIT(1,SYSCNTR_FL_WP)); - - reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) | - SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) | - SET_REG_BIT(ext_wp,SYSCNTR_FL_WP)); - out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg); - udelay(100); -} - - -void show_pld_regs(void) -{ - unsigned long reg,reg1; - reg=in32(PLD_CONFIG_BASE+PLD_PART_ID); - printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg)); - printf("SDRAM part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg)); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - printf("Board rev. %c\n",(char) (SYSCNTR_BREV(reg)+'A')); - printf("Waitstates %ld\n",GET_SYSCNTR_FLWAIT(reg)); - printf("SDRAM: CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n RC=%ld LMR=%ld IIP=%ld\n", - GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD), - GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR), - GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR), - GET_REG_BIT(reg,SDRAM_IIP)); - reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1); - reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2); - printf("HW Config: FLAG=%ld IP=%ld index=%ld PRPM=%ld\n ICW=%ld ISB=%ld BDIS=%ld PCIM=%ld\n", - GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP), - GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM), - GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg), - GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM)); - printf("Switches: MUX=%ld PCI_DIS=%ld Boot_EN=%ld Config=%ld\n",GET_SDRAM_MUX(reg), - GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN), - GET_SYSCNTR_CFG(reg1)); - printf("Misc: RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n", - GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP), - GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP)); -} - - -/**************************************************************** - * Setting IOs - * ----------- - * GPIO6 is User LED1 - * GPIO7 is Interrupt PLX (Output) - * GPIO5 is User LED0 - * GPIO2 is PLX USERi (Output) - * GPIO1 is PLX Interrupt (Input) - ****************************************************************/ - void init_ios(void) - { - volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR; - volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; - unsigned long reg; - reg=sysconf->sc_sgpiocr; /* Data direction register */ - reg &= ~0x67000000; - reg |= 0x27000000; /* set outpupts */ - sysconf->sc_sgpiocr=reg; /* Data direction register */ - reg=sysconf->sc_sgpiodt2; /* Data register */ - /* set output to 0 */ - reg &= ~0x27000000; - /* set IRQ and USERi to 1 */ - reg |= 0x28000000; - sysconf->sc_sgpiodt2=reg; /* Data register */ -} - -void user_led0(int led_on) -{ - volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR; - volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; - unsigned long reg; - reg=sysconf->sc_sgpiodt2; /* Data register */ - if(led_on) /* set output to 1 */ - reg |= 0x04000000; - else - reg &= ~0x04000000; - sysconf->sc_sgpiodt2=reg; /* Data register */ -} - -void user_led1(int led_on) -{ - volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR; - volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; - unsigned long reg; - reg=sysconf->sc_sgpiodt2; /* Data register */ - if(led_on) /* set output to 1 */ - reg |= 0x02000000; - else - reg &= ~0x02000000; - sysconf->sc_sgpiodt2=reg; /* Data register */ -} - -int board_early_init_f(void) -{ - spi_init_f(); - return 0; -} - -/**************************************************************** - * Last Stage Init - ****************************************************************/ -int last_stage_init (void) -{ - init_ios(); - return 0; -} - -/**************************************************************** - * Check the board - ****************************************************************/ - -#define BOARD_NAME "PATI" - -int checkboard (void) -{ - char s[50]; - ulong reg; - char rev; - int i; - - puts ("\nBoard: "); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - rev=(char)(SYSCNTR_BREV(reg)+'A'); - i = getenv_f("serial#", s, 32); - if ((i == -1)) { - puts ("### No HW ID - assuming " BOARD_NAME); - printf(" Rev. %c\n",rev); - } - else { - s[sizeof(BOARD_NAME)-1] = 0; - printf ("%s-1 Rev %c SN: %s\n", s,rev, - &s[sizeof(BOARD_NAME)]); - } - set_flash_vpp(1,0,0); /* set Flash VPP */ - return 0; -} - - -#ifdef CONFIG_SYS_PCI_CON_DEVICE -/************************************************************************ - * PCI Communication - * - * Alive (Pinging): - * ---------------- - * PCI Host sends message ALIVE, Local acknowledges with ALIVE - * - * PCI_CON console over PCI: - * ------------------------- - * Local side: - * - uses PCI9056_LOC_TO_PCI_DBELL register to signal that - * data is avaible (PCIMSG_CONN) - * - uses PCI9056_MAILBOX1 to send data - * - uses PCI9056_MAILBOX0 to receive data - * PCI side: - * - uses PCI9056_PCI_TO_LOC_DBELL register to signal that - * data is avaible (PCIMSG_CONN) - * - uses PCI9056_MAILBOX0 to send data - * - uses PCI9056_MAILBOX1 to receive data - * - * How it works: - * Send: - * - check if PCICON_TRANSMIT_REG is empty - * - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG - * - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data - * is waiting - * Receive: - * - get an interrupt via the PCICON_ACK_REG register message - * PCIMSG_CONN - * - write the data from the PCICON_RECEIVE_REG into the receive - * buffer and if the receive buffer is not full, clear the - * PCICON_RECEIVE_REG (this allows the counterpart to write more data) - * - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG - * - * The PCICON_RECEIVE_REG must be cleared by the routine which reads - * the receive buffer if the buffer is not full any more - * - */ - -#undef PCI_CON_DEBUG - -#ifdef PCI_CON_DEBUG -#define PCI_CON_PRINTF(fmt,args...) serial_printf (fmt ,##args) -#else -#define PCI_CON_PRINTF(fmt,args...) -#endif - - -/********************************************************* - * we work only with a receive buffer on eiter side. - * Transmit buffer is free, if mailbox is cleared. - * Transmit character is or'ed with 0x80000000 - * PATI receive register MAILBOX0 - * PATI transmit register MAILBOX1 - *********************************************************/ -#define PCICON_RECEIVE_REG PCI9056_MAILBOX0 -#define PCICON_TRANSMIT_REG PCI9056_MAILBOX1 -#define PCICON_DBELL_REG PCI9056_LOC_TO_PCI_DBELL -#define PCICON_ACK_REG PCI9056_PCI_TO_LOC_DBELL - - -#define PCIMSG_ALIVE 0x1 -#define PCIMSG_CONN 0x2 -#define PCIMSG_DISC 0x3 -#define PCIMSG_CON_DATA 0x5 - - -#define PCICON_GET_REG(x) (in32(x + PCI_CONFIG_BASE)) -#define PCICON_SET_REG(x,y) (out32(x + PCI_CONFIG_BASE,y)) -#define PCICON_TX_FLAG 0x80000000 - - -#define REC_BUFFER_SIZE 0x100 -int recbuf[REC_BUFFER_SIZE]; -static int r_ptr = 0; -int w_ptr; -struct stdio_dev pci_con_dev; -int conn=0; -int buff_full=0; - -void pci_con_put_it(const char c) -{ - /* Test for completition */ - unsigned long reg; - do { - reg=PCICON_GET_REG(PCICON_TRANSMIT_REG); - }while(reg); - reg=PCICON_TX_FLAG + c; - PCICON_SET_REG(PCICON_TRANSMIT_REG,reg); - PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA); -} - -void pci_con_putc(struct stdio_dev *dev, const char c) -{ - pci_con_put_it(c); - if(c == '\n') - pci_con_put_it('\r'); -} - - -int pci_con_getc(struct stdio_dev *dev) -{ - int res; - int diff; - while(r_ptr==(volatile int)w_ptr); - res=recbuf[r_ptr++]; - if(r_ptr==REC_BUFFER_SIZE) - r_ptr=0; - if(w_ptr<r_ptr) - diff=r_ptr+REC_BUFFER_SIZE-w_ptr; - else - diff=r_ptr-w_ptr; - if((diff<(REC_BUFFER_SIZE-4)) && buff_full) { - /* clear Mail box */ - buff_full=0; - PCICON_SET_REG(PCICON_RECEIVE_REG,0L); - } - return res; -} - -int pci_con_tstc(struct stdio_dev *dev) -{ - if(r_ptr==(volatile int)w_ptr) - return 0; - return 1; -} - -void pci_con_puts(struct stdio_dev *dev, const char *s) -{ - while (*s) { - pci_con_putc(*s); - ++s; - } -} - -void pci_con_init (void) -{ - w_ptr = 0; - r_ptr = 0; - PCICON_SET_REG(PCICON_RECEIVE_REG,0L); - conn=1; -} - -/******************************************* - * IRQ routine - ******************************************/ -int pci_dorbell_irq(void) -{ - unsigned long reg,data; - int diff; - reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT); - PCI_CON_PRINTF(" PCI9056_INT_CTRL_STAT = %08lX\n",reg); - if(reg & (1<<20) ) { - /* read doorbell */ - reg=PCICON_GET_REG(PCICON_ACK_REG); - switch(reg) { - case PCIMSG_ALIVE: - PCI_CON_PRINTF(" Alive\n"); - PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_ALIVE); - break; - case PCIMSG_CONN: - PCI_CON_PRINTF(" Conn %d",conn); - w_ptr = 0; - r_ptr = 0; - buff_full=0; - PCICON_SET_REG(PCICON_RECEIVE_REG,0L); - conn=1; - PCI_CON_PRINTF(" ... %d\n",conn); - break; - case PCIMSG_CON_DATA: - data=PCICON_GET_REG(PCICON_RECEIVE_REG); - recbuf[w_ptr++]=(int)(data&0xff); - PCI_CON_PRINTF(" Data Console %lX, %X %d %d %X\n",data,((int)(data&0xFF)), - r_ptr,w_ptr,recbuf[w_ptr-1]); - if(w_ptr==REC_BUFFER_SIZE) - w_ptr=0; - if(w_ptr<r_ptr) - diff=r_ptr+REC_BUFFER_SIZE-w_ptr; - else - diff=r_ptr-w_ptr; - if(diff>(REC_BUFFER_SIZE-4)) - buff_full=1; - else - /* clear Mail box */ - PCICON_SET_REG(PCICON_RECEIVE_REG,0L); - break; - default: - serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg); - } - /* clear IRQ */ - PCICON_SET_REG(PCICON_ACK_REG,~0L); - } - return 0; -} - -void pci_con_connect(void) -{ - unsigned long reg; - conn=0; - reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT); - /* default 0x0f010180 */ - reg &= 0xff000000; - reg |= 0x00030000; /* enable local dorbell */ - reg |= 0x00000300; /* enable PCI dorbell */ - PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg); - irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL); - memset (&pci_con_dev, 0, sizeof (pci_con_dev)); - strcpy (pci_con_dev.name, "pci_con"); - pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; - pci_con_dev.putc = pci_con_putc; - pci_con_dev.puts = pci_con_puts; - pci_con_dev.getc = pci_con_getc; - pci_con_dev.tstc = pci_con_tstc; - stdio_register (&pci_con_dev); - printf("PATI ready for PCI connection, type ctrl-c for exit\n"); - do { - udelay(10); - if((volatile int)conn) - break; - if(ctrlc()) { - irq_free_handler(0x2); - return; - } - }while(1); - console_assign(stdin,"pci_con"); - console_assign(stderr,"pci_con"); - console_assign(stdout,"pci_con"); -} - -void pci_con_disc(void) -{ - console_assign(stdin,"serial"); - console_assign(stderr,"serial"); - console_assign(stdout,"serial"); - PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC); - /* reconnection */ - irq_free_handler(0x02); - pci_con_connect(); -} -#endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */ - -/* - * Absolute environment address for linker file. - */ -GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE); diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h deleted file mode 100644 index 93a5918..0000000 --- a/board/mpl/pati/pati.h +++ /dev/null @@ -1,423 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter, d.peter@mpl.ch - * SPDX-License-Identifier: GPL-2.0+ - */ -/************************************************************************ - * MACROS and register definitions for PATI Registers - ************************************************************************/ -#ifndef __PATI_H_ -#define __PATI_H_ 1 - -#define PLD_PART_ID 0x0 -#define PLD_BOARD_TIMING 0x4 -#define PLD_CONF_REG1 0x8 -#define PLD_CONF_REG2 0xC -#define PLD_CONF_RES 0x10 - -#define SET_REG_BIT(y,x) (y<<(31-x)) -#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L) - -/* SDRAM Controller PLD_PART_ID */ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_PART3 9 -#define SDRAM_PART2 10 -#define SDRAM_PART1 11 -#define SDRAM_PART0 12 -#define SDRAM_ID3 13 -#define SDRAM_ID2 14 -#define SDRAM_ID1 19 -#define SDRAM_ID0 31 - -#define SDRAM_PART(x) ( \ - (GET_REG_BIT(x,SDRAM_PART3)<<3) |\ - (GET_REG_BIT(x,SDRAM_PART2)<<2) |\ - (GET_REG_BIT(x,SDRAM_PART1)<<1) |\ - (GET_REG_BIT(x,SDRAM_PART0))) - -#define SDRAM_ID(x) ( \ - (GET_REG_BIT(x,SDRAM_ID3)<<3) |\ - (GET_REG_BIT(x,SDRAM_ID2)<<2) |\ - (GET_REG_BIT(x,SDRAM_ID1)<<1) |\ - (GET_REG_BIT(x,SDRAM_ID0))) - -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_PART4 0 -#define SYSCNTR_PART3 1 -#define SYSCNTR_PART2 3 -#define SYSCNTR_PART1 4 -#define SYSCNTR_PART0 5 -#define SYSCNTR_ID4 16 -#define SYSCNTR_ID3 20 -#define SYSCNTR_ID2 28 -#define SYSCNTR_ID1 29 -#define SYSCNTR_ID0 30 - -#define SYSCNTR_PART(x) ( \ - (GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\ - (GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\ - (GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_PART0))) - -#define SYSCNTR_ID(x) ( \ - (GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\ - (GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\ - (GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_ID0))) - -/* SDRAM Controller PLD_BOARD_TIMING */ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_CAL 9 -#define SDRAM_RCD 10 -#define SDRAM_WREQ 11 -#define SDRAM_PR 12 -#define SDRAM_RC 13 -#define SDRAM_LMR 14 -#define SDRAM_IIP 19 -#define SDRAM_RES0 31 -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_BREV0 0 -#define SYSCNTR_BREV1 1 -#define SYSCNTR_BREV2 3 -#define SYSCNTR_BREV3 4 -#define SYSCNTR_RES0 5 -#define SYSCNTR_RES1 16 -#define SYSCNTR_RES2 20 -#define SYSCNTR_FLWAIT2 28 -#define SYSCNTR_FLWAIT1 29 -#define SYSCNTR_FLWAIT0 30 - -#define SYSCNTR_BREV(x) ( \ - (GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\ - (GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_BREV0))) - -#define GET_SYSCNTR_FLWAIT(x) ( \ - (GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_FLWAIT0))) - -#define SET_SYSCNTR_FLWAIT(x) ( \ - (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\ - (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\ - (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0))) - -/* SDRAM Controller REG 2*/ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_MUX0 9 -#define SDRAM_MUX1 10 -#define SDRAM_PDIS 11 -#define SDRAM_RES1 12 -#define SDRAM_RES2 13 -#define SDRAM_RES3 14 -#define SDRAM_RES4 19 -#define SDRAM_RIP 31 - -#define GET_SDRAM_MUX(x) ( \ - (GET_REG_BIT(x,SDRAM_MUX1)<<1)| \ - (GET_REG_BIT(x,SDRAM_MUX0))) - - -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_FLAG 0 -#define SYSCNTR_IP 1 -#define SYSCNTR_BIND2 3 -#define SYSCNTR_BIND1 4 -#define SYSCNTR_BIND0 5 -#define SYSCNTR_PRM 16 -#define SYSCNTR_ICW 20 -#define SYSCNTR_ISB2 28 -#define SYSCNTR_ISB1 29 -#define SYSCNTR_ISB0 30 - -#define GET_SYSCNTR_BOOTIND(x) ( \ - (GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_BIND0))) - -#define SET_SYSCNTR_BOOTIND(x) ( \ - (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\ - (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \ - (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0))) - -#define GET_SYSCNTR_ISB(x) ( \ - (GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \ - (GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \ - (GET_REG_BIT(x,SYSCNTR_ISB0))) - -#define SET_SYSCNTR_ISB(x) ( \ - (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \ - (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \ - (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0))) - -/* SDRAM Controller REG 3*/ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_RES5 9 -#define SDRAM_CFG1 10 -#define SDRAM_CFG2 11 -#define SDRAM_CFG3 12 -#define SDRAM_RES6 13 -#define SDRAM_CFG5 14 -#define SDRAM_CFG6 19 -#define SDRAM_RES7 31 - -#define GET_SDRAM_CFG(x) ( \ - (GET_REG_BIT(x,SDRAM_CFG6)<<4) |\ - (GET_REG_BIT(x,SDRAM_CFG5)<<3) |\ - (GET_REG_BIT(x,SDRAM_CFG3)<<2) |\ - (GET_REG_BIT(x,SDRAM_CFG2)<<1) |\ - (GET_REG_BIT(x,SDRAM_CFG1))) - -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_BDIS 0 -#define SYSCNTR_PCIM 1 -#define SYSCNTR_CFG0 3 -#define SYSCNTR_CFG1 4 -#define SYSCNTR_CFG2 5 -#define SYSCNTR_CFG3 16 -#define SYSCNTR_BOOTEN 20 -#define SYSCNTR_CPU_VPP 28 -#define SYSCNTR_FL_VPP 29 -#define SYSCNTR_FL_WP 30 - -#define GET_SYSCNTR_CFG(x) ( \ - (GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \ - (GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \ - (GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \ - (GET_REG_BIT(x,SYSCNTR_CFG0))) - - -/*************************************************************** - * MISC Defines - ***************************************************************/ - -#define PCI_VENDOR_ID_MPL 0x18E6 -#define PCI_DEVICE_ID_PATI 0x00DA - -#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T) -#define PATI_FIRMWARE_START_OFFSET 0x00300000 -#endif - -#define PATI_ENDIAN_MODE 0x3E - -/******************************************* - * PATI Mapping: - * ------------- - * PCI Map: - * ------- - * All addreses are mapped into the memory area - * (IO Area on some areas may also be possible) - * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes - * - pci_space0_addr: configurable - * - pci_space1_addr configurable - * - * Local Map: - * ---------- - * Local addresses (Remap) - * - SDRAM 0x06000000 Size 16MByte mask 0xff000000 - * - EPLD CFG 0x07000000 Size 512Bytes - * - FLASH 0x03000000 Size up to 8MByte - * - CPU 0x01000000 Size 4MByte (only accessable if special configured) - * - * Implemention: - * ------------- - * To prevent using large resources reservation on the host following - * PCI mapping is choosed: - * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes - * - pci_space0_addr: configured to the EPLD Config Area size 256Bytes - * - pci_space1_addr: configured to the SDRAM Area size 1MBytes, this - * space is used to switch between SDRAM, Flash and CPU - * - */ - -/* Attribute definitions */ -#define PATI_BUS_SIZE_8 0 -#define PATI_BUS_SIZE_16 1 -#define PATI_BUS_SIZE_32 3 - -#define PATI_SPACE0_MASK (0xFEFFFE00) /* Mask Attributes */ -#define PATI_SPACE1_MASK (0x00000000) /* Mask Attributes */ - -#define PATI_EXTRA_LONG_EEPROM 1 - -#define SPACE0_TA_ENABLE (1<<6) -#define SPACE1_TA_ENABLE (1<<6) - -/* Config Area */ -#define PATI_LOC_CFG_ADDR 0x07000000 /* Local Address */ -#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */ -/* Attributes */ -#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_CFG_BURST 0 /* No Burst */ -#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */ - -#define PATI_LOC_CFG_SPACE0_ATTR ( \ - PATI_LOC_CFG_BUS_SIZE | \ - (PATI_LOC_CFG_TA_ENABLE << 6) | \ - (PATI_LOC_CFG_NO_PREFETCH << 8) | \ - (PATI_LOC_CFG_BURST << 24) | \ - (PATI_EXTRA_LONG_EEPROM << 25)) - -/* should never be used */ -#define PATI_LOC_CFG_SPACE1_ATTR ( \ - PATI_LOC_CFG_BUS_SIZE | \ - (PATI_LOC_CFG_TA_ENABLE << 6) | \ - (PATI_LOC_CFG_NO_PREFETCH << 9) | \ - (PATI_LOC_CFG_BURST << 8)) - - -/* SDRAM Area */ -#define PATI_LOC_SDRAM_ADDR 0x06000000 /* Local Address */ -#define PATI_LOC_SDRAM_MASK 0xFFF00000 /* 1MByte */ -/* Attributes */ -#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_SDRAM_BURST 0 /* No Burst */ -#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */ -#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */ - -/* should never be used */ -#define PATI_LOC_SDRAM_SPACE0_ATTR ( \ - PATI_LOC_SDRAM_BUS_SIZE | \ - (PATI_LOC_SDRAM_TA_ENABLE << 6) | \ - (PATI_LOC_SDRAM_NO_PREFETCH << 8) | \ - (PATI_LOC_SDRAM_BURST << 24) | \ - (PATI_EXTRA_LONG_EEPROM << 25)) - -#define PATI_LOC_SDRAM_SPACE1_ATTR ( \ - PATI_LOC_SDRAM_BUS_SIZE | \ - (PATI_LOC_SDRAM_TA_ENABLE << 6) | \ - (PATI_LOC_SDRAM_NO_PREFETCH << 9) | \ - (PATI_LOC_SDRAM_BURST << 8)) - - -/* Flash Area */ -#define PATI_LOC_FLASH_ADDR 0x03000000 /* Local Address */ -#define PATI_LOC_FLASH_MASK 0xFFF00000 /* 1MByte */ -/* Attributes */ -#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */ -#define PATI_LOC_FLASH_BURST 0 /* No Burst */ -#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */ - -/* should never be used */ -#define PATI_LOC_FLASH_SPACE0_ATTR ( \ - PATI_LOC_FLASH_BUS_SIZE | \ - (PATI_LOC_FLASH_TA_ENABLE << 6) | \ - (PATI_LOC_FLASH_NO_PREFETCH << 8) | \ - (PATI_LOC_FLASH_BURST << 24) | \ - (PATI_EXTRA_LONG_EEPROM << 25)) - -#define PATI_LOC_FLASH_SPACE1_ATTR ( \ - PATI_LOC_FLASH_BUS_SIZE | \ - (PATI_LOC_FLASH_TA_ENABLE << 6) | \ - (PATI_LOC_FLASH_NO_PREFETCH << 9) | \ - (PATI_LOC_FLASH_BURST << 8)) - - -/* CPU Area */ -#define PATI_LOC_CPU_ADDR 0x01000000 /* Local Address */ -#define PATI_LOC_CPU_MASK 0xFFF00000 /* 1Mbyte */ -/* Attributes */ -#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_CPU_BURST 0 /* No Burst */ -#define PATI_LOC_CPU_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_CPU_TA_ENABLE 1 /* Enable TA */ - -/* should never be used */ -#define PATI_LOC_CPU_SPACE0_ATTR ( \ - PATI_LOC_CPU_BUS_SIZE | \ - (PATI_LOC_CPU_TA_ENABLE << 6) | \ - (PATI_LOC_CPU_NO_PREFETCH << 8) | \ - (PATI_LOC_CPU_BURST << 24) | \ - (PATI_EXTRA_CPU_EEPROM << 25)) - -#define PATI_LOC_CPU_SPACE1_ATTR ( \ - PATI_LOC_CPU_BUS_SIZE | \ - (PATI_LOC_CPU_TA_ENABLE << 6) | \ - (PATI_LOC_CPU_NO_PREFETCH << 9) | \ - (PATI_LOC_CPU_BURST << 8)) - -/*************************************************** - * Hardware Config word definition - ***************************************************/ -#define BOOT_EXT_FLASH 0x00000000 -#define BOOT_INT_FLASH 0x00000004 -#define BOOT_FROM_PCI 0x00000006 -#define BOOT_FROM_SDRAM 0x00000005 - -#define ENABLE_INT_ARB 0x00000008 - -#define INITIAL_IRQ_PREF 0x00000010 - -#define INITIAL_MEM_0M 0x00000000 -#define INITIAL_MEM_4M 0x00000080 -#define INITIAL_MEM_8M 0x00000040 -#define INITIAL_MEM_12M 0x000000C0 -#define INITIAL_MEM_16M 0x00000020 -#define INITIAL_MEM_20M 0x000000A0 -#define INITIAL_MEM_24M 0x00000060 -#define INITIAL_MEM_28M 0x000000E0 -/* CONF */ -#define INTERNAL_HWCONF 0x00000100 -/* PRPM */ -#define LOCAL_CPU_SLAVE 0x00000200 -/* BDIS */ -#define DISABLE_MEM_CNTR 0x00000400 -/* PCIM */ -#define PCI_MASTER_ONLY 0x00000800 - - -#define PATI_HW_START ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF)) -#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) -#define PATI_HW_CPU_ACC ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) -#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE)) - -/*************************************************** - * Direct Master Config - ***************************************************/ -#define PATI_DMASTER_PCI_ADDR 0x01000000 -#define PATI_BUS_MASTER 1 - - -#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */ -#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */ - -#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */ -#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */ -#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */ -#define PATI_DMASTER_PRE_SIZE_CNTRL_0 0x00000000 -#define PATI_DMASTER_PRE_SIZE_CNTRL_4 0x00000008 -#define PATI_DMASTER_PRE_SIZE_CNTRL_8 0x00001000 -#define PATI_DMASTER_PRE_SIZE_CNTRL_16 0x00001008 -#define PATI_DMASTER_REL_PCI 0x00000000 -#define PATI_DMASTER_NOT_REL_PCI 0x00000010 -#define PATI_DMASTER_WR_INVAL 0x00000200 -#define PATI_DMASTER_NOT_WR_INVAL 0x00000000 -#define PATI_DMASTER_PRE_LIMIT 0x00000800 -#define PATI_DMASTER_PRE_CONT 0x00000000 -#define PATI_DMASTER_DELAY_WR_0 0x00000000 -#define PATI_DMASTER_DELAY_WR_4 0x00004000 -#define PATI_DMASTER_DELAY_WR_8 0x00008000 -#define PATI_DMASTER_DELAY_WR_16 0x0000C000 - -#define PATI_DMASTER_PCI_ADDR_MASK 0xFFFF0000 - -#define PATI_DMASTER_ATTR \ - PATI_DMASTER_MEMORY_EN | \ - PATI_DMASTER_READ_AHEAD | \ - PATI_DMASTER_PRE_SIZE_CNTRL_4 | \ - PATI_DMASTER_REL_PCI | \ - PATI_DMASTER_NOT_WR_INVAL | \ - PATI_DMASTER_PRE_LIMIT | \ - PATI_DMASTER_DELAY_WR_0 - - -#endif /* #ifndef __PATI_H_ */ diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h deleted file mode 100644 index 459c143..0000000 --- a/board/mpl/pati/pci_eeprom.h +++ /dev/null @@ -1,90 +0,0 @@ -#ifndef __PCI_EEPROM_H_ -#define __PCI_EEPROM_H_ 1 - -#include "pati.h" -/****************************************************************************** - * Eeprom Support - ******************************************************************************/ -/********************************************** -* Definitions -**********************************************/ -#define EE46_CMD_LEN 9 /* Bits in instructions */ -#define EE56_CMD_LEN 11 /* Bits in instructions */ -#define EE66_CMD_LEN 11 /* Bits in instructions */ -#define EE_READ 0x0180 /* 01 1000 0000 read instruction */ -#define EE_WRITE 0x0140 /* 01 0100 0000 write instruction */ -#define EE_WREN 0x0130 /* 01 0011 0000 write enable instruction */ -#define EE_WRALL 0x0110 /* 01 0001 0000 write all registers */ -#define EE_PRREAD 0x0180 /* 01 1000 0000 read address stored in Protect Register */ -#define EE_PRWRITE 0x0140 /* 01 0100 0000 write the address into PR */ -#define EE_WDS 0x0100 /* 01 0000 0000 write disable instruction */ -#define EE_PREN 0x0130 /* 01 0011 0000 protect enable instruction */ -#define EE_PRCLEAR 0x01FF /* 01 1111 1111 clear protect register instr */ -#define EE_PRDS 0x0100 /* 01 0000 0000 ONE TIME ONLY, permenant */ - -/*************************************************** - * EEPROM - ***************************************************/ -#define LOW_WORD(x) (((x) & 0xFFFF)) -#define HIGH_WORD(x) (((x) >> 16) & 0xFFFF) - -typedef struct pci_eeprom_t { - unsigned short offset; - unsigned short value; -} pci_eeprom; - -static pci_eeprom pati_eeprom[] = { - { 0x00,PCI_DEVICE_ID_PATI }, /* PCI Device ID PCIIDR[31:16] */ - { 0x02,PCI_VENDOR_ID_MPL }, /* PCI Vendor ID PCIIDR[15:0] */ - { 0x04,PCI_CLASS_PROCESSOR_POWERPC }, /* PCI Class Code PCICCR[23:8] */ - { 0x06,0x00BA }, /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */ - { 0x08,0x0007 }, /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */ - { 0x0A,0x0100 }, /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */ - { 0x0C,0x0000 }, /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */ - { 0x0E,0x0000 }, /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */ - { 0x10,0x0000 }, /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */ - { 0x12,0x0000 }, /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */ - { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */ - { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */ - { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */ - { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */ - { 0x1C,0x0000 }, /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */ - { 0x1E,0x0000 }, /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */ - { 0x20,0x0030 }, /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */ - { 0x22,0x0510 }, /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */ - { 0x24,0x0000 }, /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */ - { 0x26,0x0000 }, /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1] */ - { 0x28,0x0000 }, /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */ - { 0x2A,0x0000 }, /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */ - { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */ - { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */ - { 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */ - { 0x32,LOW_WORD(PATI_DMASTER_MASK) }, /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */ - { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */ - { 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */ - { 0x38,0x0000 }, /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */ - { 0x3A,0x0000 }, /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */ - { 0x3C,0x0000 }, /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */ - { 0x3E,0x0000 }, /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */ - { 0x40,0x0000 }, /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/ - { 0x42,0x0000 }, /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */ - { 0x44,0x0000 }, /* PCI Subsystem ID PCISID[15:0] */ - { 0x46,0x0000 }, /* PCI Subsystem Vendor ID PCISVID[15:0] */ - { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */ - { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */ - { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */ - { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */ - { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */ - { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */ - { 0x54,0x0000 }, /* Hot Swap Control/Status (Reserved) Reserved */ - { 0x56,0x0000 }, /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */ - { 0x58,0x0000 }, /* Reserved Reserved */ - { 0x5A,0x0000 }, /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */ - { 0x5C,0x0000 }, /* Power Management Capabilities PMC[15:9, 2:0] */ - { 0x5E,0x0000 }, /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/ - { 0x60,0x0000 }, /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */ - { 0x62,0x0000 }, /* Power Management Control/Status PMCSR[14:8] */ - { 0xFFFF,0xFFFF} /* terminaror */ -}; -#define PATI_EEPROM_LAST_OFFSET 0x64 -#endif /* #ifndef __PCI_EEPROM_H_ */ diff --git a/board/mpl/pati/plx9056.h b/board/mpl/pati/plx9056.h deleted file mode 100644 index 754e720..0000000 --- a/board/mpl/pati/plx9056.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter, d.peter@mpl.ch - * SPDX-License-Identifier: GPL-2.0+ - */ -/* PLX9096 register definitions -*/ -#ifndef __PLX9056_H_ -#define __PLX9056_H_ 1 - -#include <pci.h> - -#ifdef PLX9056_LOC -#define LOCAL_OFFSET 0x080 -/* PCI Config regs */ -#else -#define LOCAL_OFFSET 0x000 -#endif - -#define PCI9056_VENDOR_ID PCI_VENDOR_ID -/*#define PCI9656_DEVICE_ID PCI_DEVICE_ID */ -#define PCI9056_COMMAND PCI_COMMAND -/*#define PCI9656_STATUS PCI_STATUS */ -#define PCI9056_REVISION PCI_REVISION_ID - -#define PCI9056_CACHE_SIZE PCI_CACHE_LINE_SIZE -#define PCI9056_RTR_BASE PCI_BASE_ADDRESS_0 -#define PCI9056_RTR_IO_BASE PCI_BASE_ADDRESS_1 -#define PCI9056_LOCAL_BASE0 PCI_BASE_ADDRESS_2 -#define PCI9056_LOCAL_BASE1 PCI_BASE_ADDRESS_3 -#define PCI9056_UNUSED_BASE1 PCI_BASE_ADDRESS_4 -#define PCI9056_UNUSED_BASE2 PCI_BASE_ADDRESS_5 -#define PCI9056_CIS_PTR PCI_CARDBUS_CIS -#define PCI9056_SUB_ID PCI_SUBSYSTEM_VENDOR_ID -#define PCI9056_EXP_ROM_BASE PCI_ROM_ADDRESS -#define PCI9056_CAP_PTR PCI_CAPABILITY_LIST -#define PCI9056_INT_LINE PCI_INTERRUPT_LINE - -#if defined(PLX9056_LOC) - #define PCI9056_PM_CAP_ID 0x180 - #define PCI9056_PM_CSR 0x184 - #define PCI9056_HS_CAP_ID 0x188 - #define PCI9056_VPD_CAP_ID 0x18C - #define PCI9056_VPD_DATA 0x190 -#endif - - -#define PCI_DEVICE_ID_PLX9056 0x9056 - -/* Local Configuration Registers Accessible via the PCI Base address + Variable */ -#define PCI9056_SPACE0_RANGE (0x000 + LOCAL_OFFSET) -#define PCI9056_SPACE0_REMAP (0x004 + LOCAL_OFFSET) -#define PCI9056_LOCAL_DMA_ARBIT (0x008 + LOCAL_OFFSET) -#define PCI9056_ENDIAN_DESC (0x00c + LOCAL_OFFSET) -#define PCI9056_EXP_ROM_RANGE (0x010 + LOCAL_OFFSET) -#define PCI9056_EXP_ROM_REMAP (0x014 + LOCAL_OFFSET) -#define PCI9056_SPACE0_ROM_DESC (0x018 + LOCAL_OFFSET) -#define PCI9056_DM_RANGE (0x01c + LOCAL_OFFSET) -#define PCI9056_DM_MEM_BASE (0x020 + LOCAL_OFFSET) -#define PCI9056_DM_IO_BASE (0x024 + LOCAL_OFFSET) -#define PCI9056_DM_PCI_MEM_REMAP (0x028 + LOCAL_OFFSET) -#define PCI9056_DM_PCI_IO_CONFIG (0x02c + LOCAL_OFFSET) -#define PCI9056_SPACE1_RANGE (0x0f0 + LOCAL_OFFSET) -#define PCI9056_SPACE1_REMAP (0x0f4 + LOCAL_OFFSET) -#define PCI9056_SPACE1_DESC (0x0f8 + LOCAL_OFFSET) -#define PCI9056_DM_DAC (0x0fc + LOCAL_OFFSET) - -#ifdef PLX9056_LOC -#define PCI9056_ARBITER_CTRL 0x1A0 -#define PCI9056_ABORT_ADDRESS 0x1A4 -#endif - -/* Runtime registers PCI Address + LOCAL_OFFSET */ -#ifdef PLX9056_LOC -#define PCI9056_MAILBOX0 0x0C0 -#define PCI9056_MAILBOX1 0x0C4 -#else -#define PCI9056_MAILBOX0 0x078 -#define PCI9056_MAILBOX1 0x07c -#endif - -#define PCI9056_MAILBOX2 (0x048 + LOCAL_OFFSET) -#define PCI9056_MAILBOX3 (0x04c + LOCAL_OFFSET) -#define PCI9056_MAILBOX4 (0x050 + LOCAL_OFFSET) -#define PCI9056_MAILBOX5 (0x054 + LOCAL_OFFSET) -#define PCI9056_MAILBOX6 (0x058 + LOCAL_OFFSET) -#define PCI9056_MAILBOX7 (0x05c + LOCAL_OFFSET) -#define PCI9056_PCI_TO_LOC_DBELL (0x060 + LOCAL_OFFSET) -#define PCI9056_LOC_TO_PCI_DBELL (0x064 + LOCAL_OFFSET) -#define PCI9056_INT_CTRL_STAT (0x068 + LOCAL_OFFSET) -#define PCI9056_EEPROM_CTRL_STAT (0x06c + LOCAL_OFFSET) -#define PCI9056_PERM_VENDOR_ID (0x070 + LOCAL_OFFSET) -#define PCI9056_REVISION_ID (0x074 + LOCAL_OFFSET) - -#endif /* #ifndef __PLX9056_H_ */ diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 81967ff..48dba20 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -183,8 +183,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_bi_flash(bd); print_num("sramstart", bd->bi_sramstart); print_num("sramsize", bd->bi_sramsize); -#if defined(CONFIG_5xx) || \ - defined(CONFIG_E500) +#if defined(CONFIG_E500) print_num("immr_base", bd->bi_immr_base); #endif print_num("bootflags", bd->bi_bootflags); diff --git a/cmd/reginfo.c b/cmd/reginfo.c index d971a8f..6918a9e 100644 --- a/cmd/reginfo.c +++ b/cmd/reginfo.c @@ -9,8 +9,6 @@ #include <command.h> #if defined (CONFIG_4xx) extern void ppc4xx_reginfo(void); -#elif defined (CONFIG_5xx) -#include <mpc5xx.h> #elif defined (CONFIG_MPC5200) #include <mpc5xxx.h> #elif defined (CONFIG_MPC86xx) @@ -24,41 +22,6 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, { #if defined (CONFIG_4xx) ppc4xx_reginfo(); -#elif defined(CONFIG_5xx) - - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl5xx_t *memctl = &immap->im_memctl; - volatile sysconf5xx_t *sysconf = &immap->im_siu_conf; - volatile sit5xx_t *timers = &immap->im_sit; - volatile car5xx_t *car = &immap->im_clkrst; - volatile uimb5xx_t *uimb = &immap->im_uimb; - - puts ("\nSystem Configuration registers\n"); - printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr); - printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr); - printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask); - printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec); - printf("\tTESR\t0x%08X\n", sysconf->sc_tesr); - - puts ("\nMemory Controller Registers\n"); - printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); - printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); - printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); - printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); - printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor ); - printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat); - - puts ("\nSystem Integration Timers\n"); - printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc); - printf("\tPISCR\t0x%08X \n", timers->sit_piscr); - - puts ("\nClocks and Reset\n"); - printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr); - - puts ("\nU-Bus to IMB3 Bus Interface\n"); - printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend); - puts ("\n\n"); - #elif defined(CONFIG_MPC5200) puts ("\nMPC5200 registers\n"); printf ("MBAR=%08x\n", CONFIG_SYS_MBAR); diff --git a/common/board_f.c b/common/board_f.c index b02ca37..0a1ef1a 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -547,8 +547,7 @@ static int setup_board_part1(void) bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ #endif

-#if defined(CONFIG_5xx) || \ - defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ #endif #if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) diff --git a/configs/PATI_defconfig b/configs/PATI_defconfig deleted file mode 100644 index cd78de7..0000000 --- a/configs/PATI_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -CONFIG_PPC=y -CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10084-001 released" -CONFIG_5xx=y -CONFIG_TARGET_PATI=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SYS_PROMPT="pati=> " -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -CONFIG_CMD_BSP=y -CONFIG_CMD_IRQ=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_BAUDRATE=9600 diff --git a/doc/README.mpc5xx b/doc/README.mpc5xx deleted file mode 100644 index df51b5c..0000000 --- a/doc/README.mpc5xx +++ /dev/null @@ -1,48 +0,0 @@ - -Summary: -======== - -This file contains information about the port of U-Boot to the -Motorola mpc5xx series of CPUs. Most of this code is taken from -existing code mainly from the mpc8xx port. In contrast to mpc8xx, -the mpc5xx has no CPM, MMU and cache facilities. - -The implemented features have been tested on the cmi board, a -customer specific board (see README.cmi). - -Hence this port is only tested on the cmi board further possible -tests on other boards will be very valuable. - -Not Tested Features: -==================== - -* System calls -* Interrupts - -Added or Changed Files: -======================= - -u-boot-0.2.0/common/cmd_boot.c -u-boot-0.2.0/common/cmd_reginfo.c -u-boot-0.2.0/common/environment.c -u-boot-0.2.0/arch/powerpc/cpu/mpc5xx/* -u-boot-0.2.0/include/cmd_reginfo.h -u-boot-0.2.0/include/common.h -u-boot-0.2.0/include/ppc_asm.tmpl -u-boot-0.2.0/include/watchdog.h -u-boot-0.2.0/include/mpc5xx.h -u-boot-0.2.0/include/status_led.h -u-boot-0.2.0/include/asm-ppc/u-boot.h -u-boot-0.2.0/include/asm-ppc/5xx_immap.h -u-boot-0.2.0/arch/powerpc/lib/board.c -u-boot-0.2.0/arch/powerpc/lib/cache.c -u-boot-0.2.0/arch/powerpc/lib/time.c -u-boot-0.2.0/Makefile -u-boot-0.2.0/CREDITS -u-boot-0.2.0/doc/README.mpc5xx -u-boot-0.2.0/doc/README.cmi -u-boot-0.2.0/README -u-boot-0.2.0/MAKEALL - -Regards, -Martin diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index a779713..0c1bdc7 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -41,8 +41,7 @@ typedef struct bd_info { unsigned long bi_dsp_freq; /* dsp core frequency */ unsigned long bi_ddr_freq; /* ddr frequency */ #endif -#if defined(CONFIG_5xx) \ - || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif #if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) diff --git a/include/configs/PATI.h b/include/configs/PATI.h deleted file mode 100644 index 1f26ac4..0000000 --- a/include/configs/PATI.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: PATI.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_PATI 1 /* ...On a PATI board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* Serial Console Configuration */ -#define CONFIG_5xx_CONS_SCI1 -#undef CONFIG_5xx_CONS_SCI2 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_REGINFO - -#define CONFIG_BOOTCOMMAND "" /* autoboot command */ - -#define CONFIG_BOOTARGS "" /* */ - -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ - -#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_PREBOOT - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } - -/*********************************************************************** - * Last Stage Init - ***********************************************************************/ -#define CONFIG_LAST_STAGE_INIT - -/* - * Low Level Configuration Settings - */ - -/* - * Internal Memory Mapped (This is not the IMMR content) - */ -#define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */ - -/* - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */ -/* - * Start addresses for the final memory configuration - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ -#define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */ -#define PCI_BASE 0x03000000 /* PCI Base (CS2) */ -#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ -#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ - -#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 -/* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - *----------------------------------------------------------------------- - * - */ - -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_FLASH_SHOW_PROGRESS 45 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -#define CONFIG_ENV_IS_IN_EEPROM -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_OFFSET 0 -#define CONFIG_ENV_SIZE 2048 -#endif - -#undef CONFIG_ENV_IS_IN_FLASH -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */ -#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ -#endif - -#define CONFIG_SPI 1 -#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ -#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */ -#define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */ -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * SW Watchdog freeze - */ -#undef CONFIG_WATCHDOG -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ - SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration - *----------------------------------------------------------------------- - * Data show cycle - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register - *----------------------------------------------------------------------- - * Set all bits to 40 Mhz - * - */ -#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ - -#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) - -/*----------------------------------------------------------------------- - * UMCR - UIMB Module Configuration Register - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ - -/*----------------------------------------------------------------------- - * ICTRL - I-Bus Support Control Register - */ -#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ - -/*----------------------------------------------------------------------- - * USIU - Memory Controller Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) -#define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ -/* SDRAM */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) -#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ -/* PCI */ -#define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) -#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) -/* config registers: */ -#define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) -#define CONFIG_SYS_OR3_PRELIM (0xffff0000) - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ - -/*----------------------------------------------------------------------- - * DER - Timer Decrementer - *----------------------------------------------------------------------- - * Initialise to zero - */ -#define CONFIG_SYS_DER 0x00000000 - -#endif /* __CONFIG_H */ diff --git a/include/mpc5xx.h b/include/mpc5xx.h deleted file mode 100644 index 6c170dc..0000000 --- a/include/mpc5xx.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: mpc5xx.h - * - * Discription: mpc5xx specific definitions - * - */ - -#ifndef __MPC5XX_H__ -#define __MPC5XX_H__ - - -/*----------------------------------------------------------------------- - * Exception offsets (PowerPC standard) - */ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET EXC_OFF_SYS_RESET - -/*----------------------------------------------------------------------- - * ISB bit in IMMR to set internal memory map - */ - -#define CONFIG_SYS_ISB ((CONFIG_SYS_IMMR / 0x00400000) << 1) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control Register - */ -#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */ -#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */ -#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */ -#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */ -#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ -#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */ -#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration Register - */ -#define SIUMCR_EARB 0x80000000 /* External Arbitration */ -#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */ -#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */ -#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */ -#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */ -#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */ -#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */ -#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */ -#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */ -#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */ -#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */ -#define SIUMCR_DBGC01 0x00200000 /* - " - */ -#define SIUMCR_DBGC10 0x00400000 /* - " - */ -#define SIUMCR_DBGC11 0x00600000 /* - " - */ -#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */ -#define SIUMCR_DBPC01 0x00080000 /* - " - */ -#define SIUMCR_DBPC10 0x00100000 /* - " - */ -#define SIUMCR_DBPC11 0x00180000 /* - " - */ -#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ -#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ -#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ -#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ -#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ -#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */ -#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */ -#define SIUMCR_SC10 0x00004000 /* Single adress show */ -#define SIUMCR_SC11 0x00006000 /* Single adress */ -#define SIUMCR_RCTX 0x00001000 /* Data Parity pins Config. */ -#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */ -#define SIUMCR_MLRC01 0x00000400 /* - " - */ -#define SIUMCR_MLRC10 0x00000800 /* - " - */ -#define SIUMCR_MLRC11 0x00000c00 /* - " - */ -#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control Register - */ -#define TBSCR_REFA ((ushort)0x0080) /* Reference Interrupt Status A */ -#define TBSCR_REFB ((ushort)0x0040) /* Reference Interrupt Status B */ -#define TBSCR_TBF ((ushort)0x0002) /* Time Base stops while FREEZE */ - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control Register - */ -#define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */ -#define PISCR_PS 0x0080 /* Periodic Interrupt Status */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register - */ -#define PLPRCR_MF_MSK 0xfff00000 /* MF mask */ -#define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */ -#define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */ -#define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */ -#define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */ -#define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */ -#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ -#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ -#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ -#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register - */ -#define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */ -#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ -#define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */ -#define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */ -#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */ -#define SCCR_EBDF11 0x00060000 /* reserved */ -#define SCCR_TBS 0x02000000 /* Time Base Source */ -#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ -#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ -#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ -#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ -#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ - -/*----------------------------------------------------------------------- - * MC - Memory Controller - */ -#define BR_V 0x00000001 /* Bank valid */ -#define BR_BI 0x00000002 /* Burst inhibit */ -#define BR_PS_8 0x00000400 /* 8 bit port size */ -#define BR_PS_16 0x00000800 /* 16 bit port size */ -#define BR_PS_32 0x00000000 /* 32 bit port size */ -#define BR_LBDIR 0x00000008 /* Late burst data in progess */ -#define BR_SETA 0x00000004 /* External Data Acknowledge */ -#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */ -#define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */ -#define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */ -#define OR_TRLX 0x00000001 /* Timing relaxed */ -#define OR_BSCY 0x00000060 /* Burst beats length in clocks */ -#define OR_ACS_10 0x00000600 /* Adress to chip-select setup */ -#define OR_CSNT 0x00000800 /* Chip-select negotation time */ -#define OR_ETHR 0x00000100 /* Extended hold time on read */ -#define OR_ADDR_MK_FF 0xFF000000 -#define OR_ADDR_MK_FFFF 0xFFFF0000 - -/*----------------------------------------------------------------------- - * UMCR - UIMB Module Configuration Register - */ -#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ -#define UMCR_HSPEED 0x10000000 /* Half speed */ - -/*----------------------------------------------------------------------- - * ICTRL - I-Bus Support Control Register - */ -#define ICTRL_ISCT_SER_7 0x00000007 /* All indirect change of flow */ - - -#define NR_IRQS 0 /* Place this later in a separate file */ - -/*----------------------------------------------------------------------- - * SCI - Serial communication interface - */ - -#define SCI_TDRE 0x0100 /* Transmit data register empty */ -#define SCI_TE 0x0008 /* Transmitter enabled */ -#define SCI_RE 0x0004 /* Receiver enabled */ -#define SCI_RDRF 0x0040 /* Receive data register full */ -#define SCI_PE 0x0400 /* Parity enable */ -#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ -#define SCI_SCXDR_MK 0x00ff /* Data register mask */ -#define SCI_M_11 0x0200 /* Frame size is 11 bit */ -#define SCI_M_10 0x0000 /* Frame size is 10 bit */ -#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ -#define SCI_PORT_2 ((int)2) - -#endif /* __MPC5XX_H__ */ diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 53141b1..5a0fda2 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -81,18 +81,6 @@ #define r30 30 #define r31 31

- -#if defined(CONFIG_5xx) -/* Some special purpose registers */ -#define DER 149 /* Debug Enable Register */ -#define COUNTA 150 /* Breakpoint Counter */ -#define COUNTB 151 /* Breakpoint Counter */ -#define LCTRL1 156 /* Load/Store Support */ -#define LCTRL2 157 /* Load/Store Support */ -#define ICTRL 158 /* I-Bus Support Control Register */ -#define EID 81 -#endif /* CONFIG_5xx */ - #if defined(CONFIG_MPC5xxx)

#define HID0_ICE_BITPOS 16 diff --git a/include/watchdog.h b/include/watchdog.h index 0055a83..20ac59a 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -72,11 +72,6 @@ int init_func_watchdog_reset(void); * Prototypes from $(CPU)/cpu.c. */

-/* MPC 5xx */ -#if defined(CONFIG_5xx) && !defined(__ASSEMBLY__) - void reset_5xx_watchdog(volatile immap_t *immr); -#endif - /* MPC 5xxx */ #if defined(CONFIG_MPC5xxx) && !defined(__ASSEMBLY__) void reset_5xxx_watchdog(void); diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index abe464d..135ad32 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -30,9 +30,6 @@ CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET CONFIG_4xx_DCACHE CONFIG_521X CONFIG_533MHZ_MODE -CONFIG_5xx_CONS_SCI1 -CONFIG_5xx_CONS_SCI2 -CONFIG_5xx_GCLK_FREQ CONFIG_64BIT_PHYS_ADDR CONFIG_66 CONFIG_8349_CLKIN @@ -1657,7 +1654,6 @@ CONFIG_MPC5121ADS_REV2 CONFIG_MPC512x_FEC CONFIG_MPC5200 CONFIG_MPC5200_DDR -CONFIG_MPC555 CONFIG_MPC5xxx_FEC CONFIG_MPC5xxx_FEC_MII10 CONFIG_MPC5xxx_FEC_MII100 @@ -1893,7 +1889,6 @@ CONFIG_PALMAS_SMPS7_FPWM CONFIG_PALMAS_USB_SS_PWR CONFIG_PANIC_HANG CONFIG_PARAVIRT -CONFIG_PATI CONFIG_PB1000 CONFIG_PB1100 CONFIG_PB1500 @@ -3272,7 +3267,6 @@ CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS CONFIG_SYS_DEFAULT_MBAR CONFIG_SYS_DEFAULT_VIDEO_MODE CONFIG_SYS_DEF_EEPROM_ADDR -CONFIG_SYS_DER CONFIG_SYS_DEVICE_NULLDEV CONFIG_SYS_DFU_DATA_BUF_SIZE CONFIG_SYS_DFU_MAX_FILE_SIZE @@ -4304,7 +4298,6 @@ CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_OFFSET CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_MEM -CONFIG_SYS_ISB CONFIG_SYS_ISRAM_BASE CONFIG_SYS_IVM_EEPROM_ADR CONFIG_SYS_IVM_EEPROM_MAX_LEN @@ -4460,7 +4453,6 @@ CONFIG_SYS_MARUBUN_IO CONFIG_SYS_MARUBUN_MRSHPC CONFIG_SYS_MARUBUN_MW1 CONFIG_SYS_MARUBUN_MW2 -CONFIG_SYS_MASK CONFIG_SYS_MASTER_CLOCK CONFIG_SYS_MATRIX_EBI0CSA_VAL CONFIG_SYS_MATRIX_EBICSA_VAL @@ -4915,7 +4907,6 @@ CONFIG_SYS_OR_TIMING_SDRAM CONFIG_SYS_OSC0_HZ CONFIG_SYS_OSC1_HZ CONFIG_SYS_OSCIN_FREQ -CONFIG_SYS_OSC_CLK CONFIG_SYS_OSD_DH CONFIG_SYS_OSD_SCREENS CONFIG_SYS_OSPR_OFFSET @@ -5253,7 +5244,6 @@ CONFIG_SYS_PIOC_PPUDR_VAL CONFIG_SYS_PIOD_PDR_VAL1 CONFIG_SYS_PIOD_PPUDR_VAL CONFIG_SYS_PIO_MODE -CONFIG_SYS_PISCR CONFIG_SYS_PIT_BASE CONFIG_SYS_PIT_PRESCALE CONFIG_SYS_PIXIS_VBOOT_ENABLE @@ -5276,7 +5266,6 @@ CONFIG_SYS_PLL_FDR CONFIG_SYS_PLL_ODR CONFIG_SYS_PLL_RECONFIG CONFIG_SYS_PLL_SETTLING_TIME -CONFIG_SYS_PLPRCR CONFIG_SYS_PLUG_BASE CONFIG_SYS_PMAN CONFIG_SYS_PMC_BASE @@ -5593,7 +5582,6 @@ CONFIG_SYS_SICRH CONFIG_SYS_SICRL CONFIG_SYS_SIL1178_I2C CONFIG_SYS_SIMULATE_SPD_EEPROM -CONFIG_SYS_SIUMCR CONFIG_SYS_SJA1000_BASE CONFIG_SYS_SMALL_FLASH CONFIG_SYS_SMC0_CYCLE0_VAL @@ -5622,9 +5610,6 @@ CONFIG_SYS_SPI_ARGS_OFFS CONFIG_SYS_SPI_ARGS_SIZE CONFIG_SYS_SPI_BASE CONFIG_SYS_SPI_CLK -CONFIG_SYS_SPI_CS_ACT -CONFIG_SYS_SPI_CS_BASE -CONFIG_SYS_SPI_CS_USED CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE @@ -5674,11 +5659,9 @@ CONFIG_SYS_STATUS_OK CONFIG_SYS_STMICRO_BOOT CONFIG_SYS_SUPPORT_64BIT_DATA CONFIG_SYS_SXCNFG_VAL -CONFIG_SYS_SYPCR CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_SYSTEMACE_WIDTH CONFIG_SYS_TBIPA_VALUE -CONFIG_SYS_TBSCR CONFIG_SYS_TCLK CONFIG_SYS_TEMP_STACK_OCM CONFIG_SYS_TEXT_ADDR @@ -5774,7 +5757,6 @@ CONFIG_SYS_UECx_PHY_ADDR CONFIG_SYS_UHC0_EHCI_BASE CONFIG_SYS_UHC1_EHCI_BASE CONFIG_SYS_ULB_CLK -CONFIG_SYS_UMCR CONFIG_SYS_UNIFY_CACHE CONFIG_SYS_UNSPEC_PHYID CONFIG_SYS_UNSPEC_STRID