[PATCH 1/5] spl: fit: Add board level function to decide application of DTO

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[PATCH 1/4] clk: imx: add i.MX93...

Marek Vasut

21 Sep 2023 21 Sep '23

8:44 p.m.

Add board-specific function used to indicate whether a DTO from fitImage configuration node 'fdt' property DT and DTO list should be applied onto the base DT or not applied.

This is useful in case of DTOs which implement e.g. different board revision details, where such DTO should be applied on one board revision, and should not be applied on another board revision.

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 730639f7562..ed91ddd6b40 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -357,6 +357,11 @@ static bool os_takes_devicetree(uint8_t os) } }

+__weak int board_spl_fit_append_fdt_skip(const char *name) +{ + return 0; /* Do not skip */ +} + static int spl_fit_append_fdt(struct spl_image_info *spl_image, struct spl_load_info *info, ulong sector, const struct spl_fit_info *ctx) @@ -400,11 +405,23 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image, void *tmpbuffer = NULL;

for (; ; index++) { - node = spl_fit_get_image_node(ctx, FIT_FDT_PROP, index); - if (node == -E2BIG) { + const char *str; + + ret = spl_fit_get_image_name(ctx, FIT_FDT_PROP, index, &str); + if (ret == -E2BIG) { debug("%s: No additional FDT node\n", __func__); + ret = 0; break; - } else if (node < 0) { + } else if (ret < 0) { + continue; + } + + ret = board_spl_fit_append_fdt_skip(str); + if (ret) + continue; + + node = fdt_subnode_offset(ctx->fit, ctx->images_node, str); + if (node < 0) { debug("%s: unable to find FDT node %d\n", __func__, index); continue; diff --git a/include/spl.h b/include/spl.h index 92bcaa90a4a..60a432c4b15 100644 --- a/include/spl.h +++ b/include/spl.h @@ -895,6 +895,22 @@ void spl_perform_fixups(struct spl_image_info *spl_image); */ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size);

+/** + * board_spl_fit_append_fdt_skip(): test whether DTO application should be skipped + * @name: DTO node name within fitImage images node + * + * A board-specific function used to indicate whether a DTO from fitImage + * configuration node 'fdt' property DT and DTO list should be applied onto + * the base DT or not applied. + * + * This is useful in case of DTOs which implement e.g. different board revision + * details, where such DTO should be applied on one board revision, and should + * not be applied on another board revision. + * + * Return: 0 to indicate DTO is not skipped, all else to indicate DTO is skipped. + */ +int board_spl_fit_append_fdt_skip(const char *name); + void board_boot_order(u32 *spl_boot_list); void spl_save_restore_data(void); #endif

-- 2.40.1

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Marek Vasut

21 Sep 21 Sep

8:44 p.m.

New subject: [PATCH 2/5] arm64: dts: imx8mp: Switch to DT overlays for i.MX8MP DHCOM SoM

Add DT overlays to support additional DH i.MX8MP DHCOM SoM 660-100 population options with 1x or 2x RMII PHY mounted on PDK2 or PDK3 carrier boards.

Use SPL DTO support to apply matching SoM specific DTO to cater for the SoM differences. Remove ad-hoc patching of control DT from fdtdec_board_setup().

Signed-off-by: Marek Vasut marex@denx.de --- Cc: "NXP i.MX U-Boot Team" uboot-imx@nxp.com Cc: Algapally Santosh Sagar santoshsagar.algapally@amd.com Cc: Fabio Estevam festevam@gmail.com Cc: Mayuresh Chitale mchitale@ventanamicro.com Cc: Oleksandr Suvorov oleksandr.suvorov@foundries.io Cc: Ovidiu Panait ovpanait@gmail.com Cc: Roger Quadros rogerq@kernel.org Cc: Simon Glass sjg@chromium.org Cc: Stefano Babic sbabic@denx.de Cc: u-boot@dh-electronics.com --- arch/arm/dts/Makefile | 3 + .../imx8mp-dhcom-pdk-overlay-eth2xfast.dts | 10 + .../imx8mp-dhcom-som-overlay-eth1xfast.dts | 43 ++++ .../imx8mp-dhcom-som-overlay-eth2xfast.dts | 24 ++ arch/arm/dts/imx8mp-dhcom-u-boot.dtsi | 49 ++++ .../dh_imx8mp/imx8mp_dhcom_pdk2.c | 228 ------------------ board/dhelectronics/dh_imx8mp/spl.c | 46 ++++ configs/imx8mp_dhcom_pdk3_defconfig | 3 +- 8 files changed, 177 insertions(+), 229 deletions(-) create mode 100644 arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts create mode 100644 arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts create mode 100644 arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bde2176ec7f..a116207b473 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1042,6 +1042,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-phanbell.dtb \ imx8mp-beacon-kit.dtb \ imx8mp-data-modul-edm-sbc.dtb \ + imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ + imx8mp-dhcom-som-overlay-eth2xfast.dtbo \ + imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ imx8mp-evk.dtb \ diff --git a/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts b/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts new file mode 100644 index 00000000000..3b397776920 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023 Marek Vasut marex@denx.de + */ +/dts-v1/; +/plugin/; + +&ethphypdk { /* Micrel KSZ9131RNXI */ + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts new file mode 100644 index 00000000000..bb5a2b68175 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023 Marek Vasut marex@denx.de + */ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/imx8mp-clock.h> + +&eqos { /* First ethernet */ + pinctrl-0 = <&pinctrl_eqos_rmii>; + phy-handle = <&ethphy0f>; + phy-mode = "rmii"; + + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>; +}; + +&ethphy0g { /* Micrel KSZ9131RNXI */ + status = "disabled"; +}; + +&ethphy0f { /* SMSC LAN8740Ai */ + status = "okay"; +}; + +&fec { /* Second ethernet -- HS connector not populated on 1x RMII PHY SoM */ + status = "disabled"; +}; + +/* No WiFi/BT chipset on this SoM variant. */ + +&uart2 { + bluetooth { + status = "disabled"; + }; +}; + +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts new file mode 100644 index 00000000000..82dadcea96c --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023 Marek Vasut marex@denx.de + */ +#include "imx8mp-dhcom-som-overlay-eth1xfast.dts" + +/* Dual RMII 100/Full Fast ethernet on this SoM variant. */ + +&fec { /* Second ethernet */ + pinctrl-0 = <&pinctrl_fec_rmii>; + phy-handle = <&ethphy1f>; + phy-mode = "rmii"; + status = "okay"; + + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>, <0>; +}; + +&ethphy1f { /* SMSC LAN8740Ai */ + status = "okay"; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi index 59d31eebc3e..00e1db66568 100644 --- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi @@ -133,3 +133,52 @@ &wdog1 { bootph-pre-ram; }; + +&binman { + itb { + fit { + images { + fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast { + description = "imx8mp-dhcom-som-overlay-eth1xfast"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo"; + }; + }; + + fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast { + description = "imx8mp-dhcom-som-overlay-eth2xfast"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo"; + }; + }; + + fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast { + description = "imx8mp-dhcom-pdk-overlay-eth2xfast"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo"; + }; + }; + }; + + configurations { + default = "@config-DEFAULT-SEQ"; + + @config-SEQ { + fdt = "fdt-1", + "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast", + "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast", + "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast"; + }; + }; + }; + }; +}; diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 760ea4be35c..5edb85e1de5 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -5,16 +5,12 @@

#include <common.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> #include <dm.h> -#include <dt-bindings/clock/imx8mp-clock.h> #include <env.h> #include <env_internal.h> #include <i2c_eeprom.h> -#include <linux/bitfield.h> #include <malloc.h> #include <net.h> #include <miiphy.h> @@ -120,227 +116,3 @@ enum env_location env_get_location(enum env_operation op, int prio) { return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH; } - -static const char *iomuxc_compat = "fsl,imx8mp-iomuxc"; -static const char *lan_compat = "ethernet-phy-id0007.c110"; -static const char *ksz_compat = "ethernet-phy-id0022.1642"; - -static int dh_dt_patch_som_eqos(const void *fdt_blob) -{ - const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR + - FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24); - int mac_node, mdio_node, iomuxc_node, ksz_node, lan_node, subnode; - const char *mac_compat = "nxp,imx8mp-dwmac-eqos"; - void *blob = (void *)fdt_blob; - const fdt32_t *clk_prop; - bool is_gigabit; - u32 handle; - u32 clk[6]; - - setbits_le32(mux, IOMUX_CONFIG_SION); - is_gigabit = !(readl(GPIO1_BASE_ADDR) & BIT(24)); - clrbits_le32(mux, IOMUX_CONFIG_SION); - - /* Adjust EQoS node for Gigabit KSZ9131RNXI or Fast LAN8740Ai PHY */ - mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat); - if (mac_node < 0) - return 0; - - mdio_node = fdt_first_subnode(blob, mac_node); - if (mdio_node < 0) - return 0; - - /* KSZ9131RNXI */ - ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat); - if (ksz_node < 0) - return 0; - - /* LAN8740Ai */ - lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat); - if (lan_node < 0) - return 0; - - iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat); - if (iomuxc_node < 0) - return 0; - - /* - * The code below adjusts the following DT properties: - * - assigned-clock-parents .. 125 MHz RGMII / 50 MHz RMII ref clock - * - assigned-clock-rates .... 125 MHz RGMII / 50 MHz RMII ref clock - * - phy-handle .............. KSZ9131RNXI RGMII / LAN8740Ai RMII - * - phy-mode ................ RGMII / RMII - * - pinctrl-0 ............... RGMII / RMII - * - PHY subnode status ...... "disabled"/"okay" per RGMII / RMII - */ - - /* Perform all inplace changes first, string changes last. */ - clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL); - if (!clk_prop) - return 0; - clk[0] = clk_prop[0]; - clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M); - clk[2] = clk_prop[2]; - clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M); - clk[4] = clk_prop[4]; - clk[5] = is_gigabit ? cpu_to_fdt32(IMX8MP_SYS_PLL2_125M) : - cpu_to_fdt32(IMX8MP_SYS_PLL2_50M); - fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents", - clk, 6 * sizeof(u32)); - - clk[0] = cpu_to_fdt32(0); - clk[1] = cpu_to_fdt32(100000000); - clk[2] = is_gigabit ? cpu_to_fdt32(125000000) : - cpu_to_fdt32(50000000); - fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates", - clk, 3 * sizeof(u32)); - - handle = fdt_get_phandle(blob, is_gigabit ? ksz_node : lan_node); - fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle); - - fdt_for_each_subnode(subnode, blob, iomuxc_node) { - if (!strstr(fdt_get_name(blob, subnode, NULL), - is_gigabit ? "eqos-rgmii" : "eqos-rmii")) - continue; - - handle = fdt_get_phandle(blob, subnode); - fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle); - break; - } - - fdt_setprop_string(blob, mac_node, "phy-mode", - is_gigabit ? "rgmii-id" : "rmii"); - - mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat); - mdio_node = fdt_first_subnode(blob, mac_node); - ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat); - fdt_setprop_string(blob, ksz_node, "status", - is_gigabit ? "okay" : "disabled"); - - mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat); - mdio_node = fdt_first_subnode(blob, mac_node); - lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat); - fdt_setprop_string(blob, lan_node, "status", - is_gigabit ? "disabled" : "okay"); - - return 0; -} - -static int dh_dt_patch_som_fec(const void *fdt_blob) -{ - const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR + - FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10); - int mac_node, mdio_node, iomuxc_node, lan_node, phy_node, subnode; - const char *mac_compat = "fsl,imx8mp-fec"; - void *blob = (void *)fdt_blob; - const fdt32_t *clk_prop; - bool is_gigabit; - u32 handle; - u32 clk[8]; - - setbits_le32(mux, IOMUX_CONFIG_SION); - is_gigabit = !(readl(GPIO4_BASE_ADDR) & BIT(10)); - clrbits_le32(mux, IOMUX_CONFIG_SION); - - /* Test for non-default SoM with 100/Full PHY attached to FEC */ - if (is_gigabit) - return 0; - - /* Adjust FEC node for Fast LAN8740Ai PHY */ - mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat); - if (mac_node < 0) - return 0; - - /* Optional PHY pointed to by phy-handle, possibly on carrier board */ - phy_node = fdtdec_lookup_phandle(blob, mac_node, "phy-handle"); - if (phy_node > 0) { - fdt_setprop_string(blob, phy_node, "status", "disabled"); - mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat); - } - - mdio_node = fdt_first_subnode(blob, mac_node); - if (mdio_node < 0) - return 0; - - /* LAN8740Ai */ - lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat); - if (lan_node < 0) - return 0; - - iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat); - if (iomuxc_node < 0) - return 0; - - /* - * The code below adjusts the following DT properties: - * - assigned-clock-parents .. 50 MHz RMII ref clock - * - assigned-clock-rates .... 50 MHz RMII ref clock - * - phy-handle .............. LAN8740Ai RMII - * - phy-mode ................ RMII - * - pinctrl-0 ............... RMII - * - PHY subnode status ...... "okay" for RMII PHY - */ - - /* Perform all inplace changes first, string changes last. */ - clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL); - if (!clk_prop) - return 0; - clk[0] = clk_prop[0]; - clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M); - clk[2] = clk_prop[2]; - clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M); - clk[4] = clk_prop[4]; - clk[5] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M); - clk[6] = clk_prop[6]; - clk[7] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M); - fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents", - clk, 8 * sizeof(u32)); - - clk[0] = cpu_to_fdt32(0); - clk[1] = cpu_to_fdt32(100000000); - clk[2] = cpu_to_fdt32(50000000); - clk[3] = cpu_to_fdt32(0); - fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates", - clk, 4 * sizeof(u32)); - - handle = fdt_get_phandle(blob, lan_node); - fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle); - - fdt_for_each_subnode(subnode, blob, iomuxc_node) { - if (!strstr(fdt_get_name(blob, subnode, NULL), "fec-rmii")) - continue; - - handle = fdt_get_phandle(blob, subnode); - fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle); - break; - } - - fdt_setprop_string(blob, mac_node, "phy-mode", "rmii"); - mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat); - mdio_node = fdt_first_subnode(blob, mac_node); - lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat); - fdt_setprop_string(blob, lan_node, "status", "okay"); - - return 0; -} - -static int dh_dt_patch_som(const void *fdt_blob) -{ - int ret; - - /* Do nothing if not i.MX8MP DHCOM SoM */ - ret = fdt_node_check_compatible(fdt_blob, 0, "dh,imx8mp-dhcom-som"); - if (ret) - return 0; - - ret = dh_dt_patch_som_eqos(fdt_blob); - if (ret) - return ret; - - return dh_dt_patch_som_fec(fdt_blob); -} - -int fdtdec_board_setup(const void *fdt_blob) -{ - return dh_dt_patch_som(fdt_blob); -} diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c index a8fda139aa4..8dc464b1dd7 100644 --- a/board/dhelectronics/dh_imx8mp/spl.c +++ b/board/dhelectronics/dh_imx8mp/spl.c @@ -22,6 +22,8 @@ #include <dm/uclass-internal.h> #include <dm/device-internal.h>

+#include <linux/bitfield.h> + #include <power/pmic.h> #include <power/pca9450.h>

@@ -41,6 +43,8 @@ static const iomux_v3_cfg_t wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), };

+static bool dh_gigabit_eqos, dh_gigabit_fec; + static void dh_imx8mp_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; @@ -144,6 +148,46 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) return BOOT_DEVICE_BOOTROM; }

+int board_spl_fit_append_fdt_skip(const char *name) +{ + if (!dh_gigabit_eqos) { /* 1x or 2x RMII PHY SoM */ + if (dh_gigabit_fec) { /* 1x RMII PHY SoM */ + if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast")) + return 0; + } else { /* 2x RMII PHY SoM */ + if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast")) + return 0; + if (!strcmp(name, "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast")) { + /* 2x RMII PHY SoM on PDK2 or PDK3 */ + if (of_machine_is_compatible("dh,imx8mp-dhcom-pdk2") || + of_machine_is_compatible("dh,imx8mp-dhcom-pdk3")) + return 0; + } + } + } + + return 1; /* Skip this DTO */ +} + +static void dh_imx8mp_board_cache_config(void) +{ + const void __iomem *mux_base = (void __iomem *)IOMUXC_BASE_ADDR; + const u32 mux_sion[] = { + FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24), + FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10), + }; + int i; + + for (i = 0; i < ARRAY_SIZE(mux_sion); i++) + setbits_le32(mux_base + mux_sion[i], IOMUX_CONFIG_SION); + + dh_gigabit_eqos = !(readl(GPIO1_BASE_ADDR) & BIT(24)); + dh_gigabit_fec = !(readl(GPIO4_BASE_ADDR) & BIT(10)); + + for (i = 0; i < ARRAY_SIZE(mux_sion); i++) + clrbits_le32(mux_base + mux_sion[i], IOMUX_CONFIG_SION); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -181,5 +225,7 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init();

+ dh_imx8mp_board_cache_config(); + board_init_r(NULL, 0); } diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index 3f089291ee3..55fdde4acd1 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-pdk3" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y CONFIG_SYS_PROMPT="u-boot=> " -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_MMC=y @@ -40,6 +39,7 @@ CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000 +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_BOOTARGS=y @@ -65,6 +65,7 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4c000000 CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +# CONFIG_SPL_FIT_IMAGE_TINY is not set CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y

-- 2.40.1

sbabic＠denx.de

16 Oct 16 Oct

6:46 p.m.

New subject: [PATCH 2/5] arm64: dts: imx8mp: Switch to DT overlays for i.MX8MP DHCOM SoM

...

Add DT overlays to support additional DH i.MX8MP DHCOM SoM 660-100 population options with 1x or 2x RMII PHY mounted on PDK2 or PDK3 carrier boards. Use SPL DTO support to apply matching SoM specific DTO to cater for the SoM differences. Remove ad-hoc patching of control DT from fdtdec_board_setup(). Signed-off-by: Marek Vasut marex@denx.de

Applied to u-boot-imx, master, thanks !

Best regards, Stefano Babic

-- ===================================================================== DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, 82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================

Marek Vasut

21 Sep 21 Sep

8:44 p.m.

New subject: [PATCH 3/5] arm64: dts: imx8mp: Update i.MX8MP DHCOM SoM DT to production rev.200

The current imx8mp-dhcom-som.dtsi describes prototype rev.100 SoM, update the DT to describe production rev.200 SoM which brings the following changes: - Fast SoC GPIOs exposed on the SoM edge connector - Slow GPIOs like component resets moved to I2C GPIO expander - ADC upgraded from TLA2024 to ADS1015 with conversion interrupt - EEPROM size increased from 256 B to 4 kiB

diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi index 9fd8bce8065..ea2a567447a 100644 --- a/arch/arm/dts/imx8mp-dhcom-som.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi @@ -25,9 +25,7 @@

reg_eth_vio: regulator-eth-vio { compatible = "regulator-fixed"; - gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pinctrl_enet_vio>; - pinctrl-names = "default"; + gpio = <&ioexp 2 GPIO_ACTIVE_LOW>; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; @@ -49,6 +47,14 @@ startup-delay-us = <100>; vin-supply = <&buck4>; }; + + reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo { /* VDD_3V3_AWO */ + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VDD_3P3V_AWO"; + }; };

&A53_0 { @@ -104,7 +110,7 @@ reg = <0>; reset-assert-us = <1000>; reset-deassert-us = <1000>; - reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; /* Non-default PHY population option. */ status = "disabled"; }; @@ -120,7 +126,7 @@ reg = <5>; reset-assert-us = <1000>; reset-deassert-us = <1000>; - reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; /* Default PHY population option. */ status = "okay"; }; @@ -320,8 +326,9 @@ };

adc@48 { - compatible = "ti,tla2024"; + compatible = "ti,ads1015"; reg = <0x48>; + interrupts-extended = <&ioexp 7 IRQ_TYPE_EDGE_FALLING>; #address-cells = <1>; #size-cells = <0>;

@@ -368,24 +375,40 @@ };

eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */ - compatible = "atmel,24c02"; - pagesize = <16>; + compatible = "atmel,24c32"; /* M24C32-D */ + pagesize = <32>; reg = <0x50>; };

rv3032: rtc@51 { compatible = "microcrystal,rv3032"; reg = <0x51>; - interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; + interrupts-extended = <&ioexp 3 IRQ_TYPE_EDGE_FALLING>; };

eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */ - compatible = "atmel,24c02"; - pagesize = <16>; + compatible = "atmel,24c32"; /* M24C32-D */ + pagesize = <32>; reg = <0x53>; }; + + ioexp: gpio@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ioexp>; + + gpio-line-names = + "BT_REG_EN", "WL_REG_EN", "VIO_SWITCHED_#EN", "RTC_#INT", + "ENET_QOS_#RST", "RGB_OSZ_ENABLE", "USB1_ID", "ADC_ALTER_RDY", + "DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T", + "BT_HOST_WAKE", "BT_DEV_WAKE", "", ""; + }; };

&i2c4 { @@ -427,6 +450,23 @@ pinctrl-0 = <&pinctrl_uart2>; uart-has-rtscts; status = "okay"; + + /* + * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock, + * which with 16x oversampling yields 5 Mbdps baud base, + * which can be well divided by 5/4 to achieve 4 Mbdps, + * which is exactly the maximum rate supported by muRata + * 2AE bluetooth UART. + */ + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + assigned-clock-rates = <80000000>; + + bluetooth { + compatible = "cypress,cyw4373a0-bt"; + shutdown-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + }; };

&uart3 { @@ -451,8 +491,6 @@ };

&usb_dwc3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_vbus>; dr_mode = "otg"; status = "okay"; }; @@ -496,7 +534,7 @@ * connected to the SoC, but can be connected on to * SoC pin on the carrier board. */ - reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>; }; };

@@ -538,8 +576,9 @@ &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l - /* GPIO_M is connected to CLKOUT2 */ - &pinctrl_dhcom_int>; + &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_int>; pinctrl-names = "default";

pinctrl_dhcom_a: dhcom-a-grp { @@ -626,6 +665,55 @@ >; };

+ pinctrl_dhcom_m: dhcom-m-grp { + fsl,pins = < + /* CSIx_MCLK */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x2 + >; + }; + + pinctrl_dhcom_n: dhcom-n-grp { + fsl,pins = < + /* CSI2_D3- */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x2 + >; + }; + + pinctrl_dhcom_o: dhcom-o-grp { + fsl,pins = < + /* CSI2_D3+ */ + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x2 + >; + }; + + pinctrl_dhcom_p: dhcom-p-grp { + fsl,pins = < + /* CSI2_D2- */ + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x2 + >; + }; + + pinctrl_dhcom_q: dhcom-q-grp { + fsl,pins = < + /* CSI2_D2+ */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x2 + >; + }; + + pinctrl_dhcom_r: dhcom-r-grp { + fsl,pins = < + /* CSI2_D1- */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x2 + >; + }; + + pinctrl_dhcom_s: dhcom-s-grp { + fsl,pins = < + /* CSI2_D1+ */ + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x2 + >; + }; + pinctrl_dhcom_int: dhcom-int-grp { fsl,pins = < /* INT_HIGHEST_PRIO */ @@ -699,17 +787,9 @@ >; };

- pinctrl_enet_vio: dhcom-enet-vio-grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22 - >; - }; - pinctrl_ethphy0: dhcom-ethphy0-grp { fsl,pins = < - /* ENET1_#RST Reset */ - MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 - /* ENET1_#INT Interrupt */ + /* ENET_QOS_#INT Interrupt */ MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22 >; }; @@ -834,6 +914,13 @@ >; };

+ pinctrl_ioexp: dhcom-ioexp-grp { + fsl,pins = < + /* #GPIO_EXP_INT */ + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 + >; + }; + pinctrl_pmic: dhcom-pmic-grp { fsl,pins = < /* PMIC_nINT */ @@ -847,10 +934,21 @@ >; };

- pinctrl_rtc: dhcom-rtc-grp { + pinctrl_tc9595: dhcom-tc9595-grp { fsl,pins = < - /* RTC_#INT Interrupt */ - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080 + /* RESET_DSIBRIDGE */ + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000146 + /* DSI-CONV_INT Interrupt */ + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x141 + >; + }; + + pinctrl_sai3: dhcom-sai3-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 >; };

@@ -897,12 +995,6 @@ >; };

- pinctrl_usb0_vbus: dhcom-usb0-grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0 - >; - }; - pinctrl_usb1_vbus: dhcom-usb1-grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6 @@ -918,10 +1010,6 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 - /* WL_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; };

@@ -933,10 +1021,6 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 - /* WL_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; };

@@ -948,10 +1032,6 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 - /* WL_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; };

diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi index 00e1db66568..6f21fbe1151 100644 --- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi @@ -167,6 +167,26 @@ filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo"; }; }; + + fdt-dto-imx8mp-dhcom-som-overlay-rev100 { + description = "imx8mp-dhcom-som-overlay-rev100"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-som-overlay-rev100.dtbo"; + }; + }; + + fdt-dto-imx8mp-dhcom-pdk-overlay-rev100 { + description = "imx8mp-dhcom-pdk-overlay-rev100"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-pdk-overlay-rev100.dtbo"; + }; + }; };

configurations { @@ -176,7 +196,9 @@ fdt = "fdt-1", "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast", "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast", - "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast"; + "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast", + "fdt-dto-imx8mp-dhcom-som-overlay-rev100", + "fdt-dto-imx8mp-dhcom-pdk-overlay-rev100"; }; }; }; diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index 55fdde4acd1..b3720c1acbb 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -262,3 +262,4 @@ CONFIG_USB_FUNCTION_ACM=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_IMX_WATCHDOG=y +CONFIG_DM_PCA953X=y

-- 2.40.1

sbabic＠denx.de

16 Oct 16 Oct

6:46 p.m.

New subject: [PATCH 3/5] arm64: dts: imx8mp: Update i.MX8MP DHCOM SoM DT to production rev.200

...

The current imx8mp-dhcom-som.dtsi describes prototype rev.100 SoM, update the DT to describe production rev.200 SoM which brings the following changes:

Fast SoC GPIOs exposed on the SoM edge connector

Slow GPIOs like component resets moved to I2C GPIO expander

ADC upgraded from TLA2024 to ADS1015 with conversion interrupt

EEPROM size increased from 256 B to 4 kiB

Signed-off-by: Marek Vasut marex@denx.de

Applied to u-boot-imx, master, thanks !

Best regards, Stefano Babic

Marek Vasut

21 Sep 21 Sep

8:44 p.m.

New subject: [PATCH 4/5] arm64: dts: imx8mp: Drop i.MX8MP DHCOM rev.100 PHY address workaround from PDK3 DT

In case the i.MX8MP DHCOM rev.100 has been populated on the PDK3 carrier board, the on-SoM PHY PHYAD1 signal has been pulled high by the carrier board and changed the PHY MDIO address from 5 to 7. This has been fixed on production rev.200 SoM by additional buffer on the SoM PHYAD/LED signals, remove the workaround.

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3.dts b/arch/arm/dts/imx8mp-dhcom-pdk3.dts index c5f0607f43b..867d238f2b5 100644 --- a/arch/arm/dts/imx8mp-dhcom-pdk3.dts +++ b/arch/arm/dts/imx8mp-dhcom-pdk3.dts @@ -227,10 +227,6 @@ }; };

-&ethphy0g { - reg = <7>; -}; - &fec { /* Second ethernet */ pinctrl-0 = <&pinctrl_fec_rgmii>; phy-handle = <&ethphypdk>;

-- 2.40.1

sbabic＠denx.de

16 Oct 16 Oct

6:46 p.m.

New subject: [PATCH 4/5] arm64: dts: imx8mp: Drop i.MX8MP DHCOM rev.100 PHY address workaround from PDK3 DT

...

In case the i.MX8MP DHCOM rev.100 has been populated on the PDK3 carrier board, the on-SoM PHY PHYAD1 signal has been pulled high by the carrier board and changed the PHY MDIO address from 5 to 7. This has been fixed on production rev.200 SoM by additional buffer on the SoM PHYAD/LED signals, remove the workaround. Signed-off-by: Marek Vasut marex@denx.de

Applied to u-boot-imx, master, thanks !

Best regards, Stefano Babic

Marek Vasut

21 Sep 21 Sep

8:44 p.m.

New subject: [PATCH 5/5] arm64: dts: imx8mp: Add DT overlay describing i.MX8MP DHCOM SoM rev.100

The current imx8mp-dhcom-som.dtsi describes production rev.200 SoM, add DT overlay which reinstates rev.100 SoM description to permit prototype rev.100 SoMs to be used until they get phased out.

Signed-off-by: Marek Vasut marex@denx.de --- Cc: "NXP i.MX U-Boot Team" uboot-imx@nxp.com Cc: Algapally Santosh Sagar santoshsagar.algapally@amd.com Cc: Fabio Estevam festevam@gmail.com Cc: Mayuresh Chitale mchitale@ventanamicro.com Cc: Oleksandr Suvorov oleksandr.suvorov@foundries.io Cc: Ovidiu Panait ovpanait@gmail.com Cc: Roger Quadros rogerq@kernel.org Cc: Simon Glass sjg@chromium.org Cc: Stefano Babic sbabic@denx.de Cc: u-boot@dh-electronics.com --- arch/arm/dts/Makefile | 2 + .../dts/imx8mp-dhcom-pdk3-overlay-rev100.dts | 10 ++ .../dts/imx8mp-dhcom-som-overlay-rev100.dts | 120 ++++++++++++++++++ arch/arm/dts/imx8mp-dhcom-u-boot.dtsi | 8 +- board/dhelectronics/dh_imx8mp/spl.c | 16 +++ 5 files changed, 152 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts create mode 100644 arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a116207b473..f05aa3d21f6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1042,11 +1042,13 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-phanbell.dtb \ imx8mp-beacon-kit.dtb \ imx8mp-data-modul-edm-sbc.dtb \ + imx8mp-dhcom-som-overlay-rev100.dtbo \ imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ imx8mp-dhcom-som-overlay-eth2xfast.dtbo \ imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ imx8mp-evk.dtb \ imx8mp-icore-mx8mp-edimm2.2.dtb \ imx8mp-msc-sm2s.dtb \ diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts b/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts new file mode 100644 index 00000000000..f27e6429abe --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023 Marek Vasut marex@denx.de + */ +/dts-v1/; +/plugin/; + +&ethphy0g { + reg = <7>; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts new file mode 100644 index 00000000000..5d9a00c9429 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023 Marek Vasut marex@denx.de + */ +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +#include "imx8mp-pinfunc.h" + +&brcmf { + reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +}; + +&eeprom0 { /* EEPROM with EQoS MAC address */ + compatible = "atmel,24c02"; + pagesize = <16>; +}; + +&eeprom1 { /* EEPROM with FEC MAC address */ + compatible = "atmel,24c02"; + pagesize = <16>; +}; + +&ethphy0f { /* SMSC LAN8740Ai */ + pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>; + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; +}; + +&ethphy0g { /* Micrel KSZ9131RNXI */ + pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>; + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; +}; + +&i2c3 { + adc@48 { + compatible = "ti,tla2024"; + interrupts-extended; + }; +}; + +&ioexp { + status = "disabled"; +}; + +&reg_eth_vio { + gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_enet_vio>; + pinctrl-names = "default"; +}; + +&rv3032 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>; +}; + +&uart2 { + bluetooth { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt>; + shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; +}; + +&usb_dwc3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_vbus>; +}; + +&usdhc1 { + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_wl_reg_en>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_usdhc1_wl_reg_en>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_usdhc1_wl_reg_en>; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + /* GPIO_M is connected to CLKOUT2 */ + &pinctrl_dhcom_int>; + + pinctrl_enet_vio: dhcom-enet-vio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22 + >; + }; + + pinctrl_rtc: dhcom-rtc-grp { + fsl,pins = < + /* RTC_#INT Interrupt */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6 + >; + }; + + pinctrl_uart2_bt: dhcom-uart2-bt-grp { + fsl,pins = < + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + >; + }; + + pinctrl_usb0_vbus: dhcom-usb0-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0 + >; + }; + + pinctrl_usdhc1_wl_reg_en: dhcom-usdhc1-wl-reg-en-grp { + fsl,pins = < + /* WL_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi index 6f21fbe1151..a29db0ddd3f 100644 --- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi @@ -178,13 +178,13 @@ }; };

- fdt-dto-imx8mp-dhcom-pdk-overlay-rev100 { - description = "imx8mp-dhcom-pdk-overlay-rev100"; + fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 { + description = "imx8mp-dhcom-pdk3-overlay-rev100"; type = "flat_dt"; compression = "none";

blob-ext { - filename = "imx8mp-dhcom-pdk-overlay-rev100.dtbo"; + filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo"; }; }; }; @@ -198,7 +198,7 @@ "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast", "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast", "fdt-dto-imx8mp-dhcom-som-overlay-rev100", - "fdt-dto-imx8mp-dhcom-pdk-overlay-rev100"; + "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100"; }; }; }; diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c index 8dc464b1dd7..1b05da53c35 100644 --- a/board/dhelectronics/dh_imx8mp/spl.c +++ b/board/dhelectronics/dh_imx8mp/spl.c @@ -44,6 +44,7 @@ static const iomux_v3_cfg_t wdog_pads[] = { };

static bool dh_gigabit_eqos, dh_gigabit_fec; +static u8 dh_som_rev;

static void dh_imx8mp_early_init_f(void) { @@ -166,6 +167,15 @@ int board_spl_fit_append_fdt_skip(const char *name) } }

+ if (dh_som_rev == 0x0) { /* Prototype SoM rev.100 */ + if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-rev100")) + return 0; + + if (!strcmp(name, "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100") && + of_machine_is_compatible("dh,imx8mp-dhcom-pdk3")) + return 0; + } + return 1; /* Skip this DTO */ }

@@ -175,6 +185,9 @@ static void dh_imx8mp_board_cache_config(void) const u32 mux_sion[] = { FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24), FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10), + FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_NAND_DQS__GPIO3_IO14), + FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXD7__GPIO4_IO19), + FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI5_MCLK__GPIO3_IO25), }; int i;

@@ -183,6 +196,9 @@ static void dh_imx8mp_board_cache_config(void)

dh_gigabit_eqos = !(readl(GPIO1_BASE_ADDR) & BIT(24)); dh_gigabit_fec = !(readl(GPIO4_BASE_ADDR) & BIT(10)); + dh_som_rev = !!(readl(GPIO3_BASE_ADDR) & BIT(14)); + dh_som_rev |= !!(readl(GPIO4_BASE_ADDR) & BIT(19)) << 1; + dh_som_rev |= !!(readl(GPIO3_BASE_ADDR) & BIT(25)) << 2;

for (i = 0; i < ARRAY_SIZE(mux_sion); i++) clrbits_le32(mux_base + mux_sion[i], IOMUX_CONFIG_SION);

-- 2.40.1

sbabic＠denx.de

16 Oct 16 Oct

6:46 p.m.

New subject: [PATCH 5/5] arm64: dts: imx8mp: Add DT overlay describing i.MX8MP DHCOM SoM rev.100

...

The current imx8mp-dhcom-som.dtsi describes production rev.200 SoM, add DT overlay which reinstates rev.100 SoM description to permit prototype rev.100 SoMs to be used until they get phased out. Signed-off-by: Marek Vasut marex@denx.de

Applied to u-boot-imx, master, thanks !

Best regards, Stefano Babic

sbabic＠denx.de

6:46 p.m.

...

Add board-specific function used to indicate whether a DTO from fitImage configuration node 'fdt' property DT and DTO list should be applied onto the base DT or not applied. This is useful in case of DTOs which implement e.g. different board revision details, where such DTO should be applied on one board revision, and should not be applied on another board revision. Signed-off-by: Marek Vasut marex@denx.de

Applied to u-boot-imx, master, thanks !

Best regards, Stefano Babic

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Marek Vasut
sbabic＠denx.de